JP2011029662A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a damascene structure, which can surely remove reaction inhibiting materials inducing resolution failure of a resist pattern, and to provide a method of manufacturing the same. <P>SOLUTION: The method of manufacturing the semiconductor device includes a process of forming at least a first interlayer insulating film 6 and a second interlayer insulating film 4 formed of a low-dielectric constant film on a substrate and forming via holes 9 by using a first resist pattern 1a formed on the second interlayer insulating film and a process of conducting an organic peeling treatment using organic peeling liquid containing amine components and forming a second resist pattern 1b on the second interlayer insulating film. After the wet treatment, before a second antireflection coating 2b is coated so as to be located below the second resist pattern, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis action of acid occurring in the resist during light exposure, thereby preventing degradation of the resolution of the second resist pattern 1b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a damascene semiconductor device and a manufacturing method thereof.

  In recent years, with the high integration of semiconductor devices and the reduction in chip size, miniaturization of wiring and multilayer wiring have been promoted, and as a method of forming a multilayer wiring structure, Cu is simultaneously embedded in via holes and wiring trench patterns. A so-called damascene process is generally performed in which a wiring is formed by flattening by a CMP (Chemical Mechanical Polishing) method. In this damascene process, it is possible to increase the density of wiring patterns. However, if the wiring patterns are close to each other, a problem of wiring delay due to parasitic capacitance between the wiring patterns occurs. Therefore, reduction of wiring capacitance is an important issue in order to improve wiring delay.

As a method for reducing the wiring capacitance, a method of using a material having a low dielectric constant instead of the conventionally used SiO ₂ insulating film as an interlayer insulating film has been studied (Japanese Patent Laid-Open No. 2000-77409). Gazette). Here, a conventional damascene process using a low dielectric constant film as an interlayer insulating film will be described with reference to the drawings. 23 to 25 are process cross-sectional views showing the procedure of a via first process which is one form of a conventional damascene process.

First, as shown in FIG. 23A, a first etching stop film that prevents diffusion of Cu and serves as an etching stopper for a via hole on a wiring substrate 8 on which a lower layer wiring made of Cu or the like is formed by a known method. 7, a first interlayer insulating film 6 made of SiO ₂ , a second etching stop film 5 to be an etching stopper for a wiring trench pattern, a second interlayer insulating film 4 made of a low dielectric constant film, and a cap insulating film 3 made of SiO ₂ Deposit sequentially. Then, a first antireflection coating (ARC) 2a and a photoresist are sequentially applied on the cap insulating film 3, and a first resist pattern 1a for forming a via hole 9 is formed by exposure and development.

  Next, as shown in FIG. 23B, the first antireflection film 2a, the cap insulating film 3, the second interlayer insulating film 4, the first resist pattern 1a are used as a mask and a known dry etching technique is used. (2) The etching stop film 5 and the first interlayer insulating film 6 are sequentially etched to form a via hole 9 penetrating them. Thereafter, the first resist pattern 1a and the first antireflection film 2a are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed.

  After wet treatment with an organic stripping solution, as shown in FIGS. 23C and 24A, a second antireflection film 2b and a photoresist are sequentially applied, and the wiring trench pattern is etched by exposure and development. The second resist pattern 1b is formed (see FIG. 24B). Thereafter, the second antireflection film 2b, the cap insulating film 3, and the second interlayer insulating film 4 are sequentially etched using a known dry etching technique to form a wiring trench pattern 10, and then oxygen plasma ashing and organic stripping solution are performed. The second resist pattern 1b and the second antireflection film 2b are peeled off by a wet process using, and the dry etching residue is removed (see FIGS. 24C, 25A, and 25B). Then, a wiring material 11 such as Cu is embedded in the wiring trench pattern 10 and the via hole 9, and the surface is flattened by CMP to form a dual damascene structure.

JP 2000-77409 A (page 5-7, FIG. 1)

  As described above, in the via first dual damascene process, the first resist pattern 1a is used to form the via hole 9, and after the first resist pattern 1a is peeled off, the second resist pattern 1b for etching the wiring trench pattern 10 continuously is formed. In the conventional method, after the wet stripping process using a basic organic stripper that strips the first resist pattern 1a and the first antireflection film 2a, but before the second antireflection film 2b or the resist is applied. However, pretreatment was not performed, or dehydration baking (about 2 minutes at about 150 to 250 ° C.) or thinner prewetting was performed as a pretreatment by a coating machine.

  The purpose of the dehydration baking and thinner pre-wet treatment is to remove moisture adsorbed on the substrate, particularly the inner wall of the via hole 9, and a substance that inhibits a chemical reaction in the resist such as a basic substance (hereinafter referred to as a reaction inhibitor). In other words, the resolution of the second resist pattern 1b deteriorates due to the reaction-inhibiting substance. That is, a chemical reaction is promoted using an acid catalyst generated inside the resist by exposure, and a resist pattern is formed by making it partially soluble in a developer. The acid catalyst is deactivated by leaching into the resist to suppress the chemical reaction of the resist, and a part of the wiring trench pattern 10, particularly, the resist near the via hole 9 remains without being sufficiently removed.

  Then, if the subsequent etching of the wiring trench pattern is performed in a state where the resist remains in the portion that should be removed, the shape of the wiring trench pattern 10 may be collapsed, in particular, as shown in FIG. When much resist remains, an etching residue called a crown 15 as shown in FIG. 25A remains around the via hole 9. Since this crown 15 does not dissolve in the organic stripping solution, it remains until the wiring material 11 is embedded. Therefore, there arises a problem that the reliability of the completed wiring is lowered.

This problem also occurs when SiO ₂ is used as an interlayer insulating film, but becomes more prominent when a low dielectric constant film is used. In general, since the low dielectric constant film is formed of a rough film, it has a structure in which chemicals such as organic stripping solution and cleaning solution are likely to penetrate inside, and substances that are floating in the atmosphere are likely to adhere. This is because the reaction inhibitor contained in the chemical solution gradually oozes into the resist when the antireflection film or the resist applied thereon is baked.

  In addition, it is known that not only chemical solutions such as the above organic stripping solution and cleaning solution, but also predetermined elements in the interlayer insulating film function as reaction inhibitors, and after forming via holes and wiring trench patterns, interlayer insulating films and etching stoppers are formed. When the resist pattern is formed in a state where the film is exposed on the inner wall of the via hole or the wiring trench pattern, the same defect occurs.

  This problem is not limited to the via-first dual damascene process, and other damascene processes such as a dual hard mask process and a trench first dual damascene process, and after the wet process using an organic stripping solution or a cleaning solution, the next resist pattern is formed. This also occurs in other semiconductor processes having a step of forming or a step of forming a resist pattern in a state where the insulating film is exposed on the inner wall of the via hole or trench pattern.

  The present invention has been made in view of the above-mentioned problems, and its main purpose is to reliably remove reaction inhibitory substances that cause poor resolution of resist patterns or to suppress adhesion of reaction inhibitory substances in the atmosphere or interlayers. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the influence of a reaction inhibitor in an insulating film, particularly a semiconductor device formed using a damascene process and a method for manufacturing the same.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes performing a wet process on a substrate on which an insulating film is formed using an organic stripping solution or a cleaning solution, and then forming a resist pattern on the insulating film. In the method of manufacturing a semiconductor device including the step of forming the step, after the wet treatment, before applying a resist to be the resist pattern or an antireflection film provided under the resist, it is contained in the organic stripping solution or the cleaning solution. A pretreatment is performed to remove a reaction-inhibiting substance that inhibits the chemical reaction of the resist.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: sequentially depositing at least a first interlayer insulating film and a second interlayer insulating film on a substrate on which a wiring pattern is formed; Forming a first resist pattern on the film, forming a via hole penetrating through the first interlayer insulating film and the second interlayer insulating film by dry etching using the first resist pattern as a mask, and organic A step of performing a wet process of removing at least one of a process of removing an etching residue with a stripping solution or a process of cleaning with a cleaning liquid; a step of forming a second resist pattern on the second interlayer insulating film; Etching the second interlayer insulating film using the second resist pattern as a mask to form a wiring trench pattern; and forming the via hole and the wiring trench pattern In the method of manufacturing a semiconductor device having at least a step of embedding a wiring material in a film and polishing to form a wiring pattern, a resist to be the resist pattern after the wet treatment or an antireflection film provided under the resist is provided. Before coating, a pretreatment is performed to remove a reaction-inhibiting substance that is a substance contained in the organic stripping solution or the cleaning solution and inhibits the chemical reaction of the resist.

  The method of manufacturing a semiconductor device of the present invention includes a step of depositing at least a first interlayer insulating film, a second interlayer insulating film, and a mask member made of an inorganic material on a substrate on which a wiring pattern is formed; Forming a first resist pattern on the mask member, etching the mask member using the first resist pattern to form a hard mask, and removing an etching residue with an organic stripping solution; Alternatively, a process of performing at least one wet process of a process of cleaning with a cleaning liquid, a process of forming a second resist pattern on the hard mask, and the first resist by dry etching using the second resist pattern as a mask. Forming a via hole penetrating the interlayer insulating film and the second interlayer insulating film; and removing the second resist pattern; Etching the second interlayer insulating film using a mask to form a wiring trench pattern; and embedding a wiring material in the via hole and the wiring trench pattern and polishing to form a wiring pattern at least In the manufacturing method of the semiconductor device having, before applying the resist to be the resist pattern or the antireflection film provided in the resist lower layer after the wet treatment, the substance contained in the organic stripping solution or the cleaning solution, A pretreatment is performed to remove a reaction inhibitor that inhibits the chemical reaction of the resist.

  In the present invention, at least one of the insulating film, the first interlayer insulating film, or the second interlayer insulating film may be formed of a low dielectric constant film.

  In the present invention, the reaction inhibiting substance may be a basic substance, and the basic substance may be configured to inhibit the catalytic action of an acid generated in the resist by exposure. It is preferable that the substance contains an amine.

  In the present invention, it is preferable to perform at least one of annealing, UV treatment, plasma treatment, or organic solvent treatment as the pretreatment, and as the pretreatment, UV treatment is performed after the annealing treatment. It can be set as the structure to perform.

  In the present invention, the annealing treatment may desorb the reaction-inhibiting substance that has permeated or adsorbed into the insulating film, the first interlayer insulating film, or the second interlayer insulating film by annealing at a predetermined temperature. The UV treatment is caused by oxygen or ozone activated by irradiation of UV light, and the reaction inhibition permeated or adsorbed on the insulating film, the first interlayer insulating film, or the second interlayer insulating film The plasma treatment comprises etching the reaction-inhibiting substance that has permeated or adsorbed to the insulating film or the interlayer insulating film with a plasma containing any one gas of oxygen, nitrogen, or ammonia. It can be configured by processing.

  In the present invention, the organic solvent treatment is preferably treatment using an organic solvent containing any one of polypyrene glycol monomethyl ether acetate, polypyrene glycol monomethyl ether, ethyl lactate, cyclohexanone, and methyl ethyl ketone.

  Further, in the present invention, the reaction inhibitor that contains an acidic substance in the organic solvent and penetrates or adsorbs to the insulating film, the first interlayer insulating film, or the second interlayer insulating film by the acidic substance. The composition to be neutralized or the organic solvent contains a weak basic substance, and permeates or adsorbs on the insulating film, the first interlayer insulating film, or the second interlayer insulating film by the weak basic substance. The reaction inhibitor may be replaced with a weak base.

  Further, the semiconductor device of the present invention is a semiconductor device formed by using the above manufacturing method, and at least one of annealing treatment or UV treatment is used as the pretreatment, and formed in the via hole or the wiring trench pattern. A region having a component ratio or density different from the inside is formed in the surface layer of the insulating film that contacts at least a part of the side wall of the wiring pattern.

  In the semiconductor device of the present invention, the interlayer film that contacts at least a part of at least one side wall of the via or the wiring made of a conductor is an insulating film containing Si and O as main elements, A contact surface layer having a lower nitrogen concentration than the inside of the insulating film or a low dielectric constant insulating film containing Si, O, and H as main elements, and the contact surface layer of the insulating film And a low dielectric constant insulating film having a region where the oxygen concentration is higher than that inside the insulating film and the hydrogen concentration is low, or a low dielectric constant insulating film containing Si, O, C and H as main elements. The contact surface layer has a region having a higher oxygen concentration and a lower carbon and hydrogen concentration than the inside of the insulating film.

  In the semiconductor device of the present invention, the barrier film or the etching stopper film that contacts at least a part of at least one side wall of the via or the wiring made of a conductor is an insulating film having Si, C, N, and H as main elements. The surface of the contact surface of the insulating film includes a region where the oxygen concentration is higher than the inside of the insulating film and the carbon, nitrogen and hydrogen concentrations are low, or Si, C and H are the main elements. The insulating film has a region having a higher oxygen concentration and a lower carbon and hydrogen concentration than the inside of the insulating film on the surface of the contact surface of the insulating film.

  In the semiconductor device of the present invention, the interlayer film in contact with at least a part of at least one side wall of the via or wiring made of a conductor is a low dielectric constant insulating film having Si, O and H as main elements, or Si, O , A low dielectric constant insulating film containing C and H as main elements, and a surface layer of the insulating film having a region having a higher film density than the inside of the insulating film, or a barrier film or an etching stopper The insulating film is an insulating film having Si, C, N, and H as main elements or an insulating film having Si, C, and H as main elements, and is formed on the surface of the contact surface of the insulating film from the inside of the insulating film. Has a region with a high film density.

In the semiconductor device of the present invention, the interlayer film that contacts at least a part of at least one side wall of the via or the wiring made of a conductor is a low dielectric constant insulating film containing Si, O, and H as main elements, The contact film surface layer of the insulating film has a region where the ratio of Si—O bonds is higher and the ratio of Si—H bonds is lower than the inside of the insulating film, or Si, O, C and H are mainly used. A low dielectric constant insulating film that is an element, and has a region in the surface layer of the insulating film that has a higher proportion of Si—O bonds and a lower proportion of Si—CH ₃ bonds than the inside of the insulating film. Or the barrier film or the etching stopper film is an insulating film containing Si, C, N and H as main elements or an insulating film containing Si, C and H as main elements, and is formed on the surface of the contact surface of the insulating film. , a low percentage of Si-CH ₃ bond than the inner insulating film And it has a region.

  In the present invention, the thickness of the region is preferably 30 nm or less in order to prevent an increase in dielectric constant, and ladder-type hydrogenated siloxane is used as the low dielectric constant insulating film containing Si, O, and H as main elements. L-Ox (registered trademark) can also be used as the ladder-type hydrogenated siloxane.

  As described above, in the present invention, as a pre-process for resist pattern formation, annealing, plasma processing, UV processing, organic solvent processing, and the like are performed, thereby remaining in the wafer, particularly in the low dielectric constant interlayer insulating film. It is possible to remove the amine and other reaction-inhibiting substances without fail, and to form a modified film with varying composition, density, and bonding state on the inner wall of the via hole or wiring trench pattern by annealing or UV treatment. It is possible to suppress the adhesion of reaction inhibiting substances in the atmosphere and the influence of reaction inhibiting substances in the insulating film. As a result, a resist pattern formation process, a via hole process, a wet process using an organic stripping solution or cleaning solution containing amine, such as a dual damascene process such as a via first process, a dual hard mask process, a trench first process, etc. In the process including the step of forming the resist pattern after the formation of the wiring trench pattern, the problem that the resolution of the resist pattern is degraded can be solved.

It is process sectional drawing which shows the procedure of the via first process which concerns on 1st Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on 1st Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on 1st Example of this invention. It is a figure which shows the structure of the gas analysis system for setting the conditions of the annealing process which concerns on 1st Example of this invention. It is a figure which shows the result analyzed by the gas analysis system. It shows the results of gas analysis for samples using the sample and a low dielectric constant film using SiO ₂ as an interlayer insulating film. Shows the results of SEM observation of sample using the sample and a low dielectric constant film using SiO ₂ as an interlayer insulating film. It is a figure which shows the difference of the influence of an amine component by the difference of a via pattern space | interval. It is a figure which shows the effect of the UV process which concerns on 1st Example of this invention. It is a figure which shows the effect of the organic-solvent process which concerns on 1st Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 2nd Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 2nd Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 2nd Example of this invention. It is process sectional drawing which shows the procedure of the dual hard mask process which concerns on the 3rd Example of this invention. It is process sectional drawing which shows the procedure of the dual hard mask process which concerns on the 3rd Example of this invention. It is process sectional drawing which shows the procedure of the dual hard mask process which concerns on the 3rd Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the via first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the trench first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the trench first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the trench first process which concerns on the 4th Example of this invention. It is process sectional drawing which shows the procedure of the conventional via first process. It is process sectional drawing which shows the procedure of the conventional via first process. It is process sectional drawing which shows the procedure of the conventional via first process. It is a figure which shows the method of extracting the substance which osmose | permeated the interlayer insulation film. It is a figure which shows an extraction result by the method of FIG. It is a figure explaining the mechanism in which the resolution of a resist pattern deteriorates.

  Conventionally, when the PR process is continuous with the wet treatment process such as the wet stripping process and the cleaning process as in the damascene process, when the antireflection film or resist is applied without pretreatment, the basic chemical substance soaked into the substrate Reaction inhibitors such as these penetrate the antireflection film and enter the resist. As a result, there has been a problem that the chemical reaction of the resist due to exposure is suppressed and the pattern is poorly resolved.

  In particular, this problem is often caused in a configuration in which a low dielectric constant insulating film is used instead of the conventional silicon oxide. This is because these low dielectric constant materials have a higher hole density than silicon oxide films, so that reaction-inhibiting substances are easily taken in, and they gradually ooze out when the antireflection film or resist is baked. Furthermore, in the via first process in which the via hole is processed first, the organic stripping solution used after the via hole etching penetrates deep into the substrate along the via hole.

  Therefore, in order to solve the above problem, the following experiment was conducted in order to identify a reaction inhibitor that causes the resolution of the resist pattern to deteriorate.

  First, a via-attached sample 17 (see FIG. 23B) in which a via hole 9 is formed by the above-described conventional method is prepared, and this via-attached sample 17 is placed in a quartz cell 16 as shown in FIG. Heated at a temperature of 300 ° C. And the substance which generate | occur | produced by heating after standing_to_cool was extracted in the pure water, and the component was confirmed by capillary electrophoresis. The result is shown in FIG. As can be seen from FIG. 27, when the analysis results of the standard sample shown in (a) and the via-attached sample 17 shown in (b) are compared, substances surrounded by broken lines (amine A and amine B, hereinafter collectively referred to as amine components) When electrophoresis was performed in a capillary, it was confirmed that it had a peak at the same movement time (horizontal axis). The component confirmed here is a component of an amine organic stripping solution. That is, it can be seen that the component of the amine-based organic stripping solution was adsorbed on the substrate surface.

  That is, in the organic stripping process performed after etching the via hole in the via first process, the etching residue is removed using an amine-based alkaline organic stripping solution. This organic stripping solution is used for the first interlayer insulating film 6 and the first insulating film. It penetrates into the two interlayer insulating film 4 and remains without being completely removed even in the subsequent cleaning process. In particular, a low dielectric constant organic / inorganic interlayer insulating film has a high microscopic void density, and a reaction inhibitor penetrates there. This is thought to be because the second antireflection film 2b and the second antireflection film 2b penetrate and penetrate into the resist during baking of the resist.

  The mechanism by which this amine component causes a poor resolution of the resist pattern will be described with reference to FIG. 28. First, an acid generator (onium hydrochloric acid generator, diazomethane acid generator, sulfonate ester system contained in a positive resist) An acid generator or the like) is photolyzed by exposure to generate an acid. Then, a protective group such as an acetal group that has a dissolution inhibiting effect on the developer is changed to a hydroxyl group by a deprotection reaction with an acid catalyst, and the polarity of the resist changes to be easily dissolved in the developer. When the amine component penetrates into the resist, a phenomenon called poisoning occurs in which the acid catalyst is deactivated by the neutralization reaction and the deprotection reaction is suppressed.

  As a result, it is considered that the solubility of the resist material in the developer is lowered, the resist resolution is deteriorated, or the resist embedded in the via hole is left behind, resulting in deterioration of the pattern resolution. In addition, the resist pattern resolution failure is also caused by the residue of hydrogen fluoride hydrofluoric acid used in the Cu back surface cleaning step before PR.

  The inventor of the present application confirmed that the poisoning is caused not only by the amine component but also by the concentration of elements (nitrogen, hydrogen, carbon, etc.) constituting the insulating film such as the interlayer insulating film and the etching stopper film. After forming a via hole or wiring trench pattern, the next resist pattern is formed with the interlayer insulating film or etching stopper film exposed on the inner wall of the via hole or wiring trench pattern. Acts on the resist and causes the same defects as amines.

  Therefore, in the present invention, as a pretreatment for applying a resist or an antireflection film, an annealing treatment, a plasma treatment, a UV treatment, an organic solvent treatment containing an acid or a weakly basic compound, etc. It effectively removes reaction-inhibiting substances such as hydrogen peroxide and hydrofluoric acid, and also performs annealing and UV treatment as pretreatment, so that the composition, density, and bonding can be applied to the surface of the insulating film exposed on the inner walls of via holes and wiring trench patterns. Forming a modified layer with a changed state to suppress the adhesion of reaction-inhibiting substances floating in the atmosphere or to suppress the influence of reaction-inhibiting substances in the insulating film, thereby suppressing the occurrence of poisoning and resist patterns Improves the resolution failure.

  The annealing treatment is performed at a temperature in the range of 150 to 450 ° C., preferably 200 to 450 ° C., so that the reaction-inhibiting substance can be reliably removed or a modified layer can be formed. In order to prevent the substrate from being oxidized, the annealing treatment is preferably performed under a reduced pressure condition in an inert gas atmosphere such as a nitrogen atmosphere, argon, or a hydrogen atmosphere.

  In addition, in order to remove the reaction-inhibiting substance adhering to the vicinity of the surface, washing with an organic solvent (thinner) before applying the antireflection film is also effective. Thinner treatment after application of the antireflection film is also effective in removing the reaction inhibitor that has soaked up to the upper surface of the antireflection film by baking after application of the antireflection film. In place of the above-described thinner treatment, washing with an organic solvent containing an acidic substance or an organic solvent containing a weakly basic substance is more effective in removing the alkaline reaction inhibitor. In order to neutralize the reaction inhibiting substance, it is also effective to contain an acid in the antireflection film itself.

The UV treatment is a method of removing reaction-inhibiting substances by oxygen and ozone activated by UV light irradiation, and the plasma treatment is exposed using plasma composed of gas such as oxygen, hydrogen, nitrogen and ammonia. This method involves physically etching the surface of the interlayer insulating film or oxidizing the surface. This UV treatment or plasma treatment not only removes reaction inhibitors but also modifies the exposed substrate surface. In addition, there is an effect of improving the wettability of the antireflection film or resist to be applied thereafter. For the UV treatment, it is desirable to use a high-pressure mercury lamp or excimer laser with a wavelength of 100 nm to 500 nm, and the irradiation intensity is desirably 50 mW / cm ² or more. In particular, in the UV treatment using oxygen, a modified layer in which the composition, density, and bonding state of the insulating film surface exposed on the inner wall of the via hole or wiring trench pattern can be changed, and reaction inhibitors and insulation in the atmosphere can be formed. The influence of the reaction inhibitor in the film can be suppressed.

  Hereinafter, in each embodiment, a specific procedure of a damascene process to which these pretreatments are applied will be described. In addition, although it is a well-known fact that an amine is contained in an organic stripping solution, this amine affects the resolution of the resist pattern, and nitrogen, hydrogen, carbon, etc. contained in the insulating film It is a novel fact obtained by the inventor's knowledge that the concentration of these elements functions as a reaction inhibitor similarly to amine.

  In order to describe the above-described embodiment of the present invention in more detail, examples of the present invention will be described with reference to the drawings. Both the amine contained in chemicals such as organic stripping solution and cleaning solution and the elemental composition of nitrogen, hydrogen, carbon, etc. contained in the insulating film affect the poisoning phenomenon, but only for the purpose of removing residual amine. The contents of treatment that can be used as pretreatment differ depending on the prevention of adhesion of amines in the atmosphere and the suppression of the influence of reaction-inhibiting substances in the insulating film. Therefore, for ease of explanation, in the first to third embodiments, when attention is paid to an effective removal method of residual amine, the fourth embodiment includes the prevention of adhesion of amine in the atmosphere and the insulating film. The case where attention is paid to the suppression of the influence of the reaction inhibitor is described. Further, in the following description, the dual damascene method in which vias and wirings per layer are formed at a time will be basically described, but it goes without saying that wiring layers can be stacked by repeating the process. .

[Example 1]
First, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 to FIG. 3 are process cross-sectional views showing the procedure of the via first process of this embodiment, which are divided for convenience of drawing. FIG. 4 is a diagram showing the configuration of a gas analysis system for setting conditions for annealing treatment, and FIG. 5 is a diagram showing the analysis results. 6 and 7 are diagrams showing differences between the case where SiO ₂ is used as an interlayer insulating film and the case where a low dielectric constant film is used, and FIG. 8 shows the influence of the amine component due to the difference in via pattern interval. It is a figure which shows a difference. Further, FIG. 9 is a diagram showing the effect of the UV treatment, and FIG. 10 is a diagram showing the effect of the organic solvent treatment.

Hereinafter, the via first process of the present embodiment will be described. First, as shown in FIG. 1A, after forming a lower layer wiring made of Cu or the like on the wiring substrate 8 by a known method, the first etching stop film 7 is formed by using a CVD method, a plasma CVD method or the like. The first interlayer insulating film 6 and the second etching stop film 5 are sequentially formed with a predetermined film thickness. On top of this, for example, SiO ₂ , an organic low dielectric constant film, an organic-containing silicon oxide film, an organic or inorganic porous film, L-Ox ^™ , and an insulating film containing fluorine are deposited on the second film. After forming the interlayer insulating film 4, the cap insulating film 3 is formed.

The first interlayer insulating film 6, the cap insulating film 3, the first etching stop film 7, and the second etching stop film 5 may be any combination of materials that can provide an etching selection ratio. SiO ₂ , SiC, SiN , SiON, SiCN, or the like. In addition, when SiO ₂ is used as the second interlayer insulating film 4, it is not necessary to form the cap insulating film 3, but a material other than SiO ₂ may cause problems in the wiring CMP process. It is necessary to form a cap insulating film 3.

  After that, an antireflection film 2a for suppressing reflection of exposure light is deposited on the cap insulating film 3 to about 50 nm, and then a chemically amplified resist for forming a via hole pattern is applied to about 600 nm, and KrF photo Lithographic exposure and development are performed to form the first resist pattern 1a.

  Next, as shown in FIG. 1B, the antireflection film 2a, the cap insulating film 3, the second interlayer insulating film 4, the second etching stop film 5, and the first interlayer insulating film 7 are sequentially formed by known dry etching. Etching is performed to form a via hole 9 penetrating them. Thereafter, the resist pattern 1a and the antireflection film 2a are stripped by oxygen plasma ashing and a wet process using an organic stripper, and the dry etching residue is removed.

  Here, in the conventional example, when the next resist pattern is formed, pre-processing is not performed, or as pre-processing, before applying the antireflection film 2b, dehydration baking or thinner pre-treatment at 150 to 250 ° C. for about 2 minutes is performed with a coating machine. Although only wet was performed, as described above, the amine component contained in the organic stripping solution penetrates into the first interlayer insulating film 6 and the second interlayer insulating film 4, particularly the interlayer insulating film made of a low dielectric constant film. There is a problem that the second antireflection film 2b or the baking after the resist application oozes out, penetrates through the second antireflection film 2b and enters the resist, resulting in deterioration of resolution. Therefore, this embodiment is characterized in that the following process is performed as a pre-process for forming the second resist pattern 1b.

  The pretreatment may be any method that can reliably remove reaction-inhibiting substances such as amine components that have penetrated into the interlayer insulating film, the etching stop film, and the cap insulating film. An annealing process, a plasma process for removing the amine component by etching the first interlayer insulating film 6 and the second interlayer insulating film 4 physically exposed on the inner wall of the via hole 9, oxygen or ozone activated by UV light, etc. A UV treatment for neutralizing an amine component with an oxidizing agent, an organic solvent treatment for neutralizing an amine with an organic solvent containing an acid or a weakly basic substance, or replacing it with a weak base, and the like can be considered.

  Each of these methods has its characteristics. For example, annealing is a process generally performed in a semiconductor process and easy to introduce. However, it takes a long time for the heat treatment, and the atmosphere is removed when the wafer is taken out from the annealing furnace. There is a possibility of reabsorbing the amine component present therein. In addition, plasma treatment, UV treatment, and organic solvent treatment have a short treatment time, and plasma treatment and UV treatment can further improve the wettability of the antireflection film and resist applied after the substrate surface is further modified. Accordingly, which process is selected is preferably determined appropriately in consideration of the required device performance, manufacturing man-hours, equipment used, and the like, and these can be used alone or in combination. Among them, the combination of performing the UV treatment after the annealing treatment and before applying the antireflection film is particularly effective.

  Here, it describes below about the case where annealing treatment is performed as pre-processing. When setting conditions such as annealing temperature and annealing time for annealing treatment, the effect of removing amine components increases as annealing is performed at a high temperature for a long time. On the other hand, long-term high-temperature annealing increases the number of manufacturing steps. In addition, diffusion of Cu, which is a wiring material, may be caused and the device characteristics may be deteriorated.

  Therefore, in order to set a preferable annealing temperature and time, samples having different annealing conditions are prepared, and a mass analysis method (TD-API-MS method) is used from a wafer by using a gas analysis system as shown in FIG. The desorbed gas component was analyzed. Specifically, a quartz cell for gas collection is placed on a wafer with vias and placed in a heating furnace, and a sample is heated by an infrared heater while supplying purified high-purity Ar gas at a flow rate adjusted by a mass flow controller. Then, the gas desorbed from the wafer was introduced into the API-MS apparatus and analyzed. The result is shown in FIG.

  FIG. 5 (a) shows the temperature rise curve and the detected intensity of the amine component when the sample is gradually heated from room temperature to 400 ° C. (about 10 ° C./min), gradually with increasing temperature. It can be seen that the amine component is eliminated. On the other hand, FIG. 5B shows a case where the temperature is raised from room temperature to 400 ° C. in a short time and kept at 400 ° C., and the amine component is almost eliminated within about 20 minutes from the temperature rise, and thereafter You can see that it is no longer detected.

  Thus, the amine component can be reliably removed by raising the temperature to the temperature at which the amine evaporates (400 ° C.), and in particular, by rapidly raising the temperature, the amine component can be removed in a short time of about 20 minutes. It can be effectively removed. And even if it hold | maintains at 400 degreeC, since an amine component is not detected after that, it turns out that an annealing process has a removal effect not only on the surface but the amine component which osmose | permeated the inside of the interlayer insulation film.

  Note that the annealing temperature is not limited to 400 ° C., and even if the temperature is 400 ° C. or lower, the amine component can be removed over time. According to the experiments of the present inventor, the temperature ranges from 150 to 450 ° C. Is confirmed to be preferable. Furthermore, in order to prevent the amine component from being desorbed by baking the antireflection film or resist, it is more preferable to set the annealing temperature to be 200 ° C. or higher, which is the baking temperature. In addition, in order to prevent the substrate from being oxidized, it is desirable that the annealing process be performed in a nitrogen atmosphere, an inert gas atmosphere such as argon, or a hydrogen atmosphere under reduced pressure.

  After removing the amine component in the first interlayer insulating film 6 and the second interlayer insulating film 4 by the annealing process, as shown in FIG. 1C, the second antireflection film 2b is applied to about 50 nm and baked. . At that time, the antireflection film 2 b is partially embedded also in the via hole 9.

  Next, as shown in FIG. 2A, a chemically amplified resist is applied on the antireflection film 2b to a thickness of about 600 nm, baked, and then exposed and developed by KrF photolithography to form a wiring trench pattern. A second resist pattern 1b is formed (see FIG. 2B). At that time, in the conventional manufacturing method, the amine component in the organic stripping solution used for removing the residue of via-hole etching penetrates into the interlayer insulating film and melts into the resist when the antireflection film or resist is baked. However, in this embodiment, since the amine component is sufficiently removed by performing the annealing process before the application of the antireflection film 2b, the resolution of the resist pattern can be kept good.

  Thereafter, as shown in FIG. 2C, the second antireflection film 2b is removed by a dry etching method, and subsequently, as shown in FIG. 3A, the second etching stop film 5 is used as an etching stopper. The insulating film 3 and the second interlayer insulating film 4 are etched to form a wiring trench pattern 10.

  Next, as shown in FIG. 3B, the second resist pattern 1b and the second antireflection film 2b are stripped by oxygen plasma ashing and a wet process using an organic stripping solution, and the dry etching residue is removed. To do. Then, after removing the first etching stop film 7, a wiring material 11 such as Cu is embedded in the completed wiring trench pattern 10, and the surface is planarized by polishing using a CMP method, thereby completing a dual damascene structure. (See FIG. 3C).

  When the wafer with vias thus formed was observed with an SEM, there was no pattern resolution defect, and it was confirmed that the annealing treatment of this example was effective for amine removal. The effect of this embodiment is more effective when a low dielectric constant film is used as the second interlayer insulating film 4. In order to confirm the difference, an API-MS analysis of a sample using a low dielectric constant film as the second interlayer insulating film 4 and a sample using a silicon oxide film was performed using the gas analysis system shown in FIG. It was. The analysis result is shown in FIG. 6, and the result of SEM observation is shown in FIG.

FIG. 6A shows the detected amounts of amine A (left side) and amine B (right side) when a silicon oxide film is used as the second interlayer insulating film 4. The amine A is 6.1 ng / cm. ² and amine B are not so high as 63 ng / cm ² , but when a low dielectric constant film is used as the second interlayer insulating film 4, amine A is 44 ng / cm ² as shown in FIG. Amine B is high together with 220 ng / cm ² , and the influence of amine is large in the process using a low dielectric constant film, indicating that the pretreatment of this example is necessary.

  When this is confirmed by an SEM photograph, as shown in FIG. 7A, when a silicon oxide film is used as the second interlayer insulating film 4, the resist pattern collapses at the tip of the wiring trench pattern surrounded by a white circle. It can be seen that the via hole 9 indicated by the black circle inside is not formed. On the other hand, as shown in FIG. 7B, when a low dielectric constant film is used as the second interlayer insulating film 4, most of the via holes 9 that should be originally formed are missing. Then, it turns out that the influence of an amine component is large.

  Such a defect appears more conspicuously in a portion where the patterns are isolated than in a portion where the wiring patterns are dense. That is, as shown in FIG. 8, since the width of the interlayer insulating film between the patterns is narrow in the portion where the patterns are dense (the right side in the figure), the amount of the amine component melted into the interlayer insulating film is small. Although the collapse of the pattern is small, it is considered that the pattern is easily collapsed in the portion where the pattern is isolated (the left side in the figure) because the amine component exudes from the surrounding interlayer insulating film having a large area. Therefore, the annealing process of this embodiment is more important in a semiconductor device having a configuration including many isolated patterns.

  In the above description, the case where the annealing treatment is performed as a method for removing the amine is described. However, as described above, the plasma treatment, the UV treatment, the organic solvent treatment, etc. may be performed as described above, and the annealing treatment may be performed. In addition to these, these treatments may be combined, such as plasma treatment, UV treatment, or organic solvent treatment, and the treatments can be properly used according to the device form.

In order to confirm the effect of the UV treatment, the sample subjected to UV treatment and the untreated sample were both heat-treated with the gas analysis system shown in FIG. 4 and analyzed for desorbed gas. The result is shown in FIG. FIG. 9A shows the result of measuring the intensity of the desorbed gas released when the sample not subjected to UV treatment is heated, and FIG. 9B shows the result of the sample subjected to UV treatment. Show. Comparing the two, 200 ° C. or less (Application of anti-reflection film, baking temperature) greatly reduced the amount of amine ingredient released in the following low-temperature region (hatched portion) and 1.8 ng / cm ² from 10 ng / cm ² It is shown that the amine is effectively removed by the UV treatment.

  For removing the amine component adhering to the vicinity of the surface, washing with an organic solvent such as polypyrene glycol monomethyl ether acetate, polypyrene glycol monomethyl ether, ethyl lactate, cyclohexanone, methyl ethyl ketone, etc. is also effective before applying the antireflection film 2b. is there. Further, the removal of the amine component that has soaked up to the upper surface of the antireflection film 2b by baking after application of the antireflection film 2b is also effective in treating the organic solvent after application of the antireflection film 2b. By using an organic solvent containing an organic acid such as an organic carboxylic acid or acetic acid or an inorganic acid such as hydrochloric acid for the organic solvent treatment described above, the strongly basic amine component is neutralized and the effect can be further enhanced. Further, by washing with an organic solvent containing a weakly basic substance, a strongly basic amine component can be replaced with a weak base, and the function of the amine component can also be suppressed. Furthermore, in order to neutralize the amine component, it is also effective to contain an acid in the antireflection film itself.

  In order to confirm the effects of the organic solvent treatment and the organic solvent treatment containing an acidic substance, a sample without pretreatment and a sample treated with each organic solvent were prepared, and the resist was confirmed with an SEM photograph. The number of missing portions, that is, the number of pattern defects was measured. The result is shown in FIG. From FIG. 10, in the sample without pretreatment shown in (a), the resist remaining portion of the line indicated by the arrow (the whole of the elliptical wiring trench pattern is black) is five from the end, In the sample of (b) subjected to the organic solvent (thinner) treatment, the number decreased to four, and in the sample (c) subjected to the treatment with the acidic organic solvent, the number of amine components decreased to one. It was confirmed that it could be removed effectively.

  In the above description, the amine component has been described as an example of a reaction inhibitor that degrades resist resolution. However, resolution degradation is also caused by hydrogen peroxide hydrofluoric acid residue used in the Cu back surface cleaning process before PR. cause. This hydrogen peroxide hydrofluoric acid residue can also be effectively removed by performing annealing treatment, plasma treatment, UV treatment, organic solvent treatment or a combination thereof.

[Example 2]
Next, a semiconductor device and its manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. FIGS. 11 to 13 are process cross-sectional views showing the procedure of the via first process according to the second embodiment, which are divided for convenience of drawing. This embodiment is characterized in that the antireflection film is completely filled in the via hole, and the structure and manufacturing method of the other parts are the same as those in the first embodiment.

  First, as shown in FIG. 11 (a), a lower layer wiring made of Cu or the like is formed on the wiring substrate 8 by a known method, as in the first embodiment, and then a CVD method or a plasma CVD method is used. The first etching stop film 7, the first interlayer insulating film 6, the second etching stop film 5, the second interlayer insulating film 4, and the cap insulating film 3 are sequentially formed. After that, on the cap insulating film 3, the antireflection film 2a is applied by about 50 nm and the chemically amplified resist is applied by about 600 nm, and exposure and development are performed by KrF photolithography to form the first resist pattern 1a.

  Next, as shown in FIG. 11B, the antireflection film 2a, the cap insulating film 3, the second interlayer insulating film 4, the second etching stop film 5, and the first interlayer insulating film 7 are sequentially formed by known dry etching. Etching is performed to form a via hole 9 penetrating them. Thereafter, the resist pattern 1a and the antireflection film 2a are stripped by oxygen plasma ashing and a wet process using an organic stripper, and the dry etching residue is removed.

  Next, as in the first embodiment described above, as a pre-process for forming the second resist pattern, an annealing process under a predetermined temperature and time condition, or the inner wall of the via hole 9 is physically etched to remove the amine component. Plasma treatment, UV treatment that neutralizes amine components with oxidants such as oxygen or ozone activated by UV light, or neutralization or substitution of weakly alkaline amines with organic solvents containing acids or weakly basic substances Any organic solvent treatment or a combination thereof is performed.

  After the amine component in the interlayer insulating film is removed by the pretreatment, the second antireflection film 2b is applied to about 50 nm and baked as shown in FIG. At this time, in this embodiment, in order to improve the pattern resolution by making the thickness of the resist coated on the second antireflection film 2b uniform and to facilitate the removal of the second resist pattern 1b, the via hole 9 is completely removed. The antireflection film 2b is embedded in

  Next, as shown in FIG. 12A, a chemically amplified resist is applied on the antireflection film 2b to a thickness of about 600 nm, baked, and then exposed and developed by KrF photolithography to form a wiring trench pattern. A second resist pattern 1b is formed (see FIG. 12B). At that time, similarly to the first embodiment, the amine component is sufficiently removed by applying a predetermined pretreatment before the application of the antireflection film 2b, so that the resolution of the resist pattern can be kept good.

  Next, in the first embodiment, the second antireflection film 2b, the cap insulating film 3, and the second interlayer insulating film 4 are dry-etched. However, in this embodiment, the second antireflection film is formed inside the via hole 9. Since the film 2b is filled and the etching rate of the second antireflection film 2b is slower than that of the cap insulating film 3 and the second interlayer insulating film 4, as shown in FIG. Only the film 2b is etched down to the wiring layer portion by anisotropic etch back using oxygen plasma. Subsequently, as shown in FIG. 13A, the cover insulating film 3 and the second interlayer insulating film 4 are etched using the second etching stop film 5 as an etching stopper to form a wiring trench pattern 10.

  Next, as shown in FIG. 13B, the second resist pattern 1b and the second antireflection film 2b are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed. Remove. Then, after removing the first etching stop film 7, a wiring material 11 such as Cu is embedded in the completed wiring trench pattern 10, and the surface is planarized by polishing using a CMP method, thereby completing a dual damascene structure. (See FIG. 13C).

  When the wafer with vias thus formed was confirmed by SEM photography, it was confirmed that there was no pattern resolution defect and that the annealing treatment of this example was effective for amine removal. In this embodiment, since the second antireflection film 2b is filled in the via hole 9, there is hardly a problem that the resist remains on the via hole 9, and the second antireflection film 2b passes from the inner wall of the via hole 9 through the second antireflection film 2b. Since the path to the resist is long, there is an advantage that even if an amine component remains in the interlayer insulating film, it is hardly affected by the amine component.

[Example 3]
Next, a semiconductor device and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. 14 to 16 are process sectional views showing the procedure of the dual hard mask process according to the third embodiment, which are divided for convenience of drawing. This embodiment is characterized in that a wiring trench pattern is formed using a hard mask.

  First, as shown in FIG. 14A, similarly to the first and second embodiments described above, a lower layer wiring made of Cu or the like is formed on the wiring substrate 8 by a known method, and then a CVD method, A first etching stop film 7, a first interlayer insulating film 6, a second etching stop film 5, and a second interlayer insulating film 4 are sequentially formed using a plasma CVD method or the like. Next, in this embodiment, a hard mask film lower portion 13 and a hard mask film 12 which are etching masks of the wiring trench pattern are deposited thereon with a predetermined material and film thickness. After that, on the hard mask film 12, the antireflection film 2a is applied to about 50 nm and the chemically amplified resist is applied to about 600 nm, and exposure and development are performed by KrF photolithography to form the first resist pattern 1a.

  Next, as shown in FIG. 14B, the hard mask film 12 is etched using the first resist pattern 1a by well-known dry etching to form an opening for etching the wiring trench pattern. Thereafter, the resist pattern 1a and the antireflection film 2a are stripped by oxygen plasma ashing and a wet process using an organic stripper, and the dry etching residue is removed.

  Next, as in the first and second embodiments described above, as a pretreatment for forming the second resist pattern, annealing treatment, plasma treatment, UV treatment, organic solvent treatment, or a combination thereof is performed. Do.

  Next, as shown in FIG. 14C, the second antireflection film 2b is applied to about 50 nm and the chemically amplified resist is applied to about 600 nm, baked, and then exposed and developed by KrF photolithography for via hole formation. The second resist pattern 1b is formed. At that time, as in the first and second embodiments, the amine component is sufficiently removed by applying a predetermined pretreatment before the application of the antireflection film 2b, so that the resolution of the resist pattern is kept good. Can do.

  Next, as shown in FIG. 15A, the second antireflection film 2b, the hard mask film lower portion 13, the second interlayer insulating film 4, and the second etching are performed by known dry etching using the second resist pattern 2b as a mask. The stop film 5 and the first interlayer insulating film 6 are etched, and a via hole 9 penetrating them is formed.

  Thereafter, as shown in FIG. 15B, the second resist pattern 1b and the second antireflection film 2b are peeled off by oxygen plasma ashing and wet treatment using an organic stripping solution, and the dry etching residue is removed. To do.

  Next, as shown in FIG. 15C, the hard mask film lower portion 13 and the second interlayer insulating film 4 are etched by using a known dry etching method using the hard mask film 12 as a mask to form the wiring trench pattern 10. Form. Thereafter, the second etching stop film 7 is removed, a wiring material 11 such as Cu is embedded in the completed wiring trench pattern 10, and the surface is planarized by polishing using a CMP method, thereby completing a dual damascene structure. (See FIG. 16).

  When the interlayer insulating film is entirely formed of an organic film, the second resist pattern 1b is used in the step of FIG. 15A to form the second antireflection film 2b, the hard mask film lower portion 13, and the second interlayer insulating film. The film 4 and the second etching stop film 5 are etched, and the hard mask film lower portion 13 and the second interlayer insulating film 4 are etched using the hard mask film 12 in the step of FIG. At the same time, the first interlayer insulating film 6 may be etched to form a via hole 9 that penetrates to the first etching stop film 7.

  When the wafer with vias thus formed was confirmed by SEM photography, there was no pattern resolution defect as in the first and second embodiments, and the pretreatment of this embodiment was effective for amine removal. It was confirmed. In this embodiment, since the via hole 9 is not formed when the second resist pattern 1b is formed, the unevenness of the substrate is small, the accuracy of the second resist pattern can be improved, and a hard mask is used. Since etching is performed, there is an advantage that the processing of the wiring trench pattern becomes easy. In the first to third embodiments, the via first process has been described. However, it is obvious that the trench first process can be similarly applied.

[Example 4]
Next, a semiconductor device and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS. FIGS. 17 to 19 are process cross-sectional views illustrating the procedure of the via first process according to the fourth embodiment, and FIGS. 20 to 22 are cross-sectional process diagrams illustrating the procedure of the trench first process. In this embodiment, UV treatment, annealing treatment, or a combination thereof is performed as pretreatment to change the film quality (composition, density, bonding state, etc.) of the insulating film surface exposed on the inner wall of the via hole or wiring trench pattern. It is characterized by this.

First, as shown in FIG. 17A, after a lower layer wiring 18 made of Cu or the like is formed on the wiring substrate 8 by a known damascene process, a CVD method, a plasma CVD method or the like is used as shown in FIG. As the first etching stop film 7, for example, a SiCN film is deposited to a thickness of about 30 to 100 nm, and the first interlayer insulating film 6, the second etching stop film 5, and the second interlayer insulating film 4 are deposited thereon. Are sequentially deposited. Here, the second etching stop film 5 used as the wiring groove stopper film is, for example, SiC or SiCN, and may not be provided when the wiring formation by the etching process can be stably formed without variation. The first interlayer insulating film 6 and the second interlayer insulating film 4 are, for example, SiO ₂ , L-Ox ^™ (ladder oxide), which is an inorganic low dielectric constant film, and SiOC based film. In the upper layer, SiO ₂ may be formed as a cap insulating film 3 as shown in the figure.

  Next, as shown in FIG. 17C, a first resist pattern 1a is formed by a known lithography technique, and a cap insulating film 3, a second interlayer insulating film 4, a second etching stop film are formed by a known etching technique. 5. The first interlayer insulating film 7 is sequentially etched to form a via hole 9 penetrating therethrough.

  Next, the first resist pattern 1a used for etching the via hole 9 is removed using oxygen ashing or plasma of a nitrogen-hydrogen mixed gas or a helium-hydrogen mixed gas. Thereafter, cleaning is performed with an amine-based organic stripping solution. With this, particularly in the case of a low dielectric constant film, the stripping solution is adsorbed and taken into the side wall of the via hole 9. Here, in the first to third embodiments, pretreatment such as annealing, plasma treatment, UV treatment, and organic solvent treatment is performed. In this embodiment, the surface of the insulating film exposed on the inner wall of the via hole 9 is used. In order to modify the above, as shown in FIG. 18A, irradiation with UV light, annealing at about 200 to 450 ° C., or a combination thereof is performed.

  As a result, the stripping solution remaining in the via hole 9 and the solution taken into the side wall of the interlayer insulating film are removed, and the side wall portion of the via hole 9 changes in composition, becomes dense, or changes in the bonding state (here, the change in the insulating film). However, the boundary between the reformed film 19 and the insulating film therein is not always clear, and the effective film thickness of the reformed film 19 is approximately 30 nm or less. it is conceivable that.). This change is different from the state in which the film is cured and deformed by resist peeling such as oxygen ashing. The characteristics and effects of the modified film 19 will be described in detail later.

  Next, as shown in FIG. 18B, a second resist pattern 1b is formed by a known lithography technique. At this time, an organic antireflection film may be formed under the resist. The antireflection film at this time is not completely buried in the via hole 9 but is preferably lower than the height of the wiring, that is, the second etching stop film 5. Thereafter, the cap insulating film 3 and the second interlayer insulating film 4 are etched using a known etching technique to form a wiring trench pattern 10.

  Here, in the pretreatment of this embodiment, the modified film 19 having a high film density is formed on the surface of the insulating film on the inner wall of the via hole 9, so that the reaction inhibitory substance such as amine floating in the atmosphere adheres. Therefore, the occurrence of poisoning can be surely prevented. Further, the inventor of the present application has confirmed that elements such as nitrogen, hydrogen, and carbon contained in the insulating film in addition to the amine function as a reaction inhibiting substance. Since No. 19 has a lower concentration of nitrogen, hydrogen, carbon, etc. than the inner insulating film, poisoning due to the above elements can also be effectively suppressed.

  Next, as shown in FIG. 18C, after removing the second resist pattern 1b used for wiring trench etching, the first etching stop film 7 at the bottom of the via hole 9 is removed by etching. At this time, the exposed second etching stop film 5 is simultaneously etched and removed. Thereafter, a wiring material 11 made of, for example, a barrier film made of Ta, TaN, Ti, TiN or a laminated structure thereof and a conductive film made of Cu or the like is buried in the wiring trench pattern 10 and the via hole 9. Then, as shown in FIG. 19, the wiring material 11 which becomes an unnecessary part as wiring is removed by CMP to form a dual damascene structure wiring.

  As described above, by performing UV treatment, annealing treatment, or a combination treatment after the via hole 9 is formed, the amine contained in the organic stripping solution and the cleaning solution can be surely removed, and the composition, density, bonding state on the inner wall of the via hole 9 can be removed. By forming the modified film 19 having changed, adhesion of amine floating in the atmosphere can be suppressed, and further, the influence of the reaction inhibiting substance in the insulating film can be suppressed.

  Next, a process when the pretreatment of the present embodiment is applied to a trench first process will be described in detail with reference to FIGS.

  First, the first etching stop film 7, the first interlayer insulating film 6, the second etching stop film 5, and the second interlayer are formed on the wiring substrate 8 on which the lower layer wiring 18 is formed by the same manufacturing method as the above-described via first process. An insulating film 4 and a cap insulating film 3 are sequentially formed (see FIGS. 20A and 20B).

  Next, as shown in FIG. 20C, after forming a first resist pattern 1a using a known lithography technique, a region to be a wiring is etched using a known etching technique, and a wiring trench pattern 10 is formed. Form.

  Next, as shown in FIG. 21A, after removing the first resist pattern 1a used for wiring trench etching by oxygen ashing, organic stripping solution, etc., UV treatment or 200 to 450 ° C. is performed in the same manner as the above process. A modified film 19 is formed on the inner wall of the wiring trench pattern 10 by performing a degree of annealing treatment or a combination treatment thereof. This treatment can prevent resist poisoning when forming a via hole resist pattern in the next step.

  Next, as shown in FIG. 21B, a second resist pattern 1b is formed using a known lithography technique, and a via hole 9 is formed using a known etching technique. Thereafter, wiring is formed by a manufacturing method similar to the via first process (see FIGS. 21C and 22).

  As described above, also in the trench first process, the amine contained in the organic stripping solution or the cleaning solution can be surely removed by performing the UV treatment or the annealing treatment or the combination treatment after the formation of the wiring trench pattern 10, and the wiring trench. By forming the modified film 19 having a changed composition, density, and bonding state on the inner wall of the pattern 10, it is possible to suppress the adhesion of amine floating in the atmosphere, and further, the influence of the reaction inhibitor in the insulating film Can be suppressed. Hereinafter, characteristics and effects of the modified film 19 when various materials are used for the insulating film will be described.

<SiO ₂ film>
When an SiO ₂ film is used as the interlayer insulating film of the via hole 9 in the via first process, the nitrogen concentration in the side wall portion of the SiO ₂ film after performing this process flow (UV treatment and / or annealing treatment) and relatively lower compared to the ₂ film, as a result, the desorption amount of nitrogen from the film in the subsequent step is reduced. There is a clear correlation between the nitrogen desorption amount and the via poisoning. The larger the nitrogen desorption amount, the more the via poisoning defects. From this, it can be seen that the poisoning can be effectively suppressed by the pretreatment of this embodiment when the SiO ₂ film is used as the interlayer insulating film.

<L-Ox ^TM >
In addition, when a ladder oxide film that is one of ladder-type siloxane siloxane is used for the interlayer insulating film in the wiring portion in the trench first process, the process flow after performing this process flow (UV treatment or / and annealing treatment) The film density of the side wall portion of the ladder oxide film is relatively larger than the inner side, so that the amount of amine that is a part of the chemical solution used in the organic peeling process is taken into the ladder oxide film. On the other hand, in the conventional process, since the film density on the side wall of the ladder oxide film is not increased, the amount of amine taken up is considerably increased.

  The amine uptake can be easily measured by TDS (Thermal Desorption Spectroscopy) prior to dual damascene metal embedding by degassing nitrogen or degassing with a nitrogen bond. From this measurement, it has been confirmed that the greater the amine uptake amount, the greater the resist poisoning defects. In addition, since the film density gradually increases due to the extension of the UV treatment time or the like, the amount of amine incorporated into the ladder oxide film is further reduced, and defects can be further reduced.

  Further, the composition of the side wall portion of the ladder oxide film when this process flow (UV treatment or / and annealing treatment) is performed has a relatively high oxygen concentration and a relatively low hydrogen concentration than the inside.

  Further, regarding the bonding state, the ratio of Si—O bonds is relatively higher in the side wall portion of the ladder oxide film than the inner side, and the ratio of Si—H bonds is low. The confirmation of the bonding state can be easily measured by the FTIR method if the solid film is pretreated in this process. Further, even in an actual structure, it can be confirmed by cross-sectional SEM observation after the reef etching using the buffered HF of the cross-sectional cleaved sample. That is, when the side wall of the ladder oxide film is in a bonded state as described above, the etching rate is remarkably lowered and the film remains, whereas the ladder oxide film other than the side wall portion has a considerably high etching rate. Thus, it is possible to easily confirm the coupling state. As a result of confirmation by the above method, the film thickness of the modified film 19 was 30 nm or less, and it did not increase even when the UV treatment or annealing treatment time was increased. Further, it was confirmed that the oxygen concentration was highest on the side wall surface and gradually changed toward the inner side. The bonding state and the film density have a correlation, and the amount of amine incorporated into the ladder oxide film tends to decrease as the Si-O bond ratio increases and the Si-H bond ratio decreases. From the above results, it can be seen that the poisoning can be effectively suppressed by the pretreatment of this embodiment even when the ladder oxide film is used as the correlation insulating film.

  The element concentration, film density, and bonding state of the film from the outermost surface of the insulating film to the inside of the film gradually change from the above-mentioned film quality to the inside, and the film quality of the portion excluding the side wall (bulk It approaches the quality of the interlayer film). The sidewall surface layer has a higher dielectric constant than the bulk as the film quality, and when this layer is thick, the performance of the device deteriorates. When a structure in which the film quality changes sharply is used, the film thickness of the high dielectric constant layer must be increased. By creating a structure in which the film quality gradually changes from the side wall to the inside, the effective dielectric constant does not increase compared to a structure in which the film quality changes sharply, and sufficient device performance is obtained.

<SiOC film>
Next, when a SiOC film is used as a part of the via interlayer insulating film in the via first process, the film density of the sidewall portion of the SiOC film after performing this process flow (UV treatment or / and annealing treatment) is from the inside. It is relatively large, and the amount of amine incorporated into the SiOC film is decreasing. On the other hand, in the conventional process, since the film density of the sidewall of the SiOC film is not increased, the amount of amine taken up is considerably increased.

  In addition, the composition of the sidewall portion of the SiOC film when this process flow (UV treatment or / and annealing treatment) is performed is characterized by a relatively high oxygen concentration and a relatively low carbon and hydrogen concentration than the inside. In addition, as the tendency becomes more prominent, the amount of amine incorporated into the SiOC film decreases.

Further, regarding the bonding state, the ratio of Si—O bonds is relatively higher in the side wall portion of the SiOC film than the inner side, and the ratio of Si—CH ₃ bonds is low. The bonding state and the film density are in a correlation, and the amount of amine incorporated into the SiOC film tends to decrease as the Si—CH ₃ bond ratio decreases. From the above results, it can be seen that the poisoning can be effectively suppressed by the pretreatment of this embodiment even when the SiOC film is used as the interlayer insulating film.

  The element concentration, film density, and bonding state of the film from the outermost surface of the insulating film to the inside of the film gradually change from the above-mentioned film quality to the inside, and the film quality of the portion excluding the side wall (bulk It approaches the quality of the interlayer film). The sidewall surface layer has a higher dielectric constant than the bulk as the film quality, and when this layer is thick, the performance of the device deteriorates. When a structure in which the film quality changes sharply is used, the film thickness of the high dielectric constant layer must be increased. By creating a structure in which the film quality gradually changes from the side wall to the inside, the effective dielectric constant does not increase compared to a structure in which the film quality changes sharply, and sufficient device performance is obtained.

<SiCN film>
Further, when a SiCN film is used as a barrier film or an etching stop film, the film density of the side wall portion of the SiCN film after performing this process flow (UV treatment or / and annealing treatment) becomes relatively larger than the inside. Thus, the amount of amine incorporated into the SiCN film is decreasing. On the other hand, in the conventional process, since the film density on the sidewall of the SiCN film is not increased, the amount of amine taken up is considerably increased.

  In addition, the composition of the sidewall portion of the SiCN film when this process flow (UV treatment or / and annealing treatment) is performed has a relatively high oxygen concentration and a relatively low carbon, nitrogen and hydrogen concentration than the inner portion. As the tendency becomes more prominent, the amount of nitrogen desorbed from the film surface decreases.

Further, regarding the bonding state, the ratio of Si—CH ₃ bonding is relatively higher in the side wall portion of the SiCN film than in the inner side. The bonding state and the film density have a correlation, and the amount of amine incorporated into the SiCN film tends to decrease as the Si—CH ₃ bond ratio decreases. From the above results, it can be seen that the poisoning can be effectively suppressed by the pretreatment of this embodiment even when the SiCN film is used as the barrier film or the etching stop film.

  The element concentration, film density, and bonding state of the film from the outermost surface of the insulating film to the inside of the film gradually change from the above-mentioned film quality to the inside, and the film quality of the portion excluding the side wall (bulk It approaches the quality of the interlayer film). The sidewall surface layer has a higher dielectric constant than the bulk as the film quality, and when this layer is thick, the performance of the device deteriorates. When a structure in which the film quality changes sharply is used, the film thickness of the high dielectric constant layer must be increased. By creating a structure in which the film quality gradually changes from the side wall to the inside, the effective dielectric constant does not increase compared to a structure in which the film quality changes sharply, and sufficient device performance is obtained.

<SiC film>
Further, when an SiC film is used as the barrier film and the etching stop film, the film density of the side wall portion of the SiC film after performing this process flow (UV treatment and / or annealing treatment) becomes relatively larger than the inside. Thus, the amount of amine incorporated into the SiC film is decreasing. On the other hand, in the conventional process, since the film density of the side wall of the SiC film is not increased, the amount of amine taken up is considerably increased.

Furthermore, the composition of the sidewall portion of the SiC film when performing this process flow (UV treatment + annealing treatment) is characterized in that the oxygen concentration is relatively higher than the inside, and the carbon and hydrogen concentrations are relatively low. As the tendency becomes more remarkable, the incorporation of amine into the SiC film decreases. The bonding state and the film density have a correlation, and the amount of amine incorporated into the SiC film tends to decrease as the Si—CH ₃ bond ratio decreases. From the above results, it can be seen that poisoning can be effectively suppressed by the pretreatment of this embodiment even when an SiC film is used as the barrier film and the etching stop film.

  The element concentration, film density, and bonding state of the film from the outermost surface of the insulating film to the inside of the film gradually change from the above-mentioned film quality to the inside, and the film quality of the portion excluding the side wall (bulk It approaches the quality of the interlayer film). The sidewall surface layer has a higher dielectric constant than the bulk as the film quality, and when this layer is thick, the performance of the device deteriorates. When a structure in which the film quality changes sharply is used, the film thickness of the high dielectric constant layer must be increased. By creating a structure in which the film quality gradually changes from the side wall to the inside, the effective dielectric constant does not increase compared to a structure in which the film quality changes sharply, and sufficient device performance is obtained.

  In each of the above-described embodiments, the pretreatments such as annealing, plasma treatment, UV treatment, and organic solvent treatment of the present invention were applied to the dual damascene via first process, dual hard mask process, and trench first process. Although the present invention has been described, the present invention is not limited to the above-described embodiments. The resist pattern is followed by wet treatment using an organic stripping solution or cleaning solution containing a basic substance such as an amine component or hydrogen fluoride hydrofluoric acid. The present invention can be applied to any semiconductor process including a step of forming and a step of subsequently forming a resist pattern after patterning an insulating film.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention have the following effects.

  The first effect of the present invention is that a resist pattern is formed following a wet process using an organic stripping solution or a cleaning solution containing an amine such as a dual damascene process such as a via first process, a dual hard mask process, or a trench first process. In the process including the step of performing resist pattern formation and the step of performing resist pattern formation subsequent to via hole and wiring trench pattern formation, the problem that the resolution of the resist pattern deteriorates can be solved.

  The reason for this is that the amine remaining in the wafer, particularly in the low dielectric constant interlayer insulating film, by performing an annealing process, a plasma process, a UV process, an organic solvent process, etc. as a pre-process of resist pattern formation. This is because reaction inhibitory substances such as the above can be removed reliably. Further, by performing UV treatment and annealing treatment as a pretreatment, a modified film having a changed film quality (composition, density, bonding state, etc.) may be formed on the surface of the insulating film exposed on the inner wall of the via hole or wiring trench pattern. This is because the adhesion of amines in the atmosphere can be suppressed, and the influence of a predetermined element in the insulating film serving as a reaction inhibitor can be suppressed.

  The second effect of the present invention is that it is possible to facilitate the application of an antireflection film and improve the processing accuracy of the resist pattern.

  The reason is that the wettability of the antireflection film and the resist can be improved because the surface state can be modified by plasma treatment or UV treatment.

  As described above, in the conventional dual damascene process using a low dielectric constant film, a stable resist processing shape could not be obtained by a reaction inhibitor such as amine. Resist resolution can be obtained, which can contribute to an improvement in yield.

1a first resist pattern 1b second resist pattern 2a first antireflection film 2b second antireflection film 3 cap insulating film 4 second interlayer insulating film 5 second etching stop film 6 first interlayer insulating film 7 first etching stop film 8 Wiring board 9 Via hole 10 Wiring trench pattern 11 Wiring material 12 Hard mask film 13 Hard mask film lower part 14 Resist residue 15 Crown 16 Quartz cell 17 Sample 18 with via Lower layer wiring 19 Modified film

Claims (40)

In the method of manufacturing a semiconductor device including a step of forming a resist pattern on the insulating film after performing wet processing on the substrate on which the insulating film is formed using an organic stripping solution or a cleaning solution.
After the wet treatment, before applying a resist to be the resist pattern or an antireflection film provided under the resist, it is a substance contained in the organic stripping solution or the cleaning solution and inhibits the chemical reaction of the resist. A method for manufacturing a semiconductor device, comprising performing pretreatment to remove a reaction inhibitor.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is made of a low dielectric constant film. A step of sequentially depositing at least a first interlayer insulating film and a second interlayer insulating film on a substrate on which a wiring pattern is formed; and forming a first resist pattern on the second interlayer insulating film; Forming a via hole penetrating through the first interlayer insulating film and the second interlayer insulating film by dry etching using the first resist pattern as a mask, and a process of removing an etching residue with an organic stripping solution, or Performing a wet process of at least one of a process of cleaning with a cleaning liquid, a process of forming a second resist pattern on the second interlayer insulating film, and the second resist pattern as a mask. Etching the interlayer insulating film to form a wiring trench pattern, and embedding and polishing a wiring material in the via hole and the wiring trench pattern In the method for manufacturing at least a semiconductor device and forming a line pattern,
After the wet treatment, before applying a resist to be the resist pattern or an antireflection film provided under the resist, it is a substance contained in the organic stripping solution or the cleaning solution and inhibits the chemical reaction of the resist. A method for manufacturing a semiconductor device, comprising performing pretreatment to remove a reaction inhibitor. Depositing at least a first interlayer insulating film, a second interlayer insulating film, and a mask member made of an inorganic material on the substrate on which the wiring pattern is formed; and forming a first resist pattern on the mask member Then, at least one wet of a process of forming a hard mask by etching the mask member using the first resist pattern, a process of removing an etching residue with an organic stripper, or a process of cleaning with a cleaning liquid Performing a process, forming a second resist pattern on the hard mask, and penetrating the first interlayer insulating film and the second interlayer insulating film by dry etching using the second resist pattern as a mask Forming a via hole to be removed, and removing the second resist pattern, and then forming the second interlayer insulating film using the hard mask. Forming a etching to the wiring trench pattern, the manufacturing method of the via hole and buried wiring material on the wiring trench pattern in the polishing and at least having a semiconductor device and forming a wiring pattern,
After the wet treatment, before applying a resist to be the resist pattern or an antireflection film provided under the resist, it is a substance contained in the organic stripping solution or the cleaning solution and inhibits the chemical reaction of the resist. A method for manufacturing a semiconductor device, comprising performing pretreatment to remove a reaction inhibitor.   5. The method of manufacturing a semiconductor device according to claim 3, wherein at least one of the first interlayer insulating film and the second interlayer insulating film is a low dielectric constant film.   The said reaction inhibitory substance consists of a basic substance, The catalytic action of the acid which generate | occur | produced in the said resist by exposure is inhibited by this basic substance. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 6, wherein the basic substance includes an amine.   8. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of annealing, UV, plasma, and organic solvent treatment is performed as the pretreatment.   8. The method of manufacturing a semiconductor device according to claim 1, wherein UV treatment is performed after annealing as the pretreatment.   The annealing process is a process of detaching the reaction inhibitor that has permeated or adsorbed into the insulating film, the first interlayer insulating film, or the second interlayer insulating film by annealing at a predetermined temperature. A method for manufacturing a semiconductor device according to claim 8 or 9.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the annealing treatment is performed in a temperature range of 150 to 450.degree.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the annealing treatment is performed at a temperature higher than a baking temperature of the antireflection film or the resist.   13. The method for manufacturing a semiconductor device according to claim 10, wherein the annealing treatment is performed under reduced pressure or in an atmosphere of nitrogen gas, inert gas, or hydrogen gas.   The UV treatment neutralizes the reaction-inhibiting substance that has permeated or adsorbed into the insulating film, the first interlayer insulating film, or the second interlayer insulating film with oxygen or ozone activated by UV light irradiation. The method of manufacturing a semiconductor device according to claim 8, wherein the method is a process.   The plasma treatment is a process of etching the reaction-inhibiting substance that has permeated or adsorbed into the insulating film or the interlayer insulating film with a plasma containing any one gas of oxygen, nitrogen, or ammonia. Item 9. A method for manufacturing a semiconductor device according to Item 8.   9. The semiconductor according to claim 8, wherein the organic solvent treatment is treatment using an organic solvent containing any one of polypyrene glycol monomethyl ether acetate, polypyrene glycol monomethyl ether, ethyl lactate, cyclohexanone, and methyl ethyl ketone. Device manufacturing method.   The organic solvent contains an acidic substance, and the acidic substance neutralizes the reaction-inhibiting substance that has permeated or adsorbed into the insulating film, the first interlayer insulating film, or the second interlayer insulating film. A method for manufacturing a semiconductor device according to claim 16.   The organic solvent contains a weakly basic substance, and the weakly basic substance causes the reaction-inhibiting substance that has penetrated or adsorbed to the insulating film, the first interlayer insulating film, or the second interlayer insulating film to become a weak base. The method of manufacturing a semiconductor device according to claim 16, wherein the semiconductor device is replaced. A semiconductor device formed using the manufacturing method according to claim 1, wherein at least one of annealing or UV treatment is used as the pretreatment,
A region having a component ratio or density different from the inside is formed on the contact surface layer of the insulating film that contacts at least a part of the side wall of the wiring pattern formed in the via hole or the wiring trench pattern. A semiconductor device.   The interlayer film in contact with at least a part of at least one side wall of the via or the wiring made of a conductor is an insulating film containing Si and O as main elements, and the insulating film is formed on the surface of the contact surface of the insulating film. A semiconductor device using a dual damascene wiring structure characterized by having a region having a lower nitrogen concentration.   The interlayer film in contact with at least a part of at least one side wall of the via or the wiring made of a conductor is a low dielectric constant insulating film containing Si, O and H as main elements, and is formed on the surface of the contact surface of the insulating film. A semiconductor device using a dual damascene wiring structure characterized by having a region having a higher oxygen concentration and a lower hydrogen concentration than the inside of the insulating film.   The concentration distribution in the region of the insulating film containing Si, O, and H as main elements has the highest oxygen concentration and the lowest hydrogen concentration at the outermost surface of the contact surface, and the oxygen concentration gradually decreases toward the inside. 23. The semiconductor device using a dual damascene wiring structure according to claim 21, wherein the hydrogen concentration increases and approaches the oxygen concentration and the hydrogen concentration inside the insulating film.   The interlayer film in contact with at least a part of at least one side wall of a via or wiring made of a conductor is a low dielectric constant insulating film containing Si, O, C, and H as main elements, and the contact surface of the insulating film A semiconductor device using a dual damascene wiring structure characterized in that a surface layer has a region in which oxygen concentration is higher than that in the insulating film and carbon and hydrogen concentrations are lower.   The concentration distribution in the region of the insulating film containing Si, O, C, and H as main elements has the highest oxygen concentration and the lowest hydrogen concentration and carbon concentration at the outermost surface of the contact surface, and gradually toward the inside. 24. The semiconductor using a dual damascene wiring structure according to claim 23, wherein the oxygen concentration is low and the hydrogen concentration and the carbon concentration are high, and the oxygen concentration, hydrogen concentration, and carbon concentration inside the insulating film approach each other. apparatus.   A barrier film or an etching stopper film that contacts at least a part of at least one side wall of a via or wiring made of a conductor is an insulating film containing Si, C, N, and H as main elements, and the contact of the insulating film A semiconductor device using a dual damascene wiring structure characterized in that a surface surface layer has a region in which oxygen concentration is higher than in the insulating film and carbon, nitrogen, and hydrogen concentrations are lower.   The concentration distribution in the region of the insulating film containing Si, C, N, and H as main elements has the highest oxygen concentration and the lowest nitrogen concentration, hydrogen concentration, and carbon concentration at the outermost surface of the contact surface, 26. The oxygen concentration gradually decreases and the nitrogen concentration, hydrogen concentration, and carbon concentration gradually increase toward the oxygen concentration, nitrogen concentration, hydrogen concentration, and carbon concentration in the insulating film. Semiconductor device using dual damascene wiring structure.   A barrier film or etching stopper film that contacts at least a part of at least one side wall of a via or wiring made of a conductor is an insulating film containing Si, C, and H as main elements, and the contact surface layer of the insulating film In addition, a semiconductor device using a dual damascene wiring structure having a region in which oxygen concentration is higher than that in the insulating film and carbon and hydrogen concentrations are lower.   The concentration distribution in the region of the insulating film containing Si, C, and H as the main elements has the highest oxygen concentration and the lowest hydrogen concentration and carbon concentration at the outermost surface of the contact surface, and the oxygen concentration gradually increases toward the inside. 28. The semiconductor device using a dual damascene wiring structure according to claim 27, wherein the concentration is low, the hydrogen concentration and the carbon concentration are increased, and the oxygen concentration, hydrogen concentration and carbon concentration inside the insulating film are approached.   An interlayer film in contact with at least a part of at least one side wall of a via or wiring made of a conductor is a low dielectric constant insulating film containing Si, O, and H as main elements or Si, O, C, and H as main elements. A semiconductor device using a dual damascene wiring structure, which is a low dielectric constant insulating film, and has a region having a higher film density than the inside of the insulating film on the surface of the contact surface of the insulating film.   A barrier film or an etching stopper insulating film that contacts at least a part of at least one side wall of a via or wiring made of a conductor is mainly an insulating film containing Si, C, N, and H as a main element, or Si, C, and H. A semiconductor device using a dual damascene wiring structure, which is an insulating film made of an element, and has a region having a higher film density than the inside of the insulating film on the surface of the contact surface of the insulating film.   The distribution of the film density in the region of the insulating film has the highest film density at the outermost surface of the contact surface, gradually decreases toward the inside, and approaches the film density inside the insulating film. 31. A semiconductor device using a dual damascene wiring structure according to claim 29 or 30.   The interlayer film in contact with at least a part of at least one side wall of the via or the wiring made of a conductor is a low dielectric constant insulating film containing Si, O and H as main elements, and is formed on the surface of the contact surface of the insulating film. A semiconductor device using a dual damascene wiring structure having a region in which the proportion of Si—O bonds is higher than that in the insulating film and the proportion of Si—H bonds is lower.   The distribution of the bonding state in the region of the insulating film containing Si, O, and H as main elements has the highest ratio of Si-O bonds and the lowest ratio of Si-H bonds on the outermost surface of the contact surface, The ratio of Si—O bonds gradually decreases toward the inside, and the ratio of Si—H bonds increases, approaching the ratio of Si—O bonds and Si—H bonds inside the insulating film. A semiconductor device using the dual damascene wiring structure according to claim 32. The interlayer film in contact with at least a part of at least one side wall of a via or wiring made of a conductor is a low dielectric constant insulating film containing Si, O, C, and H as main elements, and the contact surface of the insulating film A semiconductor device using a dual damascene wiring structure characterized in that a surface layer has a region in which a ratio of Si—O bonds is higher than that in the insulating film and a ratio of Si—CH ₃ bonds is lower. The distribution of the bonding state in the region of the insulating film containing Si, O, C, and H as main elements has the highest proportion of Si—O bonds and the proportion of Si—CH ₃ bonds on the outermost surface of the contact surface. lowest, gradually the percentage of the ratio is lower and Si-CH ₃ bonds of Si-O bond toward the inside becomes high, approaching the proportion of the insulating film inside the Si-O bond and Si-CH ₃ bond 35. A semiconductor device using a dual damascene wiring structure according to claim 34. A barrier film or etching stopper film that contacts at least a part of at least one side wall of a via or wiring made of a conductor is an insulating film having Si, C, N, and H as main elements, or Si, C, and H as main elements. A semiconductor device using a dual damascene wiring structure, characterized in that a region having a lower proportion of Si—CH ₃ bonds than the inside of the insulating film is provided on the surface of the contact surface of the insulating film. The distribution of the bonding state in the region of the insulating film is such that the ratio of the Si—O bond is the highest and the ratio of the Si—CH ₃ bond is the lowest on the outermost surface of the contact surface, and gradually the Si—O bond gradually toward the inside. the proportion of coupling increases the proportion of low and Si-CH ₃ bond, a dual damascene of claim 36, wherein the approaches the ratio of the insulating layer inside the Si-O bond and Si-CH ₃ bond A semiconductor device using a wiring structure.   38. The semiconductor device using a dual damascene wiring structure according to any one of claims 20 to 37, wherein the thickness of the region is approximately 30 nm or less.   The dual damascene wiring according to any one of claims 21, 22, 29, 31 to 33, wherein the low dielectric constant insulating film containing Si, O, and H as main elements is a ladder-type hydrogenated siloxane. A semiconductor device using the structure.   40. The semiconductor device using a dual damascene wiring structure according to claim 39, wherein L-Ox (registered trademark) is used as the ladder-type hydrogenated siloxane.

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