JP2011029526A - Method of manufacturing composite substrate - Google Patents

Method of manufacturing composite substrate Download PDF

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JP2011029526A
JP2011029526A JP2009176131A JP2009176131A JP2011029526A JP 2011029526 A JP2011029526 A JP 2011029526A JP 2009176131 A JP2009176131 A JP 2009176131A JP 2009176131 A JP2009176131 A JP 2009176131A JP 2011029526 A JP2011029526 A JP 2011029526A
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substrate
electrode
piezoelectric
piezoelectric substrate
polarization
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JP5413025B2 (en
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Tokuhiro Hayakawa
徳洋 早川
Hajime Kando
始 神藤
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Murata Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a composite substrate, capable of preventing hindrance derived from dielectric breakdown due to a polarization treatment of a piezoelectric substrate and suppressing an increase of the number of steps associated with the polarization treatment. <P>SOLUTION: In the method, a piezoelectric thin film 4 is laminated on a support substrate on which a conductive sacrificing layer is formed, and a meander electrode 20 turning to an open state due to over-current is formed to a wiring to form an upper surface polarizing electrode 14 on the piezoelectric thin film 4. Then, a polarizing electric field is applied between the upper surface polarizing electrode 14 and the conductive sacrificing layer, and subsequently the upper surface polarizing electrode 14, the meander electrode 20, and the conductive sacrificing layer are removed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、メンブレン構造(中空構造)を備え、圧電基板と支持基板とを積層した複合基板の製造方法に関し、特に、圧電基板に分極処理を施す複合基板の製造方法に関する。   The present invention relates to a method for manufacturing a composite substrate having a membrane structure (hollow structure) and in which a piezoelectric substrate and a support substrate are laminated, and more particularly to a method for manufacturing a composite substrate in which a piezoelectric substrate is subjected to polarization treatment.

圧電デバイスは、水晶・LiTaO3・LiNbO3などからなる圧電基板を備え、圧電基板と支持基板との間に空間を設けたメンブレン構造の複合基板として製造されることがある。メンブレン構造の複合基板は、支持基板と圧電基板との間に犠牲層を配置して支持基板と圧電基板とを接合し、犠牲層を除去することで空間部が形成される。 A piezoelectric device may be manufactured as a composite substrate having a membrane structure including a piezoelectric substrate made of quartz, LiTaO 3 , LiNbO 3, and the like, and providing a space between the piezoelectric substrate and a support substrate. In the composite substrate having a membrane structure, a sacrificial layer is disposed between the support substrate and the piezoelectric substrate, the support substrate and the piezoelectric substrate are joined, and the sacrificial layer is removed to form a space portion.

圧電基板は、スパッタ法やCVD法などの堆積法により圧電体を堆積して構成されることがある。(例えば、非特許文献1参照。)。堆積法では、圧電体の結晶軸の配向方向が限定されてしまうだけでなく、その素材もAlNやZnOなどに限定されてしまう。結晶軸の配向方向や素材は、圧電デバイスの電気機械結合係数や周波数温度特性、音速などに影響するため、堆積法を用いると圧電デバイスの設計自由度が抑制されてしまう。   The piezoelectric substrate may be configured by depositing a piezoelectric body by a deposition method such as sputtering or CVD. (For example, refer nonpatent literature 1.). In the deposition method, not only the orientation direction of the crystal axis of the piezoelectric body is limited, but also the material is limited to AlN or ZnO. Since the orientation direction of the crystal axis and the material affect the electromechanical coupling coefficient, frequency temperature characteristics, sound speed, etc. of the piezoelectric device, the use of the deposition method suppresses the degree of freedom in designing the piezoelectric device.

圧電基板における結晶軸の配向方向や素材を任意に設定するためには、圧電体ブロックからの切断や研磨により圧電基板を成形するとよい。しかしながらその場合、加工により圧電基板の分極方向が部分的に反転することがある。圧電基板に電界を与えることで分極方向は制御可能であり、圧電基板における分極方向を揃えるために分極処理が行われることがある(例えば、特許文献2および3参照。)。   In order to arbitrarily set the crystal axis orientation direction and the material in the piezoelectric substrate, the piezoelectric substrate may be formed by cutting or polishing the piezoelectric block. However, in that case, the polarization direction of the piezoelectric substrate may be partially reversed by processing. The polarization direction can be controlled by applying an electric field to the piezoelectric substrate, and polarization processing may be performed to align the polarization direction in the piezoelectric substrate (see, for example, Patent Documents 2 and 3).

Y. Osugi et al.; "Single crystalFBAR with LiNbO3 and LiTaO3", 2007 IEEE MTT-S International MicrowaveSymposium, pp.873-876Y. Osugi et al .; "Single crystal FBAR with LiNbO3 and LiTaO3", 2007 IEEE MTT-S International Microwave Symposium, pp.873-876

特開平5−90859号公報Japanese Patent Laid-Open No. 5-90859 特開平10−32454号公報Japanese Patent Laid-Open No. 10-32454

分極処理を行うためには、圧電基板の上下面に電界を印加するための分極電極対を設け、分極処理後に分極電極対を除去し、その後に圧電デバイスの機能電極を形成する必要がある。したがって、分極処理に付随して製造工程数が増加してしまう。   In order to perform the polarization treatment, it is necessary to provide polarization electrode pairs for applying an electric field on the upper and lower surfaces of the piezoelectric substrate, remove the polarization electrode pairs after the polarization treatment, and then form functional electrodes of the piezoelectric device. Therefore, the number of manufacturing steps increases with the polarization process.

また、例えばLiTaO3やLiNbO3からなる圧電基板は抗電界が高く、分極処理には、22kV/mm以上の高電界の印加が必要である。他にも、支持基板に積層された圧電基板に分極処理を施す場合にも、やはり高電界の印加が必要である。高電界を圧電基板に印加する場合、圧電基板にクラックなどの欠陥が存在して絶縁破壊が生じて分極電極対が放電により溶融・短絡し、過電流が流れて電圧源の故障が生じて問題となることがあった。 In addition, for example, a piezoelectric substrate made of LiTaO 3 or LiNbO 3 has a high coercive electric field, and application of a high electric field of 22 kV / mm or more is necessary for the polarization treatment. In addition, when a polarization treatment is applied to a piezoelectric substrate laminated on a support substrate, it is also necessary to apply a high electric field. When applying a high electric field to a piezoelectric substrate, defects such as cracks exist in the piezoelectric substrate, causing dielectric breakdown, and the polarization electrode pair melts and short-circuits due to discharge, overcurrent flows and a voltage source failure occurs. There was sometimes.

本発明の目的は、圧電基板の分極処理時の絶縁破壊に伴う障害の発生を防げ、分極処理に付随して増加する製造工程数を抑制できる複合基板の製造方法の提供を目的とする。   An object of the present invention is to provide a method of manufacturing a composite substrate that can prevent the occurrence of a failure due to dielectric breakdown during the polarization processing of a piezoelectric substrate and can suppress the number of manufacturing steps that increase accompanying the polarization processing.

この発明の複合基板の製造方法は、支持基板に導電性犠牲層を形成する工程と、導電性犠牲層および支持基板に重ねて圧電基板を設ける工程と、過電流によりオープンになる受動素子を配線に設けて圧電基板に上面分極電極を形成する工程と、上面分極電極と導電性犠牲層との間に分極電界を印加する工程と、圧電基板から上面分極電極および受動素子を除去する工程と、圧電基板を圧電デバイスとして機能させる上面機能電極を形成する工程と、導電性犠牲層を除去する工程と、を備える。
この製造方法では、上面分極電極と導電性犠牲層との間に分極電界を印加することで、圧電基板における分極方向を揃えられる。圧電基板に分極電界を印加する際に、絶縁破壊が生じて過電流が発生しても、上面分極電極の配線に設けた受動素子がオープンになるので、過電流に伴う障害の発生を防ぐことができる。さらには、メンブレン構造の空間部となる導電性犠牲層を分極電極対の一方として利用するので、別途、圧電基板の下面に分極電極を形成することや、圧電基板の下面の分極電極を除去すること無く、分極処理を行え、製造工程数の増加を抑制できる。上面分極電極および受動素子を分極後に除去することで、上面分極電極および受動素子の影響を受けずに完成品の圧電デバイスの特性を設定できる。
The method of manufacturing a composite substrate according to the present invention includes a step of forming a conductive sacrificial layer on a support substrate, a step of providing a piezoelectric substrate overlying the conductive sacrificial layer and the support substrate, and wiring a passive element that is opened by overcurrent. Forming a top polarization electrode on the piezoelectric substrate, applying a polarization electric field between the top polarization electrode and the conductive sacrificial layer, removing the top polarization electrode and the passive element from the piezoelectric substrate, The method includes a step of forming a top-surface functional electrode that causes the piezoelectric substrate to function as a piezoelectric device, and a step of removing the conductive sacrificial layer.
In this manufacturing method, the polarization direction in the piezoelectric substrate can be aligned by applying a polarization electric field between the upper surface polarization electrode and the conductive sacrificial layer. When applying a polarization electric field to a piezoelectric substrate, even if dielectric breakdown occurs and an overcurrent occurs, the passive element provided in the wiring of the upper surface polarization electrode is opened, so that the failure caused by the overcurrent is prevented. Can do. Furthermore, since the conductive sacrificial layer serving as the space portion of the membrane structure is used as one of the polarization electrode pairs, the polarization electrode is separately formed on the lower surface of the piezoelectric substrate, or the polarization electrode on the lower surface of the piezoelectric substrate is removed. Therefore, polarization treatment can be performed and increase in the number of manufacturing steps can be suppressed. By removing the upper surface polarization electrode and the passive element after polarization, the characteristics of the finished piezoelectric device can be set without being affected by the upper surface polarization electrode and the passive element.

この発明の導電性犠牲層および支持基板に重ねて圧電基板を設ける工程は、ブロック状の圧電基板にイオン注入を行う工程と、ブロック状の圧電基板のイオン注入面を導電性犠牲層および支持基板に接合する工程と、ブロック状の圧電基板のイオン注入面から一定深さを剥離面として加熱により圧電基板の薄膜を剥離する工程とを備えると好適である。   The step of providing the piezoelectric substrate overlying the conductive sacrificial layer and the support substrate of the present invention includes the step of ion implantation into the block-shaped piezoelectric substrate, and the ion-implanted surface of the block-shaped piezoelectric substrate with the conductive sacrificial layer and the support substrate. And a step of peeling the thin film of the piezoelectric substrate by heating with a certain depth from the ion implantation surface of the block-shaped piezoelectric substrate as a peeling surface.

この製造方法により、研磨などを行わなくても圧電基板の薄膜を成形でき、ブロック状の圧電基板を再利用して高価な圧電材料の使用量を抑制できる。また、イオン注入により圧電基板の薄膜の平坦度を高められる。なお、イオン注入を行うことで圧電基板における分極が反転することがあるが、分極工程を実施することで分極方向を揃えて、圧電基板の薄膜を高品位化できる。   With this manufacturing method, the thin film of the piezoelectric substrate can be formed without performing polishing or the like, and the amount of expensive piezoelectric material used can be suppressed by reusing the block-shaped piezoelectric substrate. Further, the flatness of the thin film of the piezoelectric substrate can be increased by ion implantation. In addition, although the polarization in the piezoelectric substrate may be reversed by performing ion implantation, the thin film of the piezoelectric substrate can be improved in quality by aligning the polarization direction by performing the polarization process.

この発明の受動素子は、ミアンダ形状の電極ラインであると好適である。
ミアンダ形状の電極ラインは単位面積あたりの線路長が長く、過電流が流れると熱拡散により抵抗が飛躍的に増大する。そのため、電極ラインが溶断し易く、過電流に対する応答性が高まる。また、電極ラインとして受動素子を構成することにより上面分極電極と受動素子との形成を一度に行え、製造工程数を削減できる。
The passive element of the present invention is preferably a meander-shaped electrode line.
The meander-shaped electrode line has a long line length per unit area, and when an overcurrent flows, the resistance dramatically increases due to thermal diffusion. Therefore, the electrode line is easily blown, and the response to overcurrent is increased. Moreover, by forming a passive element as an electrode line, the top surface polarization electrode and the passive element can be formed at a time, and the number of manufacturing steps can be reduced.

この発明の支持基板および圧電基板は複数に分割されるものであり、前記導電性犠牲層、前記上面分極電極、前記受動素子、および前記上面機能電極は、分割される複数の領域それぞれに設けられ、各領域に対応する受動素子は電圧源に対して並列に接続されると好適である。   The support substrate and the piezoelectric substrate of the present invention are divided into a plurality of parts, and the conductive sacrificial layer, the upper surface polarization electrode, the passive element, and the upper surface functional electrode are provided in each of a plurality of divided regions. The passive elements corresponding to each region are preferably connected in parallel to the voltage source.

単一の基板を分割して複数の圧電デバイスを形成する場合、一箇所でも絶縁破壊が生じると基板全体で分極電界を印加することが不能になる恐れがある。その場合、絶縁破壊が直接起こっていない他の圧電デバイスであっても、同一ロットの圧電デバイスであれば全て分極処理を経ずに製造されることになり、良品率が低下してしまう。この問題の解消には、複数の受動素子を電圧源に対して並列に接続すると好適である。複数の受動素子を電圧源に対して並列に接続していれば、絶縁破壊が生じた分極電極対のみが過電流によりオープンになって電圧源から分離され、他の分極電極対には引き続き分極電界を印加することができる。したがって、絶縁破壊が生じた場合でも同一ロットの他の圧電デバイスに分極処理を行うことができ、良品率を改善できる。   When a single substrate is divided to form a plurality of piezoelectric devices, if dielectric breakdown occurs even at one location, it may be impossible to apply a polarization electric field across the entire substrate. In that case, even if other piezoelectric devices are not directly broken down, all piezoelectric devices in the same lot are manufactured without undergoing polarization treatment, and the yield rate is reduced. In order to solve this problem, it is preferable to connect a plurality of passive elements in parallel to the voltage source. If multiple passive elements are connected in parallel to the voltage source, only the polarized electrode pair where dielectric breakdown has occurred is opened by overcurrent and separated from the voltage source, and the other polarized electrode pairs continue to be polarized. An electric field can be applied. Therefore, even when dielectric breakdown occurs, polarization processing can be performed on other piezoelectric devices in the same lot, and the yield rate can be improved.

この発明によれば、圧電基板における部分的な分極方向の反転を回復させられる。また、過電流によってオープンになる受動素子を上面分極電極の配線に設けることで、分極処理時の絶縁破壊に伴って発生する障害を防ぐことができる。さらには、メンブレン構造を実現するための導電性犠牲層を分極電極対の一方に利用するので、別途、圧電基板の下面に分極電極を形成することや、下面の分極電極を除去すること無く分極処理を行え、工程数の増加を抑制できる。上面分極電極および受動素子を分極後に除去するので、上面分極電極および受動素子の影響を受けることなく完成品の圧電デバイスの特性を設定できる。   According to the present invention, partial inversion of the polarization direction in the piezoelectric substrate can be recovered. In addition, by providing a passive element that is opened by an overcurrent in the wiring of the upper surface polarization electrode, it is possible to prevent a failure that occurs due to a dielectric breakdown during the polarization process. Furthermore, since a conductive sacrificial layer for realizing the membrane structure is used for one of the polarization electrode pairs, polarization can be performed without forming a polarization electrode on the lower surface of the piezoelectric substrate or removing the polarization electrode on the lower surface. Processing can be performed and an increase in the number of steps can be suppressed. Since the upper surface polarization electrode and the passive element are removed after polarization, the characteristics of the finished piezoelectric device can be set without being affected by the upper surface polarization electrode and the passive element.

本発明の実施形態に係る複合基板の製造方法の製造工程フローにおける各工程での基板状態を示す図である。It is a figure which shows the board | substrate state in each process in the manufacturing process flow of the manufacturing method of the composite substrate which concerns on embodiment of this invention. 本発明の実施形態に係る複合基板の製造方法の製造工程フローにおける各工程での基板状態を示す図である。It is a figure which shows the board | substrate state in each process in the manufacturing process flow of the manufacturing method of the composite substrate which concerns on embodiment of this invention. 上面分極電極を設けた複合基板の平面図である。It is a top view of the composite substrate which provided the upper surface polarization electrode. 導電性犠牲層を設けた支持基板の平面図である。It is a top view of the support substrate which provided the electroconductive sacrificial layer.

以下、本願発明の実施形態に係るメンブレン構造の圧電デバイスとして、FBAR(Film Bulk Acoustic Resonator)デバイスを製造する方法を例に、本願発明を説明する。   Hereinafter, the present invention will be described by taking as an example a method of manufacturing an FBAR (Film Bulk Acoustic Resonator) device as a piezoelectric device having a membrane structure according to an embodiment of the present invention.

図1は、本実施形態に係る製造工程フローにおける各工程での基板状態を示す図である。本実施形態では、複数のFBARデバイスを単一の基板から一度に製造するが、図中には同基板における一つのFBARデバイスを構成する部分のみを示している。   FIG. 1 is a diagram showing a substrate state in each process in the manufacturing process flow according to the present embodiment. In the present embodiment, a plurality of FBAR devices are manufactured from a single substrate at a time, but only a portion constituting one FBAR device on the substrate is shown in the drawing.

まず鏡面研磨を施した平坦な主面を有する圧電基板1を用意し、その主面から水素イオンを注入するイオン注入工程を実施する(S1)。圧電基板1としては42°YカットのLiTaO3基板を採用し、水素イオンの注入エネルギーは150KeVとし、ドーズ量(イオン注入密度)は9×1016atom/cm2とする。これにより圧電基板1の表面から一定距離の内部、ここでは形成深さ約1.0μmにマイクロキャビティが集中する剥離層1Cが形成される。なお、圧電基板1の各面は、正または負の極性に帯電していて、ここでは圧電基板1の負極性の主面に対して、陽イオンである水素イオンを注入する。イオン注入により、圧電基板1の分極の一部が反転するが、主面の極性と逆極性のイオンを注入することで分極反転の発生を抑制する。圧電基板1としてはLiTaO3基板の他に、LiNbO3基板、Li2B4O7基板、La3Ga5SiO14基板などを利用してもよい。 First, a piezoelectric substrate 1 having a flat principal surface subjected to mirror polishing is prepared, and an ion implantation step is performed in which hydrogen ions are implanted from the principal surface (S1). As the piezoelectric substrate 1, a 42 ° Y-cut LiTaO 3 substrate is used, the hydrogen ion implantation energy is 150 KeV, and the dose (ion implantation density) is 9 × 10 16 atoms / cm 2 . As a result, a release layer 1C is formed in which the microcavities are concentrated within a certain distance from the surface of the piezoelectric substrate 1, here, at a formation depth of about 1.0 μm. Each surface of the piezoelectric substrate 1 is charged with a positive or negative polarity. Here, hydrogen ions, which are positive ions, are implanted into the negative main surface of the piezoelectric substrate 1. Although a part of the polarization of the piezoelectric substrate 1 is reversed by the ion implantation, the occurrence of polarization reversal is suppressed by implanting ions having a polarity opposite to that of the main surface. As the piezoelectric substrate 1, in addition to the LiTaO 3 substrate, a LiNbO 3 substrate, a Li 2 B 4 O 7 substrate, a La 3 Ga 5 SiO 14 substrate, or the like may be used.

次に、圧電基板1の水素イオンを注入した主面に、圧電デバイスの下面機能電極となる電極11を形成する(S2)。   Next, the electrode 11 which becomes the lower surface functional electrode of the piezoelectric device is formed on the main surface of the piezoelectric substrate 1 into which hydrogen ions are implanted (S2).

次に、圧電基板1の電極11を形成した面に、支持基板2との密着層となる薄い絶縁膜12を形成する(S3)。絶縁膜12の主面はCMPにより平滑化すると好適である。絶縁膜12としてはSiNなど、導電性犠牲層13と圧電基板1との間での素材粒子の拡散を抑制可能な素材を選択すると好適である。   Next, a thin insulating film 12 serving as an adhesion layer with the support substrate 2 is formed on the surface of the piezoelectric substrate 1 on which the electrode 11 is formed (S3). The main surface of the insulating film 12 is preferably smoothed by CMP. As the insulating film 12, it is preferable to select a material that can suppress the diffusion of material particles between the conductive sacrificial layer 13 and the piezoelectric substrate 1, such as SiN.

また、Si、ガラス、圧電体基板などにSiO2膜を成膜した支持基板2を用意する(S4)。なお、SiO2膜に替えて、SiN、PSG(フォスフォシリケートグラス)、ZnOなどの絶縁膜を採用してもよい。 Also, a support substrate 2 having a SiO 2 film formed on Si, glass, a piezoelectric substrate, etc. is prepared (S4). In place of the SiO 2 film, an insulating film such as SiN, PSG (phosphosilicate glass), or ZnO may be employed.

次に、支持基板2にして空間部2Aを形成する(S5)。空間部2Aは、SiO2膜に対するレジストパターニング、RIE(リアクティブドライエッチング)、レジスト除去によって形成する。 Next, the space 2A is formed on the support substrate 2 (S5). The space 2A is formed by resist patterning on the SiO 2 film, RIE (reactive dry etching), and resist removal.

次に、導電性犠牲層13を空間部2Aの内部に形成し、CMPにより導電性犠牲層13の表面と支持基板2の表面とを平坦化する(S6)。導電性犠牲層としては、Cu、Al、Niなどの金属や、導電ペーストなどの導体を用い、エレクトロンマイグレーションに強い材料を採用することが好ましい。導電性犠牲層13の形成方法は、スパッタ成膜、EB蒸着、CVD、印刷法などを採用するとよい。また、導電性犠牲層13および支持基板2の表面には、さらに図示しない絶縁膜を密着層として形成する。この絶縁膜として、前述の絶縁膜12と同様に導電性犠牲層13と圧電基板1との間での素材粒子の拡散を抑制可能な素材を選択すると好適である。   Next, the conductive sacrificial layer 13 is formed inside the space 2A, and the surface of the conductive sacrificial layer 13 and the surface of the support substrate 2 are planarized by CMP (S6). As the conductive sacrificial layer, it is preferable to use a material resistant to electron migration using a metal such as Cu, Al, or Ni, or a conductor such as a conductive paste. As a method for forming the conductive sacrificial layer 13, sputtering film formation, EB vapor deposition, CVD, printing, or the like may be employed. An insulating film (not shown) is further formed as an adhesion layer on the surfaces of the conductive sacrificial layer 13 and the support substrate 2. As this insulating film, it is preferable to select a material capable of suppressing the diffusion of material particles between the conductive sacrificial layer 13 and the piezoelectric substrate 1 in the same manner as the insulating film 12 described above.

次に、圧電基板1と支持基板2とを、密着層を介して清浄化接合して複合基板5を構成する(S7)。清浄化接合を利用することにより常温での接合処理が可能となる。   Next, the piezoelectric substrate 1 and the support substrate 2 are cleaned and bonded through the adhesion layer to form the composite substrate 5 (S7). By using the clean bonding, the bonding process at room temperature is possible.

次に複合基板5を500℃加熱環境下に置く(S8)。これにより圧電基板1の剥離層1Cでマイクロキャビティが発生して成長し、圧電基板1から約1μm厚の圧電薄膜4が剥離する。   Next, the composite substrate 5 is placed in a 500 ° C. heating environment (S8). As a result, a microcavity is generated and grows in the release layer 1 </ b> C of the piezoelectric substrate 1, and the piezoelectric thin film 4 having a thickness of about 1 μm peels from the piezoelectric substrate 1.

次に、圧電薄膜4が剥落した圧電基板1と、圧電薄膜4が残存する複合基板5との剥離面をそれぞれCMPにより平滑化する(s9)。圧電薄膜4が剥落した圧電基板1は、次ロットの圧電デバイスの製造に利用するために、再びイオン注入を行う。   Next, the peeling surfaces of the piezoelectric substrate 1 from which the piezoelectric thin film 4 has been peeled off and the composite substrate 5 on which the piezoelectric thin film 4 remains are smoothed by CMP (s9). The piezoelectric substrate 1 from which the piezoelectric thin film 4 has peeled off is subjected to ion implantation again in order to be used for manufacturing the piezoelectric device of the next lot.

図2は、本実施形態に係る製造工程フローにおける各工程での基板状態を示す図である。   FIG. 2 is a diagram showing a substrate state in each process in the manufacturing process flow according to the present embodiment.

次に、剥離面を平坦化した複合基板5は、圧電薄膜4の表面に上面分極電極14を形成し、上面分極電極14と導電性犠牲層13とを電圧源に接続して、上面分極電極14と導電性犠牲層13との間に分極電界を印加する(S10)。これにより、イオン注入時に部分的に反転した分極を回復させて、圧電薄膜4における分極方向を揃える。   Next, in the composite substrate 5 having a flattened peel surface, the upper surface polarization electrode 14 is formed on the surface of the piezoelectric thin film 4, the upper surface polarization electrode 14 and the conductive sacrificial layer 13 are connected to a voltage source, and the upper surface polarization electrode is formed. A polarization electric field is applied between 14 and the conductive sacrificial layer 13 (S10). As a result, the polarization partially reversed at the time of ion implantation is recovered, and the polarization direction in the piezoelectric thin film 4 is made uniform.

圧電薄膜4の分極処理後には、上面分極電極14を除去する(S11)。   After the polarization treatment of the piezoelectric thin film 4, the upper surface polarization electrode 14 is removed (S11).

次に、下面機能電極とともにFBARデバイスを励振する上面機能電極15、電極引き回し配線(不図示)、および、バンプパッド16を圧電薄膜4の表面に形成し、絶縁膜17を全面に成膜する(S12)。   Next, the upper surface functional electrode 15 for exciting the FBAR device together with the lower surface functional electrode, the electrode routing wiring (not shown), and the bump pad 16 are formed on the surface of the piezoelectric thin film 4, and the insulating film 17 is formed on the entire surface ( S12).

次に、導電性犠牲層13を除去するためのエッチャントを導入する開口窓18を、圧電薄膜4の窓開け加工により形成する(S13)。この工程は、フォトリソグラフィー技術を用いて絶縁膜17をパターニングし、RIE法によって圧電薄膜4をエッチングするとよい。   Next, an opening window 18 for introducing an etchant for removing the conductive sacrificial layer 13 is formed by opening the piezoelectric thin film 4 (S13). In this step, the insulating film 17 may be patterned using a photolithography technique, and the piezoelectric thin film 4 may be etched by the RIE method.

次に、開口窓18からエッチング液、もしくは、エッチングガスを空間部2Aに導入し、導電性犠牲層13を除去する(S14)。   Next, an etching solution or etching gas is introduced into the space 2A from the opening window 18 to remove the conductive sacrificial layer 13 (S14).

次に、圧電薄膜4の加工に用いた絶縁膜17を剥離し、洗浄および乾燥工程を行い、FBARデバイスを外部回路に接続するためのバンプ19をバンプパッド16上に形成する(S15)。   Next, the insulating film 17 used for processing the piezoelectric thin film 4 is peeled off, and cleaning and drying processes are performed, and bumps 19 for connecting the FBAR device to an external circuit are formed on the bump pads 16 (S15).

以上の各工程により本実施形態ではFBARデバイスを製造する。圧電薄膜4を圧電基板1からの剥離により形成するので、圧電体材料、結晶方位などの設計自由度が従来よりも高く、ブロック状の圧電基板1の再利用が可能で高価な圧電材料の使用量を抑制できる。また、イオン注入を利用するので、圧電薄膜4の平坦度が高く、厚みの設計自由度も高い。これにより圧電薄膜4における電気機械結合係数や周波数温度特性、音速を精緻に設定する事が可能になり、FBARデバイスにおける周波数特性や、帯域幅、挿入損失などの特性を改善できる。イオン注入を行うことで圧電基板1における分極が反転することがあるが、分極工程を実施することで分極方向が揃い、圧電薄膜4を高品位にできる。   In this embodiment, an FBAR device is manufactured by the above steps. Since the piezoelectric thin film 4 is formed by peeling from the piezoelectric substrate 1, the degree of freedom in designing the piezoelectric material, crystal orientation, etc. is higher than before, and the block-shaped piezoelectric substrate 1 can be reused and an expensive piezoelectric material is used. The amount can be suppressed. Moreover, since ion implantation is used, the flatness of the piezoelectric thin film 4 is high, and the degree of freedom in designing the thickness is also high. This makes it possible to precisely set the electromechanical coupling coefficient, frequency temperature characteristics, and sound speed in the piezoelectric thin film 4, and improve characteristics such as frequency characteristics, bandwidth, and insertion loss in the FBAR device. By performing ion implantation, the polarization in the piezoelectric substrate 1 may be reversed, but by performing the polarization step, the polarization direction is aligned, and the piezoelectric thin film 4 can be made high quality.

図3(A)は分極工程に利用する上面分極電極14を設けた圧電薄膜4の平面図である。複数の上面分極電極14はマトリクス状に配置されていて、それぞれミアンダ電極20を介して並列に電圧印加ライン21に接続し、電圧印加ライン21を介して電圧源に接続している。図3(B)はミアンダ電極20の拡大した平面図である。ミアンダ電極20は、ミアンダ状に折り返されたライン電極であり、本願発明の受動素子に相当する。   FIG. 3A is a plan view of the piezoelectric thin film 4 provided with the upper surface polarization electrode 14 used for the polarization process. The plurality of upper surface polarization electrodes 14 are arranged in a matrix and are connected to the voltage application line 21 in parallel via the meander electrodes 20 and connected to the voltage source via the voltage application line 21. FIG. 3B is an enlarged plan view of the meander electrode 20. The meander electrode 20 is a line electrode folded back in a meander shape, and corresponds to a passive element of the present invention.

図4は、分極工程に利用する導電性犠牲層13を設けた支持基板2の平面図である。複数の導電性犠牲層13はマトリクス状に配置されていて、それぞれ上下左右に隣接する他の導電性犠牲層13と接続ライン22を介して導通し、電圧印加ライン21を介して電圧源に接続している。   FIG. 4 is a plan view of the support substrate 2 provided with the conductive sacrificial layer 13 used for the polarization step. The plurality of conductive sacrificial layers 13 are arranged in a matrix, and are electrically connected to the other conductive sacrificial layers 13 adjacent to each other in the vertical and horizontal directions through the connection line 22 and connected to the voltage source through the voltage application line 21. is doing.

前述の上面分極電極14と導電性犠牲層13とは、平面視して互いに一致する形状で対向していて、電圧印加ライン21を介して電圧源から印加される電圧によって、圧電薄膜4に分極電界を与える。この分極電界により、圧電薄膜4では、部分的に反転した分極方向が復元されることになる。   The upper surface polarization electrode 14 and the conductive sacrificial layer 13 are opposed to each other in a shape that coincides with each other in plan view, and are polarized on the piezoelectric thin film 4 by a voltage applied from a voltage source via the voltage application line 21. Give an electric field. This polarization electric field restores the partially reversed polarization direction in the piezoelectric thin film 4.

抗電界が高いLiTaO3基板やLiNbO3基板を圧電基板とした場合、室温での分極処理には22kV/mm以上もの高電界の印加が必要であり、圧電薄膜4に微細なクラックなどがあると絶縁破壊により上面分極電極14と導電性犠牲層13との間で放電が発生することがある。このようにして放電が生じると、上面分極電極14や導電性犠牲層13が融解して互いに短絡して、絶縁破壊が生じることがある。 When a LiTaO 3 substrate or a LiNbO 3 substrate having a high coercive electric field is used as a piezoelectric substrate, a high electric field of 22 kV / mm or more is required for polarization treatment at room temperature, and there are fine cracks in the piezoelectric thin film 4. A discharge may occur between the upper surface polarization electrode 14 and the conductive sacrificial layer 13 due to dielectric breakdown. When discharge occurs in this way, the top-polarized electrode 14 and the conductive sacrificial layer 13 may melt and short-circuit with each other, resulting in dielectric breakdown.

従来構成では、一箇所でも絶縁破壊が生じると、その後に基板全体で分極電界を印加することが不能になり、同一ロットの圧電デバイスが全て分極処理を完了せずに製造されることになり、良品率が低下してしまう。   In the conventional configuration, when dielectric breakdown occurs even at one location, it becomes impossible to apply a polarization electric field to the entire substrate thereafter, and all piezoelectric devices of the same lot will be manufactured without completing the polarization process, The yield rate will decrease.

一方、本構成では、各上面分極電極14と電圧源との間には、個別にミアンダ電極20を挿入しているので、圧電薄膜4の絶縁破壊により特定の上面分極電極14のショート箇所で過電流が流れると、その上面分極電極14に接続されたミアンダ電極20が熱拡散して抵抗が増大する。これにより、そのミアンダ電極20が溶断に至り、電圧印加ライン21がオープンとなってショート箇所の上面分極電極14を電圧印加ライン21から分離する。したがって、過電流による影響が他の上面分極電極14やミアンダ電極20、電圧源などに及ぶことを防ぐことができる。   On the other hand, in this configuration, since the meander electrode 20 is individually inserted between each upper surface polarization electrode 14 and the voltage source, an excess occurs at a short portion of the specific upper surface polarization electrode 14 due to dielectric breakdown of the piezoelectric thin film 4. When a current flows, the meander electrode 20 connected to the upper surface polarization electrode 14 is thermally diffused to increase the resistance. As a result, the meander electrode 20 is blown, the voltage application line 21 is opened, and the upper surface polarization electrode 14 at the short portion is separated from the voltage application line 21. Therefore, it is possible to prevent the influence of the overcurrent from reaching other upper surface polarization electrodes 14, meander electrodes 20, voltage sources, and the like.

なおミアンダ電極としては、熱拡散しやすいCu,Tiなどの材料を選択しておくと、熱拡散によりミアンダ電極の抵抗が増大させることができて好適である。ミアンダ電極は、単位面積当たりの線路長を長くできるため、抵抗を増やすのに効果的である。   As the meander electrode, it is preferable to select a material such as Cu or Ti that is easily thermally diffused, because the resistance of the meander electrode can be increased by the thermal diffusion. Since the meander electrode can increase the line length per unit area, it is effective in increasing the resistance.

以上の実施形態に示すように本願発明は実施できるが、FBARデバイスの他にも板波デバイス、ジャイロ、RFスイッチ、焦電デバイスなどであっても、本願発明は好適に実施できる。   Although the present invention can be implemented as shown in the above embodiments, the present invention can be suitably implemented even with plate wave devices, gyros, RF switches, pyroelectric devices, etc. in addition to FBAR devices.

1…圧電基板
1C…剥離層
2…支持基板
2A…空間部
4…圧電薄膜
5…複合基板
13…導電性犠牲層
14…上面分極電極
15…上面機能電極
18…開口窓
20…ミアンダ電極
21…電圧印加ライン
DESCRIPTION OF SYMBOLS 1 ... Piezoelectric substrate 1C ... Release layer 2 ... Supporting substrate 2A ... Space part 4 ... Piezoelectric thin film 5 ... Composite substrate 13 ... Conductive sacrificial layer 14 ... Upper surface polarization electrode 15 ... Upper surface functional electrode 18 ... Opening window 20 ... Meander electrode 21 ... Voltage application line

Claims (4)

支持基板に導電性犠牲層を形成する工程と、
前記導電性犠牲層および前記支持基板に重ねて圧電基板を設ける工程と、
過電流によりオープンになる受動素子を配線に設けて前記圧電基板に上面分極電極を形成する工程と、
前記上面分極電極と前記導電性犠牲層との間に分極電界を印加する工程と、
前記圧電基板から前記上面分極電極および前記受動素子を除去する工程と、
前記圧電基板を圧電デバイスとして機能させる上面機能電極を形成する工程と、
前記導電性犠牲層を除去する工程と、を備える複合基板の製造方法。
Forming a conductive sacrificial layer on the support substrate;
Providing a piezoelectric substrate overlying the conductive sacrificial layer and the support substrate;
Providing a passive element that is opened by an overcurrent in the wiring to form a top surface polarization electrode on the piezoelectric substrate;
Applying a polarization electric field between the upper surface polarization electrode and the conductive sacrificial layer;
Removing the top polarized electrode and the passive element from the piezoelectric substrate;
Forming a top functional electrode that causes the piezoelectric substrate to function as a piezoelectric device;
A step of removing the conductive sacrificial layer.
導電性犠牲層および支持基板に重ねて圧電基板を設ける前記工程は、
ブロック状の圧電基板にイオン注入を行う工程と、
前記ブロック状の圧電基板のイオン注入面を前記導電性犠牲層および前記支持基板に接合する工程と、
前記ブロック状の圧電基板のイオン注入面から一定深さを剥離面として、加熱により圧電基板の薄膜を剥離する工程とを備える、請求項1に記載の複合基板の製造方法。
The step of providing a piezoelectric substrate overlying the conductive sacrificial layer and the support substrate includes:
Ion implantation into a block-shaped piezoelectric substrate;
Bonding the ion-implanted surface of the block-shaped piezoelectric substrate to the conductive sacrificial layer and the support substrate;
2. The method of manufacturing a composite substrate according to claim 1, further comprising a step of peeling the thin film of the piezoelectric substrate by heating with a predetermined depth from the ion implantation surface of the block-shaped piezoelectric substrate as a peeling surface.
前記受動素子は、ミアンダ形状の電極ラインである、請求項1または2に記載の複合基板の製造方法。   The method for manufacturing a composite substrate according to claim 1, wherein the passive element is a meander-shaped electrode line. 前記支持基板および前記圧電基板は複数に分割されるものであり、
前記導電性犠牲層、前記上面分極電極、前記受動素子、および前記上面機能電極は、分割される複数の領域それぞれに設けられ、
各領域に対応する前記受動素子は電圧源に対して並列に接続される、請求項1〜3のいずれかに記載の複合基板の製造方法。
The support substrate and the piezoelectric substrate are divided into a plurality of parts,
The conductive sacrificial layer, the upper surface polarization electrode, the passive element, and the upper surface functional electrode are provided in each of a plurality of divided regions,
The said passive element corresponding to each area | region is a manufacturing method of the composite substrate in any one of Claims 1-3 connected in parallel with respect to a voltage source.
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