JP2011024149A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of accelerating a pixel signal read speed. <P>SOLUTION: The solid-state imaging apparatus includes a data holding mechanism 11 and a horizontal mixing mechanism which are configured as follows. The data holding mechanism 11 capable of holding pixel signals vertically transferred from a photoelectric transducer array 1 for a plurality of rows is provided to each of columns of the photoelectric transducer array 1, pixel signals for the plurality of rows to be held by the data holding mechanism 11 can be selected for each set of vertical mixing columns simultaneously mixing pixel signals in a vertical direction, and the row of the pixel signals to be mixed in the vertical direction can be selected from among the pixel signals for the plurality of rows being held in the data holding mechanism 11 for each set of the vertical mixing columns. Furthermore, the horizontal mixing mechanism is provided for mixing, in a horizontal direction, pixel signals to be mixed in the vertical direction for each set of horizontal mixing combination columns for simultaneously mixing pixel signals in the horizontal direction, so that rows of pixel signals to be mixed in the vertical direction become different for each set of the vertical mixing columns or the horizontal mixing combination columns. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In recent years, with the development of semiconductor technology, high-pixel solid-state imaging devices have been realized. That is, the number of photoelectric conversion elements (number of pixels) mounted on the photoelectric conversion element array of the solid-state imaging device has been dramatically increased. For still image shooting using a solid-state imaging device, an all-pixel readout mode is generally employed. The all pixel readout mode is a mode for reading out pixel signals of all pixels. By adopting the all-pixel readout mode, higher-definition still image shooting becomes possible as the number of pixels of the solid-state imaging device increases.

  On the other hand, there is also a solid-state imaging device configured to be able to switch between both a still image shooting mode and a moving image recording mode. At present, there is a certain limit to the operation speed of digital signal processing circuits such as DSP (Digital Signal Processor), and as the number of pixels increases and power consumption, moving image recording is similar to still image shooting. It has become difficult to shoot in the all-pixel readout mode.

  For this reason, a moving image recording generally employs a pixel mixture reading mode in which pixel signals to be read are thinned out. That is, in the pixel mixture readout mode, a plurality of pixel signals are mixed according to the purpose, and the readout pixel signals are thinned out. In the pixel mixed readout mode, pixel signals for a plurality of pixels adjacent in at least the vertical direction of the photoelectric conversion element array are mixed. By adopting the pixel mixture readout mode, the number of pixel signals to be read is reduced, the number of frames per unit time is increased, and smooth and high-speed moving image shooting is possible even in a high-pixel solid-state imaging device.

  There is also a solid-state imaging device that employs an interlaced readout mode for moving image recording (see, for example, Patent Document 1). The interlaced readout mode is a mode in which the pixel signals of all the pixels are read out several times for each different field. A digital signal processing circuit such as a DSP forms an image having a size equivalent to that in the all-pixel reading mode from the read field pixels. According to the interlaced readout mode, the pixel signals of all the pixels are read out several times, so that the number of frames per unit time can be increased.

JP 2005-130382 A

  However, in the conventional pixel mixture readout mode, all the pixels are to be mixed, which is an impediment to increasing the readout speed of the pixel signal and hinders further improvement in the quality of moving image recording. On the other hand, the interlaced readout mode has a problem that the vertical resolution is deteriorated as compared with the pixel mixed readout mode.

  In view of the above-described conventional problems, an object of the present invention is to provide a solid-state imaging device capable of increasing the readout speed of pixel signals and improving the quality of moving image recording.

  The solid-state imaging device according to claim 1 of the present invention includes a photoelectric conversion element array in which a plurality of photoelectric conversion elements for converting incident light into pixel signals are arranged in a matrix, and the photoelectric conversion elements arranged in a matrix And a data holding mechanism configured to hold a plurality of rows of the pixel signals vertically transferred from the photoelectric conversion element array, and the pixel signals from the photoelectric conversion element array vertically in units of one row. A holding data selection mechanism for selecting the pixel signals for a plurality of rows to be held by the data holding mechanism for each set of columns that simultaneously mix the pixel signals in the vertical direction in accordance with the transfer; and the data A set of columns in which the row of the pixel signals to be mixed in the vertical direction from among the plurality of rows of pixel signals held in the holding mechanism is simultaneously mixed in the vertical direction. The vertical mixed pixel selection mechanism for selecting the pixel signal and the combination of the combination signal for simultaneously mixing the pixel signals in the horizontal direction are selected by the vertical mixed pixel selection mechanism and the pixel signals to be mixed in the vertical direction in the horizontal direction. A horizontal mixing mechanism that mixes the pixel signals in a vertical direction, wherein a row of the pixel signals to be mixed in the vertical direction is a set of columns that simultaneously mix the pixel signals in the vertical direction or a combination column that simultaneously mixes the pixel signals in the horizontal direction. It is different for each group.

  A solid-state image pickup device according to claim 2 of the present invention is the solid-state image pickup device according to claim 1, wherein each frame generated based on the pixel signals mixed in the vertical direction and the horizontal direction simultaneously. The interlaced scanning is performed by shifting the row of the pixel signals to be mixed in the vertical direction.

  According to the preferred embodiment of the present invention, even in a high-pixel solid-state imaging device, it is possible to increase the readout speed of pixel signals, and to realize high-definition or comparable high-quality moving image recording.

The figure which shows the outline of the principal part structure of the solid-state imaging device concerning each embodiment of this invention. The figure which shows the detail of the principal part structure of the solid-state imaging device which concerns on Embodiment 1 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device which concerns on Embodiment 1 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device which concerns on Embodiment 1 of this invention. The figure which shows an example of the flame | frame produced | generated using the solid-state imaging device which concerns on Embodiment 1 of this invention. The figure which shows the detail of the principal part structure of the other example of the solid-state imaging device concerning Embodiment 1 of this invention. The figure which shows an example of the drive timing of each switch in the other example of the solid-state imaging device concerning Embodiment 1 of this invention. The figure which shows an example of the drive timing of each switch in the other example of the solid-state imaging device concerning Embodiment 1 of this invention. The figure which shows the detail of the principal part structure of the solid-state imaging device which concerns on Embodiment 2 of this invention. The figure which shows an example of the photoelectric conversion element array which mounted the color filter of the Bayer arrangement which concerns on Embodiment 2 and 5 of this invention The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 2 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 2 of this invention. The figure which shows an example of the flame | frame produced | generated using the solid-state imaging device concerning Embodiment 2 of this invention. The figure which shows an example of two types of flame | frames produced | generated using the solid-state imaging device concerning Embodiment 3 of this invention. The figure which shows an example of two types of flame | frames produced | generated using the solid-state imaging device which concerns on Embodiment 4 of this invention. The figure which shows the detail of the principal part structure of the solid-state imaging device which concerns on Embodiment 5 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 5 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 5 of this invention. The figure which shows an example of the flame | frame produced | generated using the solid-state imaging device which concerns on Embodiment 5 of this invention. The figure which shows the detail of the principal part structure of the solid-state imaging device which concerns on Embodiment 6 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 6 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 6 of this invention. The figure which shows an example of the drive timing of each switch of the solid-state imaging device concerning Embodiment 6 of this invention. The figure which shows an example of the flame | frame produced | generated using the solid-state imaging device which concerns on Embodiment 6 of this invention. The figure which shows an example of two types of flame | frames produced | generated using the solid-state imaging device which concerns on Embodiment 7 of this invention.

  Embodiments of the solid-state imaging device of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the member corresponding to the member demonstrated previously, and description is abbreviate | omitted suitably. First, a configuration common to the embodiments will be described.

  FIG. 1 is a diagram showing an outline of a main part configuration of a solid-state imaging device according to each embodiment of the present invention. In the following embodiments, a MOS solid-state imaging device will be described as an example, but the present invention can also be applied to a CCD solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device according to each embodiment includes a photoelectric conversion element array 1, a vertical signal line 2, a vertical scanning circuit 3, a constant current source 4, a column CDS circuit 5, and a horizontal A transfer circuit 6, a horizontal scanning circuit 7, an output circuit 8, and a read data selection circuit 9 are provided.

  In the photoelectric conversion element array 1, a plurality of photoelectric conversion elements 10 that convert incident light into pixel signals are arranged in a matrix. The photoelectric conversion element 10 generates an electric signal having a signal level corresponding to the intensity of incident light as a pixel signal. Each of these photoelectric conversion elements 10 constitutes each pixel.

  The vertical signal line 2 is provided for each column of the photoelectric conversion elements 10 arranged in a matrix and is commonly connected to the photoelectric conversion elements 10 in each column. The vertical scanning circuit 3 selects the photoelectric conversion elements 10 in units of rows, and generates a row selection signal for reading a signal from each photoelectric conversion element 10 in the selected row to each vertical signal line 2. Each constant current source 4 is connected to the upper end of the photoelectric conversion element array 1 of each vertical signal line 2. The vertical scanning circuit 3 generates a row selection signal so that pixel signals are transferred in units of one row in the vertical direction from the photoelectric conversion element array 1 during the vertical blanking period. Hereinafter, the vertical blanking period is referred to as a vertical BLK period.

  The column CDS circuit 5 is provided for each column of the photoelectric conversion elements 10 arranged in a matrix. The column CDS circuit 5 removes noise of pixel signals vertically transferred from the photoelectric conversion element array 1.

  The read data selection circuit 9 includes a data holding mechanism 11 provided for each column of the photoelectric conversion elements 10 arranged in a matrix. The data holding mechanism 11 is configured to hold a plurality of rows of pixel signals from which noise has been removed by the column CDS circuit 5 in units of pixels.

  Although not shown, the read data selection circuit 9 receives pixel signals for a plurality of rows held by the data holding mechanism 11 in accordance with the vertical transfer of pixel signals from the photoelectric conversion element array 1 in units of one row. A holding data selection mechanism for selecting each group of columns in which pixel signals are simultaneously mixed in the vertical direction is provided. Hereinafter, a set of columns in which pixel signals are simultaneously mixed in the vertical direction is referred to as a set of vertical mixed columns.

  Although not shown, the read data selection circuit 9 selects, for each set of vertical mixing columns, a row of pixel signals to be mixed in the vertical direction from among a plurality of rows of pixel signals held in the data holding mechanism 11. A vertical mixed pixel selection mechanism is provided.

  Further, although not shown, the read data selection circuit 9 generates a pixel signal that is selected by the vertical mixing pixel selection mechanism and mixed in the vertical direction for each set of combination columns that simultaneously mix the pixel signals in the horizontal direction. A horizontal mixing mechanism for mixing is provided. Hereinafter, a combination column that simultaneously mixes pixel signals in the horizontal direction is referred to as a horizontal mixing combination column.

  The horizontal transfer circuit 6 is connected in common to the lower end of the photoelectric conversion element array 1 of each vertical signal line 2, and the output circuit 8 is connected to one end of the horizontal transfer circuit 6. The horizontal scanning circuit 7 generates a column selection signal for sequentially reading pixel signals mixed in the vertical direction and the horizontal direction from the data selection circuit 9 to the horizontal transfer circuit 6. Hereinafter, the pixel signal mixed in the vertical direction and the horizontal direction is referred to as a mixed pixel signal. The mixed pixel signal read to the horizontal transfer circuit 6 is horizontally transferred to the output circuit 8. The output circuit 8 amplifies the horizontally transferred mixed pixel signal to generate a captured image signal. The captured image signal is transmitted to a digital signal processing circuit such as a DSP (not shown). The digital signal processing circuit generates a frame based on the captured image signal.

  Further, this solid-state imaging device is configured such that the rows of pixel signals to be mixed in the vertical direction are different for each set of vertical mixing columns or horizontal mixing combination columns. With this configuration, the number of mixed pixel signals to be read can be reduced without degrading the vertical resolution as compared with the conventional pixel mixed read mode. High-quality video recording comparable to that can be realized.

(Embodiment 1)
FIG. 2 is a diagram showing details of the main configuration of the solid-state imaging device according to Embodiment 1 of the present invention, and shows the detailed configuration of the read data selection circuit 9 and the horizontal transfer circuit 6 described above. The solid-state imaging device according to the first embodiment is configured to generate a mixed pixel signal obtained by mixing pixel signals of 2 × 2 four pixels adjacent in the vertical direction and the horizontal direction. This configuration is suitable for a monochrome solid-state imaging device in which no color filter is mounted on the photoelectric conversion element array.

  The read data selection circuit 9 of the solid-state imaging device includes three data holding circuits 12 juxtaposed in the vertical direction as the data holding mechanism 11. Therefore, the read data selection circuit 9 can hold pixel signals for three rows in units of pixels for each column.

  Hereinafter, a memory composed of the data holding circuits 12 juxtaposed in the horizontal direction is referred to as a line memory, and a line memory in each row is referred to as a line memory A or the like in order from the first row. Further, the data holding circuit 12 constituting the line memory of each row is referred to as a data holding circuit 12_A in order from the first row.

  Subsequently, a retained data selection mechanism and a vertical mixed pixel selection mechanism included in the read data selection circuit 9 of the solid-state imaging device will be described. Here, a data selection switch 13 is provided for each data holding circuit 12 as a holding data selection mechanism and a vertical mixed pixel selection mechanism. Hereinafter, the data selection switch 13 provided for the data holding circuit 12_A and the like in each row is referred to as a data selection switch 13_A and the like in order from the first row.

  As the pixel signals are vertically transferred from the photoelectric conversion element array 1 in units of one row, the data selection switches 13 are turned on and off to operate the pixels corresponding to a plurality of rows held by the data holding mechanism 11. A signal can be selected for each set of vertical mixing columns. Specifically, the pixel signal is held in the data holding circuit 12 connected to the data selection switch 13 in the on state.

  In addition, by operating each data selection switch 13 on and off, the pixel signal rows to be mixed in the vertical direction from among the plurality of pixel signals held in the data holding mechanism 11 are vertically mixed. You can select for each set of columns. Specifically, among the pixel signals held in the data holding circuit 12 provided on the same vertical signal line 2, the pixel signals held in the data holding circuit 12 connected to the data selection switch 13 in the on state. Are mixed.

  In the first embodiment, the set of vertical mixing columns is a combination of two adjacent rows that are skipped by two rows. Specifically, from the first vertical mixed column set consisting of the first column, the second column, the fifth column, the sixth column, etc., the third column, the fourth column, the seventh column, the eighth column, etc. There is a second set of vertical mixing columns.

  Hereinafter, the data holding circuits 12_A and the like in each row provided in the first set of vertical mixed columns are referred to as the data holding circuits 12_Aodd and the like in order from the first row. In addition, the data selection switches 13_A and the like of each row provided in the set of the first vertical mixed columns are referred to as data selection switches 13_Aodd and the like in order from the first row. Similarly, the data holding circuits 12_A and the like of each row provided in the second set of vertical mixed columns are referred to as data holding circuits 12_Aeven and the like in order from the first row, and The data selection switch 13_A and the like are sequentially referred to as a data selection switch 13_Aeven and the like from the first row.

  The data selection switches 13 in each row are connected to different control signal lines SW in units of vertical mixed columns, and are turned on and off by signals transmitted through the control signal lines SW.

  Hereinafter, the control signal lines SW connected to the data selection switches 13_Aodd and the like of each row provided in the first vertical mixed column group are referred to as control signal lines SW_Aodd and the like in order from the first row. Similarly, the control signal lines SW connected to the data selection switches 13_Aeven and the like of each row provided in the second set of vertical mixed columns are referred to as control signal lines SW_Aeven and so on in order from the first row.

  Next, the horizontal mixing mechanism provided in the read data selection circuit 9 of this solid-state imaging device will be described. Here, as a horizontal mixing mechanism, a horizontal short-circuit switch 14 connected between the vertical signal lines 2 constituting each horizontal mixing combination column is provided. By operating each horizontal short-circuit switch 14 on and off, the pixel signals selected by the data selection switch 13 and mixed in the vertical direction can be mixed in the horizontal direction for each set of horizontal mixing combination columns. Specifically, among the pixel signals held in the data holding circuit 12 provided in each vertical signal line 2 connected to the horizontal short-circuit switch 14 in the ON state, the pixel signal is selected by the data selection switch 13 and mixed in the vertical direction. The pixel signals to be processed are also mixed in the horizontal direction.

  In the first embodiment, the horizontal mixed combination column is composed of two columns that are adjacent to each other, and the horizontal mixed combination columns are combined so as not to include the same column. Specifically, the horizontal mixed combination column is a group of the first column and the second column, a group of the third column and the fourth column, and the like. On the other hand, the set of horizontal mixed combination rows is a combination of two adjacent rows skipped by two rows, and is the same combination as the set of vertical mixed rows described above. Specifically, the first horizontal mixed combination column set includes the first column, the second column, the fifth column, the sixth column, and the like, and the second horizontal mixed combination column set includes the third column, It consists of the fourth column, the seventh column, the eighth column, and the like.

  Different control signal lines Mix are connected to the horizontal short-circuit switch 14 in units of horizontal mixed combination columns, and ON and OFF are operated by signals transmitted through the control signal lines Mix.

  Hereinafter, the horizontal short-circuit switch 14 provided in the first horizontal mixed combination column set is referred to as a horizontal short-circuit switch 14_odd, and the horizontal short-circuit switch 14 provided in the second horizontal mixed combination column set is referred to as a horizontal short-circuit switch 14_even. The control signal line Mix connected to the horizontal short-circuit switch 14_odd is referred to as a control signal line Mix_odd, and the control signal line Mix connected to the horizontal short-circuit switch 14_even is referred to as a control signal line Mix_even.

  Subsequently, the horizontal transfer circuit 6 of the solid-state imaging device will be described. Here, the horizontal transfer circuit 6 includes a column selection switch 15 and a horizontal common signal line 16. Each column selection switch 15 is provided in the vicinity of the lower end of the photoelectric conversion element array 1 of each vertical signal line 2. The horizontal common signal line 16 is commonly connected to the lower end of the photoelectric conversion element array 1 of each vertical signal line 2.

  The column selection signal generated by the horizontal scanning circuit 7 is a signal for operating the column selection switch 15 on and off. The mixed pixel signal is read out from the column selection switch 15 in the on state to the horizontal common signal line 16 and transferred to the output circuit 8.

  As described above, in the solid-state imaging device in which the read data selection circuit 9 is configured, the row of pixel signals to be mixed in the vertical direction is controlled by controlling the drive timing of the data selection switch 13 and the horizontal short-circuit switch 14. Each set of columns can be different. Specifically, in the first embodiment, pixel signals shifted by one row between the first and second sets of vertical mixing columns are mixed in the vertical direction.

  Next, drive timings of the data selection switch 13 and the horizontal short-circuit switch 14 in the first embodiment will be described with reference to FIGS. As shown in FIG. 3 and FIG. 4, when the pixel signal of the (n−1) th row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Codd, the data selection switch 13_A and the data in the next vertical BLK period The selection switch 13_B is sequentially turned on, and the data holding circuit 12_A and the data holding circuit 12_B sequentially hold the pixel signal of the nth row and the pixel signal of the (n + 1) th row.

  Then, in the next horizontal readout period, as shown in FIG. 3, the data selection switch 13_Aodd, the data selection switch 13_Codd, and the horizontal short-circuit switch 14_odd are turned on, and n−1 is added to the first vertical mixed column set. FIG. 4 shows a mixed pixel signal obtained by mixing the pixel signal of the row and the pixel signal of the n-th row in the horizontal and mixed column units in the vertical direction and the horizontal direction, and horizontally transferring these mixed pixel signals. As described above, the data selection switch 13_Aeven, the data selection switch 13_Beven, and the horizontal short-circuit switch 14_even are turned on, and the pixel signal of the nth row and the pixel signal of the (n + 1) th row are horizontally mixed in the second vertical mixed column set. Generates mixed pixel signals mixed in the vertical and horizontal directions in units of combination columns, and those mixed pixel signals To the horizontal transfer.

  Similarly, after the data holding circuit 12_C holds the pixel signal of the (n + 2) th row in the next vertical BLK period and the data holding circuit 12_A holds the pixel signal of the (n + 3) th row, in the next horizontal readout period, As shown in FIG. 3, the first vertical mixed column set includes a mixed pixel signal obtained by mixing the pixel signal of the (n + 1) th row and the pixel signal of the (n + 2) th row in the horizontal and mixed combination units in the vertical direction and the horizontal direction. As shown in FIG. 4, the second vertical mixing column set is a mixture in which the pixel signal of the (n + 2) th row and the pixel signal of the (n + 3) th row are mixed in the vertical and horizontal directions in units of horizontal mixing combination columns. A pixel signal is generated. Thereafter, similarly, pixel signals shifted by one row between the first and second sets of vertical mixing columns are mixed in the vertical direction and the horizontal direction.

  FIG. 5 shows an example of a frame generated using the solid-state imaging device according to the first embodiment. FIG. 5B shows a frame generated by using the solid-state imaging device according to the first embodiment when the photoelectric conversion element array 1 is an 8 × 6 pixel array as shown in FIG. ing. For comparison, FIG. 5C shows a frame generated using a conventional solid-state imaging device. As shown in FIG. 5 (c), the conventional solid-state imaging device performs 2 × 2 pixel mixing for all pixels, whereas the solid-state imaging device according to the first embodiment is shown in FIG. 5 (b). As shown in FIG. 4, since the pixel signals shifted by one row between the first and second vertical mixed column groups are mixed in the vertical direction and the horizontal direction, the number of mixed pixel signals to be read out without deteriorating the vertical resolution The pixel signal readout speed can be increased.

  Here, the case where the control signal line SW is provided for each set of vertical mixing columns in the line memory of each row has been described as a configuration for operating the data selection switch 13 on and off in units of vertical mixing columns. However, instead of the control signal line SW, by providing a logic circuit for operating the data selection switch 13 on and off using the control signal line Mix provided for each set of the horizontal mixed combination column, the line memory of each row The configuration of the solid-state imaging device may be simplified by reducing the number of control signal lines SW provided for the.

  For example, as shown in FIG. 6, an AND circuit 17_odd having one input terminal connected to a control signal line Mix_odd provided for the first horizontal mixed combination column set and a second horizontal mixed combination column set An AND circuit 17_even having one input terminal connected to the control signal line Mix_even provided for the line memory of each row is provided, and the AND circuit 17_odd is provided in the first vertical mixed column set. If the switch 13 is turned on and off, and the AND circuit 17_even operates to turn on and off the data selection switch 13 provided in the set of the second vertical mixed columns, 1 for the line memory of each row. Since only the control signal line SW needs to be provided, the configuration of the solid-state imaging device can be simplified.

  7 and 8 are diagrams illustrating an example of drive timings of the data selection switch 13 and the horizontal short-circuit switch 14 in the solid-state imaging device having the configuration illustrated in FIG. When the data selection switch 13 and the horizontal short-circuit switch 14 are driven as shown in FIGS. 7 and 8, like the solid-state imaging device having the configuration shown in FIG. 2, between the first and second vertical mixing columns. Pixel signals shifted by one line can be mixed in the vertical direction.

(Embodiment 2)
FIG. 9 is a diagram showing details of the main configuration of the solid-state imaging device according to Embodiment 2 of the present invention, and shows the detailed configuration of the read data selection circuit 9 and the horizontal transfer circuit 6 described above. The solid-state imaging device according to the second embodiment is configured to generate a mixed pixel signal obtained by mixing pixel signals of 2 × 2 adjacent pixels by skipping one pixel in the vertical direction and the horizontal direction. This configuration is suitable for a solid-state imaging device in which a Bayer array color filter is mounted on a photoelectric conversion element array.

  FIG. 10 shows an example of a photoelectric conversion element array 1 on which a Bayer color filter is mounted. In the Bayer array, the R filter, the Gr filter, the Gb filter, and the B filter are arranged so as to skip one pixel in the vertical direction and the horizontal direction, respectively. Therefore, if the solid-state imaging device according to Embodiment 2 is applied to a solid-state imaging device in which a Bayer array color filter is mounted on a photoelectric conversion element array, a mixed pixel signal obtained by mixing pixel signals of adjacent four pixels of the same color. Can be generated. The positioning of the R filter, Gr filter, Gb filter, and B filter with respect to the photoelectric conversion element array 1 is not limited to that shown in FIG.

  The read data selection circuit 9 of this solid-state imaging device includes five data holding circuits 12 juxtaposed in the vertical direction as the data holding mechanism 11. Therefore, the read data selection circuit 9 can hold pixel signals for five rows in units of pixels for each column.

  Also in the second embodiment, as in the first embodiment described above, the line memory of each row is referred to as a line memory A or the like in order from the first row, and the data holding circuit 12 constituting the line memory of each row is designated as the first row. The data selection circuit 13_A and the like are sequentially referred to as the data holding circuit 12_A, and the data selection switch 13 provided for the data holding circuit 12_A and the like in each row is sequentially referred to as the data selection switch 13_A and the like from the first row.

  In the second embodiment, the set of vertically mixed rows is a combination of four rows that are adjacent to each other by skipping four rows. Specifically, from the first vertical mixed column set consisting of the first column to the fourth column, the ninth column to the twelfth column, the fifth column to the eighth column, the thirteenth column to the sixteenth column, etc. There is a second set of vertical mixing columns.

  Also in the second embodiment, as in the first embodiment described above, the data holding circuit 12_A and the like and the data selection switch 13_A and the like of each row provided in the first vertical mixed column set are sequentially transmitted from the first row. The holding circuit 12_Aod, etc. and the data selection switch 13_Aodd, etc., the data holding circuit 12_A, etc. and the data selection switch 13_A, etc. of each row provided in the second vertical mixed column set are sequentially arranged from the first row to the data holding circuit 12_Aeven, etc. This is referred to as a data selection switch 13_Aeven or the like. In addition, the control signal lines SW_Aodd and the like which are connected to the data selection switch 13_Aodd and the data selection switch 13_Aeven and the like of each row provided in the set of the first and second vertical mixed columns are sequentially controlled from the first row and the control signal line SW_Aodd and the like. This is referred to as a signal line SW_Aeven.

  Further, in the second embodiment, the horizontal mixed combination column is composed of two columns skipped by one column, and the horizontal mixed combination columns are combined so as not to include the same column. Specifically, the horizontal mixed combination column is a combination of the first column and the third column, a group of the second column and the fourth column, a group of the fifth column and the seventh column, a group of the sixth column and the eighth column. Etc. On the other hand, the set of horizontal mixed combination columns is a combination of four consecutive columns skipped by four columns, and is the same combination as the above-described set of vertical mixed columns. Specifically, the first horizontal combination combination column set includes the first to fourth columns, the ninth column to the twelfth column, etc., and the second horizontal mixing combination column set includes the fifth to sixth columns. It consists of the 8th, 13th to 16th columns.

  Also in the second embodiment, as in the first embodiment, the horizontal short-circuit switch 14 provided in the set of the first horizontal mixing combination row is replaced with the horizontal short-circuit switch 14_odd and the second horizontal mixing combination row set. The horizontal short-circuit switch 14 provided in FIG. 4 is referred to as a horizontal short-circuit switch 14_even, the control signal line Mix connected to the horizontal short-circuit switch 14_odd is the control signal line Mix_odd, and the control signal line Mix connected to the horizontal short-circuit switch 14_even is the control signal line Mix_even. Call it.

  As described above, in the solid-state imaging device in which the read data selection circuit 9 is configured, the row of pixel signals to be mixed in the vertical direction is controlled by controlling the drive timing of the data selection switch 13 and the horizontal short-circuit switch 14. Each set of columns can be different. Specifically, in the second embodiment, pixel signals shifted by two rows between the first and second sets of vertical mixing columns are mixed in the vertical direction.

  Next, drive timings of the data selection switch 13 and the horizontal short-circuit switch 14 in the second embodiment will be described with reference to FIGS. As shown in FIGS. 11 and 12, the pixel signal of the nth row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Aodd, and the pixel signal of the n + 1th row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Bodd. And the pixel signal of the (n + 2) th row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Codd and the data holding circuit 12_Ceven, the data selection switch 13_D and the data selection switch 13_E in the next vertical BLK period. Are sequentially turned on, and the data holding circuit 12_D and the data holding circuit 12_E sequentially hold the pixel signal of the n + 3 row and the pixel signal of the n + 4 row.

  Then, in the next horizontal readout period, as shown in FIG. 11, the data selection switch 13_Aodd, the data selection switch 13_Codd, and the horizontal short-circuit switch 14_odd are turned on, and the first row of vertical mixed columns is set to the nth row. 12 and the pixel signal of the (n + 2) -th row are mixed in the vertical and horizontal directions in units of horizontal mixing combination columns, and the mixed pixel signals are horizontally transferred, and as shown in FIG. , The data selection switch 13_Ceven, the data selection switch 13_Even, and the horizontal short-circuit switch 14_even are turned on, and the pixel signal of the (n + 2) th row and the pixel signal of the (n + 4) th row are combined into the horizontal mixed combination column in the second vertical mixing column set. Generates mixed pixel signals mixed vertically and horizontally in units and mixes them The element signals to the horizontal transfer.

  Similarly, in the next vertical BLK period, the pixel signal in the n + 5th row is held in the data holding circuit 12_Aodd and the data holding circuit 12_Ceven, and the pixel signal in the n + 6th row is held in the data holding circuit 12_Codd and the data holding circuit 12_Even. After that, in the next horizontal readout period, as shown in FIG. 11, in the first vertical mixed column set, the pixel signal of the (n + 1) th row and the pixel signal of the (n + 3) th row are arranged in the vertical direction in units of horizontal mixed combination columns Then, a mixed pixel signal mixed in the horizontal direction is generated. As shown in FIG. 12, in the second vertical mixed column set, the pixel signal of the (n + 3) th row and the pixel signal of the (n + 5) th row are horizontally mixed combination column unit. To generate a mixed pixel signal mixed in the vertical and horizontal directions. Thereafter, similarly, pixel signals shifted by two rows between the first and second vertical mixed column groups are mixed in the vertical direction and the horizontal direction.

  FIG. 13A shows an example of a frame generated using the solid-state imaging device according to the second embodiment. For comparison, FIG. 13B shows a frame generated using a conventional solid-state imaging device. As shown in FIG. 13 (b), the conventional solid-state imaging device performs adjacent pixel mixing of 2 × 2 by skipping one pixel in the vertical and horizontal directions for all pixels. As shown in FIG. 13A, the solid-state imaging device according to No. 2 mixes the pixel signals shifted by two rows between the first and second vertical mixing column sets in the vertical direction and the horizontal direction. The number of mixed pixel signals to be read can be reduced without degrading the resolution, and the pixel signal read speed can be increased.

  Here, the case where the control signal line SW is provided for each set of vertical mixing columns in the line memory of each row has been described as a configuration for operating the data selection switch 13 on and off in units of vertical mixing columns. However, instead of the control signal line SW, by providing a logic circuit for operating the data selection switch 13 on and off using the control signal line Mix provided for each set of the horizontal mixed combination column, the line memory of each row The configuration of the solid-state imaging device may be simplified by reducing the number of control signal lines SW provided for the.

(Embodiment 3)
FIG. 14 is a diagram showing an example of two types of frames generated using the solid-state imaging device according to Embodiment 3 of the present invention. The frame shown in FIG. 14A is the same as that in Embodiment 1 described above. This is the same as the frame shown in FIG.

  The configuration of the solid-state imaging device according to the third embodiment is the same as the configuration shown in FIG. 2 described in the first embodiment. In the third embodiment, the data selection switch 13 and the horizontal short-circuit switch 14 are driven so that the rows of pixel signals to be mixed simultaneously in the vertical direction are shifted for each frame, and the frame shown in FIG. The difference from Embodiment 1 described above is that interlace scanning is performed by alternately generating the frames shown in b).

  Specifically, when the frame shown in FIG. 14B is generated, the row of pixel signals to be mixed in the first set of vertical mixing columns is changed into the frame shown in FIG. The pixel signal row to be mixed in the second vertical mixed column set is replaced with the pixel signal row to be mixed in the second vertical mixed column set when the frame shown in FIG. Swap to the row of pixel signals to be mixed in the set of one vertical mixing column.

  In this manner, the row of pixel signals to be mixed in the first set of vertical mixing columns and the row of pixel signals to be mixed in the second set of vertical mixing columns are exchanged for each frame, and the frame shown in FIG. And by alternately generating the frames shown in FIG. 14B and making them interlaced, it is possible to further improve the moving image quality without changing the still image quality.

(Embodiment 4)
FIG. 15 is a diagram showing an example of two types of frames generated using the solid-state imaging device according to Embodiment 4 of the present invention. The frame shown in FIG. 15A is the same as that in Embodiment 2 described above. This is the same as the frame shown in FIG.

  The configuration of the solid-state imaging device according to the fourth embodiment is the same as the configuration shown in FIG. 9 described in the second embodiment. In the fourth embodiment, the data selection switch 13 and the horizontal short-circuit switch 14 are driven so that the rows of pixel signals to be mixed simultaneously in the vertical direction are shifted for each frame, and the frame shown in FIG. It differs from the second embodiment described above in that interlaced scanning is performed by alternately generating the frames shown in b).

  Specifically, when the frame shown in FIG. 15B is generated, the row of pixel signals to be mixed in the first set of vertical mixing columns is changed into the frame shown in FIG. The pixel signal rows to be mixed in the second vertical mixing column set are replaced with the pixel signal rows to be mixed in the second vertical mixing column set when the frame shown in FIG. 15A is generated. Swap to the row of pixel signals to be mixed in the set of one vertical mixing column.

  As described above, the row of pixel signals to be mixed in the first set of vertical mixing columns and the row of pixel signals to be mixed in the second set of vertical mixing columns are exchanged for each frame, and the frame shown in FIG. And by alternately generating the frames shown in FIG. 15B and making them interlaced, it is possible to further improve the moving image quality without changing the still image quality.

(Embodiment 5)
FIG. 16 is a diagram showing details of the main configuration of the solid-state imaging device according to Embodiment 5 of the present invention, and shows the detailed configuration of the read data selection circuit 9 and the horizontal transfer circuit 6 described above. The solid-state imaging device according to the fifth embodiment is configured to generate a mixed pixel signal obtained by mixing pixel signals of adjacent 2 × 2 four pixels by skipping one pixel in the vertical direction and the horizontal direction. This configuration is suitable for a solid-state imaging device in which a Bayer array color filter is mounted on a photoelectric conversion element array. That is, if the solid-state imaging device according to the fifth embodiment is applied to a solid-state imaging device in which a Bayer array color filter is mounted on a photoelectric conversion element array, a mixed pixel signal obtained by mixing pixel signals of adjacent four pixels of the same color. Is generated.

  The read data selection circuit 9 of this solid-state imaging device includes four data holding circuits 12 juxtaposed in the vertical direction as the data holding mechanism 11. Therefore, the read data selection circuit 9 can hold pixel signals for four rows in units of pixels for each column.

  Also in the fifth embodiment, as in the first embodiment, the line memory of each row is referred to as the line memory A in order from the first row, and the data holding circuit 12 constituting the line memory of each row is designated as the first row. The data selection circuit 13_A and the like are sequentially referred to as the data holding circuit 12_A, and the data selection switch 13 provided for the data holding circuit 12_A and the like in each row is sequentially referred to as the data selection switch 13_A and the like from the first row.

  In the fifth embodiment, the set of vertically mixed columns is a combination of adjacent columns by skipping one column. Specifically, there are a first set of vertical mixed columns composed of odd columns and a set of second vertical mixed columns composed of even columns.

  Also in the fifth embodiment, as in the first embodiment described above, the data holding circuits 12_A and the like and the data selection switches 13_A and the like of each row provided in the first set of vertical mixed columns are sequentially transmitted from the first row. The holding circuit 12_Aod, etc. and the data selection switch 13_Aodd, etc., the data holding circuit 12_A, etc. and the data selection switch 13_A, etc. of each row provided in the second vertical mixed column set are sequentially arranged from the first row to the data holding circuit 12_Aeven, etc. This is referred to as a data selection switch 13_Aeven or the like. In addition, the control signal lines SW_Aodd and the like which are connected to the data selection switch 13_Aodd and the data selection switch 13_Aeven and the like of each row provided in the set of the first and second vertical mixed columns are sequentially controlled from the first row and the control signal line SW_Aodd and the like. This is referred to as a signal line SW_Aeven.

  Further, in the fifth embodiment, the horizontal mixed combination row is composed of two rows skipped by one row. However, unlike Embodiment 2 described above, the same row is included between the horizontal mixed combination rows. Specifically, the horizontal mixed combination column is a set of the first and third columns, a set of the second and fourth columns, a set of the third and fifth columns, a set of the fourth and sixth columns. Etc. On the other hand, there are four sets of horizontal mixed combination rows, and each set is formed by shifting the start end row by one row and skipping one row. Specifically, the first set of horizontal mixed combination columns is a combination of odd columns, and includes the first column, the third column, the fifth column, the seventh column, and the like. The set of the second horizontal mixed combination column is a combination of odd columns with a column shifted by two columns from the start column of the first horizontal mixed combination column set, the third column, the fifth column, It consists of the seventh and ninth rows. The third set of horizontal mixed combination columns is a combination of even columns, and is composed of the second column, the fourth column, the sixth column, the eighth column, and the like. The set of the fourth horizontal mixed combination column is a combination of even columns with the column shifted by two columns from the start column of the third horizontal mixed combination column set as the start column, the fourth column, the sixth column, It consists of the 8th and 10th rows.

  Hereinafter, the horizontal short-circuit switch 14 provided in the first horizontal mixing combination row set is the horizontal short-circuit switch 14_1st, the horizontal short-circuit switch 14 provided in the second horizontal mixing combination row set is the horizontal short-circuit switch 14_2nd, and the third The horizontal short-circuit switch 14 provided in the set of horizontal mixing combination rows is referred to as a horizontal short-circuit switch 14_3rd, and the horizontal short-circuit switch 14 provided in the fourth horizontal mixing combination row set is referred to as a horizontal short-circuit switch 14_4th. The control signal line Mix connected to the horizontal short-circuit switch 14_1st is a control signal line Mix_1st, the control signal line Mix connected to the horizontal short-circuit switch 14_2nd is connected to the control signal line Mix_2nd, and the control signal line Mix connected to the horizontal short-circuit switch 14_3rd is a control signal. The control signal line Mix connected to the line Mix_3rd and the horizontal short-circuit switch 14_4th is referred to as a control signal line Mix_4th.

  As described above, in the solid-state imaging device in which the read data selection circuit 9 is configured, the row of pixel signals to be mixed in the vertical direction is controlled by controlling the drive timing of the data selection switch 13 and the horizontal short-circuit switch 14. Each combination group can be different. Specifically, in the fifth embodiment, pixel signals shifted by one row between the first to fourth horizontal mixed combination columns are mixed in the vertical direction.

  Subsequently, drive timings of the data selection switch 13 and the horizontal short-circuit switch 14 in the fifth embodiment will be described with reference to FIGS. 17 and 18. As shown in FIGS. 17 and 18, the pixel signal of the nth row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Aodd, and the pixel signal of the (n + 1) th row of the photoelectric conversion element array 1 is held in the data holding circuit 12_Bodd. In the next vertical BLK period, the data selection switch 13_C and the data selection switch 13_D are sequentially turned on, and the n + 2 row pixel signal and the n + 3 row are sequentially supplied to the data holding circuit 12_C and the data holding circuit 12_D. The eye pixel signal is held.

  Then, in the next horizontal readout period, as shown in FIG. 17, first, the data selection switch 13_Aodd, the data selection switch 13_Codd, and the horizontal short-circuit switch 14_1st are turned on, and n The pixel signal of the row and the pixel signal of the (n + 2) th row are mixed in the horizontal mixing combination column unit in the vertical direction and the horizontal direction to generate a mixed pixel signal, and these mixed pixel signals are horizontally transferred, and then the data selection switch 13_Bodd Then, the data selection switch 13_Dodd and the horizontal short-circuit switch 14_2nd are turned on, and the pixel signal of the (n + 1) th row and the pixel signal of the (n + 3) th row are set in the vertical direction in units of the horizontal mixing combination column in the second horizontal mixing combination column set. And mixed pixel signals that are mixed in the horizontal direction Signal to the horizontal transfer.

  Thereafter, in the next vertical BLK period, as shown in FIGS. 17 and 18, the data selection switch 13_A and the data selection switch 13_B are sequentially turned on, and the data holding circuit 12_A and the data holding circuit 12_B are sequentially turned to the n + 4th row. The pixel signal and the pixel signal in the n + 5th row are held, and in the next horizontal readout period, as shown in FIG. 18, first, the data selection switch 13_Aeven, the data selection switch 13_Ceven, and the horizontal short-circuit switch 14_3rd are turned on. 3. A mixed pixel signal is generated by mixing the pixel signal of the (n + 2) th row and the pixel signal of the (n + 4) th row in the vertical and horizontal directions in units of the horizontal mixed combination column in a set of three horizontal mixed combination columns. Are transferred horizontally, then the data selection switch 13_Beven, the data selection switch H_13_Dev and horizontal short-circuit switch 14_4th are turned on, and the pixel signals of the (n + 3) th row and the (n + 5) th row of the pixel signals in the fourth horizontal mixing combination column are set in the vertical and horizontal directions in units of horizontal mixing combination columns. Mixed pixel signals are generated, and these mixed pixel signals are horizontally transferred.

  Similarly, in the next vertical BLK period, as shown in FIGS. 17 and 18, the data selection switch 13_Codd and the data selection switch 13_Aeven are turned on, and the data holding circuit 12_Codd and the data holding circuit 12_Aeven are in the (n + 6) th row. After holding the pixel signal, the data selection switch 13_Dodd and the data selection switch 13_Beven are turned on, the data holding circuit 12_Dodd and the data holding circuit 12_Beven hold the pixel signal of the (n + 7) th row, and in the next horizontal readout period, As shown in FIG. 17, a mixed pixel signal obtained by mixing the pixel signal of the (n + 4) th row and the pixel signal of the (n + 6) th row in the first horizontal mixed combination column in the vertical and horizontal directions in units of the horizontal mixed combination column. Generate and it After the horizontal transfer of the mixed pixel signals, the pixel signal of the (n + 5) th row and the pixel signal of the (n + 7) th row are mixed in the second horizontal mixed combination column in the vertical and horizontal directions in units of the horizontal mixing combination column. The mixed pixel signals are generated, the mixed pixel signals are horizontally transferred, and in the next vertical BLK period, as shown in FIGS. 17 and 18, the data selection switch 13_Aodd and the data selection switch 13_Ceven are turned on, and the data After holding the pixel signals of the (n + 8) th row in the holding circuit 12_Aodd and the data holding circuit 12_Ceven, the data selection switch 13_Bodd and the data selection switch 13_Deven are turned on, and the data holding circuit 12_Bodd and the data holding circuit 12_Deven are turned on in the n + 9th row. Hold pixel signal In the next horizontal readout period, as shown in FIG. 18, the pixel signal of the (n + 6) th row and the pixel signal of the (n + 8) th row are arranged in the vertical direction in units of the horizontal mixing combination column in the third horizontal combination combination column set. After generating mixed pixel signals mixed in the horizontal direction and horizontally transferring the mixed pixel signals, the pixel signals of the (n + 7) th row and the (n + 9) th row of pixel signals are horizontally transferred to the set of the fourth horizontal mixed combination column. A mixed pixel signal mixed in the vertical direction and the horizontal direction is generated in units of mixed combination columns, and these mixed pixel signals are horizontally transferred. Thereafter, similarly, the pixel signals shifted by one row between the first to fourth horizontal mixing combination columns are mixed in the vertical direction and the horizontal direction.

  FIG. 19 shows an example of a frame generated using the solid-state imaging device according to the fifth embodiment. As shown in FIG. 19, the solid-state imaging device according to the fifth embodiment mixes pixel signals shifted by one row between the first to fourth horizontal mixing combination columns in the vertical direction and the horizontal direction. Therefore, the number of mixed pixel signals to be read can be further reduced as compared with the above-described second embodiment without deteriorating the vertical resolution, and the reading speed of the pixel signals can be increased.

  Here, the case where the control signal line SW is provided for each set of vertical mixing columns in the line memory of each row has been described as a configuration for operating the data selection switch 13 on and off in units of vertical mixing columns. However, instead of the control signal line SW, by providing a logic circuit for operating the data selection switch 13 on and off using the control signal line Mix provided for each set of the horizontal mixed combination column, the line memory of each row The configuration of the solid-state imaging device may be simplified by reducing the number of control signal lines SW provided for the.

(Embodiment 6)
FIG. 20 is a diagram showing details of the main configuration of the solid-state imaging device according to Embodiment 6 of the present invention, and shows the detailed configuration of the read data selection circuit 9 and the horizontal transfer circuit 6 described above. The solid-state imaging device according to the sixth embodiment is configured to generate a mixed pixel signal obtained by mixing pixel signals of 3 × 3 9 pixels adjacent in the vertical direction and the horizontal direction. This configuration is suitable for a monochrome solid-state imaging device in which no color filter is mounted on the photoelectric conversion element array.

  The read data selection circuit 9 of this solid-state imaging device includes five data holding circuits 12 juxtaposed in the vertical direction as the data holding mechanism 11. Therefore, the read data selection circuit 9 can hold pixel signals for five rows in units of pixels for each column.

  Also in the sixth embodiment, as in the first embodiment described above, the line memory of each row is referred to as a line memory A or the like in order from the first row, and the data holding circuit 12 constituting the line memory of each row is designated as the first row. The data selection circuit 13_A and the like are sequentially referred to as the data holding circuit 12_A, and the data selection switch 13 provided for the data holding circuit 12_A and the like in each row is sequentially referred to as the data selection switch 13_A and the like from the first row.

  Further, in the sixth embodiment, the set of vertically mixed columns is a combination of three consecutively adjacent columns by skipping six columns. Specifically, the first vertical mixed column set including the first column, the third column, the tenth column, the twelfth column, and the like, the fourth column, the sixth column, the thirteenth column, the fifteenth column, and the like. There are a second vertical mixing column set and a third vertical mixing column set consisting of the 7th to 9th rows, the 16th to 18th rows, and the like.

  In the sixth embodiment, the data holding circuit 12_A and the like and the data selection switch 13_A and the like in each row provided in the set of the first vertical mixed columns are sequentially changed from the first row to the data holding circuit 12_A1st and the like and the data selection switch 13_A1st and the like. The data holding circuits 12_A and the like and the data selection switches 13_A and the like in each row provided in the second vertical mixed column set are referred to as the data holding circuits 12_A2nd and the data selection switches 13_A2nd and so on in order from the first row. The data holding circuit 12_A and the like and the data selection switch 13_A and the like of each row provided in the set of the vertical mixed columns are referred to as the data holding circuit 12_A3rd and the data selection switch 13_A3rd and the like in order from the first row. In addition, the control signal line SW connected to the data selection switch 13_A3nd, the data selection switch 13_A3nd, and the data selection switch 13_A3rd of each row provided in the set of the first, second, and third vertical mixed columns is the first row. The control signal line SW_A1st and the like, the control signal line SW_A2nd and the like, and the control signal line SW_A3rd and the like are sequentially referred to.

  Further, in the sixth embodiment, the horizontal mixed combination column is composed of three consecutive columns that are adjacent to each other, and the horizontal mixed combination columns are combined so as not to include the same column. Specifically, the horizontal mixed combination columns are the first to third column groups, the fourth to sixth column groups, the seventh to ninth columns, and the like. On the other hand, the set of horizontal mixing combination rows is a combination of three consecutive rows that are skipped by six rows, and is the same combination as the above-described set of vertical mixing rows. Specifically, the first horizontal mixed combination column set includes the first to third columns, the tenth column to the twelfth column, and the second horizontal mixed combination column set includes the fourth to fourth columns. It consists of the 6th, 13th to 15th rows, etc., and the third set of horizontal mixed combination rows consists of the 7th to 9th rows, the 16th to 18th rows, etc.

  Hereinafter, the horizontal short-circuit switch 14 provided in the first horizontal mixing combination row set is the horizontal short-circuit switch 14_1st, the horizontal short-circuit switch 14 provided in the second horizontal mixing combination row set is the horizontal short-circuit switch 14_2nd, and the third The horizontal short-circuit switch 14 provided in the set of horizontal mixed combination rows is referred to as a horizontal short-circuit switch 14_3rd. The control signal line Mix connected to the horizontal short-circuit switch 14_1st is a control signal line Mix_1st, the control signal line Mix connected to the horizontal short-circuit switch 14_2nd is connected to the control signal line Mix_2nd, and the control signal line Mix connected to the horizontal short-circuit switch 14_3rd is a control signal. This is referred to as a line Mix_3rd.

  As described above, in the solid-state imaging device in which the read data selection circuit 9 is configured, the row of pixel signals to be mixed in the vertical direction is controlled by controlling the drive timing of the data selection switch 13 and the horizontal short-circuit switch 14. Each set of columns can be different. Specifically, in the sixth embodiment, pixel signals shifted by one row between the first to third sets of vertical mixing columns are mixed in the vertical direction.

  Next, drive timings of the data selection switch 13 and the horizontal short-circuit switch 14 in the sixth embodiment will be described with reference to FIGS. As shown in FIGS. 21 to 23, the pixel signal of the (n−1) th row of the photoelectric conversion element array 1 is held in the data holding circuit 12_D1st, and the photoelectric conversion element array 1 is stored in the data holding circuit 12_E1st and the data holding circuit 12_E2nd. When the pixel signal of the n-th row is held, in the next vertical BLK period, the data selection switch 13_A, the data selection switch 13_B, and the data selection switch 13_C are sequentially turned on, and the data holding circuit 12_A and the data holding circuit 12_B and the data holding circuit 12_C sequentially hold the pixel signal of the (n + 1) th row, the pixel signal of the (n + 2) th row, and the pixel signal of the (n + 3) th row.

  Then, in the next horizontal readout period, as shown in FIG. 21, the data selection switch 13_A1st, the data selection switch 13_D1st, the data selection switch 13_E1st, and the horizontal short-circuit switch 14_1st are turned on to set the first vertical mixed column group. And generating a mixed pixel signal in which the pixel signal of the (n-1) th row, the pixel signal of the (n-1) th row, and the pixel signal of the (n + 1) th row are mixed in the vertical and horizontal directions in units of horizontal mixed combination columns. After the horizontal transfer of the signal, as shown in FIG. 22, the data selection switch 13_A2nd, the data selection switch 13_B2nd, the data selection switch 13_E2nd, and the horizontal short-circuit switch 14_2nd are turned on to form the second vertical mixed column set. , Pixel signal of the nth row, pixel signal of the (n + 1) th row and image of the (n + 2) th row A mixed pixel signal in which signals are mixed in the vertical and horizontal directions in units of horizontal mixed combination columns is generated, and these mixed pixel signals are horizontally transferred. Thereafter, as shown in FIG. 23, a data selection switch 13_A3rd, data selection The switch 13_B3rd, the data selection switch 13_C3rd, and the horizontal short-circuit switch 14_C3rd are turned on, and the pixel signal of the (n + 1) th row, the pixel signal of the (n + 2) th row, and the pixel signal of the (n + 3) th row are supplied to the third vertical mixed column set. Mixed pixel signals mixed in the vertical direction and the horizontal direction are generated in units of horizontal mixed combination columns, and these mixed pixel signals are horizontally transferred.

  Similarly, in the next vertical BLK period, the data selection switch 13_A is turned on so that the data holding circuit 12_A holds the pixel signal of the (n + 4) th row, and then the data selection switch 13_D1st, the data selection switch 13_B2nd, and the data selection The switch 13_B3rd is turned on so that the data holding circuit 12_D1st, the data holding circuit 12_B2nd, and the data holding circuit 12_B3rd hold the pixel signals of the (n + 5) th row, and then the data selection switch 13_E1st, the data selection switch 13_E2nd, and the data selection switch 13_C3rd The pixel holding circuit 12_E1st, the data holding circuit 12_E2nd, and the data holding circuit 12_C3rd hold the pixel signals of the (n + 6) th row in the on state, and in the next horizontal readout period As shown in FIG. 21, in the first vertical mixed column set, the pixel signal of the (n + 2) th row, the pixel signal of the (n + 3) th row, and the pixel signal of the (n + 4) th row are arranged in the vertical direction and the horizontal direction in units of the horizontal mixed combination column. The mixed pixel signals mixed in the direction are generated, and the mixed pixel signals are horizontally transferred. Next, as shown in FIG. 22, the pixel signal of the (n + 3) th row and the (n + 4) th row are set in the second vertical mixed column set. FIG. 23 shows a mixed pixel signal obtained by mixing the pixel signal of the eye and the pixel signal of the (n + 5) th row in the vertical and horizontal directions in units of horizontal mixed combination columns, and horizontally transferring these mixed pixel signals. As described above, a mixed pixel in which the pixel signal in the (n + 4) th row, the pixel signal in the (n + 5) th row, and the pixel signal in the (n + 6) th row are mixed in the third vertical mixed column group in the vertical and horizontal directions in units of horizontal mixed combination columns. Generate a signal Those mixed pixel signals to the horizontal transfer. Thereafter, similarly, pixel signals shifted by one row between the first to third sets of vertical mixing columns are mixed in the vertical direction and the horizontal direction.

  FIG. 24A shows an example of a frame generated using the solid-state imaging device according to the sixth embodiment. For comparison, FIG. 24B shows a frame generated using a conventional solid-state imaging device. As shown in FIG. 24B, the conventional solid-state imaging device performs 3 × 3 pixel mixing for all pixels, whereas the solid-state imaging device according to the sixth embodiment has the same configuration as that shown in FIG. As shown in FIG. 4, since the pixel signals shifted by one row between the first to third vertical mixed column groups are mixed in the vertical direction and the horizontal direction, the mixed pixel signal to be read out without deteriorating the vertical resolution. The number of pixels can be reduced, and the pixel signal readout speed can be increased.

  Here, the case where the control signal line SW is provided for each set of vertical mixing columns in the line memory of each row has been described as a configuration for operating the data selection switch 13 on and off in units of vertical mixing columns. However, instead of the control signal line SW, by providing a logic circuit for operating the data selection switch 13 on and off using the control signal line Mix provided for each set of the horizontal mixed combination column, the line memory of each row The configuration of the solid-state imaging device may be simplified by reducing the number of control signal lines SW provided for the.

(Embodiment 7)
FIG. 25 is a diagram showing an example of two types of frames generated using the solid-state imaging device according to Embodiment 7 of the present invention. The frame shown in FIG. 25 (a) is the same as that in Embodiment 6 described above. This is the same as the frame shown in FIG.

  The configuration of the solid-state imaging device according to the seventh embodiment is the same as the configuration shown in FIG. 20 described in the sixth embodiment. In the seventh embodiment, the data selection switch 13 and the horizontal short circuit are arranged so that the rows of pixel signals mixed in the vertical direction simultaneously in the first vertical mixed column set and the third vertical mixed column set are shifted for each frame. The switch 14 is driven, and the frame shown in FIG. 25A and the frame shown in FIG. 25B are alternately generated to perform interlaced scanning, which is different from the above-described sixth embodiment.

  Specifically, when the frame shown in FIG. 25B is generated, the row of pixel signals to be mixed in the first set of vertical mixing columns is generated when the frame shown in FIG. 25A is generated. The pixel signal row to be mixed in the third vertical mixing column set is replaced with the pixel signal row to be mixed in the third vertical mixing column set when the frame shown in FIG. 25A is generated. Swap to the row of pixel signals to be mixed in the set of one vertical mixing column.

  As described above, the row of pixel signals to be mixed in the first set of vertical mixing columns and the row of pixel signals to be mixed in the set of third vertical mixing columns are exchanged for each frame, and the frame shown in FIG. And by alternately generating the frames shown in FIG. 25B and making them interlaced, it is possible to further improve the moving image quality without changing the still image quality.

  The solid-state imaging device according to the present invention can increase the readout speed of pixel signals, improve the quality of moving image recording, and can be switched between both still image shooting and moving image recording modes. Useful for.

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element array 2 Vertical signal line 3 Vertical scanning circuit 4 Constant current source 5 Column CDS circuit 6 Horizontal transfer circuit 7 Horizontal scanning circuit 8 Output circuit 9 Reading data selection circuit 10 Optical conversion element 11 Data holding mechanism 12 Data holding circuit 13 Data selection switch 14 Horizontal short-circuit switch 15 Column selection switch 16 Horizontal common signal line 17_odd, 17_even AND circuit

Claims (2)

A photoelectric conversion element array in which a plurality of photoelectric conversion elements that convert incident light into pixel signals are arranged in a matrix;
A data holding mechanism provided for each column of the photoelectric conversion elements arranged in a matrix, and configured to hold the pixel signals vertically transferred from the photoelectric conversion element array for a plurality of rows;
As the pixel signals are vertically transferred in units of one row from the photoelectric conversion element array, the pixel signals for a plurality of rows respectively held by the data holding mechanism are simultaneously mixed in the vertical direction. Holding data selection mechanism to select for each set of columns;
The row of the pixel signals to be mixed in the vertical direction is selected for each set of columns in which the pixel signals are simultaneously mixed in the vertical direction from among the plurality of rows of pixel signals held in the data holding mechanism. A vertical mixed pixel selection mechanism;
A horizontal mixing mechanism for horizontally mixing the pixel signals selected by the vertical mixed pixel selection mechanism and mixed in the vertical direction for each set of combination columns that simultaneously mix the pixel signals in the horizontal direction;
The row of the pixel signals to be mixed in the vertical direction is different for each set of columns for simultaneously mixing the pixel signals in the vertical direction or for each set of combination columns for simultaneously mixing the pixel signals in the horizontal direction. Solid-state imaging device.   2. The interlaced scanning is performed by shifting the row of the pixel signals to be mixed in the vertical direction simultaneously for each frame generated based on the pixel signals mixed in the vertical direction and the horizontal direction. Solid-state imaging device.

Images