JP2011023097A - Writing method in charge trapping memory device, erasing method, and charge trapping memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge trapping memory device having high rewriting resistance. <P>SOLUTION: The charge trapping memory device is constituted so that a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are laminated in order on a silicon substrate, and a voltage of one of poles is applied to the gate electrode to trap charges supplied from the silicon substrate in the charge trap film, thereby writing information, and the voltage of the other pole is applied to the gate electrode to pull out the charges trapped in the charge trap film, thereby erasing information. A film thickness of the tunnel oxide film is equal to or less than 3 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a writing method, an erasing method, and a charge trap memory device in a charge trap memory device.

  As a flash memory which is a kind of nonvolatile memory device, a floating gate type memory device is known.

  As a next-generation nonvolatile memory device, a so-called charge trap type memory device is used as a flash memory having a laminated structure in which a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially formed on a silicon substrate. Are known.

As this charge trap type memory device, there are SONOS structure (polysilicon film, SiO ₂ (amorphous) film, SiN film, SiO ₂ film, laminated structure of silicon substrate), SANOS structure (polysilicon film, Al ₂ O ₃ (crystal) Material), SiN film, SiO ₂ film, laminated structure of silicon substrate), TANOS structure (TaN film, Al ₂ O ₃ (crystalline) film, SiN film, SiO ₂ film, laminated structure of silicon substrate), MANOS structure Those having a structure such as (a metal film, an Al ₂ O ₃ (crystalline) film, a SiN film, a SiO ₂ film, a laminated structure of silicon substrates) are known.

JP-A-4-153999 JP-A-5-255853 JP 2007-193862 A

  However, the flash memory has an advantage that it is a non-volatile memory. However, since the flash memory has lower rewrite durability than a volatile memory or the like, a flash memory with high rewrite durability is desired.

  In particular, in the case of a charge trap type memory device compared to a floating gate type memory device, the height of the constituent elements can be reduced, the structure becomes simple and easy to miniaturize, and high integration and cost reduction are achieved. It is particularly desirable to improve the rewriting durability of the charge trap memory device.

  The present invention has been made in view of the above, and provides a charge trap memory device having improved rewrite durability and further improved reliability, and a charge trap memory device having good memory retention characteristics. It is an object of the present invention to provide a writing method and an erasing method.

  In the present invention, a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially stacked on a silicon substrate, and by applying a voltage of one pole to the gate electrode, The supplied charge is trapped in the charge trap film, information is written, and the voltage of the other electrode is applied to the gate electrode, thereby extracting the charge trapped in the charge trap film and In a writing method in a charge trap memory device that performs erasing, a first pulse voltage having a voltage value equal to or higher than a write start voltage is applied in a direction in which a write voltage is applied in the charge trap memory device, and the first pulse voltage is applied. After the voltage is applied, the voltage is less than the erase start voltage in the direction opposite to the direction in which the write voltage is applied. And applying a second pulse voltage.

  In the present invention, the tunnel oxide film has a thickness of 3 nm or less.

  In the present invention, the tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is higher on the charge trap film side than on the silicon substrate side and has a composition gradient. It is characterized by being.

  Further, the present invention is characterized in that when the first pulse voltage is Vpa1, Vpa1 ≧ + 14V, and when the second pulse voltage is Vpa2, −5V ≧ Vpa2 ≧ −9V. To do.

  In the present invention, a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially laminated on a silicon substrate, and the silicon electrode is applied by applying a voltage of one pole to the gate electrode. The charge supplied from the substrate is trapped in the charge trap film, information is written, and the voltage of the other electrode is applied to the gate electrode, thereby extracting the charge trapped in the charge trap film, In an erasing method in a charge trap memory device for erasing information, a first pulse voltage having a voltage value equal to or higher than an erasing start voltage is applied in an erasing voltage application direction in the charge trap memory device. After the pulse voltage is applied, a voltage value less than the write start voltage is applied in the direction opposite to the erase voltage application direction. And applying a pulse voltage.

  In the present invention, the tunnel oxide film has a thickness of 3 nm or less.

  In the present invention, the tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is higher on the charge trap film side than on the silicon substrate side and has a composition gradient. It is characterized by being.

  Further, the present invention is characterized in that when the first pulse voltage is Vpa1, Vpa1 ≦ −14V, and when the second pulse voltage is Vpa2, + 5V ≦ Vpa2 ≦ + 9V. .

  In the present invention, a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially laminated on a silicon substrate, and the silicon electrode is applied by applying a voltage of one pole to the gate electrode. The charge supplied from the substrate is trapped in the charge trap film, information is written, and the voltage of the other electrode is applied to the gate electrode, thereby extracting the charge trapped in the charge trap film, A charge trap type memory device for erasing information, wherein the tunnel oxide film has a thickness of 3 nm or less.

Further, the present invention is characterized in that the tunnel oxide film is formed of a SiO ₂ film.

  Further, the present invention is characterized in that the tunnel oxide film is formed by thermally oxidizing the surface of the silicon substrate.

  In the present invention, a tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially laminated on a silicon substrate, and the silicon electrode is applied by applying a voltage of one pole to the gate electrode. The charge supplied from the substrate is trapped in the charge trap film, information is written, and the voltage of the other electrode is applied to the gate electrode, thereby extracting the charge trapped in the charge trap film, In the charge trap type memory device for erasing information, the tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is more on the charge trap film side than on the silicon substrate side. It is a film having a high composition gradient.

  Furthermore, the present invention is characterized in that the charge trap film is formed of a SiN film.

Further, the present invention is characterized in that the blocking insulating film is formed of an Al ₂ O ₃ film or a SiO ₂ film.

  Further, the present invention is characterized in that the gate electrode is formed of any one of a polysilicon film, a metal nitride film, and a metal film.

  According to the present invention, it is possible to provide a charge trap type memory device with improved rewrite durability and further improved reliability. In addition, it is possible to provide a writing method and an erasing method in a charge trap memory device with good memory retention characteristics.

Configuration diagram of charge trap memory device Outline diagram of CV curve of charge trap type memory device CV curve diagram of charge trap type memory device in this embodiment CV curve diagram of charge trap type memory device with tunnel oxide film of 4nm thickness Correlation diagram between the number of rewrites and voltage in the charge trap memory device in this embodiment Correlation diagram between the number of rewrites and voltage in a charge trap type memory device with a tunnel oxide film with a thickness of 4 nm Correlation diagram between elapsed time after application of write pulse by positive pulse voltage and Vfb Waveform diagram of write pulse with positive pulse voltage Waveform diagram of write pulse in the second embodiment Correlation diagram between elapsed time after application of write pulse and Vfb in the second embodiment

  The form for implementing this invention is demonstrated below.

[First embodiment]
(Charge trap memory device)
A charge trap memory device according to the first embodiment will be described with reference to FIG.

  In the charge trap memory device according to the present embodiment, a tunnel oxide film 11, a charge trap film 12, a blocking insulating film 13, and a gate electrode 14 are sequentially stacked on a silicon substrate 10.

The tunnel oxide film 11 is formed of a silicon oxide film (SiO ₂ film), and the thickness of the silicon oxide film is 2 nm. In this embodiment, the tunnel oxide film 11 is formed of a silicon oxide film (SiO ₂ film). However, the tunnel oxide film 11 is formed of a silicon oxynitride film (SiON film) in which nitrogen is mixed into the silicon oxide film. Also good. A silicon oxide film (SiO ₂ film) that becomes the tunnel oxide film 11 is formed by thermally oxidizing the surface of the silicon substrate 10. The formed tunnel oxide film 11 is required to have a uniform film thickness, and since the formed film thickness is as thin as 2 nm, the tunnel oxide film 11 is preferably formed by thermal oxidation.

  The charge trap film 12 is formed of a silicon nitride film (SiN film). The film thickness of the charge trap film 12 in the present embodiment is 7 nm.

The blocking insulating film 13 is formed of a silicon oxide film (SiO ₂ film), an aluminum oxide film (Al ₂ O ₃ film), or a high dielectric constant film (High-k film). Examples of the material constituting the high dielectric constant film (High-k film) include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), and the like. Is mentioned. In the present embodiment, the blocking insulating film 13 is formed of an aluminum oxide film (Al ₂ O ₃ film), and the formed blocking insulating film 13 has a thickness of 15 nm.

  The gate electrode 14 is formed of a polysilicon film, a conductive metal nitride film, and a metal film. Examples of the conductive metal nitride film include a TiN film and a TaN film, and examples of the metal film include a film made of a metal material such as tungsten (W) or platinum (Pt). In the present embodiment, the gate electrode is formed of a TiN film.

  FIG. 1 shows the structure of a MOS (Metal Oxide Semiconductor) capacitor in a charge trap memory device, but it may be configured as a transistor having a source electrode and a drain electrode.

  Next, a method for writing and erasing information in the charge trap memory device shown in FIG. 1 will be described. Information is written and erased in the charge trap memory device by applying a predetermined voltage from the write / erase control circuit 20 connected to the gate electrode 14. Specifically, for writing, a positive pulse voltage of 18 V is applied from the write / erase control circuit 20 to supply electrons that are negative charges from the silicon substrate 10 side, and the supplied electrons are supplied to the charge trap film. This is done by trapping at 12. Erasing is performed by detrapping electrons trapped in the charge trap film 12 by applying a negative pulse voltage of −18V or −20V from the write / erase control circuit 20.

FIG. 2 shows a CV curve in the charge trap memory device according to the present embodiment. In this figure, the vertical axis represents capacity Cg (F / cm ² ), and the horizontal axis represents voltage Vg (V). As shown in this figure, at the time of writing, electrons are trapped, so the CV curve shifts in the positive direction. On the other hand, at the time of erasing, the CV curve shifts in the negative direction due to electron detrapping. Thus, the CV curve moves in parallel when writing and erasing information. In the present embodiment, the case where electrons are detrapped includes the case where positive holes are trapped.

(Tunnel oxide film)
The inventors have found that in the above-described charge trap memory device, when the thickness of the tunnel oxide film 11 is reduced, the rewrite durability is improved. Specifically, in the charge trap memory device shown in FIG. 1, when a tunnel oxide film 11 having a thickness of 2 nm and a tunnel oxide film 11 having a thickness of 4 nm were fabricated and evaluated, It has been found that the rewriting durability is improved in a charge trap memory device having a tunnel oxide film 11 having a thickness of 2 nm.

  FIG. 3 shows a CV curve at the time of erasure of the charge trap type memory device having a tunnel oxide film 11 having a thickness of 2 nm. FIG. 4 shows the charge trap type memory device having a tunnel oxide film 11 having a thickness of 4 nm. The CV curve at the time of erasure | elimination is shown.

  As shown in FIG. 3, in the case of a charge trap type memory device having a tunnel oxide film 11 with a thickness of 2 nm, the shape of the CV curve hardly changes even if erasing is repeated. On the other hand, as shown in FIG. 4, in the case of a charge trap memory device having a tunnel oxide film 11 having a thickness of 4 nm, the shape of the CV curve changes as writing and erasing are repeated. Thus, when the CV curve changes, the characteristics of the charge trap memory device become different from the initial characteristics, and the reliability is lowered.

  FIG. 5 shows the relationship between the number of rewrites and the voltage Vp1 in the written state and the voltage Ve1 in the erased state in the charge trap type memory device having a thickness of the tunnel oxide film 11 of 2 nm. As shown in this figure, the voltage Vp1 in the written state is constant around 5V and the voltage Ve1 in the erased state is constant around -4V without depending on the number of rewrites.

On the other hand, FIG. 6 shows the relationship between the number of rewrites and the voltage Vp2 in the written state and the voltage Ve2 in the erased state in the charge trap memory device having a tunnel oxide film 11 having a film thickness of 4 nm. As shown in this figure, the voltage Vp2 in the written state is about 5.5V, but it is slightly lowered depending on the number of rewrites. Further, the voltage Ve2 in the erased state is about 2V longitudinal tends to increase depending on the number of times of rewriting, in particular, are particularly elevated in more than 10 ³ times.

  As described above, the charge trap type memory device having the tunnel oxide film 11 having a thickness of 2 nm has improved the rewrite durability and the charge trap type memory device having the tunnel oxide film 11 having a thickness of 4 nm. Improve reliability. This is because in the charge trap memory device, since electrons that have passed through the tunnel oxide film 11 due to the tunnel effect are trapped in the charge trap film 12, writing is performed. It is considered that the change caused by rewriting the characteristics of the charge trap memory device can be suppressed by making the oxide film 11 thinner.

  Accordingly, it is considered that the thinner the tunnel oxide film 11 is, the more the rewriting durability in the charge trap type memory device is improved. However, in order to ensure the function as the charge trap type memory device, that is, the tunnel oxide film 11 has the tunnel effect. In order to function as a material having a thickness of 2 to 3, it is considered that a 2 to 3 atomic layer is required uniformly, and a film thickness of 1 nm or more is considered necessary.

  In the charge trap memory device according to the present embodiment, the rewriting durability is good when the thickness of the tunnel oxide film 11 is 2 nm. However, based on the results shown in FIGS. Based on the experience of the inventors, it is considered that good rewriting durability can be obtained if the thickness of the tunnel oxide film 11 is 3 nm or less.

In the present embodiment, the tunnel oxide film 11 is formed of a silicon oxide film (SiO ₂ film). However, as described above, the same effect can be obtained by forming the tunnel oxide film 11 using a silicon oxynitride film (SiON film). Can be obtained. In this case, the tunnel oxide film 11 may be formed of a gradient material having a composition gradient in the film thickness direction. Specifically, it is configured such that nitrogen is zero or the composition of nitrogen is low on the silicon substrate 10 side and the composition of nitrogen is high on the charge trap film 12 side.

  By using a silicon oxynitride film (SiON film) for the tunnel oxide film 11, the rewrite durability can be further improved, and by using the tunnel oxide film 11 as a composition gradient film, the tunnel oxide film 11 and the charge trap can be used. The change in the band structure at the interface with the film 12 can be made gradual, the rewriting durability can be further improved, and the reliability can be improved.

[Second Embodiment]
Next, a second embodiment will be described. The present embodiment relates to a writing method and an erasing method in the charge trap memory device shown in FIG. In the charge trap memory device used in this embodiment, the tunnel oxide film has a thickness of 4 nm.

  FIG. 7 shows the relationship between the elapsed time after the write operation and the flat band voltage (Vfb) when the write voltage (Vprgm) is + 14V, + 14.8V, and + 16V in the charge trap memory device. Note that writing in the charge trap memory device is performed by applying a positive pulse voltage as shown in FIG. 8 for about 10 msec (writing pulse). Originally, it is desirable that the flat band voltage is constant without changing after the write operation. However, as shown in FIG. 7, the flat band voltage (Vfb) increases with time after the write operation. The value will drop. Further, the flat band voltage decreases more significantly as the write voltage (Vprgm) is higher.

  Next, a case where a write pulse having the shape shown in FIG. 9 is applied to the charge trap memory device will be described. In this write pulse, a positive pulse voltage of + 16V is applied as the first pulse voltage Vpa1 for about 10 msec, and then a negative pulse voltage of −9V is applied as the second pulse voltage Vpa2 for about 10 msec. The charge trap memory device shown in FIG. 1 starts writing and erasing at 12 V or higher, applies a voltage of 12 V or higher as the first pulse voltage Vpa1, and writes as the second pulse voltage Vpa2. A voltage of less than 12V is applied so that the recorded information is not erased. Note that this voltage may depend on the thickness of the tunnel oxide film in the charge trap memory device. In such a case, a voltage corresponding to the thickness of the tunnel oxide film formed is applied. .

  FIG. 10 shows the relationship between the elapsed time after applying the write pulse having the shape shown in FIG. 9 and the flat band voltage (Vfb) in the charge trap memory device shown in FIG. When only a positive pulse voltage is applied, the flat band voltage decreases with respect to the elapsed time after the write operation as compared to the case where Vprgm is +14.8 V where the value of the flat band voltage is approximately the same 5 V as shown in FIG. There are fewer cases where a write pulse of the shape shown is applied. That is, the written information can be held longer when the write pulse having the shape shown in FIG. 9 is applied. In other words, in the charge trap memory device shown in FIG. 1, by performing writing with the write pulse having the shape shown in FIG. 9, the memory holding time of the written information becomes longer and the memory holding characteristics are improved. The above description is for the case where the thickness of the tunnel oxide film is 4 nm, but it is considered that the same applies to the case where the tunnel oxide film is 3 nm or less.

  As such a write pulse, in the charge trap type memory device shown in FIG. 1, after applying a voltage (first pulse voltage) higher than the write start voltage in the information write direction, the information is erased. What is necessary is just to apply a voltage (second pulse voltage) lower than the erase start voltage. In the charge trap memory device shown in FIG. 1, the voltage at which information writing and erasing starts is 12V. Therefore, the first pulse voltage Vpa1 may be Vpa1 ≧ + 12V, and in order to write information reliably. Is preferably Vpa1 ≧ + 14V, and Vpa1 is preferably + 16V. The second pulse voltage Vpa2 may be 0V> Vpa2> −12V, and in order not to erase written information, it is preferable that −5V ≧ Vpa2 ≧ −9V. Vpa2 is preferably -9V.

  Although the writing operation has been described above, the same applies to the erasing operation, and the erasing operation can be performed by applying a voltage having the opposite sign to the above. Specifically, since the voltage at which information writing and erasing is started is 12V, the first pulse voltage Vpa1 may be Vpa1 ≦ −12V during the erasing operation, and the information is surely stored. In order to erase, Vpa1 ≦ −14V is preferable, and Vpa1 is preferably −16V. The second pulse voltage Vpa2 may be 0V <Vpa2 <+ 12V, and in order to prevent further writing, it is preferable that + 5V ≦ Vpa2 ≦ + 9V, and Vpa2 is + 9V. preferable.

  As mentioned above, although the form which concerns on implementation of this invention was demonstrated, the said content does not limit the content of invention.

11 Silicon oxide film 12 Charge trap film 13 Blocking insulating film 14 Gate electrode 20 Write / erase control circuit

Claims (15)

A tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially stacked on the silicon substrate, and a charge supplied from the silicon substrate is applied by applying a voltage of one electrode to the gate electrode. The charge is trapped in the charge trap film, the information is written, the voltage of the other electrode is applied to the gate electrode, the charge trapped in the charge trap film is extracted, and the information is erased In the writing method in the trap type memory device,
In the charge trap memory device, a first pulse voltage having a voltage value equal to or higher than a write start voltage is applied in a direction in which the write voltage is applied,
A write in a charge trap memory device, wherein after applying the first pulse voltage, a second pulse voltage having a voltage value less than an erase start voltage is applied in a direction opposite to a direction in which the write voltage is applied. Method.   2. The write method according to claim 1, wherein the thickness of the tunnel oxide film is 3 nm or less.   The tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is a film having a composition gradient that is higher on the charge trap film side than on the silicon substrate side. The write method in the charge trap memory device according to claim 1. When the first pulse voltage is Vpa1, Vpa1 ≧ + 14V,
4. The method for writing in a charge trap memory device according to claim 1, wherein when the second pulse voltage is Vpa2, -5V ≧ Vpa2 ≧ −9V. A tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially stacked on the silicon substrate, and a charge supplied from the silicon substrate is applied by applying a voltage of one electrode to the gate electrode. The charge is trapped in the charge trap film, the information is written, the voltage of the other electrode is applied to the gate electrode, the charge trapped in the charge trap film is extracted, and the information is erased In the erasing method in the trap type memory device,
In the charge trap memory device, a first pulse voltage having a voltage value equal to or higher than an erasing start voltage is applied in an erasing voltage application direction;
An erasure in a charge trap memory device, wherein after applying the first pulse voltage, a second pulse voltage having a voltage value less than a write start voltage is applied in a direction opposite to the direction in which the erase voltage is applied. Method.   6. The erase method for a charge trap memory device according to claim 5, wherein the tunnel oxide film has a thickness of 3 nm or less.   The tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is a film having a composition gradient that is higher on the charge trap film side than on the silicon substrate side. 6. An erasing method in a charge trap type memory device according to claim 5. When the first pulse voltage is Vpa1, Vpa1 ≦ −14V,
8. The erasing method in the charge trap memory device according to claim 5, wherein when the second pulse voltage is Vpa2, + 5V ≦ Vpa2 ≦ + 9V. A tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially stacked on the silicon substrate.
By applying a voltage of one electrode to the gate electrode, the charge supplied from the silicon substrate is trapped in the charge trap film, and information is written,
A charge trap type memory device for erasing information by extracting a charge trapped in the charge trap film by applying a voltage of the other electrode to the gate electrode;
The charge trap memory device, wherein the tunnel oxide film has a thickness of 3 nm or less. The tunnel oxide film, a charge trap memory device according to claim 9, characterized in that it is formed by the SiO ₂ film.   11. The charge trap memory device according to claim 9, wherein the tunnel oxide film is formed by thermally oxidizing the surface of the silicon substrate. A tunnel oxide film, a charge trap film, a blocking insulating film, and a gate electrode are sequentially stacked on the silicon substrate.
By applying a voltage of one electrode to the gate electrode, the charge supplied from the silicon substrate is trapped in the charge trap film, and information is written,
A charge trap type memory device for erasing information by extracting a charge trapped in the charge trap film by applying a voltage of the other electrode to the gate electrode;
The tunnel oxide film is formed of a SiON film, and the composition of nitrogen in the tunnel oxide film is a film having a composition gradient that is higher on the charge trap film side than on the silicon substrate side. Charge trap type memory device.   13. The charge trap memory device according to claim 9, wherein the charge trap film is formed of a SiN film. The charge trap type memory device according to claim 9, wherein the blocking insulating film is formed of an Al ₂ O ₃ film or a SiO ₂ film.   15. The charge trap memory device according to claim 9, wherein the gate electrode is formed of any one of a polysilicon film, a metal nitride film, and a metal film.

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