JP2011018709A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a ferroelectric capacitor which is to be installed in a semiconductor memory device.SOLUTION: The ferroelectric capacitor 50 provided in the semiconductor memory device 70 includes a lower electrode film 14, a ferroelectric material film 15 and an upper electrode film 16 which are laminated. The lower electrode film 14 has an area to be electrically connected with a contact plug 11, provided on one of the source or the drain of a memory cell transistor 40, formed to downwardly protrude, has a form to be embedded on the upper part of the contact plug and is connected to the contact plug 11 via a reaction preventing film 13. The upper electrode film 16 is connected to a wiring layer 25 via a contact plug 23. Both ends of an interface with the contact plug 11 and the reaction preventing film 13 connected and an upper side face of the contact plug 11 are covered with a reaction preventing film 9. The ferroelectric capacitor 50 has a region which excludes the contact plugs 11 and is 23 covered with the reaction preventing film 9 and a reaction preventing film 19 in contact with the reaction preventing film 9.

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof.

  Next-generation non-volatile memory that is capable of high-speed rewriting compared to conventional EEPROM and flash memory and has a number of rewrites of 5 digits or more, aiming to realize capacity, speed, and cost comparable to DRAM Development of volatile memory is underway. The next-generation nonvolatile memory includes FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), and the like. In FeRAM, which is a ferroelectric memory, it is necessary to prevent a contact plug connected to one of the source and drain of a memory cell transistor from being oxidized when passing through a thermal process during capacitor formation. For example, a means for increasing the thickness of the lower electrode film of the ferroelectric capacitor may be taken. However, the ferroelectric memory has a problem that it is difficult to process a capacitor when the lower electrode is thick. Therefore, there is a conventional example in which a concave portion is formed in the upper part of the contact that contacts the capacitor lower electrode and the effective film thickness of the lower electrode is increased only in the upper part of the contact (for example, see Patent Document 1). However, in the FeRAM described in Patent Document 1 and the like, the oxidation-resistant reaction preventing film other than the groove is removed by etching. Further, no reaction preventing film is provided in the side end region at the interface between the lower electrode of the ferroelectric capacitor and the contact plug. For this reason, there is a problem in terms of preventing intrusion of oxygen or the like from the lateral direction of the interface between the lower electrode of the ferroelectric capacitor and the contact plug, and an oxide film is formed at the interface to reduce the contact yield. There is also a problem.

JP 2000-228373 A

  The present invention provides a semiconductor memory device that realizes high reliability of a ferroelectric capacitor and a manufacturing method thereof.

  A semiconductor memory device of one embodiment of the present invention includes a semiconductor substrate, a gate electrode provided over the semiconductor substrate, connected to a word line, and provided via a gate insulating film, and the semiconductor substrate sandwiched between the gate electrodes A memory cell transistor having a source and a drain provided on the surface, and a first contact plug connected to one of the source and drain, and a region in contact with the first contact plug is more than the other region A lower electrode film having a convex shape downward and electrically connected to the first contact plug; a ferroelectric film provided on the lower electrode film; and provided on the ferroelectric film A ferroelectric capacitor comprising an upper electrode film having an upper portion connected to the second contact plug, an upper side surface of the first contact plug, and the first contact plug. A first reaction preventing film provided so as to cover a side surface of a region where the contact plug and the lower electrode film are electrically connected and a bottom of the lower electrode film; the lower electrode film; and the ferroelectric film. And a side surface of the upper electrode film, an upper portion of the upper electrode film, and an interface contacting the upper electrode film and the second contact plug, and is in contact with the first reaction preventing film. And 2 reaction preventing film.

  Furthermore, the method for manufacturing a semiconductor memory device according to one embodiment of the present invention includes a step of forming a memory cell transistor over a semiconductor substrate, and a lower portion is in contact with the first insulating film over the source and drain of the memory cell transistor. Forming a first contact plug that is in contact with the first reaction preventing film and connected to the source or drain of the memory cell transistor; etching the upper portion of the first contact plug; and A step of forming a groove portion having a concave shape in which a side surface of the reaction preventing film is exposed; and a second reaction preventing film, a lower electrode film, a ferroelectric film, and the second electrode on the groove portion and the first reaction preventing film; Forming a ferroelectric capacitor by selectively etching the upper electrode film, the ferroelectric film, the lower electrode film, and the second reaction preventing film; Covering the upper electrode film, the upper electrode film, the ferroelectric film, the lower electrode film, and the side surfaces of the second reaction preventing film and in contact with the first reaction preventing film. Forming a third reaction preventing film and etching the third reaction preventing film on the upper electrode film to form a second contact plug in contact with the upper electrode film in the etched opening. And a step of performing.

  According to the present invention, it is possible to provide a semiconductor memory device that realizes high reliability of a ferroelectric capacitor and a manufacturing method thereof.

1 is a cross-sectional view showing a semiconductor memory device according to Embodiment 1 of the present invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the semiconductor memory device based on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor memory device and a manufacturing method thereof according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a semiconductor memory device. In this embodiment, all regions other than the portions in contact with the upper and lower contact plugs of the ferroelectric capacitor are covered with a reaction preventing film.

  As shown in FIG. 1, a semiconductor memory device 70 is provided with a plurality of memory cell transistors 40 and ferroelectric capacitors 50 on a semiconductor substrate 1.

  Here, the semiconductor memory device 70 is applied to a chain type FeRAM, but it is also applied to a 1T1C (1 transistor + 1 capacitor) type, 2T2C type, 1T2C type, 6T4C type FeRAM (also referred to as conventional FeRAM). can do.

  In the semiconductor memory device 70, the element region in which the memory cell transistor 40 and the like are formed is isolated by a shallow trench isolation (hereinafter referred to as STI) 2 embedded in the surface of the semiconductor substrate 1. A source / drain region 3 having a conductivity type opposite to that of the semiconductor substrate 1 serving as the source or drain of the memory cell transistor 40 is selectively provided on the surface of the semiconductor substrate 1.

  A gate insulating film 4, a gate electrode film 5, and an insulating film 6 are stacked on the semiconductor substrate 1 between the source / drain regions 3 so as to overlap with the source / drain regions 3. The sidewall film 7 is formed on the side surfaces of the gate insulating film 4, the gate electrode film 5, and the insulating film 6 on which the side wall film 7 is laminated.

  An insulating film 8 as an interlayer insulating film is provided on the STI 2, the insulating film 6, the sidewall film 7, and the source / drain region 3. A contact opening CH 1 is provided in the insulating film 8 on the source / drain region 3. A reaction preventing film (first reaction preventing film) 9 is provided in contact with the upper end of the contact opening CH1. A reaction preventing film 10 as a barrier film and a contact plug (first contact plug) 11 are embedded in the contact opening CH1.

  A groove 12 having a concave shape from which the reaction preventing film 10 and the contact plug 11 are removed by etching is provided in the upper part of the contact opening CH1. Here, the groove 12 is formed wider than the contact opening CH1.

  On the contact plug 11 connected to one of the source and drain of the memory cell transistor 40 (part connected to the ferroelectric capacitor 50), an oxidation-resistant reaction preventing film (third reaction preventing film) 13 and a lower electrode The film 14 is formed so as to bury the groove 12. A ferroelectric film 15, an upper electrode film 16, and a hard mask 17 are stacked on the lower electrode film 14. The lower electrode film 14, the ferroelectric film 15, and the upper electrode film 16 constitute a ferroelectric capacitor 50.

  The side surfaces of the hard mask 17, the upper electrode film 16, the ferroelectric film 15, the lower electrode film 14, and the reaction preventing film 13, the upper surface of the insulating film 8, the upper surface of the reaction preventing film 9, and the upper surface of the hard mask 17 Is provided with a reaction preventing film (second reaction preventing film) 19. An insulating film 20 as an interlayer insulating film, a reaction preventing film (fourth reaction preventing film) 21, and an insulating film 22 as an interlayer insulating film are stacked on the reaction preventing film 19.

  The hard mask 17, the reaction preventing film 19, the insulating film 20, the reaction preventing film 21, and the insulating film 22 that are stacked on the ferroelectric capacitor 50 are etched to provide a contact opening CH <b> 2. A contact plug (second contact plug) 23 is embedded in the contact opening CH2 so as to be in contact with the upper electrode film 16.

  The hard mask 17, the reaction preventing film 19, the insulating film 20, the reaction preventing film 21, and the insulating film 22 that are formed in a portion where the ferroelectric capacitor 50 is not provided are etched to provide a contact opening CH3. A contact plug 24 is embedded in the contact opening CH3 so as to be in contact with the reaction preventing film 13 and the lower electrode film 14. Unlike the portion connected to the ferroelectric capacitor 50, the upper portion of the reaction preventing film 13 and the lower electrode film 14 in this portion is removed by etching.

  A wiring layer 25 in contact with the contact plugs 23 and 24 is provided on the insulating film 22, the contact plug 23, and the contact plug 24. By this wiring layer 25, the memory cell transistor 40 and the ferroelectric capacitor 50 are connected in parallel. An insulating film 26 as an interlayer insulating film is provided on the insulating film 22 and the wiring layer 25. A wiring layer 27 as a bit line (BL) is provided on the insulating film 26. An insulating film 28 as a surface protective film of the semiconductor memory device 70 is provided on the wiring layer 27.

  Here, in the ferroelectric capacitor 50, the region excluding the contact plug 11 electrically connected to the lower electrode film 14 and the contact plug 23 in contact with the upper electrode film 16 is a reaction preventing film (first reaction preventing film) 9. And the reaction preventive film (second reaction preventive film) 19 that is in contact with the reaction preventive film (first reaction preventive film) 9 is shielded from the surroundings (covered by the reaction preventive films 9 and 19).

  In this structure, the effective thickness of the lower electrode film 14 above the contact plug 11 can be increased, and oxygen diffusion from the lower portion of the ferroelectric capacitor 50 to the upper end portion of the contact plug 11 can be suppressed. This makes it possible to prevent oxidation of the contact. Further, the oxidation-resistant reaction preventing film 13 is provided on the entire bottom of the lower electrode film 14, and the reaction preventing film 19 and the reaction preventing film 9 connected to the reaction preventing film 19 are present. The influence of oxygen or the like entering in the lateral direction from the contact interface with the upper end of the contact plug 11 can be reduced, and formation of an oxide film at the interface can be suppressed, so that a decrease in contact yield can be suppressed.

  Further, the reaction preventing films 9 and 19 can also prevent hydrogen from entering the ferroelectric capacitor 50 during the manufacturing process of the semiconductor memory device 70 or after the manufacturing process of the semiconductor memory device 70 is completed. In addition, the reaction preventing film 21 can suppress hydrogen from entering the ferroelectric capacitor 50.

  As described above, contact plug interface oxidation can be suppressed and hydrogen degradation of the capacitor can be realized without increasing the difficulty of processing the capacitor, so that high reliability of the cell capacitor and improvement in contact yield can be achieved.

  Next, a method for manufacturing the semiconductor memory device will be described with reference to FIGS. 2 to 8 are cross-sectional views showing the manufacturing process of the semiconductor memory device.

  As shown in FIG. 2, STI 2 is selectively embedded in the surface of the semiconductor substrate 1. A gate insulating film 3, a gate electrode film 4, and an insulating film 6 are selectively stacked. A source / drain region 3 having a conductivity type opposite to that of the semiconductor substrate 1 is formed on the semiconductor substrate 1 between the stacked gate insulating film 3, gate electrode film 4, and insulating film 6. Sidewall films 7 are formed on both ends of the gate insulating film 3, the gate electrode film 4, and the insulating film 6 that are stacked.

  An insulating film 8 as an interlayer insulating film is formed on the STI 2, the source / drain region 3, the insulating film 6, and the sidewall film 7. The insulating film 8 on the source / drain region 3 is etched to form a contact opening CH1. The reaction preventing film 10 and the contact plug 11 are embedded in the contact opening CH1. Here, although the titanium nitride film (TiN film) is used as the reaction preventing film 10, a titanium film (Ti film) or the like may be used instead. Tungsten (W) is used for the contact plug 11, but polycrystalline polysilicon doped with impurities at a high concentration may be used instead.

Next, as shown in FIG. 3, a reaction preventing film (first reaction preventing film) 9 is formed so as to be in contact with the upper end of the contact opening CH1. Specifically, the insulating film 8 in contact with the upper end portion of the contact opening CH1 is etched, a reaction preventing film 9 is embedded in the etching opening, and the insulating film 8 and reaction are performed using a CMP (Chemical Mechanical Polishing) method or the like. The prevention film 9 is polished and flattened. Note that the contact opening CH1 may be formed after the reaction preventing film 9 is first embedded. Here, a silicon nitride film (SiN film) is used as the reaction preventing film (first reaction preventing film) 9, but an alumina film (Al ₂ O ₃ film) or a titanium oxide film (TiO ₂ film) is used instead. Etc. may be used.

  Subsequently, as shown in FIG. 4, with the resist film 31 selectively formed by using a well-known lithography method as a mask, the reaction between the contact plug 11 and both ends thereof by using, for example, the RIE (Reactive Ion Etching) method or the like. The prevention film 9 is etched to form a groove 12 having a concave shape wider than the contact opening CH1. After forming the groove 12, the resist film 31 is removed.

Then, as shown in FIG. 5, on the insulating film 8, the reaction preventing film 9, and the groove 12, a reaction preventing film (third reaction preventing film) 13, a lower electrode film 14, a ferroelectric film 15, an upper electrode A film 16 and a hard mask 17 are stacked. The reaction preventing film (third reaction preventing film) 13 is inserted for preventing oxygen diffusion. Although an iridium film (Ir film) is used here, an iridium oxide film (IrO ₂ film), a TiAlN film, a TiAl film, or the like may be used instead. The hard mask 17 is inserted for forming the ferroelectric capacitor 50. Although an alumina film (Al ₂ O ₃ film) is used here, a TEOS film or the like may be used instead.

Here, a platinum film (Pt film) is used for the lower electrode film 14 and the upper electrode film 16, but an iridium film (Ir film), an iridium oxide film (IrO ₂ film), or an SRO film (Strontium) is used instead. (Ruthenium Oxide film) and a laminated film combining these films may be used. The ferroelectric film 15, PZT film is used a lead zirconate titanate (PbZrTiO ₃ film), SBT film (strontium bismuth tantalate SrBi ₂ Ta ₂ O ₉ film) and BLT film (lanthanum-added titanate Bismuth (Bi, La) ₄ Ti ₃ O ₁₂ film) or the like may be used.

  After the reaction prevention film (third reaction prevention film) 13, the lower electrode film 14, the ferroelectric film 15, the upper electrode film 16, and the hard mask 17 are stacked, a resist film is selectively formed using a well-known lithography method. 32 is formed.

Next, as shown in FIG. 6, using the resist film 32 as a mask, the hard mask 17 is etched using, for example, the RIE method. After the hard mask 17 is etched, the resist film 32 is removed. Using the hard mask 17 as a mask, the upper electrode film 16, the ferroelectric film 15, the lower electrode film 14, and the reaction preventing film 13 are etched using, for example, the RIE method. At this time, etching is performed until the surface of the reaction preventing film 9 is completely exposed. In the RIE processing of the upper electrode film 16, the ferroelectric film 15, the lower electrode film 14, and the reaction preventing film 13, ArCl gas is used as an etching gas species, but CF ₄ gas or the like may be used instead. After RIE, post-RIE processing is performed for the purpose of removing reactants and damage generated in the RIE process.

Subsequently, as shown in FIG. 7, after the RIE post treatment, the insulating film 8, the reaction preventing film 9, and the hard mask 17, and the lower electrode film 14, the ferroelectric film 15, the upper electrode film 16, and the hard mask are processed. A reaction preventing film (second reaction preventing film) 19 is formed on the side surface of 17. Here, a silicon nitride film (SiN film) is used as the reaction preventing film (second reaction preventing film) 19, but an alumina film (Al ₂ O ₃ film) or a titanium oxide film (TiO ₂ film) is used instead. Etc. may be used.

Then, as illustrated in FIG. 8, an insulating film 20 as an interlayer insulating film and a reaction preventing film (fourth reaction preventing film) 21 are stacked on the reaction preventing film 19. Here, although the silicon nitride film (SiN film) is used for the reaction preventing film (fourth reaction preventing film) 21, an alumina film (Al ₂ O ₃ film) or a titanium oxide film (TiO ₂ film) is used instead. Etc. may be used.

  After the formation of the reaction preventing film 21, an interlayer insulating film, a contact plug, a wiring layer, and the like are formed using a known technique, thereby completing the semiconductor memory device 70 as a chain FeRAM.

  As described above, in the semiconductor memory device and the manufacturing method thereof according to this embodiment, a plurality of memory cell transistors 40 and ferroelectric capacitors 50 are provided on the semiconductor substrate 1. A contact opening CH1 is provided in the insulating film 8 on the source or drain of the memory cell transistor 40, and a reaction preventing film 10 and a contact plug 11 are embedded in the contact opening CH1. The ferroelectric capacitor 50 includes a lower electrode film 14, a ferroelectric film 15, and an upper electrode film 16 that are stacked. The lower electrode film 14 is also embedded in a recessed shape at the upper end of the contact plug 11 provided on one of the source and drain of the memory cell transistor 40, and the contact plug 11 is interposed via the reaction preventing film 13. Connected to. The upper electrode film 16 is connected to the wiring layer 25 through the contact plug 23. Both end portions of the interface where the contact plug 11 and the reaction preventing film 13 are connected and the upper side surface of the contact plug 11 are covered with the reaction preventing film 9. In the ferroelectric capacitor 50, the region excluding the contact plugs 11 and 23 is covered with the reaction preventing film 9 and the reaction preventing film 19 in contact with the reaction preventing film 9.

  For this reason, the distance between the both end portions of the reaction preventing film 13 and the contact plug 11 can be increased, and the reaction preventing films 9 and 19 allow oxygen to penetrate laterally from the end portion of the lower electrode film 14. Since entry can be suppressed and formation of an oxide film at the interface can be suppressed, a decrease in contact yield can be suppressed. Further, the reaction preventing films 9 and 19 can suppress hydrogen from entering the ferroelectric capacitor 50 during the manufacturing process of the semiconductor memory device 70 or after the manufacturing process of the semiconductor memory device 70 is completed. Therefore, good contact and high reliability of the ferroelectric capacitor 50 and the contact plug 11 can be achieved, and the ferroelectric capacitor 50 can be highly reliable.

  Next, a semiconductor memory device and a manufacturing method thereof according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 9 is a cross-sectional view showing a semiconductor memory device. In this embodiment, the arrangement of the reaction preventing film is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 9, the semiconductor memory device 71 includes a plurality of memory cell transistors 40 and ferroelectric capacitors 50 on the semiconductor substrate 1.

  Here, the semiconductor memory device 71 is applied to a chain type FeRAM, but can also be applied to a 1T1C (1 transistor + 1 capacitor) type, 2T2C type, 1T2C type, 6T4C type FeRAM, and the like.

  In the semiconductor memory device 71, an insulating film 8 as an interlayer insulating film and a reaction preventing film (first reaction preventing film) 9 a are stacked on the STI 2, the insulating film 6, the sidewall film 7, and the source / drain region 3. .

  A contact opening CH1 is provided in the insulating film 8 and the reaction preventing film 9a on the source / drain region 3. A groove portion 12 having a concave shape from which the reaction preventing film 10 and the contact plug 11 are removed by etching is provided above the contact opening CH1 in which the reaction preventing film 10 and the contact plug 11 are embedded. The reaction preventing film 9a is provided on the entire semiconductor memory device 71 except for the contact opening CH1 so as to cover the upper portion of the memory cell transistor 40.

  Here, in the ferroelectric capacitor 50, the region excluding the contact plug 11 electrically connected to the lower electrode film 14 and the contact plug 23 in contact with the upper electrode film 16 is a reaction preventing film (first reaction preventing film). 9a and the reaction prevention film (second reaction prevention film) 19 in contact with the reaction prevention film (first reaction prevention film) 9a are shielded from the surroundings (covered by the reaction prevention films 9a and 19).

  As a result, the oxidation-resistant reaction preventing film 13 is provided on the entire bottom of the lower electrode film 14, and the reaction preventing film 19 and the reaction preventing film 9a connected to the reaction preventing film 19 are present. The influence of oxygen penetrating in the lateral direction from the contact interface portion with the upper end of the contact plug 11 can be reduced, and the formation of an oxide film at the interface can be suppressed, so that a decrease in contact yield can be suppressed. In addition, hydrogen can be prevented from entering the ferroelectric capacitor 50 during the manufacturing process of the semiconductor memory device 71 or after the manufacturing process of the semiconductor memory device 71 is completed, and the ferroelectric capacitor 50 is made highly reliable. be able to. Further, since the reaction preventing film 9a is formed on the insulating film 8 without being processed and is provided in a region other than the contact opening CH1, it is possible to completely block the hydrogen entry path.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIGS.

As shown in FIG. 10, after forming the gate, source, and drain of the memory cell transistor 40, the insulating film 8 as an interlayer insulating film and the STI 2, the source / drain region 3, the insulating film 6, and the sidewall film 7 are formed. A reaction preventing film (first reaction preventing film) 9a is laminated. Here, although the silicon nitride film (SiN film) is used for the reaction preventing film (first reaction preventing film) 9a, an alumina film (Al ₂ O ₃ film) or a titanium oxide film (TiO ₂ film) is used instead. Etc. may be used.

  Next, as shown in FIG. 11, the insulating film 8 and the reaction preventing film 9a on the source / drain region 3 are etched to form a contact opening CH1. The reaction preventing film 10 and the contact plug 11 are embedded in the contact opening CH1. Since the subsequent steps are the same as those in the first embodiment, the description thereof is omitted.

  As described above, in the semiconductor memory device and the manufacturing method thereof according to the present embodiment, there is no step of processing the reaction preventing film 9a before forming the capacitor, and the reaction preventing film 9a continuously exists below the capacitor portion. For this reason, compared with Example 1, it has a structure in which oxygen intrusion from the contact interface between the reaction preventing films 9a and 19 is less likely to occur, and the yield reduction due to oxidation of the contact interface can be further suppressed. .

  Next, a semiconductor memory device and a manufacturing method thereof according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 12 is a cross-sectional view showing a semiconductor memory device. In this embodiment, the arrangement of the reaction preventing film is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 12, the semiconductor memory device 72 is provided with a plurality of memory cell transistors 40 and ferroelectric capacitors 50 on the semiconductor substrate 1.

  Here, the semiconductor memory device 72 is applied to a chain type FeRAM, but can also be applied to a 1T1C (1 transistor + 1 capacitor) type, 2T2C type, 1T2C type, 6T4C type FeRAM, and the like.

  In the semiconductor memory device 72, a reaction preventing film (first reaction preventing film) 9 b is provided on the STI 2, the insulating film 6, the sidewall film 7, and the source / drain region 3. Contact opening CH 1 is provided in reaction preventing film 9 b on source / drain region 3. A groove portion 12 having a concave shape from which the reaction preventing film 10 and the contact plug 11 are removed by etching is provided above the contact opening CH1 in which the reaction preventing film 10 and the contact plug 11 are embedded. The reaction preventing film 9b is provided on the entire semiconductor memory device 72 excluding the contact opening CH1 so as to cover the upper and side surfaces of the memory cell transistor 40.

  Here, in the ferroelectric capacitor 50, the region other than the portion where the contact plug 11 is connected to the lower electrode film 14 is covered with a reaction preventing film (first reaction preventing film) 9b. The difference from the second embodiment is that the region from the lower portion of the ferroelectric capacitor 50 to immediately above the semiconductor substrate 1 is filled with the reaction preventing film 9b.

  As a result, it becomes difficult for oxygen to enter the interface portion of the contact plug 11 as compared with the second embodiment, and the contact yield can be improved. Furthermore, since the reaction preventing film 9b is formed directly on the semiconductor substrate 1 without using an interlayer insulating film, the number of manufacturing steps can be reduced. Further, since the reaction preventing film 9b is provided in a region other than the contact opening CH1, it is possible to completely block the hydrogen entry path.

  The manufacturing method of the semiconductor memory device 72 differs from the first embodiment in that the reaction preventing film 9b is formed around the memory cell transistor 40 without forming the insulating film 8 around the memory cell transistor 40. is there. Therefore, a description of the method for manufacturing the semiconductor memory device 72 using the drawings is omitted.

  As described above, in the semiconductor memory device and the manufacturing method thereof according to this embodiment, a plurality of memory cell transistors 40 and ferroelectric capacitors 50 are provided on the semiconductor substrate 1. A reaction preventing film 9b is formed on the upper and side surfaces of the memory cell transistor 40, the source / drain regions 3 of the memory cell transistor 40, and the STI2. A contact opening CH1 is provided in the reaction preventing film 9b on the source or drain of the memory cell transistor 40, and the reaction preventing film 10 and the contact plug 11 are embedded in the contact opening CH1. The ferroelectric capacitor 50 includes a lower electrode film 14, a ferroelectric film 15, and an upper electrode film 16 that are stacked. The lower electrode film 14 is also embedded in a recess shape above the contact plug 11 provided on one of the source and drain of the memory cell transistor 40 and is electrically connected to the contact plug 11. It is connected to the contact plug 11 via. The upper electrode film 16 is connected to the wiring layer 25 through the contact plug 23. Both ends of the interface where the contact plug 11 and the reaction preventing film 13 are connected and the upper side surface of the contact plug 11 are covered with the reaction preventing film 9b. In the ferroelectric capacitor 50, the region excluding the contact plugs 11 and 23 is covered with the reaction preventing film 9b and the reaction preventing film 19 in contact with the reaction preventing film 9b. As a result, it becomes more difficult for oxygen to enter the interface portion of the contact plug 11 than in the second embodiment, and an improvement in contact yield is expected. Furthermore, since the reaction preventing film 9b is formed directly on the semiconductor substrate 1 without using an interlayer insulating film, the number of manufacturing steps can be reduced. Further, since the reaction preventing film 9b is provided in a region other than the contact opening CH1, it is possible to completely block the hydrogen entry path.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the ferroelectric capacitor 50 is provided in the vertical direction with respect to the semiconductor substrate 1, but the ferroelectric capacitor may be provided in the horizontal direction with respect to the semiconductor substrate 1. Further, only the contact plug 23 is embedded in the contact opening CH2, and only the contact plug 24 is embedded in the contact opening CH3, but a reaction preventing film may be provided therebetween.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A semiconductor substrate, a gate electrode provided on the semiconductor substrate, connected to a word line, and provided via a gate insulating film, and a source and drain provided on the surface of the semiconductor substrate with the gate electrode interposed therebetween And a memory cell transistor having a configuration in which a region in contact with the first contact plug is protruded downward from the other region. A lower electrode film electrically connected to the first contact plug; a ferroelectric film provided on the lower electrode film; provided on the ferroelectric film; A ferroelectric capacitor composed of an upper electrode film connected to the contact plug; an upper side surface of the first contact plug; the first contact plug; A first reaction preventing film provided so as to cover a side surface of a region to which the lower electrode film is electrically connected and a bottom of the lower electrode film; the lower electrode film; the ferroelectric film; and the upper part A second reaction preventing layer which is provided so as to cover a side surface of the electrode film, an upper portion of the upper electrode film, and an interface where the upper electrode film and the second contact plug are in contact with each other, and is in contact with the first reaction preventing film; And a ferroelectric capacitor in which a region excluding a portion in contact with the first and second contact plugs is covered with the first and second reaction preventing films.

(Supplementary Note 2) The first and second reaction preventing films are a silicon nitride film (SiN film), an alumina film (Al ₂ O ₃ film), or a titanium oxide film (TiO ₂ film). Semiconductor memory device.

(Supplementary note 3) The semiconductor memory device according to supplementary note 1 or 2, wherein a third reaction preventing film is provided between the first contact plug and the lower electrode film.

(Supplementary note 4) The semiconductor memory device according to any one of supplementary notes 1 to 3, wherein the third reaction preventing film is an iridium film (Ir film), an iridium oxide film (IrO ₂ film), a TiAlN film, or a TiAl film. .

(Appendix 5) The upper and lower electrode films are platinum films (Pt films), iridium films (Ir films), iridium oxide films (IrO ₂ films), or SRO films (Strontium Ruthenium Oxide films). The semiconductor memory device according to any one of the above.

(Supplementary Note 6) The ferroelectric film may be a PZT film (Pb (Zr, Ti) O ₃ film), an SBT film (SrBi ₂ Ta ₂ O ₉ film), or a BLT film ((Bi, La) ₄ Ti ₃ O. _12. The semiconductor memory device according to any one of appendices 1 to 5, which is ₁₂ films).

(Supplementary note 7) Any one of Supplementary notes 1 to 6, wherein a fourth reaction prevention film is provided on the second reaction prevention film and is provided so as to cover the ferroelectric capacitor and the memory cell transistor. The semiconductor memory device described.

1 Semiconductor substrate 2 Shallow trench isolation (STI)
3 Source / drain region 4 Gate insulating film 5 Gate electrode film 6, 8, 20, 22, 26, 28 Insulating film 7 Side wall films 9, 9a, 9b, 10, 13, 19, 21 Reaction preventing films 11, 23, 24 Contact plug 12 Groove 14 Lower electrode film 15 Ferroelectric film 16 Upper electrode film 17 Hard mask 25, 27 Wiring layers 31, 32 Resist film 40 Memory cell transistor 50 Ferroelectric capacitor 70-72 Semiconductor memory device CH1-CH3 Contact opening Part

Claims (5)

A semiconductor substrate;
A memory cell transistor provided on the semiconductor substrate, connected to a word line and provided via a gate insulating film, and a source and drain provided on the surface of the semiconductor substrate with the gate electrode interposed therebetween;
The first contact is provided on a first contact plug connected to one of the source and the drain, and has a shape in which a region in contact with the first contact plug protrudes downward from the other region. A lower electrode film electrically connected to the plug, a ferroelectric film provided on the lower electrode film, and an upper electrode provided on the ferroelectric film and having an upper portion connected to the second contact plug A ferroelectric capacitor composed of a film;
The first contact plug is provided so as to cover an upper side surface of the first contact plug, a side surface of a region where the first contact plug and the lower electrode film are electrically connected, and a bottom portion of the lower electrode film. An anti-reaction membrane,
The lower electrode film, the ferroelectric film, and the upper electrode film are provided so as to cover the side surfaces, the upper part of the upper electrode film, and the interface where the upper electrode film and the second contact plug are in contact with each other, A second reaction preventing film in contact with the first reaction preventing film;
A semiconductor memory device comprising: A semiconductor substrate;
A memory cell transistor provided on the semiconductor substrate, connected to a word line and provided via a gate insulating film, and a source and drain provided on the surface of the semiconductor substrate with the gate electrode interposed therebetween;
The first contact is provided on a first contact plug connected to one of the source and the drain, and has a shape in which a region in contact with the first contact plug protrudes downward from the other region. A lower electrode film electrically connected to the plug, a ferroelectric film provided on the lower electrode film, and an upper electrode provided on the ferroelectric film and having an upper portion connected to the second contact plug A ferroelectric capacitor composed of a film;
An upper side surface of the first contact plug, a side surface of a region where the first contact plug and the lower electrode film are electrically connected, a bottom portion of the lower electrode film, and an upper portion of the memory cell transistor A first reaction-preventing film provided to cover; side surfaces of the lower electrode film, the ferroelectric film, and the upper electrode film; an upper portion of the upper electrode film; the upper electrode film; and the second electrode film. A second reaction preventing film provided so as to cover an interface with which the contact plug contacts and an upper portion of the memory cell transistor; and a contact with the first reaction preventing film;
A semiconductor memory device comprising: A semiconductor substrate;
A memory cell transistor provided on the semiconductor substrate, connected to a word line and provided via a gate insulating film, and a source and drain provided on the surface of the semiconductor substrate with the gate electrode interposed therebetween;
The first contact is provided on a first contact plug connected to one of the source and the drain, and has a shape in which a region in contact with the first contact plug protrudes downward from the other region. A lower electrode film electrically connected to the plug, a ferroelectric film provided on the lower electrode film, and an upper electrode provided on the ferroelectric film and having an upper portion connected to the second contact plug A ferroelectric capacitor composed of a film;
A side surface of the first contact plug; a side surface of a region where the first contact plug and the lower electrode film are electrically connected; a bottom portion of the lower electrode film; an upper portion and a side surface of the memory cell transistor; A first reaction preventing film provided so as to cover
Side surfaces of the lower electrode film, the ferroelectric film, and the upper electrode film, an upper portion of the upper electrode film, an interface between the upper electrode film and the second contact plug, and an upper portion of the memory cell transistor A second reaction-preventing film in contact with the first reaction-preventing film,
A semiconductor memory device comprising:   4. The semiconductor memory device according to claim 1, wherein a third reaction preventing film is provided between the first contact plug and the lower electrode film. 5. Forming a memory cell transistor on a semiconductor substrate;
On the source and drain of the memory cell transistor, a first contact plug having a lower portion in contact with the first insulating film, an upper portion in contact with the first reaction prevention film, and connected to the source or drain of the memory cell transistor is provided. Forming, and
Etching an upper portion of the first contact plug to form a groove having a concave shape in which a side surface of the first reaction preventing film is exposed;
Forming a second reaction preventing film, a lower electrode film, a ferroelectric film, and an upper electrode film on the groove and the first reaction preventing film;
Selectively etching the upper electrode film, the ferroelectric film, the lower electrode film, and the second reaction preventing film to form a ferroelectric capacitor;
Covering the upper part of the upper electrode film and the side surfaces of the upper electrode film, the ferroelectric film, the lower electrode film, and the second reaction preventing film, the third electrode is in contact with the first reaction preventing film. Forming a reaction preventive film of
Etching the third reaction preventing film on the upper electrode film, and forming a second contact plug in contact with the upper electrode film in the etched opening;
A method of manufacturing a semiconductor memory device, comprising:

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