JP2011018443A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time of a writing operation in a nonvolatile semiconductor memory.SOLUTION: The nonvolatile semiconductor memory includes: an electrically rewritable nonvolatile memory cell having a control gate, a drain and a source; a transmission transistor having a source connected to a drain to transmit a drain voltage to the drain of the memory cell; an operation control circuit for controlling a program operation to increase the threshold voltage of the memory cell and a verify operation executed before or after the program operation to check the threshold value of the memory cell; a drain switching circuit for connecting the gate of the transmission transistor to a first voltage line to which a first voltage is supplied during the verify operation and to a second voltage line to which a second voltage is supplied during the program operation; a gate switching circuit for connecting the control gate of the memory cell to a third voltage line to which a third voltage is supplied during the verify operation, and to a fourth voltage line to which a fourth voltage is supplied during the program operation; and a booster circuit for generating the fourth voltage on the fourth voltage line.

Description

  The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a method for generating a high voltage when writing data.

  A nonvolatile semiconductor memory such as a flash memory stores a logical value of write data as a threshold voltage of a memory cell. For example, the binary memory cell stores “logic 1” when the threshold voltage is low, and stores “logic 0” when the threshold voltage is high. In general, an operation for lowering the threshold voltage is called “erase”, and an operation for raising the threshold voltage is called “write” or “program”.

  In the NOR type flash memory, the control gate of the memory cell is connected to a word line selected according to an address. The drain of the memory cell is connected to a bit line selected according to the address. The sources of the memory cells are connected to a common source line.

  The data write operation requires a verify operation for confirming the threshold voltage of the memory cell and a program operation for increasing the threshold voltage of the memory cell. In the verify operation, for example, a high voltage (for example, 5 V) is supplied to the gate of the memory cell, and a power supply voltage (for example, 1.8 V) is supplied to the gate of the transfer transistor connected to the bit line. A voltage lower than the power supply voltage by the threshold voltage of the transfer transistor is supplied to the drain of the memory cell via the transfer transistor. The threshold voltage of the memory cell is confirmed by the current flowing through the memory cell. That is, a memory cell that needs to be programmed is identified.

  In the program operation, a high voltage (for example, 9V) is supplied to the gate of the memory cell, and a high voltage (for example, 5.5V) is supplied to the drain of the memory cell via the transfer transistor. In order to reliably transmit the drain voltage, a high voltage (for example, 9 V) is supplied to the gate of the transmission transistor. Then, charges are trapped in the charge storage layer of the memory cell, and the threshold voltage increases. Thereafter, the verify operation and the program operation are repeatedly performed until the threshold voltage of each memory cell reaches a desired value.

  The above-described flash memory has a plurality of booster circuits in order to generate a plurality of types of high voltages. The booster circuit starts an operation in response to a write command and stops the operation in response to the completion of the write operation (for example, JP-A-2002-230985).

  As described above, the write operation is executed by repeating the verify operation and the program operation. At this time, the gate voltage of the memory cell and the gate voltage of the transfer transistor must be largely changed between the verify operation and the program operation. In particular, the gate voltage of the transfer transistor needs to be increased from 1.8 V to 9 V when shifting from the verify operation to the program operation. The boosting time until the booster circuit generates 9 V is long, and the write cycle time is long.

  Recently, a non-volatile multi-level semiconductor memory for storing a plurality of bits of data in one memory cell has been developed. In this type of multi-level memory cell, the program operation is executed in a plurality of times (step program system) in order to set the threshold voltage accurately. In the step program method, since the threshold voltage distribution width is reduced, the read margin is improved. That is, multi-value data can be reliably stored in the memory cell. On the other hand, in the step program method, one write operation is executed by repeating the verify operation and the program operation a plurality of times. Since the transition from the verify operation to the program operation is performed a plurality of times during one write operation, the above-described boost time has a great influence.

  Hereinafter, prior art documents related to the present invention will be listed.

JP 2002-230985 A

  An object of the present invention is to shorten the write operation time of a nonvolatile semiconductor memory.

  In one form of the nonvolatile semiconductor memory of the present invention, a transmission transistor for transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. The operation control circuit controls a program operation that increases the threshold voltage of the memory cell and a verify operation that is executed before and after the program operation to check the threshold voltage of the memory cell. The drain switching circuit connects the gate of the transmission transistor to the first voltage line to which the first voltage is supplied during the verify operation. The drain switching circuit connects the gate of the transmission transistor to the second voltage line to which the second voltage is supplied during the program operation. Since the second voltage can be supplied to the transmission transistor only by the switching operation (selection operation) of the drain switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data into the memory cell can be shortened.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the first booster circuit starts operation during the verify operation before the program operation, and generates the second voltage on the second voltage line. Since the second voltage line can be set to the second voltage in advance before the program operation, the second voltage can be supplied to the gate of the transmission transistor when the program operation starts. As a result, the program operation time can be shortened.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the operation control circuit repeatedly performs the verify operation and the program operation until the threshold voltage of the memory cell reaches a desired value. The first booster circuit continues to generate the second voltage on the second voltage line during the execution of the verify operation and the program operation. For this reason, the frequency of operation and stop of the first booster circuit can be lowered, and the operation control circuit can be easily controlled.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the gate switching circuit connects the control gate of the memory cell to the third voltage line to which the third voltage is supplied during the verify operation. The gate switching circuit is connected to the fourth voltage line to which the fourth voltage is supplied during the program operation. Since the fourth voltage can be supplied to the control gate of the memory cell only by the switching operation (selection operation) of the gate switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data into the memory cell can be shortened.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the second booster circuit starts operation during the verify operation before the program operation, and generates the fourth voltage on the fourth voltage line. Since the fourth voltage line can be set to the fourth voltage in advance before the program operation, the fourth voltage can be supplied to the control gate of the memory cell when the program operation is started. As a result, the program operation time can be shortened.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the operation control circuit repeatedly performs the verify operation and the program operation until the threshold voltage of the memory cell reaches a desired value. The second booster circuit resets the fourth voltage line to the initial voltage every time the program operation is completed. In other words, the second booster circuit generates the fourth voltage based on the initial voltage for each verify operation. Therefore, the fourth voltage can be accurately set for each program, and the threshold voltage of the memory cell can be accurately set to a desired value.

  In another aspect of the nonvolatile semiconductor memory of the present invention, the operation control circuit sets the fourth voltage generated by the second booster circuit sequentially higher for each program operation that is repeatedly executed. That is, the nonvolatile semiconductor memory has a so-called step program function. Since the program voltage (fourth voltage) necessary for each step can be accurately generated, the threshold voltages of a plurality of memory cells can be distributed in a desired region. As a result, the write operation time can be shortened without reducing the read margin.

  In another embodiment of the nonvolatile semiconductor memory of the present invention, the third booster circuit generates the fifth voltage during the verify operation and generates the sixth voltage during the program operation. The output node of the third booster circuit is connected to the drain of the transmission transistor. The gate switching circuit selects the fifth voltage as the third voltage during the verify operation. That is, the fifth voltage generated by the third booster circuit during the verify operation can be shared by the drain voltage of the transfer transistor and the control gate voltage of the memory cell. In general, the voltage (fifth voltage) supplied to the control gate of the memory cell during the verify operation is close to the voltage (sixth voltage) supplied to the drain of the transfer transistor during the program operation. Therefore, the third booster circuit can change the generated voltage from the fifth voltage to the sixth voltage in a short time when shifting from the verify operation to the program operation. As a result, the program operation can be started in a short time after the verify operation, and the data write time to the memory cell can be shortened.

  In the nonvolatile semiconductor memory of the present invention, the second voltage can be supplied to the transfer transistor only by the switching operation (selection operation) of the drain switching circuit, so that the program operation can be started in a short time after the verify operation. As a result, the time for writing data into the memory cell can be shortened.

  In the nonvolatile semiconductor memory of the present invention, since the second voltage line can be set to the second voltage in advance before the program operation, the second voltage can be supplied to the gate of the transmission transistor at the start of the program operation. As a result, the program operation time can be shortened.

  In the nonvolatile semiconductor memory of the present invention, the frequency of operation and stop of the first booster circuit can be reduced, and the operation control circuit can be easily controlled.

  In the nonvolatile semiconductor memory of the present invention, since the fourth voltage can be supplied to the control gate of the memory cell only by the switching operation (selection operation) of the gate switching circuit, the program operation can be started in a short time after the verify operation. As a result, the time for writing data into the memory cell can be shortened.

  In the nonvolatile semiconductor memory of the present invention, since the fourth voltage line can be set to the fourth voltage in advance before the program operation, the fourth voltage can be supplied to the control gate of the memory cell at the start of the program operation. As a result, the program operation time can be shortened.

  In the nonvolatile semiconductor memory of the present invention, the fourth voltage can be accurately set for each program, and the threshold voltage of the memory cell can be accurately set to a desired value.

  In the nonvolatile semiconductor memory of the present invention, the threshold voltages of a plurality of memory cells can be distributed in a desired region. As a result, the write operation time can be shortened without reducing the read margin.

  In the nonvolatile semiconductor memory of the present invention, the third booster circuit can change the generated voltage from the fifth voltage to the sixth voltage in a short time when shifting from the verify operation to the program operation. As a result, the program operation can be started in a short time after the verify operation, and the data write time to the memory cell can be shortened.

FIG. 1 is a block diagram showing a first embodiment of a nonvolatile semiconductor memory of the present invention. FIG. 2 is a circuit diagram showing details of the booster circuit VDPP shown in FIG. FIG. 3 is a circuit diagram showing details of the booster circuit VPPP shown in FIG. FIG. 4 is a circuit diagram showing details of the booster circuit VPPIP shown in FIG. FIG. 5 is a circuit diagram showing details of the multiplexer XMUX and the row decoder XDEC shown in FIG. FIG. 6 is a circuit diagram showing details of the multiplexer YMUX and the column decoder YDEC shown in FIG. FIG. 7 is a waveform diagram showing the write operation of the flash memory of the present invention. FIG. 8 is a waveform diagram showing the write operation of the flash memory before the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. A part of the block to which the thick line is connected is composed of a plurality of circuits. The same reference numerals as the signal names are used for signal lines to which signals (voltages) are transmitted.

  FIG. 1 shows an embodiment of a nonvolatile semiconductor memory of the present invention. This nonvolatile semiconductor memory is formed as a NOR type flash memory chip on a silicon substrate using a CMOS process.

  The flash memory includes an operation control circuit OPC, boosting circuits VPPP, VPDP, VPPIP, multiplexers XMUX, YMUX, row decoder XDEC, column decoder YDEC, and memory cell array ARY.

  The operation control circuit OPC outputs a timing signal and a control signal to main circuits in response to a command signal CMD (chip enable signal / CE, write enable signal / WE, etc.) supplied from the outside.

  The booster circuit VPPP (second booster circuit) operates in synchronization with the timing signal from the operation control circuit OPC, and generates the high voltage VPP (fourth voltage) on the high voltage line VPP (fourth voltage line). The booster circuit VPDP (third booster circuit) operates in synchronization with a timing signal from the operation control circuit OPC, and applies a high voltage VPD (fifth voltage or sixth voltage) corresponding to the control signals VSEL, PSEL to a high voltage line. Generated to VPD (third voltage line). The booster circuit VPPIP (first booster circuit) operates in synchronization with the timing signal from the operation control circuit OPC, and generates the high voltage VPPI (second voltage) on the high voltage line VPPI (second voltage line).

  The multiplexer XMUX (gate switching circuit) outputs either the high voltage VPP or the high voltage VPD to the row decoder XDEC as the gate voltage VG according to the control signal SEL3 from the operation control circuit OPC. The multiplexer YMUX (drain switching circuit) receives one of the power supply voltage VCC (first voltage) or the high voltage VPPI supplied to the power supply line VCC (first voltage line) in accordance with the control signal SEL4 from the operation control circuit OPC. Output to the gate of the transfer transistor TT in the column decoder YDEC.

  The row decoder XDEC has a circuit that supplies a gate voltage VG to a word line WL selected by a decode signal of an address signal XADD supplied from the outside of the flash memory. The column decoder YDEC has a transmission transistor TT for supplying the drain voltage VD to the bit line BL selected by the decode signal of the address signal YADD supplied from the outside of the flash memory.

  The memory cell array ARY includes a plurality of memory cells MC arranged in a matrix, word lines WL connected to the control gates G of the memory cells arranged in the horizontal direction in the figure, and drains D of the memory cells arranged in the vertical direction in the figure. And a source line connected to the source S of the memory cell. The memory cell MC is composed of a transistor (cell transistor) having a trap gate for accumulating charges. The trap gate is formed of an insulating film such as a nitride film. For this reason, the charges trapped in the trap gate do not move in the trap gate. Using this, the threshold voltage of the cell transistor can be locally changed. In this embodiment, the memory cell MC operates as an electrically rewritable binary memory cell by taking in and out charges only at one place of the trap gate.

  FIG. 2 shows details of the booster circuit VPDP shown in FIG. In the figure, the shaded transistors are pMOS transistors, and the unshaded transistors are nMOS transistors. The capacitor is formed by connecting the source and drain of the nMOS transistor to each other.

  The booster circuit VPDP includes a pump unit PUMP that generates a boosted voltage and an adjustment unit ADJ for setting the high voltage VPD to a predetermined voltage. The pump unit PUMP boosts the power supply voltage VCC (1.8V) by pumping with the clock signal CLK1 through the pump node PND capacitor C1 clamped to a predetermined positive voltage by the clamp circuit, and charges due to the boost are boosted nodes Transfer to BND. The clock signal CLK1 is generated by an oscillator inside the booster circuit VPDP in accordance with a control signal from the operation control circuit OPC.

  The adjustment unit ADJ compares the comparison voltage DIV obtained by capacitively dividing the high voltage VPD with the reference voltage VREF, controls the gate of the discharge transistor DCT according to the comparison result, and sets the high voltage VPD to a predetermined voltage. The reference voltage VREF is generated by a reference voltage generation circuit formed in the flash memory. The reference voltage VREF is common to the booster circuits VPDP, VPPP, and VPPIP. The adjustment unit ADJ connects the capacitor C2 to the node DIV when the control signal VSEL is at a high level, and connects the capacitor C1 to the node DIV when the control signal PSEL is at a high level. The capacitance value of the capacitor C1 is larger than the capacitance value of the capacitor C2. The operation control circuit OPC shown in FIG. 1 sets the control signals VSEL and PSEL to a high level and a low level during a verify operation, and sets the control signals VSEL and PSEL to a low level and a high level, respectively, during a program operation. . Node DIV is set to a voltage corresponding to the capacity division of two capacitors connected between high voltage node VPD and ground line VSS. The high voltage VPD is boosted to 5 V (fifth voltage) and 5.5 V (sixth voltage) using the power supply voltage VCC (1.8 V) during the verify operation and the program operation, respectively. The difference in high voltage VPD between the verify operation and the program operation is 0.5V. Therefore, the high voltage VPD can be set quickly when shifting from the verify operation to the program operation.

FIG. 3 shows details of the booster circuit VPPP shown in FIG.
The booster circuit VPPP has a plurality of capacitors for setting the voltage of the node DIV in a plurality of ways. These capacitors and the node DIV are connected to the control signals PSEL1, PSEL2,. . . , PSELn, respectively. Control signals PSEL1, PSEL2,. . . , PSELn are output from the operation control circuit OPC. The booster circuit VPPP applies the high voltage VPP to the control signals PSEL1, PSEL2,. . . , 9V, 9.1V, 9.2V,. . . And rise.

FIG. 4 shows details of the booster circuit VPIP shown in FIG.
In the booster circuit VPPIP, only two capacitors are connected in series via the node DIV. The other logical configuration is the same as that of the booster circuit VPDP shown in FIG. For this reason, the high voltage VPPIP generated when the booster circuit VPPIP operates is of one type. Specifically, when the booster circuit VPPIP operates, the high voltage VPPI rises from 1.8V (= VCC) to 9V.

  FIG. 5 shows details of the multiplexer XMUX and the row decoder XDEC shown in FIG.

  When the control signal SEL3 is at a low level (verify operation), the multiplexer XMUX turns on the transistor PM12 and outputs the high voltage VPD (third voltage) as the gate voltage VG. When the control signal SEL3 is at a high level (program operation), the multiplexer XMUX turns on the transistor PM10 and outputs the high voltage VPP (fourth voltage) as the gate voltage VG.

  The row decoder XDEC outputs the gate voltage VG to the word line WL when the decode signal XD (negative logic) of the address signal XADD is low, and outputs the ground voltage to the word line WL when the decode signal XD is high. To do. That is, the gate voltage VG is supplied to the word line WL selected by the address signal XADD.

  FIG. 6 shows details of the multiplexer YMUX and the column decoder YDEC shown in FIG.

  When the control signal SEL4 is at a low level (verify operation), the multiplexer YMUX turns on the transistor PM20 and outputs the power supply voltage VCC (first voltage) as the drain voltage VD. When the control signal SEL4 is at a high level (program operation), the multiplexer YMUX turns on the transistor PM22 and outputs the high voltage VPPI (second voltage) as the drain voltage VD.

The column decoder YDEC includes a transmission transistor TT that transmits the high voltage VPD to the bit line BL. The transfer transistor TT is turned on when the decode signal YD (positive logic) of the address signal YADD is at a high level, and transmits the high voltage VPD to the bit line BL (drain of the memory cell MC). That is, the high voltage VPD is supplied to the bit line BL selected by the address signal YADD. Transfer transistor TT is turned off when the decode signal YD of low level, a floating state of the bit line BL. In practice, the voltage transmitted to the bit line BL is maximized by subtracting the threshold voltage of the transfer transistor TT from the gate voltage of the transfer transistor TT.

FIG. 7 shows a write operation of the flash memory of the present invention.
Here, the write operation is an operation of programming “logic 0” in the memory cell MC. In the present embodiment, the write operation employs a step program method in which the verify operation and the program operation are repeated, the threshold voltage of the memory cell MC is gradually increased, and the expected value is set.

  First, in the first verify period VRF, a verify operation is performed in order to confirm the threshold voltage of the memory cell MC. In the verify operation, the booster circuit VPDP generates 5 V at the node VPD (FIG. 7A). The multiplexer XMUX selects the node VPD during the verify period VRF. Therefore, the row decoder XDEC selected according to the address signal XADD changes the corresponding word line WL to 5V. Then, the gate voltage GATE of the memory cell MC is set to 5V (FIG. 7B).

  The multiplexer YMUX outputs the power supply voltage VCC (1.8 V) to the node VD during the verify period VRF (FIG. 7C). The column decoder YDEC selected according to the address signal YADD sets the gate of the transfer transistor TT to the power supply voltage VCC. For this reason, the drain voltage DRAIN (bit line BL) of the memory cell MC is set to a value obtained by subtracting the threshold voltage of the transfer transistor from the power supply voltage VCC (FIG. 7D). Then, the memory cell MC to be programmed is determined according to the current flowing through the memory cell MC.

  In the verify period VRF, the booster circuits VPPIP and VPPP start operation and generate the high voltages VPPI and VPP, respectively (FIG. 7 (e, f)). By starting the generation of the high voltages VPPI and VPP necessary for the program operation in advance during the verify operation before the program operation, the program operation can be started quickly.

  After the verify operation, a program operation is performed on the memory cell MC that requires data writing. In the program period PRG in which the program operation is executed, the booster circuits VPPIP and VPPP have already generated boosted voltages VPPI and VPP, respectively (FIG. 7 (g, h)). The multiplexer XMUX stops selecting the boosted voltage VPD according to the control signal SEL3 and starts selecting the boosted voltage VPP. Then, the boosted voltage VPP (9 V) is output to the node VG. The row decoder XDEC selected according to the address signal XADD changes the corresponding word line WL to the boost voltage VPP. Then, the gate voltage GATE of the memory cell MC is set to 9V (FIG. 7 (i)).

The booster circuit VPDP changes the boosted voltage VPD from 5V to 5.5V according to the control signals VSEL and PSEL (FIG. 7 (j)). The multiplexer YMUX stops selecting the power supply voltage VCC in response to the control signal SEL4 and starts selecting the boost voltage VPPI. Then, the boosted voltage VPPI (9 V) is output to the node VD (FIG. 7 (k)). The column decoder YDEC selected according to the address signal YADD sets the gate of the transfer transistor TT to the boost voltage VPPI. Therefore, the drain voltage DRAIN (bit line BL) of the memory cell MC is set to the boosted voltage VPD (5.5 V) (FIG. 7 (l)). Then, the memory cell MC selected by the word line WL and bit line BL, and the program operation to increase the threshold voltage Ru is executed.

  In the program period PRG, the boosted voltages VPP and VPPI are generated in advance in the verify period VRF. Further, the voltage that the booster circuit VPDP needs to boost is 0.5V, and the boosted voltage VPD rises to 5.5V in a short time. For this reason, the period T1 required for setting the gate voltage GATE and the drain voltage DRAIN depends only on the switching period of the multiplexers XMUX and YMUX. In other words, the period necessary for generating the boosted voltages VPP and VPPI is not included in the program period PRG. For this reason, the program period PRG is shortened and the write operation time is shortened.

  Next, after the discharge period DSC, the verify operation for confirming the threshold voltage of the memory cell MC is executed again. In the verify operation, when it is determined that the threshold voltage of the memory cell MC to be programmed is low, the program operation (not shown) is executed again (step program method). In the discharge period DSC, the boosted voltages VPD and VPP are reset to the power supply voltage VCC. The boosted voltage VPPI is not reset and maintains 9V. The gate voltage GATE and the drain voltage DRAIN are set to the ground voltage VSS.

  By resetting the boosted voltage VPP to the power supply voltage VCC, it is possible to accurately generate the gate voltage GATE that needs to be increased by 0.1 V for each program operation. Further, since the boosted voltage VPPI is maintained at 9 V, the booster circuit VPPIP does not need to repeat operation / stop during one write operation. This facilitates control of the operation control circuit OPC.

FIG. 8 shows a write operation of the flash memory before the present invention.
In the step program type flash memory before the present invention, the generation of the boosted voltages VPPI, VPD, and VPP is started in response to the start of the program operation. Therefore, in the program period PRG, the period T1 required for setting the gate voltage GATE and the drain voltage DRAIN depends on the period in which the booster circuit generates the boosted voltages VPPI, VPD, and VPP, respectively. Therefore, the period T1 becomes longer than that in FIG. 7 described above, and the program period PRG becomes longer. In particular, in the step program method, since the period T1 exists a plurality of times, the influence on the write operation time is large.

  As described above, in the present embodiment, in the data write operation, the booster circuit VPPIP starts generating the boost voltage VPPI in the verify period VRF before the program period PRG. Therefore, the multiplexer YMUX can supply the boosted voltage VPPI to the gate of the transfer transistor TT in the program period PRG simply by performing a switching operation according to the control signal SEL4. Therefore, the program operation can be started immediately after the verify operation. As a result, the time for writing data to the memory cell MC can be shortened.

  Similarly, in the data write operation, the booster circuit VPPP starts generating the boosted voltage VPP in the verify period VRF before the program period PRG. Therefore, the multiplexer XMUX can supply the boosted voltage VPP to the control gate of the memory cell MC in the program period PRG simply by performing a switching operation according to the control signal SEL3. Therefore, the program operation can be started immediately after the verify operation. As a result, the time for writing data to the memory cell MC can be shortened.

  In a flash memory employing the step program method, the booster circuit VPPIP continues to generate the boosted voltage VPPI during the write operation. For this reason, the frequency of operation and stop of the booster circuit VPPIP can be lowered, and the operation control circuit OPC can be easily controlled.

  Further, the operation control circuit OPC sets the boosted voltage VPP generated by the booster circuit VPPP higher by 0.1V sequentially for each program operation that is repeatedly executed. The booster circuit VPPP resets the boosted voltage VPP to the power supply voltage VCC every time the program operation is completed. Therefore, by generating the boosted voltage VPP for each program based on the power supply voltage VCC, the boosted voltage VPP (program voltage) required for each step can be set accurately, and the threshold voltage of the memory cell MC is set to a desired value. Can be set accurately.

  The booster circuit VPDP generates a boosted voltage VPD of 5V to be supplied to the control gate of the memory cell MC during the verify period VRF, and a boosted voltage VPD of 5.5V to be supplied to the drain of the memory cell MC during the program period PRG. Is generated. By using the booster circuit VPDP for both the gate voltage GATE and the drain voltage DRAIN of the memory cell MC, the boosted voltage used for the verify operation and the program operation can be efficiently generated.

  The difference between the gate voltage GATE used for the verify operation and the drain voltage DRAIN used for the program operation is close to 0.5V. For this reason, the booster circuit VPDP can change the boosted voltage VPD from 5V to 5.5V in a short time when shifting from the verify operation to the program operation. As a result, the program operation can be started in a short time after the verify operation, and the data write time to the memory cell can be shortened.

  In the above-described embodiment, an example in which the present invention is applied to a flash memory chip has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a flash memory core mounted on a system LSI.

  In the above-described embodiment, the example in which the present invention is applied to a flash memory having binary memory cells has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a flash memory having multilevel memory cells.

  In the above-described embodiment, the example in which the present invention is applied to the NOR type flash memory has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a NAND type or virtual ground type flash memory.

  In the above-described embodiment, the example in which the present invention is applied to the write operation of the memory cell having the trap gate has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a write operation of a memory cell having a floating gate.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

OPC operation control circuit, VPP, VPDP, VPPIP booster circuit, XMUX, YMUX multiplexer, XDEC row decoder, YDEC column decoder.

Claims (3)

An electrically rewritable nonvolatile memory cell having a control gate, a drain and a source;
A transfer transistor having a source connected to the drain to transfer a drain voltage to the drain of the memory cell;
An operation control circuit for controlling a program operation for increasing the threshold voltage of the memory cell and a verify operation executed before and after the program operation to confirm the threshold voltage of the memory cell;
A drain switch for connecting the gate of the transmission transistor to a first voltage line to which a first voltage is supplied during the verify operation and to a second voltage line to which a second voltage is supplied during the program operation. Circuit,
The control gate of the memory cell is connected to a third voltage line to which a third voltage is supplied during the verify operation, and is connected to a fourth voltage line to which a fourth voltage is supplied during the program operation. A gate switching circuit;
A first booster circuit for generating the second voltage supplied to the second power supply line by a boosting operation;
A second booster circuit that generates the fourth voltage supplied to the fourth voltage line by a boosting operation;
The operation control circuit repeatedly executes the verify program operation until a threshold voltage of the memory cell reaches a desired value,
The non-volatile semiconductor memory, wherein the second booster circuit resets the fourth voltage line to an initial voltage every time the program operation is completed. The operation control circuit, the second the fourth voltage booster circuit for generating sets sequentially higher for each operation the program to be repeatedly executed, the nonvolatile semiconductor memory according to claim 1. An electrically rewritable nonvolatile memory cell having a control gate, a drain and a source;
A transfer transistor having a source connected to the drain to transfer a drain voltage to the drain of the memory cell;
An operation control circuit for controlling a program operation for increasing the threshold voltage of the memory cell and a verify operation executed before and after the program operation to confirm the threshold voltage of the memory cell;
A drain switch for connecting the gate of the transmission transistor to a first voltage line to which a first voltage is supplied during the verify operation and to a second voltage line to which a second voltage is supplied during the program operation. Circuit,
A first booster circuit for generating the second voltage supplied to the second power supply line by a boosting operation;
A second booster circuit for generating the fourth voltage supplied to the fourth voltage line by a boosting operation;
A fifth voltage generated during the verify operation, to generate a sixth voltage during the program operation, a third boosting circuit output node is connected to a drain of the transfer transistor,
The control gate of the memory cell is connected to a third voltage line to which a third voltage is supplied during the verify operation, and is connected to a fourth voltage line to which a fourth voltage is supplied during the program operation. and a gate switching circuit, the gate switching circuit, during the verify operation, selecting the fifth voltage as the third voltage, a nonvolatile semiconductor memory.

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