JP2011018099A - Detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deterioration of elements configuring a plurality of detection circuits.SOLUTION: In a detection device, each of a plurality of detection circuits U generates a detection signal S corresponding to the presence/absence of a detected object. The plurality of detection circuits U are divided into a plurality of first detection circuits U1 and a plurality of second detection circuits U2. A driving circuit 20 selectively executes a first detecting operation to obtain the detection signal S by driving the plurality of first detection circuits U1 in each unit period PU and a second detecting operation to obtain the detection signal S by driving the plurality of second detection circuits U2 in each unit period PU.

Description

  The present invention relates to a technique for detecting the presence or absence (approach or contact) of an object to be detected.

  Techniques for detecting an object to be detected such as a user's body and a pen-shaped pointing member (stylus) have been proposed. For example, Patent Document 1 discloses a display device in which a plurality of detection circuits including light receiving elements are arranged in a matrix with display pixels. A detection signal corresponding to the illuminance (intensity) of the irradiation light with respect to the light receiving element is output from each of the plurality of detection circuits to the external device.

JP 2004-318819 A

  However, the technique of Patent Document 1 has a problem in that elements (for example, light receiving elements and switches) constituting each detection circuit are likely to deteriorate because all detection circuits are always driven to obtain detection signals. In view of the above circumstances, an object of the present invention is to suppress deterioration of a plurality of detection circuits.

  In order to solve the above problems, a detection apparatus according to the present invention includes a plurality of detection circuits each generating a detection signal corresponding to the presence or absence (contact or approach) of an object to be detected, and a plurality of detection circuits. A first detection operation for obtaining a detection signal by driving a plurality of first detection circuits in each unit period, and a plurality of second detection circuits different from each first detection circuit among the plurality of detection circuits in each unit period And a drive circuit that selectively executes a second detection operation for obtaining a detection signal by driving at.

  In the above embodiment, the first detection operation for acquiring the detection signal by driving the first detection circuit and the second detection operation for acquiring the detection signal by driving the second detection circuit are selectively executed. Compared with a configuration in which detection signals are always obtained from all detection circuits, it is possible to suppress deterioration of elements constituting each detection circuit.

  “Selectively executing the first detection operation and the second detection operation” means that the drive circuit executes the first detection operation and the drive circuit executes the second detection operation. Means. Therefore, configurations in which other detection operations can be executed in addition to the first detection operation and the second detection operation are also included in the scope of the present invention. For example, a configuration in which the drive circuit can execute a third detection operation for acquiring a detection signal by driving a third detection circuit different from the first detection circuit and the second detection circuit in addition to the first detection operation and the second detection operation. Naturally satisfies the requirement of “selectively executing the first detection operation and the second detection operation” as long as there is a case where the first detection operation is executed and a case where the second detection operation is executed. .

  In a preferred aspect of the present invention, each of the plurality of detection circuits is arranged corresponding to each intersection of the plurality of selection lines and the plurality of detection lines, and outputs a detection signal to the detection line by selection of the selection line. The plurality of detection lines include a plurality of first detection lines to which two or more first detection circuits are respectively connected, and a plurality of second detection lines to which two or more second detection circuits are respectively connected. Each of the plurality of first detection lines is located in each gap of the plurality of second detection lines, and the drive circuit includes a selection circuit that sequentially selects each of the plurality of selection lines in each unit period; A first detection operation for acquiring a detection signal output to each of the first detection lines in each unit period, and a first detection operation for acquiring a detection signal output to each of the plurality of second detection lines in each unit period. And an output circuit that selectively executes the two detection operations. In the above aspect, a set of two or more first detection circuits (first detection lines) and a set of two or more second detection circuits (second detection lines) are arranged in a distributed manner. Compared to a configuration in which one detection circuit (or a plurality of second detection circuits) is unevenly distributed only in a specific region, there is an advantage that it is easy to secure an area that can be used for detection of an object to be detected. In addition, the specific example of the above aspect is later mentioned as 1st Embodiment, for example.

  In a preferred aspect of the present invention, each of the plurality of detection circuits is arranged corresponding to each intersection of the plurality of selection lines and the plurality of detection lines, and outputs a detection signal to the detection line by selection of the selection line. The plurality of selection lines include a plurality of first selection lines to which two or more first detection circuits are respectively connected, and a plurality of second selection lines to which two or more second detection circuits are respectively connected. Each of the plurality of first selection lines is located in each gap of the plurality of second selection lines, and the drive circuit sequentially selects each of the plurality of first selection lines in each unit period. A selection circuit for selectively executing the operation and a second detection operation for sequentially selecting each of the plurality of second selection lines in each unit period; and a detection signal output to each of the plurality of detection lines. And an output circuit acquired in a unit period. In the above aspect, a set of two or more first detection circuits (first selection line) and a set of two or more second detection circuits (second selection line) are arranged in a distributed manner. Compared to a configuration in which one detection circuit (or a plurality of second detection circuits) is unevenly distributed only in a specific region, there is an advantage that it is easy to secure an area that can be used for detection of an object to be detected. In addition, the specific example of the above aspect is later mentioned as 2nd Embodiment, for example.

  A detection apparatus according to a preferred aspect of the present invention includes a control circuit that selects a detection operation (first detection operation or second detection operation) by a drive circuit. In the configuration including the operation unit operated by the user, for example, the control circuit changes the detection operation by the drive circuit from one of the first detection operation and the second detection operation when triggered by an operation on the operation unit. In addition, a configuration in which the control circuit changes the detection operation of the drive circuit from one of the first detection operation and the second detection operation to the other at every predetermined time, or the control circuit uses the drive circuit every time the detection device is turned on. According to the configuration in which the detection operation is changed from one of the first detection operation and the second detection operation to the other, the time between the first detection operation and the second detection operation is compared with the case where the operation by the user is triggered. Therefore, the degree of deterioration can be made closer between the first detection circuit and the second detection circuit.

It is a block diagram of the detecting device concerning a 1st embodiment. It is a circuit diagram of the detection circuit of the detection apparatus which concerns on 1st Embodiment. It is a conceptual diagram which shows the relationship between the 1st detection circuit and 2nd detection circuit in 1st Embodiment. It is a timing chart which shows operation | movement of the detection apparatus which concerns on 1st Embodiment. It is a flowchart of operation | movement of the control circuit of the detection apparatus which concerns on 1st Embodiment. It is a conceptual diagram which shows the relationship between the 1st detection circuit and 2nd detection circuit in 2nd Embodiment. It is a timing chart which shows operation of a detecting device concerning a 2nd embodiment. It is a flowchart of operation | movement of the control circuit of the detection apparatus which concerns on 3rd Embodiment. It is a flowchart of operation | movement of the control circuit of the detection apparatus which concerns on 4th Embodiment.

<A: First Embodiment>
FIG. 1 is a block diagram of a detection apparatus 100 according to the first embodiment of the present invention. The detection device 100 is a device (for example, a touch panel that detects contact of a user's body) that is used to detect an object (object to be detected). As shown in FIG. 1, the detection apparatus 100 includes a detection unit 10 in which a plurality of detection circuits U are arranged, a drive circuit 20 that drives each detection circuit U, and a control circuit 30 that controls the drive circuit 20. To do. The drive circuit 20 includes a selection circuit 22A and an output circuit 24A. The drive circuit 20 can be composed of a plurality of integrated circuits (chips). An operation unit 32 operated by a user is connected to the control circuit 30.

  The detection unit 10 includes M selection lines 12 extending in the X direction, M initialization lines 14 extending in the X direction in pairs with the selection lines 12, and Y crossing the X direction. 2N detection lines 16 extending in the direction are formed (M and N are natural numbers). The plurality of detection circuits U are arranged in a matrix of vertical M rows × horizontal 2N columns corresponding to the intersections of the M selection lines 12 (initialization lines 14) and the 2N detection lines 16.

  FIG. 2 is a circuit diagram of each detection circuit U. In FIG. 2, one detection circuit U located in the j-th column (j = 1 to 2N) of the i-th row (i = 1 to M) is representatively illustrated. The detection circuit U is a circuit that generates a detection signal S (S [i, j]) according to the presence / absence (approach or contact) of an object to be detected. As shown in FIG. And a selection switch TSEL and an initialization switch TRST. The light receiving element E generates a photocurrent IP having a current value corresponding to the illuminance (intensity) of the irradiation light with respect to the light receiving element E. For example, a photodiode is suitably employed as the light receiving element E. The illuminance of the irradiation light with respect to the light receiving element E changes according to the presence or absence of the object to be detected above the detection unit 10 and the distance.

  The amplification transistor TAMP, the selection switch TSEL, and the initialization switch TRST are configured by, for example, a transistor (for example, a thin film transistor in which a semiconductor layer is formed of low-temperature polysilicon) formed on the surface of the substrate together with the light receiving element E. Note that the conductivity type of each transistor constituting the detection circuit U is arbitrary.

  The amplification transistor TAMP is an element that generates a detection signal (a current signal obtained by amplifying the photocurrent IP) S [i, j] corresponding to its gate potential. Intervene between. The power supply line 18 is supplied with a predetermined potential VRST from a power supply circuit (not shown). The gate of the amplification transistor TAMP is connected to the light receiving element E (cathode).

  The selection switch TSEL is disposed on the path of the detection signal S [i, j], and controls whether the detection signal S [i, j] is output to the detection line 16. Specifically, the selection switch TSEL of the detection circuit U in the j-th column is arranged in series with the amplification transistor TAMP on a path connecting the feeder line 18 and the detection line 16 in the j-th column. The gates of the selection switches TSEL in the detection circuits U in the i-th row are commonly connected to the selection line 12 in the i-th row.

  The initialization switch TRST is interposed between the gate of the amplification transistor TAMP and the power supply line 18 (or other wiring) and controls the electrical connection (conduction / non-conduction) between the two. The gates of the initialization switches TRST in the detection circuits U in the i-th row are commonly connected to the initialization line 14 in the i-th row.

  As shown in FIG. 3, the plurality of detection circuits U in the detection unit 10 are divided into a plurality of first detection circuits U1 and a plurality of second detection circuits U2. The first detection circuit U1 is a detection circuit U located in an odd-numbered column ((2n-1) th column), and the second detection circuit U2 is a detection circuit U located in an even-numbered column (second nth column) ( n = 1 to N). That is, the set of M first detection circuits U1 arranged in the Y direction (odd number columns) and the set of M second detection circuits U2 arranged in the Y direction (even number columns) are included in the detection unit 10. Are alternately arranged along the X direction. Therefore, N first detection circuits U1 and N second detection circuits U2 exist in one row.

  As shown in FIG. 3, 2N detection lines 16 include N first detection lines 161 connected to M first detection circuits U1 and M second detection circuits U2, respectively. It is divided into N second detection lines 162 connected to each. The first detection lines 161 are located in odd-numbered columns ((2n-1) th column), and the second detection lines 162 are located in even-numbered columns (second nth column).

  The control circuit 30 in FIG. 1 detects the detection signal S [i, 2n-1] by driving each first detection circuit U1, and the detection signal S [i by driving each second detection circuit U2. , 2n] is selectively executed by the drive circuit 20. In the first detection operation, a plurality of detection circuits U are sequentially selected in units of rows in each unit period (vertical scanning period) PU shown in FIG. 4, and 2N detection circuits U in the selected row (i-th row) are selected. Of these, the detection signals S [i, 2n-1] (S [i, 1], S [i, 3], S [i, 5],..., S generated by each of the N first detection circuits U1. [i, 2N-1]) is obtained from each first detection line 161. On the other hand, in the second detection operation, the plurality of detection circuits U are sequentially selected in units of rows in each unit period PU, and N second detection circuits out of 2N detection circuits U in the selected row (i-th row). Each detection signal S [i, 2n] (S [i, 2], S [i, 4], S [i, 6],..., S [i, 2N]) generated by each circuit U2 This operation is acquired from the two detection lines 162.

  The control circuit 30 changes the operation of the drive circuit 20 from one of the first detection operation and the second detection operation to the other, triggered by an operation on the operation unit 32. FIG. 5 is a flowchart of a process in which the control circuit 30 selects the operation of the drive circuit 20 (first detection operation / second detection operation). The processing shown in FIG. 5 is executed every predetermined time.

  When the processing of FIG. 5 is started, the control circuit 30 determines whether or not an operation for instructing a change in operation has been given to the operation unit 32 (SA1). The process of FIG. 5 is terminated. On the other hand, when an operation change is instructed (SA1: YES), the control circuit 30 determines whether the current operation (operation mode) corresponds to the first detection operation or the second detection operation (SA2). . The control circuit 30 selects the second detection operation when the current operation is the first detection operation (SA3), and selects the first detection operation when the current operation is the second detection operation (S3). SA4). That is, every time the operation unit 32 is operated, the operation of the drive circuit 20 is changed.

  The selection circuit 22A in FIG. 1 generates a selection signal GSEL [i] (GSEL [1] to GSEL [M]) that specifies selection / non-selection of each selection line 12 and outputs it to the selection line 12 in the i-th row. Then, the initialization signal GRST [i] (GRST [1] to GRST [M]) is generated and output to the i-th row initialization line 14 (see FIG. 2). A configuration in which a circuit for generating selection signals GSEL [1] to GSEL [M] and a circuit for generating initialization signals GRST [1] to GRST [M] are separately mounted is also employed.

  As shown in FIG. 4, each unit period PU includes M selection periods PSEL [1] to PSEL [M]. The selection signal GSEL [i] is set to a high level (active level meaning selection of the i-th row) in the selection period PSEL [i] within each unit period PU, and is set to a low level except for the selection period PSEL [i]. Maintained. The initialization signal GRST [i] is set to a high level (active) within a predetermined period before the start of the selection period PSEL [i], and is maintained at a low level during other periods (not shown).

  When the initialization signal GRST [i] is set to a high level, the initialization switches TRST of the 2N detection circuits U (U1, U2) in the i-th row are turned on. Therefore, the potential of the gate of each amplification transistor TAMP in the i-th row is initialized to the potential VRST of the feeder line 18. Then, when the initialization signal GRST [i] changes to the low level and each initialization switch TRST in the i-th row transitions to the OFF state, the gate of the amplification transistor TAMP enters an electrically floating state. Therefore, the potential of the gate of the amplification transistor TAMP is set to a potential corresponding to the photocurrent IP of the light receiving element E.

  As shown in FIG. 4, in the selection period PSEL [i], the selection signal GSEL [i] is set to a high level, so that each of the 2N detection circuits U (U1, U2) in the i-th row is selected. The switch TSEL transitions to the on state. Therefore, in each of the 2N detection circuits U in the i-th row, the current flowing through the amplification transistor TAMP can be output to the detection line 16 in the j-th column as the detection signal S [i, j]. . Since the potential of the gate of the amplification transistor TAMP is set according to the photocurrent IP, the detection signal S [i, j] is a current signal having a current value corresponding to the illuminance of the irradiation light with respect to the light receiving element E.

  The output circuit 24A of FIG. 1 includes N switches 42 [1] to 42 [N] and a signal processing circuit 44 as shown in FIG. The switch 42 [n] selectively selects the first detection line 161 (a end) in the (2n-1) th column and the second detection line 162 (b end) in the second n column adjacent to each other. To conduct. The control circuit 30 controls the switches 42 [1] to 42 [N] with the output of the control signal GX.

  When the first detection operation is selected in the process of FIG. 5, the control circuit 30 supplies a high-level control signal GX, which means selection of the first detection line 161 (a end), to the switch 42 [ 1] to 42 [N]. The switches 42 [1] to 42 [N] conduct the N first detection lines 161 (first detection circuit U1) to the signal processing circuit 44 in response to the control signal GX. Therefore, in each of the selection periods PSEL [1] to PSEL [M] in each unit period PU, as shown in FIG. 4, N first detection circuits U1 out of 2N detection circuits U in the i-th row. Detection signal S [i, 2n-1] (S [i, 1], S [i, 3], S [i, 5],..., S [i, 2N-1] ]) Is supplied in parallel to the signal processing circuit 44 via each first detection line 161. That is, the drive circuit 20 (output circuit 24A) performs the first detection operation. On the other hand, since the signal processing circuit 44 and the N second detection lines 162 are electrically insulated, no current (detection signal S [i, 2n]) flows through the amplification transistor TAMP of each second detection circuit U2. .

  When the second detection operation is selected in the processing of FIG. 5, the control circuit 30 sets the control signal GX to a low level (a level meaning selection of the second detection line 162) as shown in FIG. 4. The N second detection lines 162 (second detection circuit U2) are conducted to the signal processing circuit 44. Therefore, in the selection period PSEL [i] in each unit period PU, as shown in FIG. 4, N systems generated by N second detection circuits U2 among 2N detection circuits U in the i-th row. Detection signals S [i, 2n] (S [i, 2], S [i, 4], S [i, 6],..., S [i, 2N]) are transmitted via the second detection lines 162. To the signal processing circuit 44 in parallel. That is, the drive circuit 20 performs the second detection operation. On the other hand, since the signal processing circuit 44 and the N first detection lines 161 are electrically insulated, a current (detection signal S [i, 2n-1]) is supplied to the amplification transistor TAMP of each first detection circuit U1. Not flowing.

  The signal processing circuit 44 in FIG. 3 sequentially selects the N detection signals S supplied in parallel from the detection unit 10 within the selection period PSEL [i], and outputs one detection signal SOUT. S (parallel to serial) converter. The detection signal SOUT is supplied to an external device via the control circuit 30 and then used to determine the presence or absence of the detection object and to specify the shape of the detection object. A configuration is also employed in which the control circuit 30 determines the presence or absence and shape of an object to be detected using the detection signal SOUT.

  As described above, the driving circuit 20 detects the detection signal S [i, 2n-1] by driving the first detection circuit U1, and the detection signal S [i by driving the second detection circuit U2. , 2n] is selectively executed. Therefore, in comparison with the configuration in which the detection signals S [i, j] are always obtained from all the detection circuits U in each unit period PU (that is, the current flows through the amplification transistors TAMP of all the detection circuits U), It is possible to suppress degradation of elements (for example, the amplification transistor TAMP) that constitute the detection circuit U. In each unit period PU, since the current (detection signal S [i, j]) flows only in one amplification transistor TAMP of the first detection circuit U1 and the second detection circuit U2, the detection signal is always output from all the detection circuits U. Compared with the configuration for acquiring S [i, j], there is also an advantage that the power consumed in the detection unit 10 is reduced.

  Further, since the first detection circuit U1 and the second detection circuit U2 are distributed in the X direction in the detection unit 10, the first detection circuit U1 and the second detection circuit U2 are arranged in a specific manner in the detection unit 10. Compared with a configuration that is unevenly distributed in the region, the entire detection unit 10 can be used for detection of an object to be detected (a sufficiently large area can be detected).

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as that of 1st Embodiment in each following form, the same code | symbol as above is attached | subjected and each detailed description is abbreviate | omitted suitably.

  As shown in FIG. 6, the detection unit 10 includes 2M selection lines 12 and initialization lines 14 (not shown) extending in the X direction, and N detection lines 16 extending in the Y direction. It is formed. Therefore, the plurality of detection circuits U are arranged in a matrix of 2M vertical rows × N horizontal columns. The plurality of detection circuits U are divided into a first detection circuit U1 located in an odd-numbered row and a second detection circuit U2 located in an even-numbered row. That is, a set of N first detection circuits U1 arranged in the X direction (odd rows) and a set of N second detection circuits U2 arranged in the X direction (even rows) are included in the detection unit 10. Are alternately arranged along the Y direction. The 2M selection lines 12 include M first selection lines 121 each having N first detection circuits U1 connected thereto, and M lines each having N second detection circuits U2 connected thereto. And the second selection line 122.

  As shown in FIG. 6, the drive circuit 20 of the second embodiment includes a selection circuit 22B and an output circuit 24B. Similarly to the signal processing circuit 44 of the first embodiment, the output circuit 24B sequentially selects the N detection signals S supplied in parallel from the detection unit 10 and outputs one detection signal SOUT.

  As shown in FIG. 6, the selection circuit 22 </ b> B includes M switches 52 [1] to 52 [M] and a signal generation circuit 54. As shown in FIG. 7, the signal generation circuit 54 (for example, a shift register) sequentially controls the control signals G0 [1] to G0 [1] to be set to high level (active) in each selection period PSEL [i] in the unit period PU. G0 [M] is generated. That is, the waveform of the control signal G0 [m] (m = 1 to M) is the same as that of the selection signal GSEL [m] of the first embodiment.

  The switch 52 [m] in FIG. 6 selectively signals the first selection line 121 (a end) in the (2m-1) th row and the second selection line 122 (b end) in the second m row adjacent to each other. Connected to the generation circuit 54. The switches 52 [1] to 52 [M] are controlled by a control signal GX supplied from the control circuit 30. The control circuit 30 sets the level of the control signal GX in accordance with the operation (first detection operation / second detection operation) selected in the processing of FIG.

  When the first detection operation for obtaining the detection signal S [i, j] from the first detection circuit U1 is selected, the control circuit 30 selects the first selection line 121 (a end) as shown in FIG. Meaning high level control signal GX is output to switches 52 [1] to 52 [M]. The switches 52 [1] to 52 [M] connect the M first selection lines 121 to the signal generation circuit 54 in accordance with the control signal GX. Therefore, the control signal G0 [m] generated by the signal generation circuit 54 is selected from the selection signals GSEL [2m-1] (GSEL [1], GSEL [3], GSEL [5],..., As shown in FIG. , GSEL [2M-1]) is output to the first selection line 121 in the (2m-1) th row. That is, the selection circuit 22B sequentially selects each of the M first selection lines 121 in each selection period PSEL [m] within the unit period PU.

  Therefore, in each selection period PSEL [m] in the unit period PU, as shown in FIG. 7, N detection signals S generated by the N first detection circuits U1 in the (2m-1) th row. [2m-1, j] (S [2m-1,1], S [2m-1,2], S [2m-1, N]) are supplied in parallel to the output circuit 24B via each detection line 16 Is done. That is, the drive circuit 20 (selection circuit 22B) performs the first detection operation. On the other hand, since the signal generation circuit 54 and the M second selection lines 122 are electrically insulated, no current flows through the amplification transistor TAMP of each second detection circuit U2.

  On the other hand, when the second detection operation for obtaining the detection signal S [i, j] from the second detection circuit U2 is selected, the control circuit 30 sets the control signal GX to the low level, so that the M second The selection line 122 is conducted to the signal generation circuit 54. Therefore, the control signal G0 [m] generated by the signal generation circuit 54 is selected from the selection signals GSEL [2m] (GSEL [2], GSEL [4], GSEL [6],..., GSEL as shown in FIG. [2M]) is output to the second selection line 122 in the 2m-th row. That is, the selection circuit 22B sequentially selects each of the M second selection lines 122 in each selection period PSEL [m] within the unit period PU.

  Therefore, in each selection period PSEL [m], N detection signals S [2m, j] (S [2m, 1], S [2m] generated by the N second detection circuits U2 in the 2mth row. , 2], S [2m, N]) are supplied in parallel to the output circuit 24B via the detection lines 16. That is, the drive circuit 20 performs the second detection operation. On the other hand, since the signal generation circuit 54 and the M first selection lines 121 are electrically insulated, no current flows through the amplification transistor TAMP of each first detection circuit U1.

  As described above, the detection signal S [2m-1, j] is acquired by driving the first detection circuit U1, and the detection signal S [2m, j] is acquired by driving the second detection circuit U2. Since the second detection operation is selectively executed, the same operations and effects as those of the first embodiment are realized also in the second embodiment.

<C: Third Embodiment>
FIG. 8 is a flowchart of a process in which the control circuit 30 according to the third embodiment of the present invention selects the operation (first detection operation / second detection operation) of the drive circuit 20. When the power of the detection apparatus 100 is turned on, the control circuit 30 selects one of the first detection operation and the second detection operation, and sequentially executes the processing of FIG. 8 at predetermined time intervals.

  When the processing of FIG. 8 is started, the control circuit 30 adds a predetermined value Δ to the variable T (SB1). The variable T means the time during which one of the first detection operation and the second detection operation is continued. The control circuit 30 determines whether or not the variable T after the addition exceeds a predetermined threshold value T0 (SB2). If the result of the determination is negative, the process of FIG. 8 is terminated.

  On the other hand, when the variable T exceeds the threshold value T0, the control circuit 30 determines the current detection operation (SB3), similarly to steps SA2 to SA4 in FIG. 2 detection operation is selected (SB4), and if the second detection operation is being executed, the first detection operation is selected (SB5). Then, the control circuit 30 initializes the variable T to zero (SB6) and ends the processing of FIG. The drive circuit 20 executes the detection operation selected by the control circuit 30 in the process of FIG. As the configuration of the drive circuit 20, the configuration exemplified in the first embodiment or the second embodiment is suitably employed.

  In the above configuration, the operation of the drive circuit 20 is changed from one of the first detection operation and the second detection operation each time a time corresponding to the threshold value T0 elapses. Compared to the first embodiment requiring the above, it is possible to make the degree of deterioration uniform between the first detection circuit U1 and the second detection circuit U2.

<D: Fourth Embodiment>
FIG. 9 is a flowchart of processing in which the control circuit 30 according to the fourth embodiment of the present invention selects the operation (first detection operation / second detection operation) of the drive circuit 20. The control circuit 30 executes the process of FIG. 9 every time the detection apparatus 100 is powered on.

  When the processing of FIG. 9 is started, the control circuit 30 determines whether the operation of the drive circuit 20 during the previous operation of the detection apparatus 100 corresponds to the first detection operation or the second detection operation (SC1). The control circuit 30 selects the second detection operation when the previous operation is the first detection operation (SC2), and selects the first detection operation when the previous operation is the second detection operation. (SC3). For determining the previous operation, for example, a flag stored in a storage circuit (not shown) is used.

  In the above configuration, every time the power of the detection device 100 is turned on, the operation of the drive circuit 20 is changed from one of the first detection operation and the second detection operation to the other. Therefore, as in the third embodiment, It is possible to make the degree of deterioration uniform between the first detection circuit U1 and the second detection circuit U2.

<E: Modification>
Various modifications are added to the above embodiment. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples may be merged.

(1) Modification 1
In each of the above embodiments, the plurality of detection circuits U are divided into two types (first detection circuit U1 and second detection circuit U2). However, a configuration in which the plurality of detection circuits U are divided into three or more types may be employed. For example, assuming that a plurality of detection circuits U are divided into K types (K ≧ 3), in the first embodiment, the switch 42 [n] selectively selects any one of the K detection lines 16. A configuration in which the signal processing circuit 44 is conducted is employed, and in the second embodiment, a configuration in which the switch 52 [m] selectively conducts any one of the K selection lines 12 to the signal generation circuit 54 is employed. .

(2) Modification 2
The trigger (condition) for changing the detection operation of the drive circuit 20 is not limited to the above examples (instructions from the user, elapse of a predetermined time, power-on of the detection device 100). Moreover, the structure which uses together the some opportunity illustrated above is also employ | adopted. For example, a configuration in which the detection operation is changed when the detection device 100 is turned on, and the detection operation is changed when the detection device 100 is in operation when a predetermined time elapses or an operation on the operation unit 32 is triggered. . In the above example, a plurality of detection operations are cyclically selected (first detection operation → second detection operation → first detection operation), but cyclic (reversible) selection of the detection operation is essential in the present invention. is not. For example, a configuration in which the operation by the drive circuit 20 is changed only once from the first detection operation to the second detection operation may be employed.

(3) Modification 3
The method of dividing the first detection circuit U1 and the second detection circuit U2 is arbitrary. For example, a configuration in which a plurality of detection circuits U are arranged so that the first detection circuit U1 and the second detection circuit U2 are adjacent to each other in both the X direction and the Y direction is also employed. Further, the configuration in which the first detection circuit U1 and the second detection circuit U2 are arranged in a distributed manner is not essential in the present invention. For example, a configuration in which a plurality of first detection circuits U1 are distributed in one region as viewed from a boundary line defined in the detection unit 10 and a plurality of second detection circuits U2 is distributed in the other region is also employed.

(4) Modification 4
The method for detecting an object to be detected is not limited to the above example (light detection type). For example, each of the above embodiments can be similarly applied to a capacitive detection device that uses a capacitive element whose capacitance value changes depending on whether or not an object is touched instead of the light receiving element E. is there. Moreover, the use of the detection apparatus 100 is not limited to a touch panel. For example, the detection device 100 according to each of the above embodiments includes a fingerprint sensor that detects a user's fingerprint, a vein sensor that detects a vein of the user's hand, and a reading device (scanner) that detects reflected light from a document. Can be used.

DESCRIPTION OF SYMBOLS 100 ... Detection apparatus, 10 ... Detection part, U ... Detection circuit, U1 ... 1st detection circuit, U2 ... 2nd detection circuit, 12 ... Selection line, 14 ... Initialization line, 16 ... Detection line, 18 ... feed line, 20 ... driving circuit, 22A, 22B ... selection circuit, 24A, 24B ... output circuit, 30 ... control circuit, 32 ... operation unit, 42 [1] to 42 [ N] ... switch, 44 ... signal processing circuit, 52 [1] to 52 [M] ... switch, 54 ... signal generation circuit.

Claims (7)

A plurality of detection circuits each generating a detection signal according to the presence or absence of the detected object;
A first detection operation for obtaining a detection signal by driving a plurality of first detection circuits among the plurality of detection circuits in each unit period is different from each first detection circuit among the plurality of detection circuits. And a driving circuit that selectively executes a second detection operation of driving a plurality of second detection circuits in each unit period to acquire a detection signal. Each of the plurality of detection circuits is arranged corresponding to each intersection of a plurality of selection lines and a plurality of detection lines and outputs the detection signal to the detection lines by selection of the selection lines,
The plurality of detection lines include a plurality of first detection lines connected to two or more first detection circuits, and a plurality of second detection lines connected to two or more second detection circuits, respectively. Including
Each of the plurality of first detection lines is located in each gap of the plurality of second detection lines,
The drive circuit is
A selection circuit that sequentially selects each of the plurality of selection lines in each unit period;
The first detection operation for acquiring the detection signal output to each of the plurality of first detection lines in each unit period, and the detection signal output to each of the plurality of second detection lines to each unit. The detection device according to claim 1, further comprising: an output circuit that selectively executes the second detection operation acquired in a period. Each of the plurality of detection circuits is arranged corresponding to each intersection of a plurality of selection lines and a plurality of detection lines and outputs the detection signal to the detection lines by selection of the selection lines,
The plurality of selection lines include a plurality of first selection lines connected to two or more first detection circuits, and a plurality of second selection lines connected to two or more second detection circuits, respectively. Including
Each of the plurality of first selection lines is located in each gap of the plurality of second selection lines,
The drive circuit is
The first detection operation that sequentially selects each of the plurality of first selection lines in each unit period, and the second that sequentially selects each of the plurality of second selection lines in each unit period. A selection circuit that selectively executes a detection operation;
The detection device according to claim 1, further comprising: an output circuit that acquires a detection signal output to each of the plurality of detection lines in each unit period. The detection device according to any one of claims 1 to 3, further comprising a control circuit that selects the first detection operation or the second detection operation. It has an operation unit that is operated by the user,
The detection device according to claim 4, wherein the control circuit changes the detection operation by the drive circuit from one of the first detection operation and the second detection operation to the other when triggered by an operation on the operation unit. The detection device according to claim 4, wherein the control circuit changes the detection operation by the drive circuit from one of the first detection operation and the second detection operation to the other at every predetermined time. The control circuit changes the detection operation by the drive circuit from one of the first detection operation and the second detection operation to the other each time the power of the detection device is turned on. Detection device.

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