JP2011009837A - Solid-state imager and digital camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imager capable of performing an operation of a front curtain of a shutter by an electronic shutter as an operation that resembles a back curtain of a focal plane shutter with a simple configuration and preventing shading generated in a photographed image, and to provide a digital camera.SOLUTION: The solid-state imager includes an imaging element, a first scanning circuit, a second scanning circuit, and a control means. At the imaging element, a plurality of pixels are arranged in matrix direction. Each of the plurality of pixels includes a photoelectric conversion means for converting incident light into a signal charge, a transfer means for transferring the signal charge generated at the photoelectric conversion means, an amplification means for amplifying the transferred signal charge, and a reset means for resetting the signal charge. The first scanning circuit resets the signal charge at the imaging element one by one. The second scanning circuit reads out signal charge at the imaging element one by one. The control means controls the first scanning circuit and the second scanning circuit to drive in parallel, when reset of the signal charge at the imaging element is performed as the other of the front curtain or the back curtain in response to running of a shutter which shades the imaging element as one of the front curtain or the back curtain.

Description

  The present invention relates to a solid-state imaging device and a digital camera used for a video camera, a digital still camera, and the like.

In recent years, CMOS (Complementary Metal Oxide Semiconductor) type imaging devices (hereinafter referred to as “MOS type imaging devices”) have attracted attention and are put into practical use as solid-state imaging devices.
Unlike a CCD (Charge Coupled Device) type image sensor, this MOS type image sensor can be driven by a single power source. In addition, a CCD type image pickup device requires a dedicated manufacturing process, whereas a MOS type image pickup device can be manufactured using the same manufacturing process as other LSIs. It is easy to deal with and enables multi-functionalization of the solid-state imaging device.
In addition, since the MOS type image pickup device amplifies the signal charge in each pixel by providing an amplification circuit in each pixel, the MOS type image pickup device is not easily influenced by noise from the signal transmission path. Further, the signal charge of each pixel can be selected and taken out (selection method), and in principle, the signal accumulation time and readout order can be freely controlled for each pixel.

  One example of a device that uses a MOS image sensor is a single-lens reflex camera. FIG. 8 is a block diagram showing a schematic configuration of a general digital camera. The digital camera 1 shown in FIG. 8 includes a lens 2, a mechanical shutter 3, an image sensor 4, an image signal processing circuit 5, a memory 6, a recording device 7, a lens control device 8, a shutter driving device 9, an imager driving device 10, and a camera. It comprises a control device 11 and a display device 12.

The lens 2 is driven and controlled by a lens control device 8 such as zoom, focus, and diaphragm, and forms a subject image on the image sensor 4.
The mechanical shutter 3 is a light shielding member (shutter) that is driven and controlled by the shutter driving device 9 and shields light incident on the digital camera 1 through the lens 2. The mechanical shutter 3 is a focal plane type used in a so-called single-lens reflex camera. This is a shutter mechanism.
The image sensor 4 is a solid-state imaging device that is driven and controlled by the imager driving device 10 and converts subject light incident on the digital camera 1 through the lens 2 into an image signal. In the following description, the term “image sensor” refers to a MOS type image sensor.
The image signal processing circuit 5 performs processing such as signal amplification, conversion into image data, various corrections, and image data compression on the image signal output from the image sensor 4. The image signal processing circuit 5 uses a memory 6 as a temporary storage unit for image data in each process.
The recording device 7 is a detachable recording medium such as a semiconductor memory, and records or reads out image data.
The display device 12 is a display device such as a liquid crystal that displays an image based on image data imaged on the image sensor 4 and processed by the image signal processing circuit 5 or image data read from the recording device 7.
The camera control device 11 is a control device that performs overall control of the digital camera 1.

  FIG. 9 is a block diagram showing a schematic configuration of a conventional solid-state imaging device. 9, the image sensor 4 includes an image sensor control signal generation circuit 41, a vertical scanning circuit 42, a horizontal scanning circuit 43, a constant current source 44, a unit pixel 45, a CDS circuit 46, and a column selection circuit 47. In the image sensor 4 shown in FIG. 9, a plurality of unit pixels 45 are two-dimensionally arranged in 3 rows and 3 columns. The constant current source 44, the CDS circuit 46, and the column selection circuit 47 are arranged for each column direction of the unit pixels 45.

In the image sensor 4 shown in FIG. 9, numbers and symbols in “(): parentheses” shown after each symbol are a row number and a column number corresponding to the unit pixel 45 arranged in the image sensor 4. The first number indicates the row number, and the last number indicates the column number. For example, the unit pixel 45 in the second row and the third column is represented as a unit pixel 45 ₍₂₃₎ . When only one of the row numbers or column numbers, that is, the same row number or column number is represented, the same row number or column number is represented by a number, and the non-identical row number or column number is designated by “*: asterisk”. ". For example, the constant current source 44 in the third column is represented as a constant current source 44 _{(* 3)} . Further, when both the row number and the column number are not specified, “(): parenthesis” after each code is not written.

  The image sensor control signal generation circuit 41 controls the vertical scanning circuit 42, the horizontal scanning circuit 43, and the CDS circuit 46. The vertical scanning circuit 42 controls the unit pixel 45. The horizontal scanning circuit 43 controls the column selection circuit 47. Under the control of the image sensor control signal generation circuit 41, vertical scanning circuit 42, and horizontal scanning circuit 43, the image sensor 4 outputs an image signal of incident subject light.

More specifically, the image sensor 4 includes reset pulses φRS _{(1 *) to} φRS _{(3 *)} , transfer pulses φTX _{(1 *) to} φTX _{(3 *),} and a select pulse φSE output from the vertical scanning circuit 42. The outputs of the unit pixels 45 in the row direction selected by _{(1 *) to} φSE _{(3 *)} are output to the vertical signal lines V _{(* 1) to} V _{(* 3)} as pixel signals. Then, the image sensor 4 suppresses the noise component of the pixel signal output from the unit pixel 45 to the vertical signal lines V _{(* 1) to} V _{(* 3)} by the CDS circuit 46. The pixel signal after noise suppression in the column direction selected by the column selection pulses φH _{(* 1) to} φH _{(* 3)} output from the horizontal scanning circuit 43 is used as an image signal of the image sensor 4 as a horizontal signal line H. Output to.

The unit pixel 45 is a circuit that converts incident light into an electric signal and outputs it to the vertical signal line V. Each unit pixel 45 includes a photodiode PD, a floating diffusion FD, a reset transistor M1, a transfer transistor M2, an amplification transistor M3, and a selection transistor M4.
The photodiode PD is a photoelectric conversion unit that photoelectrically converts incident light to generate charges. Based on the transfer pulse φTX input from the vertical scanning circuit 42, the transfer transistor M2 transfers the charge generated in the photodiode PD to the floating diffusion FD connected to the gate terminal of the amplification transistor M3. The charges transferred by the transfer transistor M2 are accumulated in the floating diffusion FD. The amplification transistor M3 outputs a voltage corresponding to the electric charge accumulated in the floating diffusion FD. The reset transistor M1 resets the floating diffusion FD to the power supply voltage Vd based on the reset pulse φRS input from the vertical scanning circuit 42. The selection transistor M4 outputs the voltage output from the amplification transistor M3 to the vertical signal line V as the output of the unit pixel 45 based on the select pulse φSE input from the vertical scanning circuit.

The vertical signal lines V _{(* 1) to} V _{(* 3)} are connected to the unit pixel 45, the CDS circuit 46, and the constant current source 44 for each column direction.
The drain terminal of the transistor in the constant current source 44 is connected to the vertical signal line V, and the source terminal is fixed to the ground. The gate terminal of the transistor in the constant current source 44 is connected to the current source bias Vbias.

The CDS circuit 46 is a circuit that suppresses noise of a pixel signal generated in the unit pixel 45. The CDS circuit 46 includes a clamp transistor M5, a sample hold transistor M6, a clamp capacitor C1, and a sample hold capacitor C2, respectively.
The clamp capacitor C1 holds the output voltage of the pixel signal output from the unit pixel 45 to the vertical signal line V. The clamp transistor M5 outputs the reset voltage of the unit pixel 45, that is, the power supply voltage Vd, based on the clamp pulse φCL input from the image sensor control signal generation circuit 41. Based on the sample hold pulse φSH input from the image sensor control signal generating circuit 41, the sample hold transistor M6 is output via the clamp transistor M5 and the voltage of the pixel signal of the unit pixel 45 held in the clamp capacitor C1. The difference voltage from the reset voltage, that is, the noise-suppressed pixel signal is held in the sample hold capacitor C2.

The column selection circuit 47 performs the noise-suppressed noise held in the sample hold capacitor C2 in the CDS circuit 46 based on the column selection pulses φH _{(* 1) to} φH _{(* 3)} output from the horizontal scanning circuit 43. A pixel signal is selected and output to the horizontal signal line H as an image signal of the image sensor 4.

  FIG. 10 is a diagram schematically showing a general operation of shutter driving in photographing with a conventional digital camera. In FIG. 10, the mechanical shutter 3 includes a focal plane shutter rear curtain 31 and a focal plane shutter front curtain 32. FIG. 10A shows in real time the image from the image sensor 4 on the display device 12 provided in the digital camera in a state where both the focal plane shutter rear curtain 31 and the focal plane shutter front curtain 32 are “open”. The so-called live view state is shown. When the shutter button is pressed from this live view state, a release signal for starting still image capturing is generated, and the focal plane shutter front curtain 32 is once closed as shown in FIG. 10B. . Thereafter, as shown in FIGS. 10C to 10D, the exposure time is controlled by the focal plane shutter rear curtain 31 and the focal plane shutter front curtain 32 traveling at a constant interval. Finally, shooting is completed when the state shown in FIG. 10E, that is, when the focal plane shutter rear curtain 31 is completely closed, and thereafter the image signals of the image sensor 4 are sequentially read out.

  However, in the conventional digital camera shown in FIG. 10, during the period from when the shutter button is pressed until the focal plane shutter front curtain 32 is in the “closed” state (FIG. 10B), still image capture is performed. This period has been a problem as a time lag until photographing.

Various techniques have been devised in order to improve the above-described problem of time lag until photographing. For example, Patent Document 1 discloses a method of using an electronic shutter operation instead of the focal plane shutter front curtain 32. The electronic shutter operation is an operation of resetting the charge accumulated in the photodiode PD in the unit pixel 45 by turning on the reset transistor M1 and the transfer transistor M2 in the unit pixel 45.
In the following description, a method using an electronic shutter operation instead of the focal plane shutter front curtain 32 will be referred to as a “front curtain electronic shutter”.

  FIG. 11 shows a schematic diagram of the schematic operation of the front curtain electronic shutter drive. FIG. 11A shows a live view state similar to FIG. When the shutter button is pressed from this live view state, unlike FIG. 10B, the focal plane shutter front curtain 32 does not shift to the “closed” state, and FIGS. As shown in c), the traveling of the focal plane shutter rear curtain 31 and the scanning of the image sensor 4 by the electronic shutter are performed. That is, the exposure time is controlled by synchronizing the focal plane shutter rear curtain 31 and the electronic shutter operation ON area. Finally, shooting is completed when the state shown in FIG. 11D, that is, when the focal plane shutter rear curtain 31 is completely closed, and then the image signals of the image sensor 4 are sequentially read out.

FIG. 12 is a timing chart showing the timing of the conventional front curtain electronic shutter drive. First, when the shutter button is pressed and a release signal (“High” pulse in FIG. 12) is generated at time t1, the select pulse φSE is set to the “Low” level, and the reset pulse φRS and the transfer pulse φTX are sequentially supplied for each row. The electronic shutter is scanned at the “High” level at the leading shutter electronic shutter timing. As a result, exposure for still image capturing is started. Thereafter, the travel of the focal plane shutter rear curtain 31 is started at the mechanical shutter travel timing from the time t2 when a predetermined time has elapsed. At time t3 when the travel of the focal plane shutter rear curtain 31 is completed, the image sensor 4 is completely shielded from light and the exposure for still image capturing is completed. Subsequently, image signals are sequentially read from the image sensor 4.
In this way, by performing the operation of the front curtain electronic shutter, the time lag from when the shutter button is pressed until the exposure of still image capturing is started is reduced.

Japanese Patent No. 3709724

However, in the conventional front curtain electronic shutter technology described in Patent Document 1, the time required for shielding the image sensor 4 by the electronic shutter and the time required for shielding the image sensor 4 by the focal plane shutter rear curtain 31 are as follows. There is a problem of being different.
FIG. 13 is a diagram for explaining the above-described problem in the conventional front curtain electronic shutter.

  In the operation of the electronic shutter, as shown in FIG. 12, the charges accumulated in the photodiode PD in the unit pixel 45 are sequentially reset for each row. The time for sequentially resetting all the rows of the image sensor 4 by the operation of the electronic shutter is several ms as shown in FIG. For example, assuming that the readout time per row is 1.5 μs and the image sensor 4 has 3000 rows as a whole, the time required to reset all the rows of the image sensor 4 by the operation of the electronic shutter, that is, the electronic shutter. The curtain speed of the front curtain by the operation is about 4.5 ms. On the other hand, the curtain speed of the focal plane shutter rear curtain 31 is normally about 2 to 3 ms. For this reason, the exposure time of the unit pixel 45 in the first row after the shutter button is pressed is significantly different from the exposure time of the unit pixel 45 in the subsequent n row, as shown in FIG. Shading due to the difference in exposure time for each row of unit pixels 45 occurs in the captured image.

  The present invention has been made on the basis of the above-mentioned problem recognition. In a solid-state imaging device that uses the electronic shutter operation of a solid-state imaging device as a shutter front curtain, the operation of the shutter front curtain by the electronic shutter can be simplified. An object of the present invention is to provide a solid-state imaging device and a digital camera that can operate close to the rear curtain of the focal plane shutter with the configuration and can prevent shading that occurs in a captured image.

  In order to solve the above problems, a solid-state imaging device of the present invention includes a photoelectric conversion unit (for example, a photodiode PD in the embodiment) that converts incident light into a signal charge, and the signal charge generated by the photoelectric conversion unit. Transfer means for transferring (for example, transfer transistor M2 in the embodiment), amplification means for amplifying the transferred signal charge (for example, amplification transistor M3 in the embodiment), and reset means (for example, resetting the signal charge) , And a reset transistor M1) in the embodiment, for example, an image sensor in which a plurality of pixels (for example, the unit pixel 45 in the embodiment) are arranged in a matrix direction, and a first for resetting the signal charges of the image sensor in sequence. Scanning circuit (for example, electronic shutter shift register 422 in the embodiment) and the imaging Corresponding to the second scanning circuit (for example, the read shift register 421 in the embodiment) for sequentially reading the signal charges of the child and the travel of the shutter that shields the image sensor as one of the front curtain and the rear curtain Control means for controlling the first scanning circuit and the second scanning circuit to be driven in parallel when resetting the signal charge of the imaging device as the other of the front curtain or the rear curtain (For example, the image sensor control signal generation circuit 141 in the embodiment).

  Further, the control means of the present invention is characterized in that the first scanning circuit and the second scanning circuit are controlled so that the image sensor is simultaneously reset in a plurality of rows.

  Further, the control means of the present invention is characterized in that the first scanning circuit and the second scanning circuit are controlled so as to reset by resetting reset times for each row of the image sensor.

  The solid-state imaging device according to the present invention further includes one or a plurality of third scanning circuits (for example, a read mode switching shift register 427 in the embodiment) for sequentially resetting the signal charges of the imaging element. The control means controls the first scanning circuit, the second scanning circuit, and the plurality of third scanning circuits to be driven in parallel.

  Further, the control means of the present invention is a means for generating a signal for reading the signal charge of the image sensor from the output signal from the second scanning circuit (for example, the read shift register pulse φRSR in the embodiment) ( For example, a scanning circuit selection switch (for example, a signal charge readout circuit 425 in the embodiment) or a means for generating a signal for resetting the signal charge of the imaging element (for example, the signal charge reset circuit 426 in the embodiment) (for example, The shift register selection switches 423 and 424) according to the embodiment and the output signal of the second scanning circuit output via the scanning circuit selection switch in response to the reset operation of the signal charge of the image sensor. A control signal for generating a signal for switching the destination (for example, the selection signal φSEL in the embodiment). Signal generation means (for example, the image sensor control signal generation circuit 141 in the embodiment).

  The digital camera of the present invention is disposed between the solid-state imaging device, a lens (for example, the lens 2 in the embodiment) that guides incident light to the solid-state imaging device, and the solid-state imaging device. And a camera control device (for example, the camera control device 11 in the embodiment) that controls the solid-state imaging device, the lens, and the shutter. .

  According to the present invention, in the solid-state imaging device that uses the electronic shutter operation of the solid-state imaging device as the front curtain of the shutter, the operation of the front curtain of the shutter by the electronic shutter is an operation close to the rear curtain of the focal plane shutter with a simple configuration. Therefore, it is possible to prevent the shading that occurs in the final captured image to be obtained.

1 is a block diagram showing a schematic configuration of a digital camera according to an embodiment of the present invention. It is the block diagram which showed schematic structure of the solid-state imaging device by embodiment of this invention. 1 is a block diagram illustrating a schematic configuration of a vertical scanning circuit of a first embodiment in a solid-state imaging device of the present embodiment. 3 is a timing chart showing the operation timing of the front curtain electronic shutter drive of the solid-state imaging device in the vertical scanning circuit of the first embodiment of the present invention. 6 is a timing chart showing another example of the operation timing of the front curtain electronic shutter drive of the solid-state imaging device in the vertical scanning circuit of the first embodiment of the present invention. It is the block diagram which showed schematic structure of the vertical scanning circuit of 2nd Embodiment in the solid-state imaging device of this embodiment. 10 is a timing chart showing the operation timing of the front curtain electronic shutter drive of the solid-state imaging device in the vertical scanning circuit of the second embodiment of the present invention. It is the block diagram which showed schematic structure of the general digital camera. It is the block diagram which showed schematic structure of the conventional solid-state imaging device. It is the figure which modeled schematic operation | movement of the shutter drive in imaging | photography of the conventional digital camera. It is the figure which schematized schematic operation | movement of the conventional front curtain electronic shutter drive. It is a timing chart which showed the timing of the conventional front curtain electronic shutter drive. It is a figure explaining the problem in the conventional front curtain electronic shutter operation | movement.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a digital camera (for example, a digital camera) of the present embodiment. A digital camera 101 shown in FIG. 1 includes a lens 2, a mechanical shutter 103, an image sensor 104, an image signal processing circuit 5, a memory 6, a recording device 7, a lens control device 8, a shutter driving device 109, an imager driving device 110, and a camera. It comprises a control device 111 and a display device 12.

  The digital camera 101 of this embodiment has the same configuration as the conventional digital camera 1 shown in FIG. 8, but the image sensor 4 of the conventional digital camera 1 is changed to the image sensor 104 of the present invention. . With the change to the image sensor 104, the mechanical shutter 3 is the mechanical shutter 103, the shutter driving device 9 is the shutter driving device 109, the imager driving device 10 is the imager driving device 110, and the camera control device 11 is the camera control device. 111 respectively.

  In addition, about the component in which the digital camera 101 of this embodiment and the conventional digital camera 1 shown in FIG. 8 operate | moved similarly, the same code | symbol is provided and description is abbreviate | omitted. In the following description, the meanings of numerals and symbols in “(): parentheses” after each symbol are the same.

The mechanical shutter 103 is a focal plane type shutter mechanism that is driven and controlled by a shutter driving device 109 and shields light incident on the digital camera via the lens 2, but only the rear curtain of the focal plane shutter is driven and controlled. . For example, the configuration is the same as that of the mechanical shutter 3 shown in FIG. 10, and only the focal plane shutter rear curtain 31 is driven and controlled by the shutter driving device 109.
For example, the mechanical shutter 103 may be configured to include only the focal plane shutter rear curtain 31 shown in FIG.

  The image sensor 104 is a solid-state imaging device that is driven and controlled by the imager driving device 110 and converts subject light incident on the digital camera via the lens 2 into an image signal. A detailed description of the image sensor 104 will be described later.

  The camera control device 111 is a control device that performs overall control of the digital camera, similar to the camera control device 11 in the conventional digital camera 1 shown in FIG. 8, and includes a shutter drive device 109 and an imager drive device 110. The mechanical shutter 103 and the image sensor 104 are cooperatively controlled by the control.

<First Embodiment>
Next, the image sensor of this embodiment will be described. FIG. 2 is a block diagram showing a schematic configuration of the image sensor 104 according to the present embodiment. 2, the image sensor 104 includes an image sensor control signal generation circuit 141, a vertical scanning circuit 142, a horizontal scanning circuit 43, a constant current source 44, a unit pixel 45, a CDS circuit 46, and a column selection circuit 47. 2 shows an example in which a plurality of unit pixels 45 are two-dimensionally arranged in 3 rows and 3 columns. The constant current source 44, the CDS circuit 46, and the column selection circuit 47 are arranged for each column direction of the unit pixels 45.

The image sensor 104 shown in FIG. 2 performs a first curtain electronic shutter operation at high speed using two shift registers.
Note that the image sensor 104 of the present embodiment and the conventional image sensor 4 shown in FIG. 9 differ only in the image sensor control signal generation circuit 141 and the vertical scanning circuit 142, and differ from the conventional image sensor 4 shown in FIG. Similar components are given the same reference numerals and description thereof is omitted.

The image sensor control signal generation circuit 141 controls the vertical scanning circuit 142, the horizontal scanning circuit 43, and the CDS circuit 46.
The vertical scanning circuit 142 controls the unit pixel 45. Further, the vertical scanning circuit 142 can perform a row thinning operation in the control of the unit pixel 45. A detailed description of the vertical scanning circuit 142 will be described later.

Next, the vertical scanning circuit 142 of this embodiment will be described. FIG. 3 is a block diagram showing a schematic configuration of the vertical scanning circuit 142 according to the present embodiment. In FIG. 3, the vertical scanning circuit 142 includes a readout shift register 421, an electronic shutter shift register 422, shift register selection switches 423 and 424, a plurality of OR gates OR2, a signal charge readout circuit 425, and a signal charge reset circuit 426. Composed. The signal charge readout circuit 425 and the signal charge reset circuit 426 are composed of a plurality of OR gates OR and a plurality of AND gates AND.
In FIG. 3, the meanings of numerals and symbols in “(): parentheses” shown after the reference numerals and signal line names of the components are the same as those of the image sensor 104 shown in FIG. Represents the corresponding row number and column number.

The read shift register 421 is a shift register that has a thinning mode and can skip and select each row.
An output pulse φRSR of each bit of the read shift register 421 (hereinafter referred to as “read shift register pulse φRSR”) is input to the signal charge read circuit 425 via the shift register selection switch 423. The read shift register pulse φRSR is input to the signal charge reset circuit 426 via the shift register selection switch 424.

The electronic shutter shift register 422 is a shift register that has a thinning mode and can skip and select each row.
An output pulse φSSR of each bit of the electronic shutter shift register 422 (hereinafter referred to as “electronic shutter shift register pulse φSSR”) is read out by the OR gate OR2 via the shift register selection switch 424. ORed with the pulse φRSR and input to the signal charge reset circuit 426.

  The shift register selection switches 423 and 424 are switched between an “ON” state and an “OFF” state by a selection signal φSEL input from the image sensor control signal generation circuit 141. In FIG. 3, the selection signal φSEL is collectively displayed, but the selection signal φSEL input from the image sensor control signal generation circuit 141 is a signal different for each of the shift register selection switches 423 and 424.

The signal charge read circuit 425 receives the read shift register pulse φRSR and φRS1, φTX1, and φSE. φRS 1, φTX 1, and φSE are pulses used for reading by the image sensor 104 and are output from the image sensor control signal generation circuit 141.
When the shift register selection switch 423 is “ON” and the shift register selection switch 424 is in the “OFF” state, the signal charge readout circuit 425 generates a normal readout control signal based on the value of the readout shift register pulse φRSR. Is output to the unit pixel 45 of the image sensor 104.

More specifically, the signal charge readout circuit 425 receives φRS1, φTX1, and φSE input from the image sensor control signal generation circuit 141 when the read shift register pulse φRSR is at “High” level in a normal read operation. Are selected as read select pulses φSE _{(1 *) to} φSE _{(3 *)} , reset pulses φRS _{(1 *) to} φRS _{(3 *)} and transfer pulses φTX _{(1 *) to} φTX _{(3 *).} A pulse of “High” level is output to the unit pixel 45 of 104.

The signal charge reset circuit 426 receives the output signal of the OR gate OR2 obtained by ORing the read shift register pulse φRSR and the electronic shutter shift register pulse φSSR, and φRS2 and φTX2. φRS2 and φTX2 are pulses used for the electronic shutter of the image sensor 104, and are output from the image sensor control signal generation circuit 141.
The signal charge reset circuit 426 controls the electronic shutter control signal based on the value of the read shift register pulse φRSR when the shift register selection switch 423 is “OFF” and the shift register selection switch 424 is in the “ON” state. Is output to the unit pixel 45 of the image sensor 104.

More specifically, when the signal charge reset circuit 426 outputs a control signal for electronic shutter based on the value of the read shift register pulse φRSR, when the read shift register pulse φRSR is at the “High” level, φRS2 input from the image sensor control signal generation circuit 141, the FaiTX2, as a reset pulse φRS for electronic shutter _{(1 *) ~φRS (3 *} ) and the transfer pulse _{φTX (1 *) ~φTX (3} *), image A pulse of “High” level is output to the unit pixel 45 of the sensor 104.

The signal charge reset circuit 426 sends an electronic shutter control signal to the unit pixel 45 of the image sensor 104 based on the value of the electronic shutter shift register pulse φSSR regardless of the state of the shift register selection switches 423 and 424. Output to. That is, in a normal electronic shutter operation, when the electronic shutter shift register pulse φSSR is at the “High” level, φRS2 and φTX2 input from the image sensor control signal generation circuit 141 are used as the electronic shutter reset pulse φRS _{(1 *)} “High” level pulses are output to the unit pixel 45 of the image sensor 104 as ~ φRS _{(3 *)} and transfer pulses φTX _{(1 *) to} φTX _{( 3 *)} .

Next, the operation of the image sensor of this embodiment will be described. FIG. 4 is a timing chart showing the operation timing of the image sensor 104 according to the present embodiment. FIG. 4 shows an example of the image sensor 104 in which the unit pixels 45 are arranged in a grid in 4 rows and 3 columns. In addition, as described above, the unit pixel 45 has the “High” level by the φRS1, φRS2, φTX1, φTX2, and φSE selected by the “High” level of the read shift register pulse φRSR or the electronic shutter shift register pulse φSSR. It is driven by select pulses φSE _{(1 *) to} φSE _{(4 *)} , reset pulses φRS _{(1 *) to} φRS _{(4 *)} and transfer pulses φTX _{(1 *) to} φTX _{(4 *)} .

First, the drive timing of a normal electronic shutter will be described. At time t1, the shift register selection switch 423 is set to “ON” and the shift register selection switch 424 is set to “OFF”. At this time, the select pulse φSE _{(1 *)} , the reset pulse φRS _{(1 *)} and the transfer that are input to the unit pixel 45 in the first row where the read shift register pulse φRSR _{(1 *)} is at the “High” level. The pulse φTX _{(1 *)} becomes the “High” level. As a result, the pixel signal exposed by the unit pixel 45 in the first row is read out. Thereafter, a voltage corresponding to the read pixel signal is output to the horizontal signal line H.
At this time, both the focal plane shutter rear curtain 31 and the focal plane shutter front curtain 32 are in the live view state, which is an “open” state.

Subsequently, the read shift register 421 sequentially shifts, and the read shift register pulses φRSR _{(2 *) to} φRSR _{(4 *)} are sequentially set to the “High” level, thereby being input to the unit pixels 45 in the corresponding row. Select pulses φSE _{(2 *) to} φSE _{(4 *)} , reset pulses φRS _{(2 *) to} φRS _{(4 *)} and transfer pulses φTX _{(2 *) to} φTX _{(4 *)} are sequentially set to the “High” level. Become. As a result, the pixel signals exposed by the unit pixels 45 in the second to fourth rows are sequentially read, and voltages corresponding to the read pixel signals are sequentially output to the horizontal signal line H.

Also, at time t2 after a certain time from time t1, the pixel is reset at normal electronic shutter timing. At normal electronic shutter timing, first, the reset pulse φRS _{(1 *)} and the transfer pulse input to the unit pixel 45 in the first row where the electronic shutter shift register pulse φSSR _{(1 *)} is at the “High” level. φTX _{(1 *)} becomes the “High” level. As a result, the unit pixels 45 in the first row are reset.

Subsequently, the electronic shutter shift register 422 sequentially shifts, and the electronic shutter shift register pulses φSSR _{(2 *) to} φSSR _{(4 *)} are sequentially set to the “High” level, so that the unit pixels 45 of the corresponding row are displayed. The reset pulses φRS _{(2 *) to} φRS _{(4 *)} and the transfer pulses φTX _{(2 *) to} φTX _{(4 *)} that are input to are sequentially set to the “High” level. As a result, the unit pixels 45 in the second to fourth rows are sequentially reset.
In the live view state, in order to make the exposure time the same for all the rows, the inclination of the normal electronic shutter timing needs to be the same as the inclination of the readout timing.

  Next, the driving timing of the front curtain electronic shutter will be described. When the shutter button is pressed at an arbitrary timing in the live view state, for example, at time t3, and a “High” level pulse is input to the release signal for starting still image capturing, scanning of the front curtain electronic shutter starts. .

  At the front curtain electronic shutter timing, first, the shift register selection switches 423 and 424 select the electronic shutter reset pulse φRS and the transfer pulse φTX to be output to the odd-numbered unit pixels 45 and the even-numbered unit pixels 45. More specifically, in the odd-numbered row, the shift pulse selection switch 423 is set to “OFF” and the shift register selection switch 424 is set to the “ON” state, and the electronic shutter reset pulse φRS and the transfer based on the read shift register 421 are transferred. Control to output pulse φTX. In the even-numbered row, the shift register selection switch 423 is set to “OFF” and the shift register selection switch 424 is set to the “OFF” state, and the electronic shutter reset pulse φRS and transfer pulse φTX based on the electronic shutter shift register 422 are generated. Control to output. Further, the thinning mode is set in the read shift register 421 and the electronic shutter shift register 422.

As a result, the reset pulse φRS _{(1 *)} and the transfer pulse φTX _{(1 *)} input to the unit pixel 45 in the first row where the read shift register pulse φRSR _{(1 *)} is at the “High” level. It becomes “High” level, and the unit pixels 45 in the first row are reset. At the same time, the reset pulse φRS _{(2 *)} and the transfer pulse φTX _{(2 *)} input to the unit pixel 45 in the second row in which the electronic shutter shift register pulse φSSR _{(2 *)} is at the “High” level. It becomes “High” level, and the unit pixels 45 in the second row are reset.

Subsequently, when the read shift register 421 is shifted, the reset pulse φRS _{(3 *)} input to the unit pixels 45 in the third row in which the read shift register pulse φRSR _{(3 *)} is at the “High” level. The transfer pulse φTX _{(3 *)} becomes “High” level, and the unit pixels 45 in the third row are reset. At the same time, when the electronic shutter shift register 422 is shifted, the reset pulse φRS _{(4 *)} input to the unit pixels 45 in the fourth row where the electronic shutter shift register pulse φSSR _{(4 *)} is at the “High” level _{. ) And the} transfer pulse φTX _{(4 *)} become “High” level, and the unit pixels 45 in the fourth row are reset.

  By controlling in this way, the inclination of the front curtain electronic shutter timing becomes twice the inclination of the normal electronic shutter timing, and can be adapted to the fast traveling timing of the mechanical shutter.

  Thereafter, the photographing is completed when the focal plane shutter rear curtain 31 that has started to be driven after a certain time from time t3 is completely closed (time t4). Then, pixel signals are sequentially read out. Note that readout of the pixel signal is the same as the readout timing started from time t1, and thus description thereof is omitted. In addition, after the shooting is completed, unlike the live view state, the normal electronic shutter that is started after a predetermined time is not driven.

  Next, another embodiment of the driving timing of the front curtain electronic shutter will be described. FIG. 5 is a timing chart showing another example of the operation timing of the image sensor 104 according to the present embodiment. The timing chart shown in FIG. 5 is similar to the timing chart shown in FIG. 4 by setting the shift register selection switches 423 and 424 and setting the thinning mode for the read shift register 421 and the electronic shutter shift register 422. This is an example in which the front curtain electronic shutter operation is performed and the inclination of the front curtain electronic shutter timing is changed.

  Note that the timing chart shown in FIG. 5 shows an example of the image sensor 104 in which the unit pixels 45 are arranged in a grid of 4 rows and 3 columns, similarly to the timing chart shown in FIG. In FIG. 5, the operation in the live view state from time t1 to time t3 and the readout operation of the pixel signal after completion of shooting from time t5 are the same as those in the live view state from time t1 to time t3 shown in FIG. Since this is the same as the operation and the readout operation of the pixel signal after completion of imaging from time t4, the description is omitted.

  Further, the setting of the shift register selection switches 423 and 424 at the front curtain electronic shutter timing and the setting of the thinning mode of the reading shift register 421 and the electronic shutter shift register 422 are the same as those of the front curtain electronic shutter timing shown in FIG. It is.

  At the front curtain electronic shutter timing starting from time t3 shown in FIG. 5, the timing of the electronic shutter shift register pulse φSSR output from the electronic shutter shift register 422 is the read shift register output from the read shift register 421. The timing is delayed by a half cycle with respect to the timing of the pulse φRSR. That is, the read shift register pulse φRSR is at the “High” level at time t3, whereas the electronic shutter shift register pulse φSSR is at the “High” level at time t4 delayed by half a cycle. It has become.

  Further, at the front curtain electronic shutter timing shown in FIG. 5, between time t3 and time t5, φRS2 and φTX2, which are pulses input from the image sensor control signal generation circuit 141, are always set to the “High” level. Thus, the timing of the front curtain electronic shutter can be completely synchronized with the read shift register 421 and the electronic shutter shift register 422.

In the first-curtain electronic shutter timing shown in FIG. 5, first, the reset pulse φRS _{(1 *)} and the transfer pulse φTX _{( 1) in the} first row in which the read shift register pulse φRSR _{(1 *)} is at “High” level. _{1 *)} resets the unit pixel 45 in the first row.
Subsequently, the reset pulse φRS _{(2 *} ) in the second row in which the electronic shutter shift register pulse φSSR _{(2 *)} is at the “High” level at a timing delayed by a half cycle from the reset of the unit pixels 45 in the first row _{. ) And the} transfer pulse φTX _{(2 *)} , the unit pixels 45 in the second row are reset.

Subsequently, when the read shift register 421 shifts, the read shift register pulse φRSR _{(3 *)} is at the “High” level at a timing delayed by a half cycle from the reset of the unit pixels 45 in the second row. The unit pixels 45 in the third row are reset by the reset pulse φRS _{(3 *)} of the eye and the transfer pulse φTX _{(3 *)} .
Subsequently, when the electronic shutter shift register 422 is shifted, the electronic shutter shift register pulse φSSR _{(4 *)} is at the “High” level at a timing delayed by a half cycle from the reset of the unit pixel 45 in the third row. The unit pixels 45 in the fourth row are reset by the reset pulse φRS _{(4 *)} and the transfer pulse φTX _{(4 *)} in the fourth row.

  By controlling in this way, the reset of the odd-numbered unit pixels 45 and the reset of the even-numbered unit pixels 45 are delayed by a half cycle. Thus, the inclination of the front curtain electronic shutter timing is different from the inclination of the normal electronic shutter timing, and can be adapted to the fast traveling timing of the mechanical shutter.

  As described above, according to the first embodiment of the present invention, the shift register selection switches 423 and 424 and the thinning mode setting of the read shift register 421 and the electronic shutter shift register 422 are first performed. The inclination of the curtain electronic shutter timing can be changed. As a result, the driving speed of the front curtain electronic shutter can be increased.

  Also, in a normal digital camera with a live view function, since an electronic shutter and a thinning-out operation are indispensable functions, shift register selection switches 423 and 424 are provided since they are used in most cameras. The timing of the front curtain electronic shutter can be increased by simply changing the configuration.

  In addition to setting the shift register selection switches 423 and 424 and setting the thinning mode for the read shift register 421 and the electronic shutter shift register 422, by varying the pulse start timing of the electronic shutter shift register 422, The inclination of the front curtain electronic shutter timing can be varied. Thus, the driving speed of the front curtain electronic shutter can be made variable with only a simple configuration and timing change, and the inclination of the front curtain electronic shutter timing can be optimized.

Second Embodiment
Next, a second embodiment of the vertical scanning circuit of this embodiment will be described. FIG. 6 is a block diagram showing a schematic configuration of the vertical scanning circuit 242 according to the present embodiment. In FIG. 6, a vertical scanning circuit 242 includes a read shift register 421, an electronic shutter shift register 422, a read mode switching shift register 427, shift register selection switches 423, 424, 428, 429, a plurality of OR gates OR3, A signal charge readout circuit 425 and a signal charge reset circuit 426 are included.

A vertical scanning circuit 242 illustrated in FIG. 6 is a vertical scanning circuit provided in the image sensor 104 instead of the vertical scanning circuit 142 illustrated in FIGS. 2 and 3. Further, the vertical scanning circuit 242 shown in FIG. 6 is different from the vertical scanning circuit 142 shown in FIG. 3 in that a read mode switching shift register 427 and shift register selection switches 428 and 429 are added. In addition, with the addition of the read mode switching shift register 427, the signal charge reset circuit 426 receives the output signals of the plurality of OR gates OR3 instead of the output signals of the plurality of OR gates OR2. .
In FIG. 6, the components other than the above-described changes are the same as those of the vertical scanning circuit 142 shown in FIG. 3, and the same components as those of the vertical scanning circuit 142 are given the same reference numerals and the same operations are performed. Will not be described.

The read mode switching shift register 427 has a thinning mode, and is a shift register used for special reading when changing the thinning rate according to the camera mode or when displaying a cut-out image on the live view screen, for example.
The output pulse φESR of each bit of the read mode switching shift register 427 (hereinafter referred to as “read mode switching shift register pulse φESR”) is output to the OR gate OR3 via the shift register selection switch 429.

The read mode switching shift register pulse φESR is logically ORed with the read shift register pulse φRSR input via the shift register selection switch 424 and the electronic shutter shift register pulse φSSR by the OR gate OR3 to reset the signal charge. Input to the circuit 426. Further, the read mode switching shift register pulse φESR is input to, for example, a special read circuit (not shown) via the shift register selection switch 428.
More specifically, when the shift register selection switch 428 is “ON” and the shift register selection switch 429 is in the “OFF” state, the read mode switching shift register pulse φESR is used for special reading. When the shift register selection switch 428 is “OFF” and the shift register selection switch 429 is “ON”, it is used in the vertical scanning circuit 242 shown in FIG. 6 for the front curtain electronic shutter.

  The shift register selection switches 428 and 429 are switched between an “ON” state and an “OFF” state by a selection signal φSEL input from the image sensor control signal generation circuit 141. In FIG. 6, the selection signal φSEL is collectively displayed, but the selection signal φSEL input from the image sensor control signal generation circuit 141 is different for each of the shift register selection switches 423, 424, 428, and 429. Signal.

The signal charge reset circuit 426 includes an output signal of an OR gate OR3 obtained by ORing a read shift register pulse φRSR, an electronic shutter shift register pulse φSSR, and a read mode switching shift register pulse φESR, and φRS2, φTX2 is input.
Similarly to the vertical scanning circuit 142 shown in FIG. 3, the signal charge reset circuit 426 outputs a control signal for electronic shutter based on the value of the read shift register pulse φRSR to the unit pixel 45 of the image sensor 104. In addition, the signal charge reset circuit 426 performs electronic shuttering based on the value of the read mode switching shift register pulse φESR when the shift register selection switch 428 is “OFF” and the shift register selection switch 429 is in the “ON” state. Control signal is output to the unit pixel 45 of the image sensor 104.

More specifically, when the signal charge reset circuit 426 outputs a control signal for electronic shutter based on the value of the read mode switching shift register pulse φESR, the read mode switching shift register pulse φESR is at the “High” level. In this case, φRS2 and φTX2 input from the image sensor control signal generation circuit 141 are used as electronic shutter reset pulses φRS _{(1 *) to} φRS _{(3 *)} and transfer pulses φTX _{(1 *) to} φTX _{( 3 *) . )} , A pulse of “High” level is output to the unit pixel 45 of the image sensor 104.

  The signal charge reset circuit 426 sends an electronic shutter control signal to the image sensor 104 based on the value of the electronic shutter shift register pulse φSSR regardless of the state of the shift register selection switches 423, 424, 428, and 429. Are output to the unit pixel 45.

Next, the driving timing of the front curtain electronic shutter by the vertical scanning circuit 242 of this embodiment will be described. FIG. 7 is a timing chart showing the driving timing of the front curtain electronic shutter by the vertical scanning circuit 242 according to the present embodiment. 7 shows an example of the image sensor 104 in which the unit pixels 45 are arranged in a grid pattern in 19 rows. The read shift register pulse φRSR, the electronic shutter shift register pulse φSSR, and the read mode switching shift register pulse φESR. Only shows. The operation of other signals is the same as the operation timing of the image sensor 104 in the first embodiment shown in FIGS. In other words, the unit pixel 45 in the image sensor 104 includes the read shift register pulse φRSR, the electronic shutter shift register pulse φSSR, and the read mode switching shift register pulse φESR selected by the “High” level φRS1, φRS2, φTX1, “High” level select pulses φSE _{(1 *) to} φSE _{(19 *)} , reset pulses φRS _{(1 *) to} φRS _{(19 *)} and transfer pulses φTX _{(1 *) to} φTX _{(19 *) by} φTX2 and φSE Driven by.

  At the front curtain electronic shutter timing shown in FIG. 7, the shutter button is pressed at an arbitrary timing in the live view state, for example, at time t1, and a “High” level pulse is input to the release signal for starting the still image capturing. As a result, scanning of the front curtain electronic shutter starts.

  When scanning of the front curtain electronic shutter starts, setting of the shift register selection switches 423, 424, 428, and 429 and setting of a thinning mode for the reading shift register 421, the electronic shutter shift register 422, and the reading mode switching shift register 427 are performed. To adjust the inclination of the leading shutter electronic shutter timing to the traveling timing of the mechanical shutter (for example, the focal plane shutter rear curtain 31).

More specifically, the shift register selection switch 423 is set to “OFF” and the shift register selection switch 424 is set to the “ON” state, and the electronic shutter reset pulse φRS and transfer pulse φTX based on the read shift register 421 are output. Control to do. Further, the shift register selection switch 428 is set to “OFF” and the shift register selection switch 429 is set to the “ON” state, so that the electronic shutter reset pulse φRS and the transfer pulse φTX based on the read mode switching shift register 427 are output. To control.
At time t2 and time t3, the decimation rate of the read shift register 421 is changed, and further, at time t3, the decimation rate of the read mode switching shift register 427 is changed to be input to the unit pixel 45. Control is performed so as to change the timing at which the reset pulse φRS and transfer pulse φTX become “High” level.

  After that, after the focal plane shutter rear curtain 31 that has started to drive after a certain time from time t1 is completely in the “closed” state (time t4) and the photographing is completed, pixel signals are sequentially read out.

  As described above, according to the second embodiment of the present invention, the inclination of the front curtain electronic shutter timing is controlled to match the inclination of the mechanical shutter traveling timing, that is, the inclination of the front curtain electronic shutter timing. Can be changed on the way. This makes it possible to change the inclination of the front curtain electronic shutter timing in accordance with the mechanical shutter timing in accordance with the traveling speed that is non-linear in a normal mechanical shutter. The same exposure time can be realized.

  In many cases, a multifunctional digital camera is equipped with a special reading function such as changing a thinning rate depending on a camera mode or displaying a cut-out image on a live view screen. The timing characteristics of the front curtain electronic shutter can be made non-linear timing characteristics in accordance with the running of the mechanical shutter only by a simple configuration change of providing 428 and 429.

In the second embodiment, in addition to the read shift register 421 and the electronic shutter shift register 422, the reset pulse φRS and the transfer pulse input to the unit pixel 45 using the read mode switching shift register 427. Although the case of changing the timing at which the φTX becomes “High” level has been described, still another shift register (a plurality of shift registers may be used) may be used.
In this case, a shift register selection switch for selecting an output pulse of another shift register is added by the number of shift registers to be used, and an OR gate for inputting the selected pulse to the signal charge reset circuit 426 (for example, This can be dealt with by changing the OR gate in place of the OR gate OR3 shown in FIG. 6 to an OR gate corresponding to the shift register to be used.
As a result, the timing at which the reset pulse φRS and the transfer pulse φTX input to the unit pixel 45 become “High” level can be changed more finely.

As described above, according to the embodiment for carrying out the present invention, the inclination of the front curtain electronic shutter timing can be changed with a simple configuration, and is close to the rear curtain of the focal plane shutter that performs non-linear running. It can be an action.
Thus, it is possible to prevent shading that occurs in the final captured image obtained when the digital camera equipped with the image sensor of the present embodiment is captured.

  In the present embodiment, the case where the traveling speed of the mechanical shutter is higher than the scanning speed of the front curtain electronic shutter has been described. However, the present invention describes the traveling speed of the mechanical shutter and the scanning speed of the front curtain electronic shutter. For example, the present invention can also be applied to a case where the traveling speed of the mechanical shutter is lower than the scanning speed of the front curtain electronic shutter.

  Further, in the present embodiment, some examples have been shown regarding the arrangement of the unit pixels 45 in the row direction and the column direction, but the arrangement of the unit pixels 45 in the row direction and the column direction is for carrying out the present invention. The number of row and column directions in which the unit pixels 45 are arranged can be changed without departing from the scope of the present invention.

The specific configurations of the vertical scanning circuit and the image sensor control signal generation circuit in the present invention are not limited to the embodiments for carrying out the present invention, and various modifications can be made without departing from the spirit of the present invention. Can do.
For example, in the vertical scanning circuit of the present embodiment, selection of the shift register pulse φRSR for reading, the shift register pulse φSSR for electronic shutter, and the shift register pulse φESR for reading mode switching is performed by shift register selection switches 423, 424, 428, 429 Although the configuration for selecting the connection path has been described, the present invention is not limited to this configuration, and any configuration that can be controlled so as to change the output timing of the reset pulse φRS and the transfer pulse φTX input to the unit pixel 45 may be used. .

  For example, in the vertical scanning circuit of this embodiment, the shift register selection switches 423, 424, 428, and 429 are switched between the “ON” state and the “OFF” state by the selection input from the image sensor control signal generation circuit 141. Although the configuration performed based on the signal φSEL has been described, the configuration is not limited to this configuration, and the read shift register pulse is changed in accordance with the change in the output timing of the reset pulse φRS and the transfer pulse φTX input to the unit pixel 45. Any configuration capable of switching control of φRSR, electronic shutter shift register pulse φSSR, and readout mode switching shift register pulse φESR may be used.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

DESCRIPTION OF SYMBOLS 1,101 ... Digital camera, 2 ... Lens, 3,103 ... Mechanical shutter, 4,104 ... Image sensor, 5 ... Image signal processing circuit, 6 ... Memory, 7. ..Recording device, 8 ... Lens control device, 9,109 ... Shutter drive device, 10,110 ... Imager drive device, 11,111 ... Camera control device, 12 ... Display device, 41, 141 ... image sensor control signal generation circuit, 42, 142, 242 ... vertical scanning circuit, 43 ... horizontal scanning circuit, 44 ... constant current source, 45 ... unit pixel, 46. ..CDS circuit, 47 ... column selection circuit, 421 ... readout shift register, 422 ... electronic shutter shift register, 423,424,428,429 ... shift register selection switch 425 ... Signal charge readout circuit, 426 ... Signal charge reset circuit, 427 ... Read mode switching shift register, PD ... Photodiode, FD ... Floating diffusion, M1 ... Reset transistor, M2 ... Transfer transistor, M3 ... Amplification transistor, M4 ... Select transistor, M5 ... Clamp transistor, M6 ... Sample hold transistor, C1 ... Clamp capacitor, C2 ... Sample hold capacitor 31 ... Focal plane shutter rear curtain, 32 ... Focal plane shutter front curtain, V ... Vertical signal line, H ... Horizontal signal line, φRS ... Reset pulse, φTX ... Transfer pulse , ΦSE: Select pulse, φCL: Clan Pulse, φSH ... sample hold pulse, φH ... column selection pulse, Vbias ... current source bias, Vd ... power supply voltage, φRSR ... readout shift register pulse, φSSR ... for electronic shutter Shift register pulse, φESR: Shift register pulse for reading mode switching, φSEL: Selection signal

Claims (6)

Photoelectric conversion means for converting incident light into signal charge; transfer means for transferring the signal charge generated by the photoelectric conversion means; amplification means for amplifying the transferred signal charge; and resetting the signal charge An image pickup device in which a plurality of pixels having reset means are arranged in a matrix direction;
A first scanning circuit for sequentially resetting the signal charges of the image sensor;
A second scanning circuit for sequentially reading out the signal charges of the image sensor;
When the signal charge of the image sensor is reset as the other of the front curtain or the rear curtain in response to the travel of a shutter that shields the image sensor as one of the front curtain or the rear curtain, Control means for controlling the scanning circuit and the second scanning circuit to drive in parallel;
A solid-state imaging device comprising: The control means includes
Controlling the first scanning circuit and the second scanning circuit so as to simultaneously reset the imaging elements in a plurality of rows;
The solid-state imaging device according to claim 1. The control means includes
Controlling the first scanning circuit and the second scanning circuit so as to overlap and reset the reset time for each row of the image sensor;
The solid-state imaging device according to claim 1. One or more third scanning circuits for sequentially resetting the signal charges of the image sensor;
Further comprising
The control means includes
Controlling the first scanning circuit and the second scanning circuit and the plurality of third scanning circuits to be driven in parallel;
The solid-state imaging device according to claim 1. The control means includes
A scanning circuit selection switch for outputting an output signal from the second scanning circuit to a means for generating a signal for reading out the signal charge of the image sensor or a means for generating a signal for resetting the signal charge of the image sensor When,
Control signal generating means for generating a signal for switching the output destination of the output signal of the second scanning circuit output via the scanning circuit selection switch in response to the reset operation of the signal charge of the imaging device;
The solid-state imaging device according to claim 1, further comprising: A solid-state imaging device according to any one of claims 1 to 5,
A lens for guiding incident light to the solid-state imaging device;
A shutter disposed between the solid-state imaging device and the lens;
A camera control device for controlling the solid-state imaging device, the lens and the shutter;
A digital camera comprising:

Images