JP2011003603A - System for manufacturing semiconductor, and method of controlling device for manufacturing semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for manufacturing a semiconductor capable of reducing dispersion in a wafer surface, and improving a manufacturing yield, and to provide a method of controlling a device for manufacturing a semiconductor.SOLUTION: With regard to a wafer which has been processed in either of processing chambers 31, 32 of a device 3 for manufacturing a semiconductor and thereafter processed in any of processing chambers 41, 42, 43 of a device 4 for manufacturing a semiconductor, the processing results by the devices 3, 4 for processing a semiconductor are acquired by being related to the processing paths of the wafer. With regard to a group of wafers planned to be processed by the devices 3, 4 for manufacturing a semiconductor, a wafer processing ratio for each of the processing paths is determined based on the acquired processing result for each of the processing paths. According to the determined wafer processing ratio for each of the processing paths, processing to the group of wafers planned to be processed is executed in the devices 3, 4 for manufacturing a semiconductor.

Description

  The present invention relates to a semiconductor manufacturing system and a method for controlling a semiconductor manufacturing apparatus, and in particular, a semiconductor manufacturing system applied to a semiconductor manufacturing line having a plurality of processing paths for processing a workpiece to be processed by the same process flow and The present invention relates to a method for controlling a semiconductor manufacturing apparatus.

  In recent years, with the increase in the diameter of semiconductor wafers and the reduction in process margins, it has become important to increase the in-plane uniformity of processing performed on wafers in semiconductor manufacturing apparatuses. When the wafer in-plane uniformity is low, the manufacturing yield is remarkably lowered and the manufacturing cost is increased.

  As a conventional technique for increasing the in-plane uniformity of the wafer, for example, there is a technique disclosed in Patent Document 1. Patent Document 1 discloses a technique for improving the in-wafer uniformity of processing accuracy in a plasma processing apparatus. In this prior art, the temperature of the focus ring arranged on the outer periphery of the stage on which the wafer is placed in the processing chamber is adjusted based on the gas temperature distribution in the processing chamber, and in-plane uniformity of processing accuracy in processing by plasma processing Has improved.

JP 2008-251866 A

  According to the above prior art, in the plasma processing apparatus, it is possible to improve the in-wafer uniformity of processing accuracy. However, the above prior art cannot be applied to other semiconductor manufacturing apparatuses that perform processing different from plasma processing. In general, many semiconductor manufacturing apparatuses that perform processing without using plasma, such as an exposure apparatus, a heat treatment apparatus, and a CMP polishing apparatus, belong to a semiconductor manufacturing line. Therefore, in order to realize an improvement in manufacturing yield and a reduction in manufacturing cost, it is important to improve the in-wafer uniformity in these other apparatuses.

  In recent years, semiconductor manufacturing apparatuses have adopted single-wafer processing chambers for processing wafers one by one in order to improve uniformity within the wafer surface. In many cases, such a semiconductor manufacturing apparatus includes a plurality of processing chambers and performs the same processing in parallel to improve processing throughput. When wafers are processed through a plurality of semiconductor manufacturing apparatuses having a plurality of such single wafer processing chambers, the processing paths are different even for wafers processed under the same process flow and processing conditions. A situation occurs. When there are a plurality of processing paths as described above, the in-plane uniformity of the wafer after the processing is completed depends on the processing path, that is, the combination of processing chambers passing through the wafer. Therefore, it is difficult to further increase the uniformity within the wafer surface unless a semiconductor device is produced in consideration of such processing path dependency.

  The present invention has been proposed in view of the above-described conventional problems, and carries in a plurality of processing chambers for performing the first processing and a wafer for which the first processing has been completed in any of the processing chambers. An object of the present invention is to provide a semiconductor manufacturing system and a semiconductor manufacturing apparatus control method capable of reducing the variation in the wafer surface and improving the manufacturing yield in a semiconductor manufacturing line including a plurality of processing chambers for performing the processing of 2. .

  In order to achieve the above object, the present invention employs the following technical means. That is, according to the method for controlling a semiconductor manufacturing apparatus according to the present invention, first, a first semiconductor manufacturing apparatus including a plurality of processing chambers each performing a first process and a processing chamber of any of the first semiconductor manufacturing apparatuses. In the second semiconductor manufacturing apparatus including a plurality of processing chambers that carry in the second process different from the first process in which the wafer that has completed the first process is carried in, in the first and second processes, For the wafer that has been processed, the processing results of the first and second processing are acquired in association with the processing path of the wafer. Next, based on the obtained processing result for each processing path, the wafer processing ratio for each processing path is determined for the group of wafers to be processed by the first and second semiconductor manufacturing apparatuses. Then, according to the determined wafer processing ratio for each processing path, the first and second semiconductor manufacturing apparatuses perform processing on the group of wafers to be processed.

  On the other hand, in another aspect, the present invention can provide a semiconductor manufacturing system that realizes the above-described control method. That is, the semiconductor manufacturing system according to the present invention includes a first semiconductor manufacturing apparatus including a plurality of processing chambers each performing the first processing, and the first processing in any of the processing chambers of the first semiconductor manufacturing apparatus. And a second semiconductor manufacturing apparatus including a plurality of processing chambers for carrying out a second process different from the first process. Further, in the first and second semiconductor manufacturing apparatuses, a measuring apparatus that acquires the processing results of the first and second processes in association with the processing paths of the wafers for the wafers for which the first and second processes have been completed. Is provided. The calculation unit determines a wafer processing ratio for each processing path for the group of wafers to be processed by the first and second semiconductor manufacturing apparatuses based on the acquired processing result for each processing path. The instruction unit causes the first and second semiconductor manufacturing apparatuses to perform processing on the group of wafers to be processed according to the determined wafer processing ratio for each processing path.

  Here, as the processing result, any physical quantity indicating the state of processing performed on the wafer by the first and second processing can be used. For example, the processing result can be the distribution (uniformity) in the wafer surface of the processing performed on the wafer by the first and second processing. The processing path means a combination of processing chambers through which the wafer passes.

  According to the present invention, based on the processing path and the processing result associated with the processing path, the wafer processing path and the number of inserted sheets are obtained so that the in-plane uniformity allowed after the processing is obtained for the wafer to be processed. To decide. As a result, variations in the wafer surface can be reduced and the manufacturing yield can be improved.

The block diagram which shows the semiconductor manufacturing system in one Embodiment of this invention The flowchart which shows the processing route determination process in one Embodiment of this invention The figure which shows an example of the processing accuracy table | surface in one Embodiment of this invention. The figure which shows an example of the priority and the process availability judgment table in one Embodiment of this invention The flowchart which shows the process ratio determination process in one Embodiment of this invention. The figure which shows an example of the process ratio table | surface in one Embodiment of this invention. The flowchart which shows the insertion number determination process in one Embodiment of this invention The figure which shows an example of the insertion number table | surface in one Embodiment of this invention. The figure which shows an example of the state table after a process in one Embodiment of this invention The flowchart which shows the process precision table update process in one Embodiment of this invention

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing a semiconductor manufacturing system according to an embodiment of the present invention. The semiconductor manufacturing system 100 includes a management device 1 such as a host computer or MES (Manufacturing Execution System) for managing production in the semiconductor manufacturing line 110, and a route determination device 2. A plurality of semiconductor manufacturing apparatuses belong to the semiconductor manufacturing line 110. In FIG. 1, only the first semiconductor manufacturing apparatus 3, the second semiconductor manufacturing apparatus 4, and the measuring apparatus 5 among the plurality of semiconductor manufacturing apparatuses are illustrated. The management device 1, the route determination device 2, the first semiconductor manufacturing device 3, the second semiconductor manufacturing device 4, and the measuring device 5 are connected via a network line 6 and can send and receive data to and from each other. It is configured.

  As shown in FIG. 1, the first semiconductor manufacturing apparatus 3 includes a plurality of single-wafer processing chambers (here, processing chambers 31 and 32), and each processing chamber is designated by the management apparatus 1 or the like. The process is executed for the input lot. In the example of FIG. 1, the processing chambers 31 and 32 have, for example, the same structure (same specifications), and both the processing chambers 31 and 32 have the ability to execute the specified processing in the same manner. ing. Note that the wafers are carried into and out of the processing chambers 31 and 32 and the processing in the processing chambers 31 and 32 are performed based on instructions from the apparatus control unit 35 provided in the first semiconductor manufacturing apparatus 3.

  Similarly, the second semiconductor manufacturing apparatus 4 includes a plurality of single-wafer processing chambers (in this case, the processing chambers 41, 42, and 43), and the processing designated by the management device 1 or the like is performed in each processing chamber. Execute for the input lot. In the example of FIG. 1, the processing chambers 41, 42, and 43 have, for example, the same structure (same specifications), and any of the processing chambers 41 to 43 has the ability to execute the specified processing in the same manner. Have. Note that the wafers are carried into and out of the process chambers 41 to 43 and the processes in the process chambers 41 to 43 are performed based on instructions from the apparatus control unit 45 provided in the second semiconductor manufacturing apparatus 4.

  The measurement apparatus 5 is configured to process each wafer processed in any one of the processing chambers 41, 42, and 43 of the semiconductor manufacturing apparatus 4 after being processed in any of the processing chambers 31 and 32 of the first semiconductor manufacturing apparatus 3. The processing result (processing accuracy) by the semiconductor manufacturing apparatuses 3 and 4 is measured.

  In the present embodiment, the first semiconductor manufacturing apparatus 3 performs film formation on the wafer in each of the processing chambers 31 and 32, for example. In addition, the second semiconductor manufacturing apparatus 4 planarizes the film formed on the wafer in each of the processing chambers 41 to 43. In this case, the measuring device 5 is, for example, an optical film thickness measuring device. That is, the measuring device 5 is deposited in any one of the processing chambers 31 and 32 of the first semiconductor manufacturing apparatus 3 and then flat in any of the processing chambers 41, 42 and 43 of the second semiconductor manufacturing apparatus 4. The film thickness which is the processing result of the converted wafer is measured.

  On the other hand, the route determination device 2 includes a data acquisition unit 21, a storage unit 22, a selection unit 23, a calculation unit 24, and an instruction unit 25. The data acquisition unit 21 acquires data in which the processing result acquired by the measurement device 5 is associated with the processing path of the wafer from which the processing result is measured.

  Here, as long as the processing result is information indicating the processing accuracy of processing by the first semiconductor manufacturing apparatus 3 and the second semiconductor manufacturing apparatus 4, any physical quantity can be used. The processing path refers to a combination of a processing chamber used for processing in the first semiconductor manufacturing apparatus 3 and a processing chamber used for processing in the second semiconductor manufacturing apparatus 4, and the first and second semiconductor manufacturing processes. One processing path is determined for each wafer processed in the apparatuses 3 and 4. In the present embodiment, the first semiconductor manufacturing apparatus 3 has two processing chambers 31 and 32, and the second semiconductor manufacturing apparatus 4 has three processing chambers 41 to 43. There is a processing path. Hereinafter, “Pjk” is used as a code indicating the processing path. Here, j = 1 when the processing is performed in the processing chamber 31 of the first semiconductor manufacturing apparatus 3, and j = 2 when the processing is performed in the processing chamber 32. Further, k = 1 when processed in the processing chamber 41 of the second semiconductor manufacturing apparatus 4, k = 2 when processed in the processing chamber 42, and k when processed in the processing chamber 43. = 3.

  Although not particularly limited, the measurement device 5 may associate the processing result acquired by the measurement device 5 with the wafer processing path from which the processing result is measured. You may go. In the former case, for example, when the measurement device 5 measures a processing result, information on the processing path of the measurement target wafer is acquired from the management device 1 and the association is performed. In the latter case, for example, when the measurement device 5 measures the processing result, the wafer ID for specifying the wafer and the measurement result are associated with each other and output to the management device 1 or the like, and the data acquisition unit 21 manages them. Information on the processing path of the wafer specified by the measurement result and the wafer ID is acquired from the apparatus 1 and the association is performed. The data acquisition unit 21 stores the acquired data in the storage unit 22. The selection unit 23, the calculation unit 24, and the instruction unit 25 will be described in detail below.

  The semiconductor manufacturing system 100 having the above-described configuration determines a processing path of a wafer group to be processed (hereinafter referred to as a processing scheduled lot) in the first and second semiconductor manufacturing apparatuses 3 and 4 according to the following procedure. FIG. 2 is a flowchart showing processing route determination processing in the present embodiment. The processing is performed, for example, at a timing when an instruction to carry a processing-scheduled lot into the first semiconductor manufacturing apparatus 3 is output from the management apparatus 1 to the manufacturing line 110 in the first and second semiconductor manufacturing apparatuses 3 and 4. Executed.

  As shown in FIG. 2, when the route determination device 2 starts the processing route determination processing, the data obtained by associating the processing result acquired by the measurement device 5 with the processing route of the wafer from which the processing result is measured is stored as data. Acquired by the collection unit 21. The data collection unit 21 creates the machining accuracy table 300 based on the obtained machining accuracy information for each processing path Pjk, and stores it in the storage unit 22 (step S201).

  FIG. 3 is a diagram illustrating an example of the processing accuracy table 300. As shown in FIG. 3, the machining accuracy table 300 is a table that records the processing path Pjk and the machining accuracy in association with each other. In the example of FIG. 3, in-plane uniformity of the processing result on the wafer that has been processed in the first semiconductor manufacturing apparatus 3 and the second semiconductor manufacturing apparatus 4 is adopted as the processing accuracy. That is, after a film is formed in one of the processing chambers 31 and 32 included in the first semiconductor manufacturing apparatus 3, the film is planarized (polished) in any one of the processing chambers 41 to 43 included in the second semiconductor manufacturing apparatus 4. ), The variation in film thickness (uniformity) within the wafer surface of the film formed on the wafer is regarded as the processing accuracy. Uniformity can be expressed by film thickness dispersion, standard deviation, or range (difference between maximum value and minimum value) acquired at a plurality of points on the wafer. In this embodiment, based on the film thickness measured at a plurality of points in the surface of each wafer, the value calculated by the range of the film thickness measurement value / (average value of the film thickness measurement value × 2) × 100 is uniform. It is defined as sex (%). When the film formed in the first semiconductor manufacturing apparatus 3 is an insulating film, the film thickness of the insulating film can be measured by an optical film thickness measuring instrument that is the measuring apparatus 5. Such a film thickness may be directly measured from the area of the product chip formed on the wafer, and the film thickness included in PCM (Process Control Monitor) patterns arranged at a plurality of points on the wafer. You may measure from the pattern for a measurement.

  Next, the data collection unit 21 that has stored the data in the storage unit 22 notifies the selection unit 23 accordingly. The selecting unit 23 that has received the notification gives priority to each processing path Pjk based on the machining accuracy recorded in the machining accuracy table 300 (step S202). FIG. 4 is a diagram showing a priority / processability determination table 400 in which the assigned priority is recorded. As illustrated in FIG. 4, the priority / processability determination table 400 is a table that records the processing path Pjk, the priority, and a processability determination result described later in association with each other, and is stored in the storage unit 22. In FIG. 4, the processing accuracy is recorded in the table for easy understanding, but the item is not an essential item in the priority / processability determination table 400. As shown in FIG. 4, in the present embodiment, a small ordinal number (1, 2, 3,...) Is assigned as a priority in order from a processing path with high processing accuracy (a processing path with a small uniformity value). ing. Therefore, the smaller the priority number, the higher the priority. In the example of FIGS. 3 and 4, the uniformity of the processing path P21 is the best “2%”, so the priority is “1”. Further, since the uniformity of the processing paths P11 and P23 is next good, the priority is “2”. The processing path P12 has the worst uniformity of “15%”, so the priority is “6”.

  Subsequently, the selecting unit 23 selects a processing path Pjk that can process the scheduled processing lot (step S203). The processing path that can be processed is a processing path for obtaining in-plane uniformity that is allowed after the processing by the first and second semiconductor manufacturing apparatuses 3 and 4 for each wafer belonging to the processing scheduled lot. It is derived on the basis of the value of the in-plane uniformity of the wafer that is allowed later, or the priority. For example, if the condition that the in-plane uniformity of the wafer allowed after processing by the first and second semiconductor manufacturing apparatuses 3 and 4 is 10% or less is set, the processing path P12 cannot satisfy the condition. . Therefore, the selection unit 23 determines that the processing path P12 cannot be processed. In this case, the processing paths P11, P13, P21, P22, and P23 are selected as processable processing paths. Further, for example, the processing is performed only in the processing path Pjk having a wafer in-plane uniformity of 10% or less and a priority of 3 or less that is allowed after the processing by the first and second semiconductor manufacturing apparatuses 3 and 4. If the conditions are set, the processing paths P12, P13, and P22 cannot satisfy the conditions, and therefore the selection unit 23 determines that the processing paths P12, P13, and P22 cannot be processed. In this case, the processing paths P11, P21, and P23 are selected as processing paths that can be processed. Although not particularly limited, in the present embodiment, conditions such as in-plane uniformity of the wafer that are allowed after processing are registered in advance in the management apparatus 1 for each scheduled processing lot, and the selection unit 23 acquires data. The configuration is obtained from the management apparatus 1 via the unit 21.

  The selection unit 23 records the selection result as described above in the priority / processability determination table 400 as a processability determination result. FIG. 4 shows a case where it is determined that only the processing path P12 cannot be processed.

  The selection unit 23 that has recorded the selection result in the priority / processability determination table 400 as described above notifies the calculation unit 24 to that effect. The computing unit 24 that has received the notification determines the wafer processing ratio for each selected processing path based on the selection result (step S204). The wafer processing ratio is a ratio of wafers put into the processing path among all wafers belonging to the processing scheduled lot.

  FIG. 5 is a flowchart showing the processing ratio determination process executed by the calculation unit 24. The computing unit 24 that has started the processing ratio determination process first extracts a processing route that can be processed from the priority / processing availability determination table 400 stored in the storage unit 22 based on the processing availability determination result (step S501). ). Then, the uniformity (machining accuracy) is read from the machining accuracy table 300 for the processable processing path, and the uniformity sum S is calculated (step S502). In the example of FIGS. 3 and 4, the calculation unit 24 calculates the total sum S = 25 of the uniformity of the five processing paths P11, P13, P21, P22, and P23 excluding the processing path P12.

  Next, the computing unit 24 calculates a wafer processing amount for each processing path extracted as a process path that can be processed (step S503). Here, the wafer processing amount is a value obtained by dividing the calculated sum S of uniformity by the uniformity value of each processing path Pjk. For example, for the processing path P11, the wafer processing amount is calculated as 25/3 = 8.3. The wafer processing amount is calculated for all the extracted processing paths that can be processed (No in steps S504 and S503). In this embodiment, the wafer throughput is a value obtained by normalizing the reciprocal of uniformity by the sum S of uniformity. Therefore, a larger wafer processing amount is calculated for a processing path with higher uniformity, and a smaller wafer processing amount is calculated for a processing path with lower uniformity.

  The computing unit 24 that has calculated the wafer processing amount for all the processing paths next calculates the sum S2 of the wafer processing amounts for the processing paths that can be processed (Yes in steps S504 and S505). In the above example, the calculation unit 24 calculates the sum S2 = 35 of the wafer processing amounts of the five processing paths P11, P13, P21, P22, and P23 excluding the processing path P12.

  Subsequently, the computing unit 24 calculates a wafer processing ratio for each extracted processing path (step S506). As described above, the wafer processing ratio is the ratio of the wafer processing amount of each processing path Pjk to the calculated total amount S2 of wafer processing. For example, for the processing path P11, the wafer processing ratio is calculated as 8.3 / 35 = 0.24 (= 24%). The computing unit 24 calculates the wafer processing ratio for all the extracted processing paths that can be processed (No in steps S507 and S506). In addition, the computing unit 24 that has completed the calculation of the wafer processing ratio for all the processing paths that can be processed ends the processing ratio determination process (Yes in step S507).

  In the present embodiment, the calculation unit 24 records the wafer processing amount and wafer processing ratio calculated as described above in the storage unit 22 as the processing ratio table 600. FIG. 6 is a diagram illustrating an example of the processing ratio table 600. As shown in FIG. 6, the processing ratio table 600 is a table for recording each processing path Pjk in association with the wafer processing amount and the wafer processing ratio. In the example of FIG. 6, the calculation unit 24 records “0” as the wafer processing ratio of the unprocessable processing path (here, the processing path P12). In FIG. 6, the processing accuracy is shown in the table for easy understanding, but this item is not an essential item in the processing ratio table 600.

  The arithmetic unit 24 that has calculated the wafer processing ratio for each processing path as described above notifies the instruction unit 25 to that effect. The instruction unit 25 that has received the notification causes the first semiconductor manufacturing apparatus 3 and the second semiconductor manufacturing apparatus to perform the process for the scheduled processing lot according to the calculated wafer processing ratio (step S205). In the present embodiment, the instruction unit 25 that has received the notification from the calculation unit 24 first determines the number of wafers to be input for each processing path according to the wafer processing ratio calculated by the calculation unit 24. FIG. 7 is a flowchart showing the number-of-insertions determination process executed by the instruction unit 25. The instruction unit 25 that has started the inserted number determination process acquires the number of wafers belonging to the scheduled processing lot (step S701). Although not particularly limited, in the present embodiment, the instruction unit 25 is configured to acquire the information from the management device 1. In this example, it is assumed that the number of wafers in the processing scheduled lot is 12.

  Next, the instruction unit 25 integrates the acquired number of wafers and the wafer processing ratio of each processing path Pjk that can be processed, which is recorded in the processing ratio table 600 stored in the storage unit 22. The number of wafers to be input to Pjk is determined (step S702). For example, for the processing path P11, the instruction unit 25 calculates 0.24 × 12 = 3 wafers as the number of wafers input. The instruction unit 25 performs the calculation of the number of inserted wafers for all the processing paths that can be processed (No in steps S703 and S704). In addition, the instruction unit 25 that has completed the calculation of the number of inserted wafers for all of the processable processing paths ends the inserted number determination process (Yes in step S703). As described above, in the present embodiment, “0” is recorded as the wafer processing ratio of unprocessable processing paths in the processing ratio table 600. Therefore, the wafer processing ratios of all the processing paths and the processing schedule are recorded. By adding up the number of wafers in the lot, the number of wafers input for a process path that can be processed can be calculated.

  In the present embodiment, the instruction unit 25 holds the number of inserted wafers calculated as described above as the input number table 800. FIG. 8 is a diagram showing an example of the input number table 800 (when the number of wafers in a scheduled processing lot is 12). As shown in FIG. 8, the input number table 800 is a table that records each processing path Pjk and the number of wafer input in association with each other with respect to the planned input lot. In FIG. 8, the processing accuracy, the wafer processing amount, and the wafer processing ratio are shown in the table for easy understanding, but these items are not essential items in the input number table 800.

  The instruction unit 25 that has determined the number of wafers input for each processing path as described above causes the first semiconductor manufacturing apparatus 3 and the second semiconductor manufacturing apparatus to perform processing in accordance with the number of wafers input (step S205). In the present embodiment, the instruction unit 25 notifies the management apparatus 1 of the determined number of inserted wafers for each processing path. Upon receiving the notification, the management apparatus 1 determines the transfer path of each wafer belonging to the scheduled lot based on the notified information, and the apparatus control unit 35 of the first semiconductor manufacturing apparatus 3 and the second semiconductor manufacturing The apparatus control unit 45 of the apparatus 4 is instructed to execute processing along the conveyance path.

  The instruction unit 25 may directly instruct the device control unit 35 of the first semiconductor manufacturing apparatus 3 and the device control unit 45 of the second semiconductor manufacturing apparatus 4. In this case, the instruction unit 25 first instructs the apparatus control unit 35 of the first semiconductor manufacturing apparatus 3 as to the number of wafers to be processed in the processing chamber 31 and the number of wafers to be processed in the processing chamber 32. In the example of FIG. 8, the sum of the number of inserted processing paths P <b> 11 and the number of inserted processing paths P <b> 13 is the number of wafers to be processed in the processing chamber 31. Similarly, the sum of the number of input of the processing path P21, the number of input of the processing path P22, and the number of input of the processing path P23 is the number of wafers to be processed in the processing chamber 32. In addition, the instruction unit 25 should process each of the processing chambers 41 to 43 out of the wafers processed in the processing chamber 31 of the first semiconductor manufacturing apparatus 3 to the apparatus control unit 45 of the second semiconductor manufacturing apparatus 4. The number of wafers and the number of wafers to be processed in each of the processing chambers 41 to 43 among the wafers processed in the processing chamber 32 of the first semiconductor manufacturing apparatus 3 are indicated. In the example of FIG. 8, among the four wafers processed in the processing chamber 31, the number of wafers to be processed in the processing chamber 41 is three, the number of wafers to be processed in the processing chamber 42 is zero, and the processing chamber 43 is processed. The number of wafers to be used is one. Of the nine wafers processed in the processing chamber 32, the number of wafers to be processed in the processing chamber 41 is four, the number of wafers to be processed in the processing chamber 42 is one, and the number of wafers to be processed in the processing chamber 43. Is three. In response to the instruction as described above, the apparatus control units 35 and 45 perform wafer processing according to the instruction.

  As described above, when the processing in the first and second semiconductor manufacturing apparatuses 3 and 4 is completed, the wafer group is loaded into the measuring device 5, the processing result (processing accuracy) is measured, and the processing is completed ( Step S206).

  Note that when a new processing result is measured by the measuring device 5, the machining accuracy table 300 is updated with the new processing result when the data acquisition unit 21 acquires data thereafter. Hereinafter, the update process will be briefly described.

  For example, when the measuring device 5 is configured to associate the processing result with the wafer processing path, the measuring device 5 measures the measured processing result in a storage unit (not shown) included in the measuring device 5. Record in correspondence with the wafer processing path. FIG. 9 is a diagram illustrating an example of the post-processing state table 900 recorded by the measuring device 5. As shown in FIG. 9, the post-processing state table 900 is a table that records each processing path Pjk, processing result (processing accuracy), and information indicating the processing order of the wafer in association with each other. In FIG. 9, the processing completion order within the lot is shown as information indicating the processing order of the wafers. However, for example, arbitrary data that can indicate the processing order such as a time stamp can be adopted. On the other hand, when the data acquisition unit 21 is configured to associate the processing result with the wafer processing path, the post-processing state table 900 is created in the data acquisition unit 21. Note that the post-processing state table 900 illustrated in FIG. 9 shows a state in which a sorting process described later has been performed.

  The data acquisition unit 21 updates the processing accuracy table 300 based on the post-processing state table 900 when acquiring the above-described data. FIG. 10 is a flowchart showing the machining accuracy table update processing in the present embodiment. First, the data acquisition unit 21 sorts the post-processing state table 900 in the processing order (here, ascending order) (step S1001). Then, the data acquisition unit 21 extracts the latest machining accuracy data for each processing path from the post-machining state table 900. In the example of FIG. 9, since the data is sorted in ascending order, the lower data in the table becomes newer data. The data acquisition unit 21 that has extracted the latest machining accuracy data records the data in association with the corresponding processing path in the machining accuracy table 300 (S1002). The data acquisition unit 21 updates the machining accuracy for all the processing paths in the machining accuracy table 300 (steps S1003 No and S1002). In addition, the data acquisition unit 21 that has completed the processing accuracy update for all of the processing paths ends the processing accuracy table update processing (Yes in step S1003).

  The machining accuracy table update process may be performed every time a new process result is acquired in the measurement device 5. In this case, since the latest machining accuracy data is always recorded in the machining accuracy table 300, step S201 in FIG. 2 is omitted.

  In addition, the data acquisition unit 21, the selection unit 23, the calculation unit 24, the instruction unit 25, and the like described above are, for example, a dedicated calculation circuit or a processor and a memory such as a RAM (Random Access Memory) and a ROM (Read Only Memory). And software stored in the memory and operating on the processor. The storage unit 22 can be realized by a storage device such as an HDD (Hard Disk Drive). Furthermore, the above-described processes can also be realized as software (programs).

  As described above, according to the present invention, in two or more continuous processes in a semiconductor production line, it is possible to select a processing path that suppresses occurrence of in-plane variation and execute the process with high accuracy. Processing and manufacturing yield can be improved. Further, in the present invention, since only the measurement result after the completion of processing is used without using the processing conditions of the semiconductor manufacturing device and the parameter values at the time of processing, any semiconductor manufacturing device can be applied. In addition, since the processing accuracy of the latest processing path can be obtained from the measurement result of the processed wafer at any time, it is not necessary to flow the evaluation wafer before processing the product wafer. Furthermore, since only the final results of two or more consecutive processes are referred to, it is possible to omit the equipment evaluation in a single unit after each semiconductor manufacturing process.

  The present invention is not limited to the embodiment described above, and various modifications and applications are possible without departing from the technical idea of the present invention. For example, in the above embodiment, the data acquisition unit 21, the storage unit 22, the selection unit 23, the calculation unit 24, and the instruction unit 25 constitute a route determination device, but these units are arranged in the management device 1. Of course, the same effect can be obtained even if they are distributed in a semiconductor manufacturing apparatus or the like. Moreover, in the said embodiment, although it has the structure which has arrange | positioned the single measuring device, even if the said measuring device is incorporated in the semiconductor manufacturing apparatus etc., there is no problem.

  In the above-described embodiment, an example in which each semiconductor manufacturing apparatus has a plurality of processing chambers for performing the same processing has been described. For example, each semiconductor manufacturing apparatus has a plurality of semiconductors for performing the same processing. You may be comprised from the manufacturing apparatus. For example, when the same processing is performed in a plurality of semiconductor manufacturing apparatuses having a single processing chamber, the plurality of semiconductor manufacturing apparatuses are regarded as one semiconductor manufacturing apparatus in the above-described embodiment, The invention can be applied.

  In addition, when there are a plurality of recipe combinations for the processing conditions of the first and second processes, each of the above-described tables may be created for each recipe type. These tables may be used.

  Furthermore, the first semiconductor manufacturing apparatus of the above embodiment is a lithography apparatus that forms a resist pattern on a wafer in each processing chamber, and the second semiconductor manufacturing apparatus performs an etching apparatus that performs pattern etching in each processing chamber. Even with other device combinations such as the above, similar effects can be obtained.

  INDUSTRIAL APPLICABILITY The present invention can reduce variations in the wafer surface and improve the manufacturing yield, and is useful as a semiconductor manufacturing system and a method for controlling a semiconductor manufacturing apparatus.

DESCRIPTION OF SYMBOLS 1 Management apparatus 2 Path | route determination apparatus 3 1st semiconductor manufacturing apparatus 4 2nd semiconductor manufacturing apparatus 5 Measurement apparatus 6 Network line 21 Data acquisition part 22 Storage part 23 Selection part 24 Calculation part 25 Instruction part 31, 32 Processing chamber 35, 45 Device control unit 41, 42, 43 Processing chamber 100 Semiconductor manufacturing system 110 Semiconductor manufacturing line

Claims (2)

A first semiconductor manufacturing apparatus having a plurality of processing chambers for performing each of the first processes, and a wafer that has been subjected to the first processing in any of the processing chambers of the first semiconductor manufacturing apparatus, are loaded into the first semiconductor manufacturing apparatus. And a second semiconductor manufacturing apparatus including a plurality of processing chambers for performing a second process different from the first process, and the first and second processes for a wafer for which the first and second processes have been completed. A process of acquiring the processing result according to the processing path of the wafer,
Determining a wafer processing ratio for each processing path for a group of wafers to be processed by the first and second semiconductor manufacturing apparatuses based on the acquired processing results for each processing path;
In the first and second semiconductor manufacturing apparatuses, according to the determined wafer processing ratio for each processing path, a process for performing processing on the group of wafers to be processed;
A method for controlling a semiconductor manufacturing apparatus, comprising: A first semiconductor manufacturing apparatus comprising a plurality of processing chambers each for performing a first process;
A second process chamber is provided with a plurality of process chambers each carrying a second process different from the first process into which a wafer having been subjected to the first process is loaded in any one of the process chambers of the first semiconductor manufacturing apparatus. Semiconductor manufacturing equipment,
In the first and second semiconductor manufacturing apparatuses, for the wafers for which the first and second processes have been completed, measurement results obtained by associating the processing results of the first and second processes with the processing paths of the wafers. Equipment,
Based on the acquired processing result for each processing path, a calculation unit that determines a wafer processing ratio for each processing path for a group of wafers scheduled to be processed by the first and second semiconductor manufacturing apparatuses;
In accordance with the determined wafer processing ratio for each processing path, in the first and second semiconductor manufacturing apparatuses, an instruction unit that performs processing on the group of wafers to be processed,
A semiconductor manufacturing system comprising:

Images