JP2010534888A5 - - Google Patents

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Publication number
JP2010534888A5
JP2010534888A5 JP2010518384A JP2010518384A JP2010534888A5 JP 2010534888 A5 JP2010534888 A5 JP 2010534888A5 JP 2010518384 A JP2010518384 A JP 2010518384A JP 2010518384 A JP2010518384 A JP 2010518384A JP 2010534888 A5 JP2010534888 A5 JP 2010534888A5
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JP
Japan
Prior art keywords
module
data
processing lanes
processing
high integrity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010518384A
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English (en)
Japanese (ja)
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JP2010534888A (ja
JP5436422B2 (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/US2008/071023 external-priority patent/WO2009015276A2/en
Publication of JP2010534888A publication Critical patent/JP2010534888A/ja
Publication of JP2010534888A5 publication Critical patent/JP2010534888A5/ja
Application granted granted Critical
Publication of JP5436422B2 publication Critical patent/JP5436422B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010518384A 2007-07-24 2008-07-24 高インテグリティと高可用性のコンピュータ処理モジュール Expired - Fee Related JP5436422B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US93504407P 2007-07-24 2007-07-24
US60/935,044 2007-07-24
US13871708A 2008-06-13 2008-06-13
US12/138,717 2008-06-13
PCT/US2008/071023 WO2009015276A2 (en) 2007-07-24 2008-07-24 High integrity and high availability computer processing module

Publications (3)

Publication Number Publication Date
JP2010534888A JP2010534888A (ja) 2010-11-11
JP2010534888A5 true JP2010534888A5 (enrdf_load_stackoverflow) 2013-03-28
JP5436422B2 JP5436422B2 (ja) 2014-03-05

Family

ID=40149643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010518384A Expired - Fee Related JP5436422B2 (ja) 2007-07-24 2008-07-24 高インテグリティと高可用性のコンピュータ処理モジュール

Country Status (6)

Country Link
EP (1) EP2174221A2 (enrdf_load_stackoverflow)
JP (1) JP5436422B2 (enrdf_load_stackoverflow)
CN (1) CN101861569B (enrdf_load_stackoverflow)
BR (1) BRPI0813077B8 (enrdf_load_stackoverflow)
CA (1) CA2694198C (enrdf_load_stackoverflow)
WO (1) WO2009015276A2 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011078630A1 (de) * 2011-07-05 2013-01-10 Robert Bosch Gmbh Verfahren zum Einrichten einer Anordnung technischer Einheiten
US8924780B2 (en) * 2011-11-10 2014-12-30 Ge Aviation Systems Llc Method of providing high integrity processing
CN104699550B (zh) * 2014-12-05 2017-09-12 中国航空工业集团公司第六三一研究所 一种基于lockstep架构的错误恢复方法
EP3273353B1 (en) * 2015-03-20 2020-07-29 Renesas Electronics Corporation Data processing device
US10599513B2 (en) * 2017-11-21 2020-03-24 The Boeing Company Message synchronization system
US10802932B2 (en) 2017-12-04 2020-10-13 Nxp Usa, Inc. Data processing system having lockstep operation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
JP3123844B2 (ja) * 1992-12-18 2001-01-15 日本電気通信システム株式会社 二重化装置
US6247143B1 (en) * 1998-06-30 2001-06-12 Sun Microsystems, Inc. I/O handling for a multiprocessor computer system
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
EP1398700A1 (de) * 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zur Synchronisation redundanter Verarbeitungseinheiten
US7290169B2 (en) * 2004-04-06 2007-10-30 Hewlett-Packard Development Company, L.P. Core-level processor lockstepping
DE502005006441D1 (de) * 2004-10-25 2009-02-26 Bosch Gmbh Robert Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
CN100392420C (zh) * 2005-03-17 2008-06-04 上海华虹集成电路有限责任公司 非接触式应用芯片的多通道测试仪
US8826288B2 (en) * 2005-04-19 2014-09-02 Hewlett-Packard Development Company, L.P. Computing with both lock-step and free-step processor modes

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