JP2010531543A - HIGH FORWARD CURRENT DIODE AND MANUFACTURING METHOD THEREOF FOR BACKWARD-WRITE 3D CELL - Google Patents

Abstract

  The non-volatile memory element includes at least one memory cell that includes a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode that are in electrical contact with the at least one memory cell. In use, the diode functions as a read / write element for a memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity in response to an applied bias.

Description

  The present invention relates to a nonvolatile memory array.

CROSS-REFERENCE TO RELATED APPLICATIONS its entirety is hereby incorporated by reference, filed on June 25, 2007 U.S. Patent Application Serial No. 11 / 819,078 (Patent Document 1) and the He claims the interest of 11 / 819,079 (Patent Document 2).

  The nonvolatile memory array continues to hold data even when power supply to the element is cut off. In a one-time programmable array, each memory cell is formed in an initial unprogrammed state, which can be changed to a programmed state. This change is permanent and such cells are not erasable. On the other hand, there is another type of memory in which the memory cells can be erased and can be rewritten any number of times.

  There are various cells depending on the number of data states each cell can reach. The data state can be stored by changing a detectable cell characteristic, such as a current flowing through the cell with a predetermined voltage applied or a threshold voltage of a transistor in the cell. The data state is an individual value of a cell such as data “0” or data “1”.

  There are complex methods for obtaining erasable or multi-state cells. For example, the floating gate and the SONOS memory cell operate by accumulating charges, and the transistor threshold voltage changes according to the presence or absence of the accumulated charges. Although these memory cells are three-terminal elements, it is relatively difficult to manufacture and operate the smallest three-terminal elements required to gain competitiveness in modern integrated circuits.

  In addition, there are memory cells that operate by changing the resistivity of relatively new types of materials such as chalcogenides, but chalcogenides are difficult to handle and are considered difficult to manufacture in most semiconductor manufacturing facilities.

  Realizing a non-volatile memory array having erasable memory cells or multi-state memory cells formed using conventional semiconductor materials in an easily miniaturized structure provides significant advantages.

US patent application Ser. No. 11 / 819,078 US patent application Ser. No. 11 / 819,079 US patent application Ser. No. 10 / 955,549 US patent application Ser. No. 11 / 395,995 US patent application Ser. No. 11 / 148,530 US patent application Ser. No. 10 / 954,510 US patent application Ser. No. 10 / 320,470 US patent application Ser. No. 11 / 015,824 US patent application Ser. No. 10 / 883,417 US patent application Ser. No. 10 / 728,436 US patent application Ser. No. 10 / 815,312 US Pat. No. 5,915,167 US patent application Ser. No. 11 / 444,936

The invention is defined by the appended claims, and nothing in this section should be taken as a limitation on those claims.
In one embodiment, a non-volatile memory comprising at least one memory cell comprising a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode in electrical contact with the at least one memory cell An element is provided. In use, the diode functions as a memory cell read / write element by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

  In another embodiment, a non-volatile memory element is provided that includes a plurality of memory cells and a first electrode and a second electrode in electrical contact with the plurality of memory cells. Each memory cell of the plurality of memory cells includes a diode and a metal oxide antifuse dielectric layer provided in series between the first and second electrodes, the diode having a substantially cylindrical shape. Including polycrystalline silicon, germanium or silicon-germanium pin pillar-shaped diodes.

Each of the aspects and embodiments of the invention described herein can be used alone or in combination with other aspects and embodiments.
Preferred aspects and embodiments will now be described with reference to the accompanying drawings.

FIG. 3 is a circuit diagram illustrating the need for electrical shielding between memory cells in a memory array. 1 is a perspective view of a multi-state or rewritable memory cell formed according to one embodiment of the present invention. FIG. FIG. 3 is a perspective view of a portion of a memory level comprising the memory cell of FIG. It is a graph which shows the change of the read current of the memory cell of this invention accompanying the increase in the reverse bias voltage applied to a diode. 6 is a probability plot showing memory cells that are switched from a V state to a P state, from a P state to an R state, and from an R state to an S state. 6 is a probability plot showing memory cells that are switched from a V state to a P state, from a P state to an S state, and from an S state to an R state. 6 is a probability plot showing memory cells that are switched from a V state to an R state, from an R state to an S state, and from an S state to a P state. 1 is a perspective view of a pin diode that may be used in embodiments of the present invention, placed vertically. FIG. It is a probability plot showing a memory cell that is switched from the V state to the P state and from the P state to the M state. 6 is a plot showing the relationship between the applied voltage and the current flowing through the diode in each diode state shown in FIG. 5. 6 is a probability plot showing memory cells that are repeatedly switched from the V state to the P state, from the P state to the R state, from the R state to the S state, and then between the S state and the R state. It is a circuit diagram which shows one bias system which applies a bias to S cell by a forward bias. It is a circuit diagram which shows one bias system which applies a bias to S cell by reverse direction bias. Fig. 5 shows a read-verify-write repeat cycle for moving a cell to one data state. FIG. 6 is a cross-sectional view illustrating a formation step of a memory level formed according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a formation step of a memory level formed according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a formation step of a memory level formed according to an embodiment of the present invention. 1 is a perspective view of a multi-state or rewritable memory cell formed according to one embodiment of the present invention. FIG. 2 is a side cross-sectional view of a multi-state or rewritable memory cell formed according to one embodiment of the present invention. FIG. 3 is a probability plot of various memory cells according to an embodiment of the present invention. 3 is a probability plot of various memory cells according to an embodiment of the present invention. It is a probability plot of the memory cell by a comparative example.

  Conventionally, it is well known that the resistance of a resistor formed of doped polycrystalline silicon, i.e., polysilicon, can be adjusted by applying an electrical pulse to adjust between stable resistance states, and such adjustment in integrated circuits. Possible resistors are used as elements.

  However, it is not yet common to use adjustable polysilicon resistors for storing data states in non-volatile memory cells. There are problems in forming the memory array with polysilicon resistors. When a resistor is used as a memory cell in a large crosspoint array, applying a voltage to a selected cell causes undesirable leakage currents in the half-selected and unselected cells throughout the array. . For example, in FIG. 1, it is assumed that a voltage is applied between the bit line B and the word line A in order to set, reset, or detect the state of the selected cell S. Thereby, it is intended that a current flows through the selected cell S. However, some leakage current may flow through another path, for example, between the bit line B and the word line A through unselected cells U1, U2 and U3. There can be many such alternative paths.

  By forming each memory cell as a two-terminal element including a diode, leakage current can be greatly reduced. The diode has non-linear IV characteristics, and only a small amount of current flows below the rising voltage, and a significantly high current flows above the rising voltage. In general, the diode also functions as a one-way valve that allows current to flow more easily in one direction than in the other direction. Therefore, if the bias method is selected so that only the selected cell receives the forward current exceeding the rising voltage, the leakage current flowing through an unintended path (such as the U1-U2-U3 leakage path in FIG. 1). Can be greatly reduced.

  US patent application Ser. No. 10 / 955,549 entitled “Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States” by Herner et al., Filed Sep. 29, 2004, incorporated herein by reference. (Patent Document 3) describes a monolithic three-dimensional memory array in which a data state of a memory cell is stored in a resistivity state of a polycrystalline semiconductor material of a semiconductor junction diode. This memory cell is a one-time programmable cell having two data states. The diode is formed in a high resistivity state and is permanently changed to a low resistivity state by application of a program voltage.

  The present invention includes a memory element formed of a doped semiconductor material, for example, the semiconductor material of US Pat. There are embodiments that can reach the state. The present invention also has another embodiment in which the semiconductor material is changed from the initial high resistivity state to the low resistivity state and then returned to the high resistivity state by applying an appropriate electric pulse. These embodiments can be used independently or in combination to form a memory cell that has more than one data state and that can be programmed or rewritten only once.

  As described above, by providing the diode between the conductors in the memory cell, it is possible to form the memory cell in the high-density cross-point memory array. In a preferred embodiment of the present invention, either a polycrystalline, amorphous or microcrystalline semiconductor memory element is then formed in series with the diode. Or, more preferably, it is formed as a diode itself.

  In this description, the transition from the high resistivity state to the low resistivity state is referred to as a set transition. A set transition is a transition that is affected by a set current, a set voltage, or a set pulse. On the other hand, the reverse transition from the low resistivity state to the high resistivity state is called a reset transition. A reset transition is a transition that is affected by a reset current, a reset voltage, or a reset pulse.

  As described in more detail below, in a preferred one-time programmable embodiment, a polycrystalline semiconductor diode is paired with a dielectric breakdown antifuse, such as a high dielectric constant material antifuse layer.

  FIG. 2 illustrates a memory cell formed according to a preferred embodiment of the present invention. The lower conductor 12 is made of a conductive material, such as tungsten, and extends in the first direction. The lower conductor 12 may include a shielding layer and an adhesive layer. The polycrystalline semiconductor diode 2 has a lower heavily doped n-type region 4, an intentionally undoped intrinsic region 6, and an upper heavily doped region 8. The direction of the diode may be reversed. Such a diode is called a p-i-n diode regardless of its orientation. A dielectric breakdown antifuse 14 is provided in series with the diode 2. The upper conductor 16 may be formed of the same method and the same material as the lower conductor 12 and extends in a second direction different from the first direction. The polycrystalline semiconductor diode 2 is vertically disposed between the lower conductor 12 and the upper conductor 16. The polycrystalline semiconductor diode 2 is formed in a high resistivity state. The memory cell can be formed on a suitable substrate, such as a single crystal silicon wafer. FIG. 3 shows the memory level of the above-mentioned element formed in a cross-point array in which the diode 2 is arranged between the lower conductor 12 and the upper conductor 16 (the antifuse 14 is omitted in this figure). Some are shown. By stacking multiple memory levels on one substrate, a high density monolithic three-dimensional memory array can be formed.

  In this description, a region of semiconductor material that is not intentionally doped is referred to as an intrinsic region. However, it should be understood by those skilled in the art that in practice the intrinsic region may contain a low concentration of p-type or n-type dopant. The dopant may diffuse from the adjacent region into the intrinsic region. Or, it may be present in the deposition chamber during deposition due to contamination from previous depositions. It should also be understood that the deposited intrinsic semiconductor material (such as silicon) may contain defects and operate as if the semiconductor material was slightly n-doped. Even if the term “intrinsic” is used to describe silicon, germanium, silicon-germanium alloys, or other semiconductor materials, this region does not contain any dopants or such regions are completely electrically It does not mean that it is neutral.

  The resistivity of a doped polycrystalline or microcrystalline semiconductor material, such as silicon, can be changed between stable states by applying appropriate electrical pulses. In the preferred embodiment, the set transition is advantageously performed with the diode under forward bias, while the reset transition is most easily performed and controlled with the diode under reverse bias. It was discovered. However, in some cases, a set transition may occur with the diode under reverse bias, while a reset transition may occur with the diode under forward bias.

  The semiconductor switching operation is complicated. Conventionally, for a single diode, both the set transition and the reset transition occur with the diode under forward bias. Generally, a reset pulse sufficient to switch the polycrystalline semiconductor material comprising the diode from one resistivity state to a higher resistivity state, applied with the diode under forward bias, corresponds to that ( The same polycrystalline semiconductor material is switched from the same resistivity state to a lower resistivity state) and has a lower amplitude and longer pulse width than the set pulse.

  Switching under reverse bias shows a different behavior. Assume that a polycrystalline pin diode as shown in FIG. 2 receives a relatively large switching pulse under reverse bias. After applying the switching pulse, a lower reading pulse of, for example, 2V is applied, and a current called a reading current flowing through the diode with the reading voltage is measured. In subsequent pulses, increasing the switching pulse voltage under reverse bias, the subsequent read current at 2V changes as shown in FIG. Initially, as the reverse voltage and current of the switching pulse are increased, the read current when the read voltage is applied after each switching pulse increases. That is, it should be understood that the initial transition of the semiconductor material (in this case silicon) is in the set direction towards lower resistivity. At position K in FIG. 4, when the switching pulse reaches a certain reverse bias voltage, in this example about -14.6V, a reset occurs and the read current begins to suddenly decrease and the silicon resistivity increases. . The switching voltage at which the setting tendency is reversed and the resetting of the silicon of the diode starts depends on, for example, the resistivity state of the silicon constituting the diode when the application of the reverse bias switching pulse is started. Thus, it should be understood that by selecting an appropriate voltage, it is possible to cause the diode to be either reverse-biased and to set or reset the semiconductor material comprising the diode.

  The individual data states of the memory cells of the embodiments of the present invention correspond to the resistivity states of the polycrystalline or microcrystalline semiconductor material that makes up the diode, which are applied when the read voltage is applied (upper conductor 16 and lower conductor). It is identified by detecting the current flowing in the memory cell (with respect to the conductor 12). The difference in current flowing between any individual data state and any other individual data state is preferably at least twice so that the difference between states can be easily detected.

  This memory cell can be used as a one-time programmable cell or a rewritable memory cell, but also has two, three, four or more individual data states Also good. A cell can switch from any data state to any other data state in any order and with either forward or reverse bias applied. In use, the diode functions as a memory cell read / write element by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

In one embodiment of the present invention, a high dielectric constant (k) antifuse can be used to increase the read current of the programmed diode. These antifuses have been found to increase the programmed read current at a predetermined read voltage, such as a 2V read voltage, by 50% compared to a lower dielectric constant SiO ₂ antifuse. This increases the difference between the programmed state and reset state currents in the reverse write memory cell.

The antifuse is preferably formed of a metal oxide antifuse dielectric layer, such as a layer having a dielectric constant greater than 3.9, such as about 4.5 to about 8. Other dielectric layers having a dielectric constant greater than 3.9 may be used. The metal oxide material may be a stoichiometric or non-stoichiometric material. For example, the metal oxide may be hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium oxide-silicon, aluminum oxide-silicon, hafnium oxide-silicon, hafnium-aluminum, hafnium oxynitride-silicon, It may be selected from one or a combination of two or more of zirconium oxide-silicon-aluminum, hafnium oxide-aluminum-silicon, hafnium oxynitride-aluminum-silicon, or zirconium oxynitride-silicon-aluminum. These _{materials, HfO 2, Al 2 O 3} , ZrO 2, TiO 2, La 2 O 3, Ta 2 O 5, RuO 2, ZrSiO x, AlSiO x, HfSiO x, HfAlO x, HfSiON, ZrSiAlO x, HfSiAlO _x , HfSiAlON and ZrSiAlON chemical formulas, and may be combined with SiO ₂ and / or SiN _x . Hafnium oxide or aluminum oxide is preferred.

  The metal oxide antifuse dielectric layer is preferably provided adjacent to the p-type region of the diode. Desirably, the thickness of the antifuse dielectric layer is from about 10 to about 100 angstroms, such as from about 30 to about 40 angstroms.

  Several preferred embodiments are shown. However, it should be understood that these examples are not intended to be limiting. Those skilled in the art will appreciate that other methods of programming a two-terminal device comprising a diode and a polycrystalline or microcrystalline semiconductor material are within the scope of the present invention.

Multi-level cell programmable only once In a preferred embodiment of the present invention, a diode made of polycrystalline semiconductor material and a breakdown antifuse are provided in series between the upper and lower conductors. This two-terminal element is used as a one-time programmable multi-level cell, and in preferred embodiments has three or four individual data states.

  A preferred memory cell is shown in FIG. The diode 2 is preferably formed of a polycrystalline or microcrystalline semiconductor material such as silicon, germanium, or an alloy of silicon and / or germanium. The diode 2 is most preferably polysilicon. In this example, the lower heavily doped region 4 is n-type and the upper heavily doped region 8 is p-type. However, the polarity of the diode may be reversed. The memory cell includes a part of the upper conductor, a part of the lower conductor, and a diode disposed between the two conductors.

  When formed, the polysilicon of the diode 2 is in a high resistivity state and the dielectric breakdown antifuse 14 has not yet been manipulated. FIG. 5 is a probability plot showing the current of a plurality of memory cells with silicon dioxide antifuse dielectric layers in various states. Referring to FIG. 5, when a read voltage of 2V, for example, is applied between the upper conductor 16 and the lower conductor 12 (with the diode 2 under forward bias), the upper conductor 16 and the lower conductor 12 It is desirable that the read current that flows during the period is in the nanoampere range, for example, less than about 5 nA. Region V on the graph of FIG. 5 corresponds to the first data state of the memory cell. In some memory cells in the array, this cell does not receive a set or reset pulse, and this state is read as the data state of that memory cell. This first data state is called a V state.

  The first electrical pulse is preferably applied between the upper conductor 16 and the lower conductor 12 with the diode 2 under forward bias. This pulse is, for example, about 8V to about 12V, for example, about 10V. The current is, for example, about 80 to about 200 μA. The pulse width is desirably about 100 to about 500 nanoseconds. With this first electric pulse, the dielectric breakdown antifuse 14 is broken down, and the semiconductor material of the diode 2 is switched from the first resistivity state to the second resistivity state where the resistivity is lower than the first resistivity state. It is done. This second data state is referred to as a P state, and this transition is indicated as “V → P” in FIG. The current flowing between the upper conductor 16 and the lower conductor 12 at a read voltage of 2 V is about 10 μA or more. The resistivity of the semiconductor material constituting the diode 2 is reduced to about 1/1000 to about 1/2000. In another embodiment, the change in resistivity is made smaller, but the change between any data state and any other data state is preferably at least 2 times, preferably at least 3 times or 5 times, More typically, it is desirable to be 100 times or more. Some of the memory cells in the array are read in this data state and do not receive any further set or reset pulses. This second data state is called a P state.

For example, the read current at 2V may increase from 1 × 10 ⁻⁸ A in the unprogrammed state to at least 1 × 10 ⁻⁵ A after application of the program pulse. The table below shows that the read current increases with increasing program voltage. The last column of the table shows the standard deviation of the read current.

Program After program
Read current 1σ at pulse voltage + 2V
+ 6.4V 1.1 × 10 ⁻⁵ A 6.1 × 10 ⁻⁶ A
+ 7.4V 1.7 × 10 ⁻⁵ A 7.2 × 10 ⁻⁶ A
+ 8.4V 1.8 × 10 ⁻⁵ A 5.4 × 10 ⁻⁶ A

It should be noted that the read current shown in the table above is that of the cell with wiring and silicon oxide antifuse shown in FIG. When the wiring is excluded and a metal oxide antifuse is used, the read current is further increased. For example, at a program voltage of 8.4 V, the read current of a cell without wiring is at least 3.5 × 10 ⁻⁵ A with a read voltage of at least +1.5 V such as +1.5 to +2 V. If the program voltage is further increased, the read current is expected to increase further. For example, if the program voltage is increased from 8.4 V to 10 V, the read current increases by about 70%, and the read current at a read voltage of 2 V of a cell without wiring becomes about 6 × 10 ⁻⁵ A. is expected. As described above, a large number of program pulses such as 2 to 10 pulses, for example, 3 to 5 pulses may be applied to the diode. Furthermore, the read current is further increased by using a metal oxide antifuse dielectric layer, as described below with respect to FIGS. 17a-17c.

  A second electrical pulse is preferably applied between the upper conductor 16 and the lower conductor 12 with the diode 2 under reverse bias. This pulse is, for example, about −8V to about −14V, preferably about −10 to about −12V, and preferably about −11V. The current is, for example, about 80 to about 200 μA. The pulse width is, for example, about 100 nanoseconds to about 10 microseconds, preferably about 100 nanoseconds to about 1 microsecond, and most preferably about 200 to about 800 nanoseconds. The second electrical pulse switches the semiconductor material of the diode 2 from the second resistivity state to a third resistivity state having a higher resistivity than the second resistivity state. The current flowing between the upper conductor 16 and the lower conductor 12 at a read voltage of 2V is about 10 to about 500 nA, and preferably about 100 to about 500 nA. Some of the memory cells in the array are read in this data state and do not receive any further set or reset pulses. This third data state is called an R state, and this transition is displayed as “P → R” in FIG.

  FIG. 10 is a plot showing the read current against the read voltage for each diode state shown in FIG. The diode initially begins to operate from a low read current state V (referred to as an unprogrammed or “unused” state). The diode is changed to the programmed state P by a high forward bias pulse. It is desirable to make this change at a diode manufacturing plant that does not have power problems before being sold as a product. Once sold as a product, the diode is then changed to the reset state R by a reverse bias program pulse. The difference between the read currents in the programmed state P and the reset state R forms a “window” of the memory cell, as shown in FIG. To avoid being affected by product quality variations, this window can be made as large as possible by applying high program voltages and / or multiple program pulses.

  In order to achieve the fourth data state, a third electrical pulse is applied between the upper conductor 16 and the lower conductor 12, preferably with the diode 2 under forward bias. This pulse is, for example, about 8V to about 12V, for example about 10V, and the flowing current is about 5 to about 20 μA. The third electrical pulse causes the semiconductor material of the diode 2 to have a resistivity lower than that of the third resistivity state from the third resistivity state, and preferably higher than that of the second resistivity state. 4 to the resistivity state. The current flowing between the upper conductor 16 and the lower conductor 12 at a read voltage of 2 V is about 1.5 to about 4.5 μA. Some of the memory cells in the array are read in this data state. This data state is referred to as a set state S, and this transition is indicated as “R → S” in FIG.

  Desirably, the difference in current at the read voltage (eg, 2V) is at least twice between any two adjacent data states. For example, it is desirable that the read current of any cell in data state R is at least twice the read current of any cell in data state V. Desirably, the read current of any cell in data state S is at least twice the read current of any cell in data state R. Desirably, the read current of any cell in data state P is at least twice the read current of any cell in data state S. For example, the read current in data state R may be twice the read current in data state V. The read current in data state S may be twice the read current in data state R. The read current in data state P may be twice the read current in data state S. If the range is defined smaller, the difference in read current can be greatly increased. For example, if the read current of a cell in which the highest current in that state flows in the V state is 5 nA and the read current of the cell in which the lowest current flows in the R state is 100 nA, the current difference is at least 20 times. Become. Selecting a different boundary ensures that the read current difference between adjacent memory states is at least tripled.

  A read-verify-write process to ensure that the memory cell is switched to one of the defined data states and not between the data states after application of a set or reset pulse, as described below. May be repeated.

  Up to this point, the difference between the highest current in one data state and the lowest current in the next higher adjacent data state has been described, but the read current difference is even greater in most cells in the adjacent data state. For example, the read current of the memory cell in the V state may be 1 nA. The read current of the cell in the R state may be 100 nA. The read current of the cell in the S state may be 2 μA (2,000 nA). The read current of the cell in the P state may be 20 μA. These currents in each adjacent state are more than 10 times different.

  Although a memory cell having four individual data states has been described, it may be desirable to select three data states rather than four to facilitate discrimination between data states. For example, a tri-state memory cell can be formed in data state V, set to data state P, and reset to data state R. This cell does not have the fourth data state S. In this case, the difference between adjacent data states, eg, between the R and P data states, can be greatly increased.

  A one-time programmable memory array of memory cells as described above can be programmed as described above, each of which (in one embodiment) one of three individual data states, or (in another embodiment). ) Programmed into one of four individual data states. Obviously, these are only examples, and there may be examples with more than three or more than four individual resistivity states and corresponding data states.

  On the other hand, in a memory array of memory cells that can be programmed only once, the cells can be programmed in various ways. For example, referring to FIG. 6, the memory cell of FIG. 2 may be formed in a first state of V state. A first electrical pulse, preferably under forward bias, causes the antifuse 14 to break down, and the diode polysilicon has a second resistivity lower than the first resistivity state from the first resistivity state. Switch to resistivity state. This causes the memory cell to transition to the P state having the lowest resistivity in this example. Preferably, under reverse bias, the second electrical pulse switches the polysilicon of the diode from the second resistivity state to a third resistivity state where the resistivity is higher than the second resistivity state. As a result, the memory cell transitions to the S state. Similarly, under reverse bias, the third electrical pulse switches the diode polysilicon from the third resistivity state to the fourth resistivity state. The fourth resistivity state has a higher resistivity than the third resistivity state. As a result, the memory cell transitions to the R state. For any memory cell, any data state of the V state, R state, S state and P state can be read as the data state of that memory cell. Each transition is displayed in FIG. Although four individual data states are shown, the number of states can be three or more than four as desired.

  In yet another embodiment, each successive electrical pulse can continuously switch the semiconductor material of the diode to a low resistivity state. For example, as shown in FIG. 7, the memory cell can go from the initial V state to the R state, from the R state to the S state, and from the S state to the P state. The read current in each state is at least twice the read current in the previous state, each corresponding to one individual data state. In this example, the pulse may be applied with either a forward or reverse bias applied. In other embodiments, the number of data states may be three or more than four.

  In one embodiment, the memory cell is shown in FIG. 8 with a lower heavily doped p-type region 4, a central intrinsic or lightly doped region 6, and an upper heavily doped. A polysilicon or microcrystalline diode 2 including the n-type region 8 is provided. Similar to the embodiment described above, the diode 2 can be placed in series with the breakdown antifuse between the upper and lower conductors together with the breakdown antifuse. The lower heavily doped p-type region 4 may be doped in situ during stacking. That is, doping may be performed by flowing a gas supplying a p-type dopant such as boron during the deposition of polysilicon so that dopant atoms are taken into the thin film as the thin film is formed.

  Please refer to FIG. It has been discovered that this memory cell is formed in a V state with a read voltage of 2V and a current between the upper conductor 16 and the lower conductor 12 of less than about 80 nA. Preferably, for example, under a forward bias of about 8V, the first electrical pulse causes the breakdown antifuse 14 to break down, so that the polysilicon of the diode 2 changes from the first resistivity state to the first resistivity state. It is switched to the second resistivity state having a low resistivity. As a result, the memory cell transits to the data state P. In data state P, the current between upper conductor 16 and lower conductor 12 at the read voltage described above is between about 1 μA and about 4 μA. Preferably, under reverse bias, the second electrical pulse switches the polysilicon of diode 2 from the second resistivity state to a third resistivity state having a lower resistivity than the first resistivity state. This third resistivity state corresponds to the data state M. In the data state M, the current between the upper conductor 16 and the lower conductor 12 at the read voltage described above is greater than about 10 μA. As in the previous embodiment, between any cells in adjacent data states (between the cell in state V where the highest current flows in that state and the cell in state P where the lowest current flows in that state, or in state P) The difference in current between the cell through which the highest current flows in that state and the cell through which the lowest current flows in state M) is preferably at least twice, and more preferably three times or more. Any data state of data state V, P or M can be detected as the data state of the memory cell.

  In FIG. 4, when a semiconductor diode is reverse-biased, in general, the semiconductor material first makes a set transition to a low resistivity state, and then when the voltage is increased, it resets to a high resistivity state. It has been shown. However, this particular has an upper heavily doped n-type region 8 and preferably a lower heavily doped region 4 formed by doping with a p-type dopant by in-situ doping. For a simple diode, the transition from a set transition to a reset transition caused by an increase in reverse bias voltage does not occur as steeply or as steeply as other diode embodiments. This means that with such a diode, the set transition under a reverse bias is easier to control.

In another group of embodiments of rewritable memory cells, the memory cells operate as memory cells that can be repeatedly switched (rewritable) between two or three data states.

  Referring to FIG. 11, in one embodiment, the memory cell is formed in a high resistivity state V with a current at 2V of about 5 nA or less. The plot shown in FIG. 11 is for a cell with a silicon oxide antifuse. In most rewritable embodiments, the initial V state is not used as the data state of the memory cell. The first electrical pulse is preferably applied between the upper conductor 16 and the lower conductor 12 with the diode 2 under forward bias. This pulse is, for example, from about 8 to about 12V, preferably about 10V. The first electrical pulse switches the semiconductor material of the diode 2 from the first resistivity state to the second resistivity state P, which has a lower resistivity than the first resistivity state. In the preferred embodiment, the P state is also not used as the data state of the memory cell. However, in another embodiment, the P state is used as the data state of the memory cell.

  A second electrical pulse is preferably applied between the upper conductor 16 and the lower conductor 12 with the diode 2 under reverse bias. This pulse is, for example, about −8 to about −14V, preferably about −9 to about −13V, and more preferably about −10 or −11V. The required voltage varies with the thickness of the intrinsic region. This second electrical pulse switches the semiconductor material of the diode 2 from the second resistivity state to the third resistivity state R, which has a higher resistivity than the second resistivity state. In the preferred embodiment, the R state corresponds to the data state of the memory cell.

  The application of the third electrical pulse between the upper conductor 16 and the lower conductor 12 can also take place, preferably under a forward bias. This pulse is, for example, about 5.5 to about 9V, and preferably about 6.5V. The corresponding current is about 10 to about 200 [mu] A, preferably about 50 to about 100 [mu] A. By this third electric pulse, the semiconductor material of the diode 2 is switched from the third resistivity state R to the fourth resistivity state S having a lower resistivity than the third resistivity state. In the preferred embodiment, the S state corresponds to the data state of the memory cell.

  In this rewritable two-state embodiment, the R and S states are detected as data states. That is, it is read out. The memory cell can be repeatedly switched between these two states. For example, preferably with the diode 2 under reverse bias, the fourth electrical pulse causes the semiconductor material of the diode to change from the fourth resistivity state S to substantially the same as the third resistivity state R. , Switched to the fifth resistivity state S. Preferably, with the diode 2 under forward bias, the fifth electrical pulse causes the semiconductor material of the diode to be substantially the same from the fifth resistivity state R to the fourth resistivity state S, Switch to the sixth resistivity state S. It may be more difficult to return the memory cell to the initial V state and the second P state. Therefore, these states may not be used as data states in a rewritable memory cell. In that case, the first electrical pulse switches the cell from the initial V state to the P state before the end user obtains the memory array, e.g., at the factory or test facility, or prior to sale by the vendor, and the second It is desirable to switch the cell from the P state to the R state by the electrical pulse. In another embodiment, it may be desirable to only switch the cell from the initial V state to the P state by the first electrical pulse before the end user obtains the memory array.

  As can be seen from FIG. 11, in this example, a current flowing between the upper conductor 16 and the lower conductor 12 at a read voltage of 2 V, for example, an arbitrary cell in a certain data state and an arbitrary data state in its adjacent data state The difference between the current flowing through the cell, in this example the R data state (about 10 to about 500 nA) and the S data state (about 1.5 to about 4.5 μA) is at least three times. Depending on the range selected for each data state, the current difference can be two, three, five, or more.

  In another embodiment, rewritable memory cells can be switched in any order between three or more data states. Either set or reset transitions can be made with either forward or reverse bias applied to the diode.

  It should be noted that in both the one-time programmable embodiment and the rewritable embodiment described above, the data state corresponds to the resistivity state of the polycrystalline or microcrystalline semiconductor material comprising the diode. The data state is “Nonvolatile Memory Cell Comprising a Diode and a Resistance-Switching Material” by Herner et al., Filed Mar. 31, 2006, owned by the assignee of the present invention and incorporated herein by reference. Does not correspond to the resistivity state of oxidized or nitrided metals that switches resistivity, as described in US patent application Ser. No. 11 / 395,995.

Reverse Bias Set and Reset In an array of memory cells formed and programmed according to the embodiments described so far, any process in which a cell receives a high voltage under a reverse bias is a process that is performed with a forward bias applied. Compared to the leakage current.

  Please refer to FIG. It is assumed that 10 V is applied after the selected cell S is under a forward bias. (The voltage actually used depends on many factors including the structure of the cell, the dopant concentration, the height of the intrinsic region, etc. 10V is merely an example.) The bit line B0 is set to 10V and the word line W0 is set. Is set to ground voltage. Word line W1 is less than and relatively close to the voltage on bit line B0 to ensure that half-selected cell F (which shares bit line B0 with selected cell S) stays below the rising voltage of the diode. Set to voltage. For example, the word line W1 may be set to 9.3V so that 0.7V is applied to the F cell (only one F cell is shown, but there are hundreds or thousands of F cells. Or more than that). Similarly, to ensure that half-selected cell H (which shares selected cell S and word line W0) stays below the rising voltage of the diode, bit line B1 is higher than and compared to the voltage on word line W0. Set the voltage close to the target. For example, the bit line B1 may be set to 0.7 V so that 0.7 V is applied to the cell H (similarly, there may be thousands of H cells). Unselected cell U, which does not share selected cell S and either word line W0 or bit line B0, receives −8.6V. This can result in very high leakage currents in the array, since there can be millions of unselected cells U.

  FIG. 13 shows a bias system that is advantageous for applying a large reverse bias to a memory cell, for example, as a reset pulse. By setting the bit line B0 to −5V and the word line W0 to 5V, −10V is applied to the selected cell S. The diode is in a state where a reverse bias is applied. By setting the word line W1 and the bit line B1 to the ground voltage with a sufficiently low reverse bias applied to the half-selected cells F and H so that unintended set or reset does not occur, both cells F and H receive -5V. In general, it appears that setting or resetting under reverse bias occurs at or near the voltage where the diode undergoes reverse breakdown, usually above -5V. If this method is used, no voltage is applied to the non-selected cell U, so that no reverse leakage current occurs.

  The bias application method of FIG. 13 is only an example, and it is obvious that many other methods can be used. For example, the bit line B0 can be set to 0V, the word line W0 can be set to -10V, and the bit line B1 and the word line W1 can be set to -5V. The voltages applied to the selected cell S, the half-selected cells H and F, and the non-selected cell U are the same as in the method of FIG. In another example, the bit line B0 is set to the ground voltage, the word line W0 is set to 10V, and the bit line B1 and the word line W1 are set to 5V.

Repeated set and reset So far we have described switching the semiconductor material of a diode from one resistivity state to another and switching the memory cell between two individual data states by applying an appropriate electrical pulse. . In practice, these set and reset steps may be iterative processes.

  As described above, it is desirable that the difference in read current between adjacent data states is at least twice. In many embodiments, it may be desirable to separate the current ranges for each data state such that the current difference is three times, five times, ten times, or greater.

  Referring to FIG. 14, as described above, the data state V can be defined as a read current of 5 nA or less at a read voltage of 2V. Data state R can be defined as a read current of about 10 to about 500 nA, data state S can be defined as a read current of about 1.5 to about 4.5 μA, and data state P can be defined as a read current of greater than about 10 μA. . It will be apparent to those skilled in the art that these are only examples. For example, in another embodiment, the read current in data state V is about 5 nA or less at a read voltage of 2V, although the range may be defined smaller. The actual read current will vary depending on cell characteristics, array structure, selected read voltage and many other factors.

  Assume that a memory cell that can be programmed only once is in data state P. An electrical pulse is applied to the memory cell under reverse bias to switch the cell to the data state S. However, in some cases, the read current may not be in the desired range after application of the electrical pulse. That is, the resistivity state of the semiconductor material of the diode is higher or lower than intended. For example, it is assumed that the read current of the memory cell is at a position indicated by Q on the graph between the current ranges of the S state and the P state after application of the electric pulse.

  After applying an electrical pulse to switch the memory cell to the desired data state, the memory cell may be read to determine whether the desired data state has been reached. If the desired data state has not been reached, an additional pulse is applied. For example, if current Q is detected, an additional reset pulse is applied to increase the resistivity of the semiconductor material and reduce the read current to a range corresponding to the S data state. As described above, this set pulse may be applied in a state where a forward bias or a reverse bias is applied. The one or more additional pulses may be higher in amplitude (voltage or current) than the first pulse. Alternatively, the pulse width may be longer or shorter than the first pulse. After the additional set pulse, the cell is read again and an appropriate set or reset pulse is applied until the read current is in the desired range.

  In a two-terminal element such as a memory cell including a diode as described above, it is particularly advantageous to perform read and verify of set or reset, and adjust if necessary. Applying a large reverse bias to a diode can damage the diode, so it is advantageous to minimize the reverse bias voltage when setting or resetting the diode under reverse bias. is there.

Both manufacturing considerations , “Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor” by Herner et al. US Patent Application No. 11 / 148,530 entitled "Material" and US Patent Application "Healer" by Herner filed "Serial Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide" filed September 29, 2004 No. 10 / 954,510 (Patent Document 6) describes that when polysilicon is crystallized adjacent to an appropriate silicide, the physical properties of the polysilicon change. Certain metal silicides, such as cobalt silicide and titanium silicide, have a lattice structure very close to silicon. When amorphous or microcrystalline silicon crystallizes in contact with one of these silicides, the crystal lattice of the silicide becomes the template for the silicon being crystallized. The resulting polysilicon has a highly ordered structure and a relatively low defect density. This high quality polysilicon, when doped with a conductivity-enhancing dopant, has a relatively high conductivity when formed.

  In contrast, amorphous or microcrystalline silicon materials do not come into contact with highly lattice matched silicon with silicides, but only with materials such as silicon dioxide and titanium nitride that have very low lattice matching. When crystallized in this manner, the resulting polysilicon contains more defects, and the conductivity at the time of formation of the thus-crystallized doped polysilicon is significantly reduced.

  The present invention changes the amount of current flowing through the diode at a predetermined read voltage by switching the semiconductor material forming the diode between two or more resistivity states, and the individual current amounts (and resistivity states) are individually Other suitable, such as high defect density silicon (or germanium or silicon-germanium alloys) that are not crystallized adjacent to the silicide or similar material that serves as a template for crystallization. It has been discovered that diodes made of (semiconductor materials) exhibit the most advantageous switching behavior.

  While not wishing to be bound by any particular theory, one mechanism that is likely to explain the observed resistivity change is that the set pulse above the threshold voltage causes the dopant atoms to become inactive. It is thought that dopant atoms move from the grain boundaries into the crystal body, increasing the conductivity of the semiconductor material and decreasing the resistance. On the other hand, it is believed that the reset pulse returns the dopant atoms to the grain boundaries, decreasing the conductivity and increasing the resistance. However, it is possible that other mechanisms such as increasing and decreasing the degree of order of the polycrystalline material may work simultaneously with or instead of the above-described mechanism.

  It has been discovered that the resistivity state of very low defect silicon crystallized adjacent to a suitable silicide cannot be switched as easily as if the semiconductor material has a higher defect concentration. It is possible that switching is facilitated by the presence of defects or the presence of a larger number of grain boundaries. Thus, in a preferred embodiment, the crystallization of the polycrystalline or microcrystalline material that forms the diode is performed without being adjacent to a material with poor lattice matching. The low lattice matching is, for example, a lattice matching of about 3% or less.

  Evidence indicates that the switching behavior may be concentrated in changes within the intrinsic region. Switching behavior is also observed in resistors and pn diodes and is not limited to pin diodes, but it may be particularly advantageous to use pin diodes. The embodiments described so far have included p-i-n diodes. However, in another embodiment, the diode may not be a pin diode, but a pn diode with little or no intrinsic region.

  Detailed examples for producing the preferred embodiments of the present invention will be described. US patent application Ser. No. 10 / 320,470, “An Improved Method for Making High Density Nonvolatile Memory” by Herner et al., Filed Dec. 19, 2002, and later abandoned and incorporated herein by reference. The details of the manufacturing described in US Pat. No. 6,057,077 are useful in forming the diodes of these embodiments, as well as the information described in US Pat. US Patent Application No. 11 entitled “Nonvolatile Memory Cell Comprising a Reduced Height Vertical Diode” by Herner et al., Filed Dec. 17, 2004, owned by the assignee of the present invention and incorporated herein by reference. / 015,824 (Patent Document 8) can also provide useful information. In order to avoid obscuring the present invention, not all of the details described in these patent applications are described, but it is understood that the information described in these patent applications is not intended to be excluded. Should do.

  A single memory level manufacturing will be described in detail. Each additional memory level can be monolithically formed and stacked on top of the underlying memory level. In this embodiment, the polycrystalline semiconductor diode functions as a switchable memory element.

Referring to FIG. 15 a, memory formation starts from the substrate 100. The substrate 100 may be a single crystal silicon, a group IV-IV compound such as silicon-germanium or silicon-germanium-carbon, a group III-V compound, a group II-VII compound, an epitaxial layer on the substrate as described above, or It may be any semiconductor substrate known in the art, such as any other semiconductor material. An integrated circuit may be formed and included on the substrate.
An insulating layer 102 is formed over the substrate 100. The insulating layer 102 may be silicon oxide, silicon nitride, a high dielectric thin film, a Si—C—O—H thin film, or any other suitable insulating material.

A first conductor 200 is formed on the substrate and the insulator. An adhesive layer 104 may be included between the insulating layer 102 and the conductor layer 106 to help adhere the conductor layer 106 to the insulating layer 102. If the upper conductor layer is tungsten, titanium nitride is desirable as the adhesion layer 104.
The next layer to be deposited is the conductor layer 106. The conductor layer 106 may include any conductive material known in the art, such as tungsten or other materials such as tantalum, titanium, copper, cobalt, or alloys thereof.

Once all the layers to form the conductor lines are deposited, the layers are patterned and etched using any suitable masking and etching process, and are substantially parallel and substantially as shown in cross section in FIG. 15a. Thus, the conductor 200 is formed in the same plane. In one embodiment, a photoresist is deposited, patterned by photolithography, and further layer etching is performed. In addition, the photoresist is removed using standard processing techniques. Alternatively, the conductor 200 can be formed by the damascene method.
Next, a dielectric material 108 is deposited on the conductor line 200 and between the lines. Dielectric material 108 may be any well-known electrically insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In the preferred embodiment, silicon dioxide is used as the dielectric material 108.

  Finally, excess dielectric material 108 on conductor line 200 is removed, exposing the top of conductor line 200 separated by dielectric material 108, leaving a substantially flat surface 109. The resulting structure is shown in FIG. 15a. This step of removing excess dielectric material to form a flat surface 109 can be performed by any process known in the art, such as chemical mechanical planarization (CMP) or etchback. . US patent application Ser. No. 10 / 883,417 entitled “Nonselective Unpatterned Etchback to Exposed Buried Patterned Features” by Raghuram et al., Filed Jun. 30, 2004, incorporated by reference herein. Describes an etchback technique that can be advantageously used. At this stage, a plurality of substantially parallel first conductors were formed at a first height on the substrate 100.

  Next, referring to FIG. 15 b, vertical pillars are formed on the completed conductor line 200. (For the sake of space saving, the substrate 100 is not shown in FIG. 15b, but its presence is assumed.) After planarization of the conductor lines, the shielding layer 110 is deposited as the first layer. Is desirable. Any suitable material can be used in the shielding layer, such as tungsten nitride, tantalum nitride, titanium nitride, or combinations of these materials. In a preferred embodiment, titanium nitride is used as the shielding layer. If the shielding layer is titanium nitride, it can be deposited in the same manner as the adhesive layer described above.

  Next, a semiconductor material to be patterned to form pillars is deposited. The semiconductor material may be silicon, germanium, a silicon-germanium alloy or other suitable semiconductor or semiconductor alloy. For convenience, this semiconductor material is referred to as silicon in this description. However, it should be understood by those skilled in the art that any of these other suitable materials may be selected in place of silicon.

  In a preferred embodiment, the pillar includes a semiconductor junction diode. In the specification of the present application, the term “junction diode” refers to a semiconductor element having a non-ohmic conductive property and having two terminal electrodes, one electrode side being made of a p-type semiconductor material and the other electrode side being made of an n-type semiconductor material. Is used to indicate A pn diode and an np diode, such as a Zener diode, in which a p-type semiconductor material and an n-type semiconductor material are in contact with each other, and an intrinsic (undoped) semiconductor material is a p-type semiconductor material and an n-type semiconductor material. An example is a pin diode interposed between the two.

The lower heavily doped region 112 can be formed by any deposition and doping method known in the art. Although doping can be performed after silicon deposition, it is desirable to perform in-situ doping by flowing a donor gas that supplies n-type dopant atoms, such as phosphorus, during silicon deposition. The thickness of the heavily doped region 112 is desirably about 100 to about 800 angstroms.
Intrinsic region 114 can be formed by any method known in the art. Layer 114 may be silicon, germanium, or any alloy of silicon or germanium. Its thickness is from about 1,100 to about 3,300 angstroms, preferably about 2,000 angstroms.

  Referring again to FIG. 15 b, the semiconductor layers 114 and 112 deposited with the underlying shielding layer 110 are patterned and etched to form pillars 300. The pillars 300 should have approximately the same period and approximately the same width as the underlying conductors 200 so that each pillar 300 is formed on the conductors 200. Some deviation is acceptable.

  The pillar 300 can be formed using any suitable masking and etching process. For example, the photoresist can be removed after the photoresist has been deposited and patterned using standard photolithography techniques and further etched. As another method, a lower layer antireflection film (BARC) is formed on a multilayer stack of semiconductor layers, and a hard mask made of another material, for example, silicon dioxide, is formed thereon, and then patterned and etched. You can also. Similarly, an antireflection insulating film (DARC) can be used as a hard mask.

  Filed on Dec. 5, 2003, both owned by the assignee of the present invention and incorporated herein by reference to perform any photolithography process used to form the memory array according to the present invention. "Photomask Features with Interior Nonprinting Window Using lternating Phase Shifting" by US Patent Application No. 10 / 728,436 (Patent Document 10) or "Photomask Features with Chromeless" by Chen filed on April 1, 2004 The photolithography technique described in US patent application Ser. No. 10 / 815,312 entitled “Nonprinting Phase Shifting Window” can be advantageously used.

  Dielectric material 108 is deposited on and between the semiconductor pillars 300 to fill the gaps between them. Dielectric material 108 may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the insulating material.

Next, the dielectric material on the pillar 300 is removed, exposing the top of the pillar 300 separated by the dielectric material 108, leaving a substantially flat surface. This removal of excess dielectric material can be accomplished by any process known in the art, such as CMP or etchback. After CMP or etchback, ion implantation is performed to form a heavily doped p-type upper region 116. The p-type dopant is preferably boron or BCl ₃ . The formation of the diode 111 is completed by this implantation step. The completed structure is shown in FIG. 15b. In the diode formed as described above, the lower heavily doped region 112 is n-type and the upper heavily doped region 116 is p-type, but the polarity is reversed. It is clear that it is good.

  Referring to FIG. 15c, antifuse dielectric layers 118 are formed on regions 116 that are each heavily doped. The antifuse layer 118 is preferably a metal oxide layer having a thickness of 10 to 100 Å formed by any suitable deposition method such as sputtering. If desired, the pillar 300 may be patterned after the deposition process of the antifuse dielectric layer 118 so that the antifuse layer 118 becomes part of the pillar 300.

  The upper conductor 400 can be formed, for example, by depositing the adhesive layer 120 and the conductor layer 122 in the same manner as the lower conductor 200. The adhesive layer 120 is preferably made of titanium nitride, and the conductor layer 122 is preferably made of tungsten. Next, using any suitable masking and etching technique, the conductor layer 122 and the adhesive layer 120 are patterned and etched to extend from left to right in FIG. 15c, substantially parallel, as shown in FIG. Conductors 400 are formed that are substantially aligned in the same plane. In a preferred embodiment, a photoresist is deposited by photolithography and patterned, and after further layer etching, the photoresist is removed using standard processing techniques.

  Next, a dielectric material (not shown) is deposited on the conductor line 400 and between the lines. The dielectric material may be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as the dielectric material.

  The formation of the first memory level has been described. Additional memory levels can be formed on this first memory level to form a monolithic three-dimensional memory array. Some embodiments can share conductors between memory levels. That is, the upper conductor 400 also serves as the lower conductor of the next memory level. In another embodiment, an intermediate dielectric layer (not shown) is formed on the first memory level of FIG. 15c to planarize the surface, from which the conductors are routed. Start building a second memory level that is not shared.

  A monolithic three-dimensional memory array is obtained by forming a large number of memory levels on a single substrate such as a wafer without interposing another substrate. The layers forming one memory level are deposited or grown directly on one or more existing levels. On the other hand, as described in US Pat. No. 5,915,167 called “Three dimensional structure memory” by Leedy, conventionally, a stacked memory forms memory levels on different substrates. And it was built by gluing its memory levels on top of each other. Although the substrate may be thinned or removed from the memory level prior to bonding, such a memory is not a true monolithic three-dimensional memory array because the memory level is first formed on a separate substrate.

  The monolithic three-dimensional memory array formed on the substrate is formed at least at a first memory level formed at a first height on the substrate and at a second height different from the first height. A second memory level. In such a multi-level array, any number of memory levels can be formed on the substrate at three, four, eight, or indeed any number of levels.

  Another method of forming a similar array is to form a conductor using a damascene structure, as of May 31, 2006, owned by the assignee of the present invention and incorporated herein by reference. No. 11 / 444,936 (Patent Document 13) entitled “Conductive Hard Mask to Protect Patterned Features During Trench Etch” by Radigan et al. The method of U.S. Pat. No. 6,057,836 may be used as an alternative method of forming an array according to the present invention.

  In addition to the embodiments described so far, many other embodiments are possible as memory cells in which the data state is stored in the resistivity state of the polycrystalline or microcrystalline semiconductor material and are within the scope of the present invention. It is. For example, the positions of the p-type region 8 and the n-type region 4 in the diode 2 may be reversed so that the p-type region 8 is provided below the vertical diode and the n-type region 4 is provided above the diode 2.

Although a detailed manufacturing method has been described herein, any other method can be used to form the same structure, and the effect is within the scope of the present invention.
Figures 16a and 16b show examples of two different memory cells. FIG. 16a shows a cell in which a metal oxide antifuse dielectric layer 14 is provided over the diode. In particular, an antifuse dielectric layer 14 is provided on the p-type region 8 of the diode.

In FIG. 16 b, an antifuse dielectric layer 14 is provided below the diode 2. In particular, a metal oxide (Al ₂ O ₃ ) antifuse dielectric layer 14 is separated from the n-type silicon region 4 of the diode by a titanium nitride layer 110. Accordingly, the Al ₂ O ₃ antifuse dielectric layer 14 comprises a W layer 106 and a TiN layer 110 in a MIM (metal-insulator-metal) structure under the diode in the cell shown in FIG. 16b. Between. A titanium layer 124 is provided between the p-type region of the diode 2 and the upper titanium nitride layer 120.

  FIG. 17a shows the read current (square) of the memory cell shown in FIG. 16a with a 10 angstrom thick aluminum oxide antifuse dielectric layer, similar to that with a 16 angstrom thick silicon dioxide antifuse dielectric layer. It is a probability plot compared with a memory cell (circle). Both cells were programmed with a + 8V pulse. As can be seen from FIG. 17a, the read current of the programmed cell with the aluminum oxide antifuse dielectric layer was 30 μA at a read voltage of 2V. On the other hand, the read current of the programmed cell with the silicon dioxide antifuse dielectric layer was 20 μA at a read voltage of 2V. Therefore, the read current is improved by 50% by using an aluminum oxide antifuse dielectric layer instead of silicon oxide.

FIG. 17b is a probability plot showing the read current of the memory cell shown in FIG. 16a with a 30 Å thick hafnium oxide (HfO ₂ ) antifuse dielectric layer. The cell was programmed with a + 10V pulse. As can be seen from FIG. 17b, the read current of the programmed cell was 30 μA at a read voltage of 2V.

FIG. 17c is a probability plot comparing the read current of the programmed memory cell shown in FIG. 16a with the read current of the programmed memory cell shown in FIG. 16b. Both cells have a similar thickness of Al ₂ O ₃ antifuse, but the structure of FIG. 16a with Al ₂ O ₃ on the diode in contact with the p ⁺ doped silicon region 8 is better than the structure of FIG. 16b. Also show significantly higher forward current. As can be seen from FIG. 17c, the read current was reduced by the antifuse dielectric in the MIM structure shown in FIG. 16b. This is undesirable for applications where high read current is required.

While not wishing to be bound by any particular theory, the inventors of the present application are able to diffuse and mix Al in the Al ₂ O ₃ layer into the p-type silicon region 8 of the diode during programming, We believe that the forward current may increase. Thus, after programming the cell and forming the connecting conductive path through the dielectric layer, the p-type region of the diode contains aluminum diffused from the antifuse dielectric layer. Since Al is a p-type dopant in silicon, the p-type dopant increases the p-type dopant concentration in the region 8, thereby improving the ohmic contact between adjacent electrodes in the p-type region 8. The forward current of the diode increases. This indicates that Al ₂ O ₃ can be placed in contact with the p-type region of the diode in the memory cell. Therefore, when the p-type region 8 is provided below the diode, the Al ₂ O ₃ layer 14 can be provided below the diode. In the case where the p-type region 8 is provided above the diode, an Al ₂ O ₃ layer can be provided above the diode. On the other hand, in practice, Si may diffuse from the SiO ₂ antifuse dielectric layer into the diode, reducing the p-type dopant concentration in the p-type region 8 of the diode and possibly degrading the diode. Thus, this is one possibility to explain why the aluminum oxide antifuse has a higher read current than the silicon dioxide antifuse, as shown in FIG. 17a.

Hafnium is also a p-type dopant in silicon and can play a role similar to aluminum, which may be the reason for the results shown in FIG. 17b. However, metals other than aluminum from metal oxide antifuse dielectrics are generally much less soluble in silicon than aluminum. Thus, even if those metals diffuse from the antifuse dielectric layer into the silicon, the p-type carrier concentration in the silicon should be lower than in the case of aluminum. For example, the solubility of Al in Si at 700 ° C. is more than 1 × 10 ²⁰ cm ⁻³ , while the solubility of Hf in Si at a higher temperature is less than 1 ppm (less than 1 × 10 ¹⁷ cm ⁻³ ). Presumed.

  The foregoing detailed description has described only a few examples of the many forms that the invention can take. Accordingly, this detailed description is intended to be illustrative and not limiting. It is only the following claims, including all equivalents, that are intended to define the scope of this invention.

Claims (40)

A non-volatile memory device,
At least one memory cell comprising a diode and a metal oxide antifuse dielectric layer;
A first electrode and a second electrode in electrical contact with the at least one memory cell;
In use, as the read / write element of the memory cell, the diode switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. Non-volatile memory device that functions. The device of claim 1, wherein
An element in which the diode and the metal oxide antifuse dielectric layer are provided in series between the first and second electrodes. The device of claim 2, wherein
The device wherein the metal oxide antifuse dielectric layer has a dielectric constant greater than 3.9. The device of claim 2, wherein
The metal oxide antifuse dielectric layer is made of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium oxide-silicon, aluminum oxide-silicon, hafnium oxide-silicon, hafnium oxide-aluminum, oxynitride At least one of hafnium-silicon, zirconium oxide-silicon-aluminum, hafnium oxide-aluminum-silicon, hafnium oxynitride-aluminum-silicon or zirconium oxynitride-silicon-aluminum, or at least one of SiO _{2 and} SiN _x A device containing a compound of heel. The device of claim 4, wherein
The device wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide. The device of claim 5, wherein
An element wherein the metal oxide antifuse dielectric layer is provided adjacent to a p-type region of the diode. The device of claim 6.
The diode comprises a polycrystalline silicon, germanium or silicon-germanium pin pillar-shaped diode having a substantially cylindrical shape;
The device wherein the p-type region of the diode comprises aluminum or hafnium diffused from the antifuse dielectric layer after the cell is programmed. The device of claim 1, wherein
The memory cell comprises a read / write memory cell;
A device in which the diode includes a pin semiconductor diode that functions as a read / write element of the memory cell. The device of claim 8, wherein
An element in which the memory cell includes a rewritable memory cell. The device of claim 9, wherein
Applying a forward bias between the first and second electrodes forms a connection conductive path that breaks down the metal oxide antifuse dielectric layer and programs the diode;
The programmed diode is placed in a high resistivity state (unprogrammed state) by applying a reverse bias to the diode;
An element in which a diode in the high resistivity state (unprogrammed state) is returned to a low resistivity state (programmed state) by applying a forward bias to the diode. The device of claim 1, wherein
An element comprising a monolithic three-dimensional array of memory cells provided on the diode; A non-volatile memory device,
A plurality of memory cells;
A first electrode and a second electrode in electrical contact with the plurality of memory cells,
Each memory cell of the plurality of memory cells includes a diode and a metal oxide antifuse dielectric layer provided in series between the first and second electrodes, the diode having a substantially cylindrical shape A non-volatile memory device comprising a polycrystalline silicon, germanium or silicon-germanium pin pin-like diode having The device of claim 12, wherein
The metal oxide antifuse dielectric layer is made of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium oxide-silicon, aluminum oxide-silicon, hafnium oxide-silicon, hafnium oxide-aluminum, oxynitride At least one of hafnium-silicon, zirconium oxide-silicon-aluminum, hafnium oxide-aluminum-silicon, hafnium oxynitride-aluminum-silicon or zirconium oxynitride-silicon-aluminum, or at least one of SiO _{2 and} SiN _x A device containing a compound of heel. The device of claim 13, wherein
The device wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide. The device of claim 14, wherein
The device wherein the p-type region of the diode comprises aluminum or hafnium diffused from the antifuse dielectric layer after programming the cell. The device of claim 14, wherein
An element having a read current of at least 3.5 × 10 ⁻⁵ A at a read voltage of at least 1.5 V in each memory cell The device of claim 12, wherein
The device wherein the metal oxide antifuse dielectric layer has a thickness of 10-100 angstroms. The device of claim 12, wherein
The plurality of memory cells comprise read / write memory cells;
An element including a p-i-n semiconductor diode in which the diode in each memory cell of the plurality of memory cells functions as a read / write element of each memory cell of the plurality of memory cells. The device of claim 18, wherein
In use, the diode in each memory cell of the plurality of memory cells switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. A device that functions as a read / write element of each memory cell of the plurality of memory cells. The device of claim 19, wherein
The plurality of memory cells comprise rewritable memory cells,
Application of a forward bias between the first and second electrodes forms a connection conductive path that breaks down the metal oxide antifuse dielectric layer, and the memory cell in each of the plurality of memory cells The diode is programmed,
The programmed diode is placed in a high resistivity state (unprogrammed state) by applying a reverse bias to the diode;
A diode in the high resistivity state (unprogrammed state) is returned to the low resistivity state (programmed state) by applying a forward bias to the diode,
The metal oxide antifuse dielectric layer is dielectrically broken by a connection conductive path by applying a forward bias between the first and second electrodes to program the diode;
The programmed diode is placed in a high resistivity state (unprogrammed state) by applying a reverse bias to the diode having a value higher than a predetermined critical voltage value;
An element in which the unprogrammed diode is returned to the low resistivity state (programmed state) by applying a forward bias to the diode. A method of manufacturing a non-volatile memory device, comprising:
Forming a first electrode;
Forming at least one non-volatile memory cell comprising a diode and a metal oxide antifuse dielectric layer on the first electrode;
Forming a second electrode on the at least one non-volatile memory cell;
In use, the diode switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias, thereby reading / writing the nonvolatile memory cell How to act as an element. The method of claim 21, wherein
A method in which the diode and the metal oxide antifuse dielectric layer are provided in series between the first and second electrodes. The method of claim 22, wherein
The metal oxide antifuse dielectric layer is made of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium oxide-silicon, aluminum oxide-silicon, hafnium oxide-silicon, hafnium oxide-aluminum, oxynitride At least one of hafnium-silicon, zirconium oxide-silicon-aluminum, hafnium oxide-aluminum-silicon, hafnium oxynitride-aluminum-silicon or zirconium oxynitride-silicon-aluminum, or at least one of SiO _{2 and} SiN _x A method comprising a compound of heel. 24. The method of claim 23.
The method wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide. 25. The method of claim 24, wherein
The method wherein the metal oxide antifuse dielectric layer is provided adjacent to a p-type region of the diode. The method of claim 21, wherein
The method further comprises patterning the diode and the metal oxide antifuse dielectric layer such that the diode and the metal oxide antifuse dielectric layer form a pillar having a substantially cylindrical shape. The method of claim 21, wherein
Apply a forward bias to the diode to switch the diode from the first resistivity state (unprogrammed state) to the second resistivity state (programmed state) lower than the first resistivity state The method further comprising the step of: 28. The method of claim 27, wherein
Applying a forward bias to the diode to form a connecting conductive path through the metal oxide antifuse dielectric layer. 30. The method of claim 28, wherein
A method in which after forming the connection conductive path, a metal dopant diffuses from the metal oxide antifuse dielectric layer into a p-type region of the diode provided adjacent to the metal oxide antifuse dielectric layer. The method of claim 21, wherein
The method wherein the metal oxide antifuse dielectric layer has a thickness of 10-100 angstroms. A method for operating a non-volatile memory device, comprising:
A diode that is switched from a first higher resistivity state (unprogrammed state) to a second lower resistivity state (programmed state); and a metal oxide antifuse dielectric layer that is broken down by a connecting conductive path. Providing at least one memory cell comprising:
Applying a reverse bias to the diode to switch the diode to a third resistivity state (unprogrammed state) higher than the second resistivity state;
Including methods. 32. The method of claim 31, wherein
A method further comprising applying a forward bias to the diode to switch the diode to a fourth resistivity state (programmed state) that is lower than the third resistivity state. 32. The method of claim 31, wherein
The method further comprises detecting a resistivity state of the diode as a data state of the memory cell. 34. The method of claim 33.
The method wherein the sensing includes applying a read voltage to the memory to bring the read current of the memory cell to at least 3.5 × 10 ⁻⁵ A with a read voltage of at least 1.5V. 32. The method of claim 31, wherein
The diode is switched to the second programmed state at the factory where the memory cell is manufactured;
The method of applying a reverse bias to the diode is performed by a user of the memory cell after the memory cell is shipped from a factory where the memory cell is manufactured. 32. The method of claim 31, wherein
The method further comprising: breaking down the metal oxide antifuse dielectric layer with a connecting conductive path. 32. The method of claim 31, wherein
The diode and the metal oxide antifuse dielectric layer are provided in series between the first and second electrodes;
The metal oxide antifuse dielectric layer is made of hafnium oxide, aluminum oxide, titanium oxide, lanthanum oxide, tantalum oxide, ruthenium oxide, zirconium oxide-silicon, aluminum oxide-silicon, hafnium oxide-silicon, hafnium oxide-aluminum, oxynitride At least one of hafnium-silicon, zirconium oxide-silicon-aluminum, hafnium oxide-aluminum-silicon, hafnium oxynitride-aluminum-silicon or zirconium oxynitride-silicon-aluminum, or at least one of SiO _{2 and} SiN _x A method comprising a compound of heel. 38. The method of claim 37, wherein
The method wherein the metal oxide antifuse dielectric layer comprises hafnium oxide or aluminum oxide. 40. The method of claim 38, wherein
The metal oxide antifuse dielectric layer is in the p-type region of the diode so that aluminum or hafnium diffuses from the metal oxide antifuse dielectric layer into the p-type region of the diode during operation of the memory cell. Adjacent method. 32. The method of claim 31, wherein
A method in which the diode and the metal oxide antifuse dielectric layer form a pillar having a substantially cylindrical shape.

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