JP2010524107A - プロセッサによる電力消費を低減する方法、プロセッサ、及び、情報処理システム - Google Patents
プロセッサによる電力消費を低減する方法、プロセッサ、及び、情報処理システム Download PDFInfo
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Abstract
【解決手段】 情報処理システムは、分岐命令キュー内に格納された分岐命令に関する分岐予測における不正確さまたは信頼の欠如が、不正確さまたは誤差の所定の信頼度しきい値レベルを超える場合は、必ず命令フェッチャを抑制する、プロセッサを含む。このように、プロセッサが分岐命令の成果を誤予測する可能性の高い場合、プロセッサの電力を節約するために、フェッチ動作の速度が低下される。プロセッサが分岐命令の成果を正しく予測する可能性の高い場合、フェッチ動作は全速に戻る。
【選択図】 図1
Description
Claims (14)
- 分岐命令を含む命令ストリームを提供するために、フェッチャによって、命令ソースから命令をフェッチするステップと、
分岐命令キューによって、前記命令ストリームから複数のフェッチ済み分岐命令を格納するステップと、
分岐実行ユニットによって、分岐予測情報を使用することによりフェッチ済み分岐命令を投機的に実行し、各フェッチ済み分岐命令で分岐が選択されるか否かを解決し、実行済み分岐命令を提供するステップと、
信頼ストレージ・メモリによって、前記分岐命令キュー内のそれぞれのフェッチ済み分岐命令の前記分岐予測情報における信頼度をそれぞれ記述する、1つまたは複数の信頼値を格納するステップと、
前記信頼値の合計が所定の信頼しきい値未満の場合、抑制回路によって、前記命令ソースからの前記命令のフェッチを抑制するステップであって、前記抑制により、プロセッサによる電力消費が低減される、抑制するステップと、
を含む、プロセッサを動作する方法。 - 前記信頼ストレージ・メモリによって格納するステップが、前記分岐命令キュー内に格納された各フェッチ済み分岐命令について、前記信頼ストレージ・メモリ内にそれぞれの信頼値を格納するステップを含む、請求項1に記載の方法。
- 有効ベクトル生成回路によって、前記分岐命令キューに格納された有効なフェッチ済み分岐回路を識別する有効ベクトルを生成するステップをさらに含む、請求項1または2に記載の方法。
- AND回路によって、有効信頼値を取得するために、前記有効ベクトルと前記信頼値とを論理的にAND演算するステップをさらに含む、請求項3に記載の方法。
- 加算器回路によって、前記信頼ストレージ・メモリに格納された前記有効信頼値の合計を取得するために、前記有効信頼値を加算するステップをさらに含む、請求項4に記載の方法。
- 前記抑制ステップが、
比較器によって、前記有効信頼値の合計と前記所定のしきい値とを比較するステップと、
前記比較器が、前記有効信頼値の合計が前記所定のしきい値を超えると判別した場合、フェッチ抑制状態マシンによって、前記フェッチャによる前記命令ソースからの命令のフェッチ速度を低下させ、超えない場合、前記フェッチ抑制状態マシンが、前記命令ソースからの前記フェッチャによる全速での命令のフェッチを許可するステップと、
を含む、請求項5に記載の方法。 - 前記所定のしきい値がプログラム可能しきい値である、請求項1から6のいずれか一項に記載の方法。
- 命令を格納する命令ソースと、
フェッチ済み分岐命令を含む命令ストリームを提供するために前記命令ソースから命令をフェッチする、前記命令ソースに結合されたフェッチャと、
分岐予測情報を使用することによってフェッチ済み分岐命令を投機的に実行し、各フェッチ済み分岐命令内で分岐が選択されるか否かを解決し、したがって実行済み分岐命令を提供する、前記フェッチャに結合された分岐実行ユニットと、
前記フェッチャによる前記命令のフェッチを抑制することが可能な、前記フェッチャに結合された抑制コントローラと、
を備えるプロセッサであって、前記抑制コントローラは、
複数のフェッチ済み分岐命令を格納する分岐命令キューと、
前記分岐命令キュー内のフェッチ済み分岐命令に関するそれぞれの信頼値を格納する、信頼ストレージ・メモリであって、前記信頼値が、前記分岐命令キュー内のそれぞれのフェッチ済み分岐命令に関する前記分岐予測情報における信頼の欠如を記述する、信頼ストレージ・メモリと、を含み、
前記抑制コントローラは、前記信頼ストレージ・メモリ内の前記信頼値の合計が所定のしきい値を超えた場合、前記命令ソースからの前記命令のフェッチを抑制し、前記抑制によって、前記プロセッサによる電力消費を低減させる、
プロセッサ。 - 前記分岐命令キューに格納された有効なフェッチ済み分岐回路を識別する有効ベクトルを生成する、有効ベクトル生成回路をさらに備える、請求項8に記載のプロセッサ。
- 有効信頼値を取得するために、前記有効ベクトルと前記信頼値とを論理的にAND演算する、前記信頼ストレージ・メモリおよび前記有効ベクトル生成回路に結合された、AND回路をさらに備える、請求項9に記載のプロセッサ。
- 前記信頼ストレージ・メモリに格納された前記有効信頼値の合計を取得するために、前記有効信頼値を加算する、前記AND回路に結合された加算器回路をさらに備える、請求項10に記載のプロセッサ。
- 前記有効信頼値と、しきい値回路が提供する前記所定のしきい値とを比較する、前記加算器回路およびしきい値回路に結合された比較器をさらに備える、請求項11に記載のプロセッサ。
- 前記比較器および前記フェッチャに結合されたフェッチ抑制状態マシンをさらに備え、前記フェッチ抑制状態マシンは、前記比較器が、前記有効信頼値の合計が前記所定のしきい値を超えると判別した場合、前記フェッチャによる前記命令ソースからの命令のフェッチ速度を低下させ、超えない場合、前記フェッチ抑制状態マシンは、前記命令ソースからの前記フェッチャによる全速での命令のフェッチを許可する、請求項12に記載のプロセッサ。
- メモリと、
前記メモリに結合されたプロセッサと、を備える、情報処理システム(IHS)であって、前記プロセッサは、
命令を格納する命令ソースと、
フェッチ済み分岐命令を含む命令ストリームを提供するために前記命令ソースから命令をフェッチする、前記命令ソースに結合されたフェッチャと、
分岐予測情報を使用することによってフェッチ済み分岐命令を投機的に実行し、各フェッチ済み分岐命令内で分岐が選択されるか否かを解決し、したがって実行済み分岐命令を提供する、前記フェッチャに結合された分岐実行ユニットと、
前記フェッチャによる前記命令のフェッチを抑制することが可能な、前記フェッチャに結合された抑制コントローラと、を備え、前記抑制コントローラは、
複数のフェッチ済み分岐命令を格納する分岐命令キューと、
前記分岐命令キュー内のフェッチ済み分岐命令に関するそれぞれの信頼値を格納する、信頼ストレージ・メモリであって、前記信頼値が、前記分岐命令キュー内のそれぞれのフェッチ済み分岐命令に関する前記分岐予測情報における信頼の欠如を記述する、信頼ストレージ・メモリと、を含み、
前記抑制コントローラは、前記信頼ストレージ・メモリ内の前記信頼値の合計が所定のしきい値を超えた場合、前記命令ソースからの前記命令のフェッチを抑制し、前記抑制によって、前記プロセッサによる電力消費を低減させる、
情報処理システム。
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US11/733,589 US7627742B2 (en) | 2007-04-10 | 2007-04-10 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system |
US11/733,589 | 2007-04-10 | ||
PCT/EP2008/054335 WO2008122662A1 (en) | 2007-04-10 | 2008-04-10 | Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system |
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Also Published As
Publication number | Publication date |
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KR101159407B1 (ko) | 2012-06-28 |
KR20090112645A (ko) | 2009-10-28 |
CN101652739A (zh) | 2010-02-17 |
JP5172942B2 (ja) | 2013-03-27 |
US7627742B2 (en) | 2009-12-01 |
US20080256345A1 (en) | 2008-10-16 |
CN101652739B (zh) | 2011-10-12 |
WO2008122662A1 (en) | 2008-10-16 |
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