JP2010511530A - Fluid ejection device with data signal latch circuit - Google Patents

Abstract

The fluid ejection device 22/44 includes first and second firing lines 110a to 110n / 214a to 214f, data lines 108a to 108m / 208a to 208h, latch circuits 152, 404/162/184, and 186, 1 and a second droplet generator 60. The first and second emission lines transmit the first and second energy signals including the first and second energy pulses, respectively. The data line is adapted to transmit a data signal representing an image, and the latch circuit is configured to latch the data signal and provide a latched data signal based on at least one clock signal. The first and second droplet generators are configured to eject fluid based on the latched data signal in response to the first and second energy signals, respectively.
[Selection] Figure 10

Description

  The present invention relates to a liquid ejection device.

  As one embodiment of a fluid ejection system, an ink jet printing system can include a printhead, an ink supply that provides liquid ink to the printhead, and an electronic controller that controls the printhead. In one embodiment of the fluid ejection device, the print head ejects ink drops through a plurality of orifices or nozzles. The ink is fired toward a print medium such as a piece of paper, and an image is printed on the print medium. The nozzles are typically arranged as one or more arrays, and characters or other images are ejected from the nozzles in the proper order as the printhead and print media are moved relative to each other. Is printed on the print medium.

  In a typical thermal ink jet printing system, a print head ejects ink drops through nozzles by rapidly heating a small amount of ink in a vaporization chamber. The ink is heated with a small electric heater such as a thin film resistor, referred to herein as a firing resistor. By heating the ink, the ink is vaporized and ejected through the nozzle.

  To eject a drop of ink, an electronic controller that controls the printhead draws current from a power source external to the printhead. The current flows into the selected firing resistor, heats the ink in the corresponding selected vaporization chamber, and ejects the ink through the corresponding nozzle. Known drop generators include firing resistors, corresponding vaporization chambers, and corresponding nozzles.

  As inkjet printheads have evolved, the number of droplet generators in the printhead has been increased to improve printing speed and / or quality. As a result of increasing the number of drop generators per printhead, the number of firing resistors increases and accordingly the input pads required on the printhead die to apply a voltage to the firing resistors The number of people also increased. In one type of printhead, each firing resistor is connected to one corresponding input pad that provides power and supplies voltage to that firing resistor. One input pad per firing resistor becomes impractical as the number of firing resistors increases.

  In another type of printhead with primitives, the number of drop generators per input pad is significantly increased. One power lead provides power to all firing resistors in one primitive. Each firing resistor is connected in series with a power supply lead and a drain-source path of a corresponding field effect transistor (FET). The gate of each FET in the primitive is connected to an address lead to which a voltage can be individually applied, and that lead is shared by many primitives.

  Manufacturers continue to increase the number of drop generators per input pad by reducing the number of input pads and / or increasing the number of drop generators on the printhead die. Typically, a printhead with a small number of input pads is less expensive than a printhead with a large number of input pads. Also, printheads with a large number of drop generators typically have higher printing quality and / or higher printing speed.

  For the above reasons and other reasons, the present invention is needed.

  One aspect of the invention provides a fluid ejection device that includes a first firing line, a second firing line, a data line, a latch circuit, a first droplet generator, and a second droplet generator. The first firing line is adapted to transmit a first energy signal including a first energy pulse, and the second firing line is configured to transmit a second energy signal including a second energy pulse. It is like that. The data line transmits a data signal representing an image, and the latch circuit latches the data signal based on at least one clock signal and provides the latched data signal. The first drop generator is adapted to eject fluid based on the latched data signal in response to the first energy signal, and the second drop generator is configured to discharge the second energy. In response to the signal, fluid is dispensed based on the latched data signal.

  Embodiments of the present invention can be further understood with reference to the accompanying drawings. The components of the drawings are not necessarily drawn to scale with each other. Similar reference numbers indicate corresponding similar parts.

1 illustrates an embodiment of an inkjet printing system. FIG. 4 illustrates a portion of an embodiment of a printhead die. FIG. 5 illustrates a layout of drop generators disposed along an ink supply slot in one embodiment of a printhead die. FIG. 3 illustrates one embodiment of a firing cell used in one embodiment of a printhead die. FIG. 2 is a circuit diagram illustrating one embodiment of an inkjet printhead firing cell array. FIG. 6 is a circuit diagram illustrating one embodiment of a precharged firing cell. FIG. 2 is a circuit diagram illustrating one embodiment of an inkjet printhead firing cell array. FIG. 6 is a timing diagram illustrating the operation of one embodiment of a firing cell array. FIG. 3 is a circuit diagram illustrating one embodiment of a precharged firing cell configured to latch data. FIG. 6 is a circuit diagram illustrating one embodiment of a double data rate firing cell circuit. FIG. 6 is a timing diagram illustrating the operation of one embodiment of a double data rate firing cell circuit. FIG. 6 is a circuit diagram illustrating one embodiment of a precharged firing cell. FIG. 13 is a timing diagram illustrating the operation of one embodiment of a double data rate firing cell circuit using the precharged firing cell of FIG. 12. FIG. 3 is a circuit diagram illustrating one embodiment of a two-pass transistor precharged firing cell. FIG. 15 is a timing diagram illustrating the operation of one embodiment of a double data rate firing cell circuit using the precharged firing cell of FIG. 12 and the 2-pass transistor precharged firing cell of FIG. 14.

  In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terms such as “up”, “down”, “front”, “back”, “front”, “back” and the like are used with reference to the orientation of the described drawings. Since components of embodiments of the present invention can be arranged in a number of different orientations, the directional terms are used for illustration and are in no way limiting. It should be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

  FIG. 1 illustrates one embodiment of an inkjet printing system 20. Inkjet printing system 20 constitutes one embodiment of a fluid ejection system, which includes a fluid ejection device, such as inkjet printhead assembly 22, and a fluid source assembly, such as ink source assembly 24. . Inkjet printing system 20 also includes mounting assembly 26, media transport assembly 28, and electronic controller 30. At least one power supply 32 provides power to various electrical components of the inkjet printing system 20.

  In one embodiment, the inkjet printhead assembly 22 includes at least one printhead or printhead die that ejects ink drops toward the print media 36 through a plurality of orifices or nozzles 34 for printing on the print media 36. 40. The printhead die 40 is an embodiment of a fluid ejection device. As the print medium 36, any type of appropriate sheet material such as paper, card stock, transparent paper, mylar, and cloth can be used. Typically, the nozzles 34 are arranged in one or more rows or arrays, with the nozzles 34 from the nozzles 34 in an appropriate order as the inkjet printhead assembly 22 and print media 36 are moved relative to each other. By ejecting ink, characters, symbols, and / or other graphics or images are printed on the print media 36. The following description refers to the ejection of ink from the inkjet printhead assembly 22, but it is understood that other liquids, fluids, or flowable materials can be ejected from the printhead assembly 22, including transparent liquids. I want to be.

  Ink source assembly 24 as one embodiment of a fluid source assembly includes a container 38 for supplying ink to and storing ink to printhead assembly 22. Thus, ink flows from the container 38 to the inkjet printhead assembly 22. Ink supply assembly 24 and inkjet printhead assembly 22 can be formed in either a disposable ink supply system or a recirculating ink supply system. In a disposable ink supply system, substantially all of the ink supplied to the inkjet printhead assembly 22 is consumed during printing. In the recirculating ink supply system, only a portion of the ink supplied to the printhead assembly 22 is consumed during printing. Thus, ink that is not consumed during printing is returned to the ink supply assembly 24.

  In one embodiment, the inkjet printhead assembly 22 and the ink supply assembly 24 are both housed in an inkjet cartridge or pen. An inkjet cartridge or pen is one embodiment of a fluid ejection device. In another embodiment, ink supply assembly 24 is separate from inkjet printhead assembly 22 and supplies ink to inkjet printhead assembly 22 through an interface connection, such as a supply tube (not shown). In either embodiment, the container 38 of the ink source assembly 24 can be removed, replaced, and / or refilled. In one embodiment, when the inkjet printhead assembly 22 and the ink supply assembly 24 are both housed in an inkjet cartridge, the container 38 includes a built-in container disposed within the cartridge and is a large-sized container disposed separately from the cartridge. A container can also be provided. Thus, the individual large containers serve to replenish the built-in containers. Thus, individual large containers and / or built-in containers can be removed, replaced, and / or refilled.

  Mounting assembly 26 positions inkjet printhead assembly 22 relative to media transport assembly 28, and media transport assembly 28 positions print media 36 relative to inkjet printhead assembly 22. Thus, a print zone 37 is defined adjacent to the nozzle 34 in the area between the inkjet printhead assembly 22 and the print medium 36. In one embodiment, inkjet printhead assembly 22 is a scanning type printhead assembly. Accordingly, the mounting assembly 26 includes a carriage (not shown) for moving the inkjet printhead assembly 22 relative to the media transport assembly 28 to scan the print media 36. In another embodiment, the inkjet printhead assembly 22 is a non-scanning type printhead assembly. In that case, mounting assembly 26 secures inkjet printhead assembly 22 in place relative to media transport assembly 28. Thus, the media transport assembly 28 positions the print media 36 relative to the inkjet printhead assembly 22.

  The electronic controller or printer controller 30 typically communicates with and controls the inkjet printhead assembly 22, mounting assembly 26, and media transport assembly 28, firmware, and other electronic circuitry, or any of its Including a combination of The electronic controller 30 receives data 39 from a host system such as a computer, and typically includes a memory for temporarily storing the data 39. Typically, data 39 is transmitted to inkjet printing system 20 along an electronic, infrared, light, or other information transfer path. Data 39 represents, for example, a document and / or file to be printed. Thus, the data 39 forms a print job for the inkjet printing system 20 and includes one or more print job commands and / or command parameters.

  In one embodiment, the electronic controller 30 controls the inkjet printhead assembly 22 to eject ink drops from the nozzles 34. Thus, the electronic controller 30 defines a pattern of ejected ink drops that form characters, symbols, and / or graphics or images on the print media 36. The pattern of ejected ink droplets is determined by a print job command and / or command parameters.

  In one embodiment, inkjet printhead assembly 22 includes a single printhead die 40. In another embodiment, the inkjet printhead assembly 22 is a wide array or multihead printhead assembly. In one wide array embodiment, the inkjet printhead assembly 22 includes a carrier that supports the printhead die 40 and enables electrical communication between the printhead die 40 and the electronic controller 30. Allowing fluid to flow between the printhead die 40 and the ink supply assembly 24.

  FIG. 2 is a diagram illustrating a portion of one embodiment of printhead die 40. Printhead die 40 includes an array of printing elements or fluid ejection elements 42. The printing element 42 is formed on a substrate 44, and an ink supply slot 46 is formed in the substrate. Thus, the ink supply slot 46 provides a source of liquid ink to the printing element 42. The ink supply slot 46 is one embodiment of a fluid supply source. Other embodiments of the fluid supply include, but are not limited to, a plurality of short ink supply trenches each leading to a corresponding individual ink supply hole for supplying a corresponding vaporization chamber and a corresponding group of fluid ejection elements. Formed in the thin film structure 48 is an ink supply channel 54 that communicates with an ink supply slot 46 formed in the substrate 44. The orifice layer 50 has a front surface 50a and a nozzle opening 34 formed in the front surface 50a. The orifice layer 50 also has a nozzle chamber or vaporization chamber 56 formed therein, which communicates with the nozzle opening 34 and the ink supply channel 54 of the thin film structure 48. A firing resistor 52 is disposed in the vaporization chamber 56 and a lead 58 electrically connects the firing resistor 52 to circuitry that controls the flow of current through the selected firing resistor. Droplet generator 60 as referred to herein includes firing resistor 52, nozzle chamber or vaporization chamber 56, and nozzle opening 34.

  During printing, ink flows from the ink supply slot 46 through the ink supply channel 54 to the vaporization chamber 56. When a voltage is applied to firing resistor 52, ink drops in vaporization chamber 56 pass through nozzle opening 34 (eg, generally perpendicular to the plane of firing resistor 52) toward print media 36. The nozzle opening 34 is operatively associated with the firing resistor 52 so as to be discharged.

  Exemplary embodiments of the printhead die 40 can be incorporated into a thermal printhead, piezoelectric printhead, electrostatic printhead, or multilayer structure and any other type known in the art. Including a fluid ejection device. The substrate 44 is formed from, for example, silicon, glass, ceramic, or stable polymer, and the thin film structure 48 is one or more of silicon dioxide, silicon carbide, silicon nitride, tantalum, polysilicon glass, or other suitable material. It is formed to include a plurality of passivation or insulating layers. The thin film structure 48 also includes at least one conductive layer that defines the firing resistor 52 and the lead 58. The conductive layer is formed to include, for example, aluminum, gold, tantalum, tantalum-aluminum, or other metals or alloys. In one embodiment, firing cell circuitry as described in detail below is implemented in the substrate and thin film layers, such as the substrate 44 and thin film structure 48.

  In one embodiment, the orifice layer 50 comprises a photosensitive epoxy resin, for example, an epoxy called SU8 marketed by Micro-Chem (Newton, Mass.). An exemplary technique for forming the orifice layer 50 with SU8 or other polymer is detailed in US Pat. No. 6,162,589, which is hereby incorporated by reference. In one embodiment, the orifice layer 50 comprises a barrier layer (eg, a dry film photoresist barrier layer) and a metal orifice layer (eg, nickel, copper, iron / nickel alloy, palladium, gold or rhodium) formed on the barrier layer. Formed from two separate layers called layers. However, other suitable materials can be used to form the orifice layer 50.

  FIG. 3 is a diagram illustrating a droplet generator 60 disposed along an ink supply slot 46 in one embodiment of the printhead die 40. The ink supply slot 46 includes opposing ink supply slot sides 46a and 46b. A drop generator 60 is disposed along each of the opposing ink supply slot sides 46a and 46b. A total of n droplet generators 60 are disposed along the ink supply slot 46, and m droplet generators 60 are disposed along the ink supply slot side 46a. N−m droplet generators 60 are arranged along. In one embodiment, n is equal to 200 droplet generators 60 disposed along the ink supply slot 46, and m is 100 disposed along each of the opposing ink supply slot sides 46a and 46b. The droplet generator 60 is equal. In other embodiments, any number of suitable droplet generators 60 can be positioned along the ink supply slot 46.

  The ink supply slot 46 supplies ink to each of the n droplet generators 60 arranged along the ink supply slot 46. Each of the n drop generators 60 includes a firing resistor 52, a vaporization chamber 56, and a nozzle 34. Each of the n vaporization chambers 56 is in fluid communication with the ink supply slot 46 through at least one ink supply channel 54. The firing resistor 52 of the drop generator 60 is energized in a control sequence to eject fluid from the vaporization chamber 56 through the nozzle 34 and print an image on the print media 36.

  FIG. 4 is a diagram illustrating one embodiment of a firing cell 70 used in one embodiment of the printhead die 40. The firing cell 70 includes a firing resistor 52, a resistor drive switch 72, and a memory circuit 74. Firing resistor 52 is part of drop generator 60. Drive switch 72 and memory circuit 74 are part of a circuit that controls the flow of current through firing resistor 52. The firing cell 70 is formed in the thin film structure 48 and on the substrate 44.

  In one embodiment, firing resistor 52 is a thin film resistor and drive switch 72 is a field effect transistor (FET). Firing resistor 52 is electrically connected to firing line 76 and the drain-source path of drive switch 72. The drain-source path of the drive switch 72 is also electrically connected to a reference line 78, which is connected to a reference voltage such as ground. The gate of the drive switch 72 is electrically connected to a memory circuit 74 that controls the state of the drive switch 72.

  The memory circuit 74 is electrically connected to the data line 80 and the enable line 82. The data line 80 receives a data signal DATA representing a part of the image, and the enable line 82 receives an enable signal ENABLE that controls the operation of the memory circuit 74. The memory circuit 74 stores 1-bit data in response to being activated by the enable signal. The logic level of the stored data bit sets the state of drive switch 72 (eg, on or off, conducting or non-conducting). The enable signal may include one or more selection signals and one or more address signals.

  Firing line 76 receives an energy signal FIRE that includes an energy pulse and provides an energy pulse to firing resistor 52. In one embodiment, the energy pulse heats the fluid in the vaporization chamber 56 of the droplet generator 60 and provides a determined start time and duration, to provide an appropriate amount of energy sufficient to vaporize it. Therefore, it is provided by the electronic controller 30 to have an end time as a result. When the drive switch 72 is on (conducting), the energy pulse heats the firing resistor 52, heats the fluid, and ejects the fluid from the droplet generator 60. When the drive switch 72 is off (not conducting), the energy pulse does not heat the firing resistor 52 and the fluid remains in the droplet generator 60.

  FIG. 5 is a circuit diagram illustrating one embodiment of an inkjet printhead firing cell array 100. Firing cell array 100 includes a plurality of firing cells 70 arranged as n firing groups 102a-102n. In one embodiment, firing cells 70 are arranged in six firing groups 102a-102n. In other embodiments, the firing cells 70 can be arranged in any suitable number of firing groups 102a-102n, such as four or more firing groups 102a-102n.

The firing cells 70 in the array 100 are schematically arranged in L rows and m columns. The L rows of firing cells 70 are electrically connected to an enable line 104 that receives an enable signal ENABLE. Each row of firing cells 70 is referred to herein as a row subgroup or subgroup of firing cells 70 and is electrically connected to a set of subgroup enable lines 106a-106L. Subgroup enable lines 106a to 106L are connected to subgroup enable signals SG1, SG2,. . . Receiving the SG _L, these signals can activate the corresponding subgroup of firing cells 70.

  The m column includes data signals D1, D2,. . . It is electrically connected to m data lines 108a to 108m that respectively receive Dm. Each of the m columns includes a firing cell 70 in each of the n firing groups 102a-102n, and each column of firing cells 70 is referred to herein as a data line group or data group, and the data lines 108a- It is electrically connected to one of 108m. In other words, each of the data lines 108a-108m is electrically connected to each firing cell 70 in a column, including the firing cells 70 in each firing group 102a-102n. For example, data line 108a is electrically connected to each firing cell 70 in the leftmost column, including firing cells 70 in each firing group 102a-102n. Data line 108b is electrically connected to each firing cell 70 in the adjacent column, and thereafter to each firing cell 70 in the rightmost column, including firing cells 70 in each firing group 102a-102n. The same applies to the electrically connected data line 108m.

  In one embodiment, array 100 is arranged in six firing groups 102a-102n, each of six firing groups 102a-102n including 13 subgroups and 8 data line groups. In other embodiments, the array 100 can be arranged in any suitable number of firing groups 102a-102n, and can be arranged in any suitable number of subgroups and data line groups. In any embodiment, firing groups 102a-102n are not limited to having the same number of subgroups and data line groups. Instead, each firing group 102a-102n can have a different number of subgroups and / or data line groups compared to any other firing group 102a-102n. In addition, each subgroup can have a different number of firing cells 70 compared to any other subgroup, and each data line group can have a different number of firing cells compared to any other data line group. A cell 70 may be included.

  The firing cell 70 in each firing group 102a-102n is electrically connected to one of the firing lines 110a-110n. In the firing group 102a, each firing cell 70 is electrically connected to a firing line 110a that receives a firing signal or energy signal FIRE1. In launch group 102b, each launch cell 70 is electrically connected to launch line 110b that receives a launch signal or energy signal FIRE2, and thereafter each launch cell 110n from which each launch cell 70 receives a launch signal or energy signal FIREn. The same applies to the launch group 102n that is electrically connected to. Furthermore, each firing cell 70 in each firing group 102a-102n is also electrically connected to a common reference line 112 that is connected to ground.

In operation, the subgroup enable signals SG1, SG2,. . . SG _L is given on a subgroup enable lines 106A～106L, 1 subgroup of firing cells 70 is activated. The activated launch cell 70 has data signals D1, D2,. . . Store Dm. Data signals D1, D2. . . Dm is stored in the memory circuit 74 of the activated launch cell 70. Stored data signals D1, D2. . . Each Dm sets the state of one drive switch 72 of the activated firing cells 70. The drive switch 72 is set to be conductive or not conductive based on the stored data signal value.

  After the state of the selected drive switch 72 is set, energy signals FIRE1-FIREn are provided on firing lines 110a-110n corresponding to firing groups 102a-102n, including the selected subgroup of firing cells 70. The energy signals FIRE1 to FIREn include energy pulses. An energy pulse is applied on selected firing lines 110a-100n to apply a voltage to firing resistor 52 in firing cell 70 having drive switch 72 in conduction. The firing resistor 52 to which the voltage is applied heats the ink and ejects it onto the print medium 36, and the data signals D1, D2,. . . Print the image represented by Dm. Activating a subgroup of launch cells 70 and data signals D1, D2,. . . The process of storing Dm and applying energy signals FIRE1-FIREn to apply a voltage to firing resistors 52 in the activated subgroup continues until printing is complete.

In one embodiment, subgroup enable signals SG1, SG2,... Responsive to energy signals FIRE1-FIREn being provided to selected firing groups 102a-102n. . . SG _L selects another subgroup in a different fire groups 102a-102n, changes to boot. The newly activated subgroup includes data signals D1, D2... Provided on the data lines 108a to 108n. . . Dm is stored, energy signals FIRE1-FIREn are applied to one of the firing lines 110a-110n, and a voltage is applied to the firing resistor 52 in the newly activated launch cell 70. At any time, only one subgroup of the firing cells 70 will receive subgroup enable signals SG1, SG2,. . . Is activated by the SG _L, the data signal applied on the data lines 108a-108m D1, D2. . . Store Dm. In this embodiment, data signals D1, D2. . . Dm is a time division multiplexed data signal. Also, only one subgroup in the selected firing group 102a-102n has a drive switch set to conduct while the energy signals FIRE1-FIREn are applied to the selected firing group 102a-102n. Including. However, the energy signals FIRE1-FIREn provided to different firing groups 102a-102n can overlap.

  FIG. 6 is a circuit diagram illustrating one embodiment of the precharged firing cell 120. Precharged firing cell 120 includes a drive switch 172 that is electrically connected to firing resistor 52. In one embodiment, the drive switch 172 is a FET that includes a drain-source path that is electrically connected to one terminal of the firing resistor 52 at one end and electrically connected to the reference line 122 at the other end. The reference line 122 is connected to a reference voltage such as ground. The other terminal of the firing resistor 52 is electrically connected to a firing line 124 that receives a firing signal including an energy pulse or an energy signal FIRE. When the drive switch 172 is on (conducting), the energy pulse applies a voltage to the firing resistor 52.

  The gate of the drive switch 172 forms a storage node capacitance 126, which serves as a memory element for storing data in response to sequentially starting the precharge transistor 128 and the select transistor 130. The storage node capacitance 126 is shown as a dashed line because it is part of the drive switch 172. Alternatively, a capacitor other than the drive switch 172 can be used as the memory element.

  The drain-source path and gate of the precharge transistor 128 are electrically connected to a precharge line 132 that receives the precharge signal PRECHARGE. The gate of the drive switch 172 is electrically connected to the drain-source path of the precharge transistor 128 and the drain-source path of the selection transistor 130. The gate of the selection transistor 130 is electrically connected to a selection line 134 that receives a selection signal SELECT. The precharge signal PRECHARGE is a charge control signal of one type of pulse format. Another type of pulsed charge control signal is a discharge signal used in embodiments of a discharge-type firing cell.

  The data transistor 136, the first address transistor 138, and the second address transistor 140 include drain-source paths that are electrically connected in parallel. A parallel combination of the data transistor 136, the first address transistor 138, and the second address transistor 140 is electrically connected between the drain-source path of the selection transistor 130 and the reference line 122. A series circuit including a select transistor 130 connected to a parallel combination of a data transistor 136, a first address transistor 138, and a second address transistor 140 is electrically connected across the node capacitance 126 of the drive switch 172. The The gate of the data transistor 136 is electrically connected to the data line 142 that receives the data signal to DATA. The gate of the first address transistor 138 is electrically connected to the address line 144 that receives the address signal .about.ADDRESS1, and the gate of the second address transistor 140 is the second address line 146 that receives the address signal .about.ADDRESS2. Is electrically connected. The data signal ~ DATA and the address signals ~ ADDRESS1 and ~ ADDRESS2 are active when low, as indicated by the waveform symbol (~) at the beginning of the signal name. Node capacitance 126, precharge transistor 128, select transistor 130, data transistor 136, and address transistors 138 and 140 form a memory cell.

  In operation, the node capacitance 126 is precharged through the precharge transistor 128 by applying a high level voltage pulse on the precharge line 132. In one embodiment, after a high level voltage pulse is applied on the precharge line 132, the data signal ~ DATA is applied on the data line 142, the state of the data transistor 136 is set, and the address lines 144 and 146 are addressed. Signals .about.ADDRESS1 and .about.ADDRESS2 are applied, and the states of the first address transistor 138 and the second address transistor 140 are set. When a high level voltage pulse is applied on the select line 134, the select transistor 130 is turned on, and the data transistor 136, the first address transistor 138, and / or the second address transistor 140 are on, the node Capacitance 126 is discharged. Alternatively, node capacitance 126 remains charged when data transistor 136, first address transistor 138, and second address transistor 140 are all off.

  When both address signals -ADDRESS1 and -ADDRESS2 are low, the precharged firing cell 120 is the addressed firing cell, and when the data signal -DATA is high, the node capacitance 126 is discharged. However, when the data signal ~ DATA is low, it remains charged. If at least one of the address signals ~ ADDRESS1 and ~ ADDRESS2 is high, the precharged firing cell 120 is not an addressed firing cell and the node capacitance 126 is related to the voltage level of the data signal ~ DATA. Discharge without. The first address transistor 136 and the second address transistor 138 constitute an address decoder, and the data transistor 136 controls the voltage level on the node capacitance 126 when the precharged firing cell 120 is addressed. .

  FIG. 7 is a circuit diagram illustrating one embodiment of an inkjet printhead firing cell array 200. Firing cell array 200 includes a plurality of precharged firing cells 120 arranged in six firing groups 202a-202f. The precharged firing cells 120 in each firing group 202a-202f are schematically arranged in 13 rows and 8 columns. The firing groups 202a-202f and precharged firing cells 120 in the array 200 are diagrammatically arranged in 78 rows and 8 columns.

  The eight columns of precharged firing cells 120 have data signals ~ D1, ~ D2,. . . Are electrically connected to eight data lines 208a to 208h that respectively receive .about.D8. Each of the eight columns, referred to herein as a data line group or data group, includes a precharged firing cell 120 within each of the six firing groups 202a-202f. Each firing cell 120 in each column of precharged firing cells 120 is electrically connected to one of the data lines 208a-202h. All precharged firing cells 120 in a data line group are electrically connected to the same data lines 208a-208h, which is the gate of the data transistor 136 in the precharged firing cells 120 in that column. Is electrically connected. In one embodiment, the data signals ~ D1, ~ D2,. . . -D8 each represents a part of one image. In one embodiment, each of the data lines 208a to 208h is electrically connected to an external control circuit via a corresponding interface data pad.

  Data lines 208a are each electrically connected to precharged firing cells 120 in the leftmost column, including the precharged firing cells in each firing group 202a-202f. Data lines 208b are each electrically connected to precharged firing cells 120 in adjacent columns, and thereafter in the rightmost column that includes precharged firing cells 120 in each firing group 202a-202f. The same applies to the data line 208h electrically connected to each of the precharge-type firing cells 120.

  78 rows of precharged firing cells 120 are address signals ~ A1, ~ A2. . . Are electrically connected to address lines 206a to 206g that respectively receive .about.A7. Each precharged firing cell 120 in a row of precharged firing cells 120 is referred to herein as a row subgroup or a subgroup of precharged firing cells 120, and two of the address lines 206a-206g. Is electrically connected. All precharged firing cells 120 in one row subgroup are electrically connected to the same two address lines 206a-206g.

  The subgroups of launch groups 202a-202f are identified as subgroups SG1-1 to SG1-13 in launch group 1 (FG1) 202a, subgroups SG2-1 to SG2-13 in launch group 2 (FG2) 202b, etc. Thereafter, the same applies to subgroups SG6-1 to SG6-13 in firing group 6 (FG6) 202f. In other embodiments, each firing group 202a-202f can include any suitable number of subgroups, such as 14 or more subgroups.

  Each subgroup of precharged firing cell 120 is electrically connected to two address lines 206a-20g. Two address lines 206a-206g corresponding to one subgroup are electrically connected to the first address transistor 138 and the second address transistor 140 in all the precharged firing cells 120 of the subgroup. . One address line 206a to 206g is electrically connected to one gate of the first address transistor 138 and the second address transistor 140, and the other address line 206a to 206g is connected to the first address transistor 138. And the other gate of the second address transistor 140 is electrically connected. Address lines 206a to 206g are connected to address signals ~ A1, ~ A2. . . ˜A7 are received and the address signals ˜A1, ˜A2. . . ~ A7 is given to a subgroup of array 200 as follows.

  In other embodiments, the address lines 206a-206g are at any suitable connection between the address lines 206a-206g and the subgroup to provide any suitable mapping between the row subgroup address signal and the row subgroup. It is electrically connected to a subgroup of array 200.

  A sub-group of precharged firing cells 120 has address signals ~ A1, ~ A2. . . Addressed by giving ~ A7. In one embodiment, address lines 206a-206g are electrically connected to one or more address generators provided on printhead die 40. In other embodiments, the address lines 206a-206g are electrically connected to an external control circuit by interface pads.

  Precharge lines 210a to 210f are connected to precharge signals PRE1, PRE2,. . . PRE6 is received and precharge signals PRE1, PRE2,. . . PRE6 is given to the corresponding firing group 202a-202f. Precharge line 210a is electrically connected to all prechargeable firing cells 120 in FG1 202a. Precharge line 210b is electrically connected to all precharged firing cells 120 in FG2 202b, and thereafter precharged line 210f electrically connected to all precharged firing cells 120 in FG6 202f. The same applies until. Precharge lines 210a-210f are electrically connected to the gate and drain-source paths of all precharge transistors 128 in the corresponding firing group 202a-202f, respectively, and are connected to all precharge lines 202a-202f. Rechargeable firing cell 120 is electrically connected to only one precharge line 210a-210f. Thus, the node capacitances 126 of all precharged firing cells 120 in firing groups 202a-202f are connected to corresponding precharge lines 210a-210f with corresponding precharge signals PRE1, PRE2,. . . Charged by giving PRE6. In one embodiment, each precharge line 210a-210f is electrically connected to an external control circuit via a corresponding interface pad.

  The selection lines 212a to 212f are connected to the selection signals SEL1, SEL2,. . . SEL6 is received and the selection signals SEL1, SEL2. . . SEL6 is given to the corresponding firing group 202a-202f. Select line 212a is electrically connected to all precharged firing cells 120 in FG1 202a. Selection line 212b is electrically connected to all prechargeable firing cells 120 in FG2 202b and thereafter to selection line 212f electrically connected to all prechargeable firing cells 120 in FG6 202f. It is the same. Each select line 212a-212f is electrically connected to the gate of all select transistors 130 in the corresponding fire group 202a-202f, and all precharged fire cells 120 in one fire group 202a-202f are It is electrically connected to only one selection line 212a to 212f. In one embodiment, each select line 212a-212f is electrically connected to an external control circuit via a corresponding interface pad. In one embodiment, some of the precharge lines 210a to 210f and some of the selection lines 212a to 212f are electrically connected to each other and share an interface pad.

  The firing lines 214a to 214f are fire signals or energy signals FIRE1, FIRE2,. . . FIRE6 is received and energy signals FIRE1, FIRE2,. . . FIRE6 is given to the corresponding fire group 202a-202f. Firing line 214a is electrically connected to all precharged firing cells 120 in FG1 202a. Launch line 214b is electrically connected to all precharged firing cells 120 in FG2 202b and thereafter to launch line 214f that is electrically connected to all precharged firing cells 120 in FG6 202f. It is the same. Each firing line 214a-214f is electrically connected to all firing resistors 52 in the corresponding firing group 202a-202f, and all precharged firing cells 120 in one firing group 202a-202f are just It is electrically connected to one firing line 214a to 214f. The firing lines 214a to 214f are electrically connected to an external power supply circuit through appropriate interface pads. All precharged firing cells 120 in array 200 are electrically connected to a reference line 216 that is connected to a reference voltage such as ground. Thus, precharged firing cells 120 within the row subgroup of precharged firing cells 120 are electrically connected to the same address lines 206a-206g, precharge lines 210a-210f, select lines 212a-212f and firing lines 214a-214f. Connected to.

  In operation, in one embodiment, firing groups 202a-202f are selected and fired one after another. FG1 202a is selected before FG2 202b, FG2 202b is selected before FG3, and so on until FG6 202f. After FG6 202f, at FG1 202a, the first group cycle begins anew.

  Address signals ~ A1, ~ A2. . . ~ A7 cycle through 13 row subgroup addresses before repeating row subgroup addresses. Address signals .about.A1, .about.A2... Applied on address lines 206a to 206g. . . ˜A7 is set to one row subgroup address each time the shooting groups 202a to 202f make a round. Address signals ~ A1, ~ A2. . . ~ A7 selects one row subgroup in each fire group 202a-202f while cycling through fire groups 202a-202f. During the next round of firing groups 202a-202f, address signals ~ A1, ~ A2. . . ~ A7 is modified to select a different row subgroup in each firing group 202a-202f. This is because the address signals ~ A1, ~ A2. . . -A7 is continued until the last row subgroup in fire group 202a-202f is selected. After the last row subgroup, the address signals ~ A1, ~ A2. . . ~ A7 selects the first row subgroup and repeats the address cycle.

  In another aspect of operation, one of the firing groups 202a-202f is precharged on the precharge lines 210a-210f of one firing group 202a-202f. . . Operates by giving PRE6. Precharge signals PRE1, PRE2,. . . PRE6 defines a precharge time interval or period, during which time the node capacitance 126 on each drive switch 172 in one firing group 202a-202f to precharge one firing group 202a-202f. Is charged to a high voltage level.

  Address signals ~ A1, ~ A2. . . ~ A7 is provided on address lines 206a-206g to address one row subgroup in each firing group 202a-202f, including one row subgroup in precharged firing groups 202a-202f. Data signals ~ D1, ~ D2. . . ~ D8 is provided on data lines 208a-208h to provide data to all firing groups 202a-202f, including the addressed row subgroup in precharged firing groups 202a-202f.

  Next, the selection signals SEL1, SEL2,. . . SEL6 is applied on selection lines 212a-212f of precharged firing groups 202a-202f to select precharged firing groups 202a-202f. Select signals SEL1, SEL2. . . SEL6 is not in the addressed row subgroup in the selected firing group 202a-202f or is addressed in the selected firing group 202a-202f, and the high level data signals D1, -D2. . . Define a discharge time interval for discharging the node capacitance 126 on each drive switch 172 in the precharged firing cell 120 receiving -D8. Node capacitance 126 is addressed in the selected firing group 202a-202f and low level data signals ~ D1, ~ D2. . . The precharged firing cell 120 receiving ~ D8 does not discharge. A high voltage level on node capacitance 126 turns drive switch 172 on (conducts).

  After the drive switch 172 in the selected firing group 202a-202f is set to conduct or not conduct, an energy pulse or voltage pulse is present on the firing lines 214a-214f of the selected firing group 202a-202f. Given. A precharged firing cell 120 having a conducting drive switch 172 conducts current through the firing resistor 52 to heat the ink and eject ink from the corresponding droplet generator 60.

  When the fire groups 202a to 202f are operating one after another, the selection signals SEL1, SEL2,. . . SEL6 receives precharge signals PRE1, PRE2... For the next firing group 202a-202f. . . Used as PRE6. Precharge signals PRE1, PRE2... For one firing group 202a-202f. . . PRE6 receives select signals SEL1, SEL2,. . . SEL6 and energy signals FIRE1, FIRE2. . . Prior to FIRE6. Precharge signals PRE1, PRE2,. . . After PRE6, data signals D1,. . . ... D8 are multiplexed in time to select signals SEL1, SEL2. . . SEL6 stores it in the addressed row subgroup of its firing group 202a-202f. Select signals SEL1, SEL2... For selected fire groups 202a-202f. . . SEL6 receives precharge signals PRE1, PRE2... For the next firing group 202a-202f. . . It is also PRE6. Select signals SEL1, SEL2... For selected fire groups 202a-202f. . . After SEL6 is completed, select signals SEL1, SEL2,. . . SEL6 is given. The precharged firing cells 120 in the selected firing group 202a-202f receive energy signals FIRE1, FIRE2,. . . In response to FIRE 6 being applied to the selected firing group 202a-202f, the stored data signals D1, -D2. . . Fire or heat ink based on ~ D8.

  FIG. 8 is a timing diagram illustrating the operation of one embodiment of firing cell array 200. Firing groups 202a-202f are selected one after the other and data signals ~ D1, ~ D2. . . A voltage is applied to the precharged firing cell 120 based on ~ D8. 300 data signals ~ D1, ~ D2. . . ~ D8 is changed as needed, as shown at 302, for each combination of row subgroup address and firing groups 202a-202f. 304 address signals ~ A1, ~ A2. . . ~ A7 is provided on address lines 206a-206g to address one row subgroup from each firing group 202a-202f. 304 address signals ~ A1, ~ A2. . . -A7 is set to one address each time it makes a round of the firing groups 202a-202f, as shown at 306. After the cycle is complete, address signals ~ A1, ~ A2. . . ~ A7 is changed at 308 to address a different row subgroup from each firing group 202a-202f. 304 address signals ~ A1, ~ A2. . . ~ A7 increments for each row subgroup, sequentially addresses the row subgroup from 1 to 13, and returns to 1. In other embodiments, the address signals ~ A1, ~ A2. . . ~ A7 can be set to address row subgroups in any suitable order.

  While making a round of firing groups 202a-202f, select line 212f connected to FG6 202f and precharge line 210a connected to FG1 202a receive SEL6 / PRE1 signal 309, including SEL6 / PRE1 signal pulse 310. Receive. In one embodiment, select line 212f and precharge line 210a are electrically connected to each other to receive the same signal. In another embodiment, select line 212f and precharge line 210a are not electrically connected to each other and receive similar signals.

  The SEL6 / PRE1 signal pulse at 310 on precharge line 210a precharges all firing cells 120 in FG1 202a. The node capacitance 126 for each prechargeable firing cell 120 in FG1 202a is charged to a high voltage level. Node capacitance 126 for precharged firing cells 120 in one row subgroup SG1-K shown at 311 is precharged to 312 at a high voltage level. The row subgroup address in 306 selects subgroup SG1-K, and the data signal set in 314 includes all pre-groups in all firing groups 202a-202f, including the address selected row subgroup SG1-K. The data transistor 136 in the rechargeable firing cell 120 is provided.

  Select line 212a for FG1 202a and precharge line 210b for FG2 202b receive SEL1 / PRE2 signal 315, including SEL1 / PRE2 signal pulse 316. A SEL1 / PRE2 signal pulse 316 on select line 212a turns on select transistor 130 in each precharged firing cell 120 in FG1 202a. Node capacitance 126 is discharged in all precharged firing cells 120 in FG1 202a that are not in the addressed row subgroup SG1-K. In the address selected row subgroup SG1-K, the data at 314 is stored in the node capacitance 126 of the drive switch 172 in the row subgroup SG1-K, as shown at 318, turning on the drive switch. (Conduct) or turn off (do not conduct).

  The SEL1 / PRE2 signal pulse at 316 on precharge line 210b precharges all firing cells 120 in FG2 202b. The node capacitance 126 for each prechargeable firing cell 120 in FG2 202b is charged to a high voltage level. The node capacitance 126 for the precharged firing cell 120 in one row subgroup SG2-K shown at 319 is precharged at 320 to a high voltage level. The row subgroup address at 306 selects subgroup SG2-K, and the data signal set at 328 includes all pregroups for all firing groups 202a-202f that include the addressed row subgroup SG2-K. The data transistor 136 in the rechargeable firing cell 120 is provided.

  The firing line 214a includes the energy pulses shown at 323, including 322 energy pulses, to apply a voltage to the firing resistor 52 in the precharged firing cell 120 with the conductive drive switch 172 in FG1 202a. The signal FIRE1 is received. While the SEL1 / PRE2 signal pulse 316 is high and the node capacitance 126 on the non-conducting drive switch 172 is actively pulled low, as shown at 324 on the energy signal FIRE1 323, the FIRE1 energy Pulse 322 goes high. By switching energy pulse 322 high while node capacitance 126 is actively pulled low, node capacitance 126 is erroneously charged through drive switch 172 in response to energy pulse 322 going high. To prevent. The SEL1 / PRE2 signal 315 goes low, the energy pulse 322 is applied to the FG1 202a for a predetermined time, the ink is heated, and the ink is ejected through the nozzle 34 corresponding to the conducting precharged firing cell 120. The

  Select line 212b for FG2 202b and precharge line 210c for FG3 202c receive SEL2 / PRE3 signal 325, including SEL2 / PRE3 signal pulse 326. After the SEL1 / PRE2 signal pulse 316 transitions low and while the energy pulse 322 is high, the SEL2 / PRE3 signal pulse 326 on the select line 212b is within each precharged firing cell 120 in FG2 202b. The selection transistor 130 is turned on. Node capacitance 126 is discharged in all precharged firing cells 120 in FG2 202b that are not in the addressed row subgroup SG2-K. As shown at 330, a data signal set 328 for the subgroup SG2-K is stored in the precharged firing cell 120 of the subgroup SG2-K, and the drive switch 172 is on (conducting) or off (nonconducting). ). The SEL2 / PRE3 signal pulse on precharge line 210c precharges all precharged firing cells 120 in FG3 202c.

  To apply a voltage to firing resistor 52 in precharged firing cell 120 of FG2 202b with drive switch 172 conducting, firing line 214b includes energy pulse 322, energy signal FIRE2 shown at 331. Receive. As shown at 334, the FIRE2 energy pulse 332 transitions high while the SEL2 / PRE3 signal pulse 326 is high. The SEL2 / PRE3 signal pulse 326 goes low, the FIRE2 energy pulse 332 remains high, the ink is heated, and ink is ejected from the corresponding droplet generator 60.

  The SEL3 / PRE4 signal is applied to select FG3 202c and precharge FG4 202d after the SEL2 / PRE3 signal pulse 326 goes low and while the energy pulse 332 is high. The process of precharging, selecting and providing an energy signal including an energy pulse continues until FG6 202f.

  The SEL5 / PRE6 signal pulse on precharge line 210f precharges all firing cells 120 in FG6 202f. The node capacitance 126 for each prechargeable firing cell 120 in FG6 202f is charged to a high voltage level. Node capacitance 126 for precharged firing cell 120 in one row subgroup SG6-K shown at 339 is precharged to a high voltage level at 341. The row subgroup address at 306 selects subgroup SG6-K and data signal set 338 includes all precharged firings of all firing groups 202a-202f that include the addressed row subgroup SG6-K. This is applied to the data transistor 136 in the cell 120.

  Select line 212f for FG6 202f and precharge line 210a for FG1 202a receive a second SEL6 / PRE1 signal pulse at 336. A second SEL6 / PRE1 signal pulse 336 on select line 212f turns on select transistor 130 in each precharged firing cell 120 in FG6 202f. Node capacitance 126 is discharged in all precharged firing cells 120 in FG6 202f that are not in the addressed row subgroup SG6-K. In the addressed row subgroup SG6-K, data 338 is stored at 340 in the node capacitance 126 of each drive switch 172, turning the drive switch on or off.

  The SEL6 / PRE1 signal on precharge line 210a causes the node capacitance 126 in all firing cells 120 in FG1 202a, including firing cells 120 in row subgroup SG1-K, shown at 342 to be at a high voltage level. Precharge until. Address signals ~ A1, ~ A2. . . While ~ A7 304 selects row subgroups SG1-K, SG2-K, and finally to row subgroup SG6-K, firing cells 120 in FG1 202a are precharged.

  The firing line 214f includes energy pulses 344 including 344 energy pulses to apply a voltage to the firing resistor 52 in the pre-charged firing cell 120 having a conducting drive switch 172 in FG6 202f. A signal FIRE6 is received. While the SEL6 / PRE1 signal pulse 336 is high and the node capacitance 126 on the non-conducting drive switch 172 is actively pulled low, the energy pulse 344 transitions high as shown at 346. . By switching energy pulse 344 high while node capacitance 126 is actively pulled low, node capacitance 126 is erroneously charged through drive switch 172 in response to energy pulse 344 going high. To prevent. The SEL6 / PRE1 signal pulse 336 goes low, the energy pulse 344 is held high for a predetermined time, the ink is heated, and ink is ejected through the nozzle 34 corresponding to the conducting precharged firing cell 120. The

  After the SEL6 / PRE1 signal pulse 336 goes low and while the energy pulse 344 is high, at 308 the address signals ~ A1, ~ A2. . . ... -A7 304 is modified to select another set of subgroups SG1-K + 1, SG2-K + 1, and finally SG6-K + 1. Select line 212a for FG1 202a and precharge line 210b for FG2 202b receive the SEL1 / PRE2 signal pulse, shown at 348. A SEL1 / PRE2 signal pulse 348 on select line 212a turns on select transistor 130 in each precharged firing cell 120 in FG1 202a. Node capacitance 126 is discharged in all precharged firing cells 120 in FG1 202a that are not in the addressed subgroup SG1-K + 1. To turn drive switch 172 on or off, a data signal set 350 for row subgroup SG1-K + 1 is stored in precharged firing cell 120 of subgroup SG1-K + 1. The SEL1 / PRE2 signal pulse 348 on precharge line 210b precharges all firing cells 120 in FG2 202b.

  To apply a voltage to firing resistor 52 and precharged firing cell 120 of FG1 202a with drive switch 172 conducting, firing line 214a receives energy pulse 352. While the SEL1 / PRE2 signal pulse at 348 is high, the energy pulse 352 goes high. The SEL1 / PRE2 signal pulse 348 goes low and the energy pulse 352 remains high, the ink is heated and ink is ejected from the corresponding liquid generator 60. The process continues until printing is complete.

  FIG. 9 is a circuit diagram illustrating one embodiment of a prechargeable firing cell 150 configured to latch data. In one embodiment, the precharged firing cell 150 is part of a current firing group that is part of an inkjet printhead firing cell array. The inkjet printhead firing cell array includes a plurality of firing groups.

  The precharged firing cell 150 is similar to the precharged firing cell 120 of FIG. 6 and includes the drive switch 172, firing resistor 52, and memory cell of the precharged firing cell 120. The components of the precharged firing cell 150 that match the components of the precharged firing cell 120 have the same numbers as the components of the precharged launch cell 120 and are described in the description of FIG. Although not electrically connected to the signal line, the gate of the data transistor 136 is not connected to the data line 142 that receives the data signal ~ DATA, but the latch output that receives the latched data signal ~ LDATAIN. The difference is that it is electrically connected to the data line 156. Further, the components of the precharged firing cell 150 that match the components of the precharged firing cell 120 function and operate as described in the description of FIG.

  Precharge firing cell 150 includes a data latch transistor 152 that includes a drain-source path that is electrically connected between data line 154 and latch output data line 156. Data line 154 receives the data signal ~ DATAIN, and data latch transistor 152 latches the data into precharged firing cell 150 and provides the latched data signal ~ LDATAIN. The data signal ~ DATAIN and the latched data signal ~ LDATAIN are active when low, as indicated by the waveform symbol (~) at the beginning of the signal name. The gate of the data latch transistor 152 is electrically connected to a precharge line 132 that receives a precharge signal for the current firing group.

  In another embodiment, the gate of data latch transistor 152 is not electrically connected to precharge line 132 of the current firing group. Instead, the gate of data latch transistor 152 is electrically connected to a different signal line that provides a pulse signal, such as a precharge line of another firing group.

  In one embodiment, the data latch transistor 152 is coupled between the latch output data line 156 and the gate-source node of the data latch transistor 152 when the precharge signal transitions from a high voltage level to a low voltage level. In order to minimize charge sharing, it is the smallest transistor size. This charge sharing reduces the data latched to the high voltage level. Also, in one embodiment, when the precharge signal is at a low voltage level and the smallest sized transistor keeps the capacitance seen on the data signal line 154 low, the drain of the data latch transistor 152 is connected to this capacitance. To decide.

  The data latch transistor 152 passes data from the data line 154 to the latch output data line 156 and the latch output data storage node capacitance 158 according to the high level precharge signal. The data is latched onto the latch output data line 154 and the latch output data storage node capacitance 158 as the precharge signal transitions from a high level to a low level. The latch output data storage node capacitance 158 is shown as a dashed line because it is part of the data transistor 136. Alternatively, a capacitor separate from data transistor 136 can be used to store the latched data.

  The latch output data storage node capacitance 158 is large enough to remain generally high when the precharge signal transitions from high to low. Also, the latch output data storage node capacitance 158 is sufficiently large to remain generally at a low level when an energy pulse is provided by the firing signal FIRE and a high voltage pulse is provided in the select signal SELECT. Further, the data transistor 136 is small enough to hold a low level on the latch output data storage node capacitance 158 when the gate of the drive switch 172 is discharged and before the start of the energy pulse in the firing signal FIRE. , Large enough to completely discharge the gate of the drive switch 172.

  In one embodiment, multiple precharged firing cells use the same data and share the same data latch transistors 152 and 156 latched data signals ~ LDATAIN. 156 latched data signals ~ LDATAIN are latched once and used by multiple precharged firing cells. This increases the capacitance on any individual latch output data line 156, making it less susceptible to switching problems and reducing the total capacitance driven through the data line 154.

  In operation, the data signal ~ DATAIN is received by the data line 154 and provides a high level voltage pulse on the precharge line 132 to cause the latch output data line 156 and the latch output data storage node capacitance through the data latch transistor 152. 158. Also, the storage node capacitance 126 is precharged through the precharge transistor 128 by a high level voltage pulse on the precharge line 132. In response to the voltage pulse on precharge line 132 transitioning from a high voltage level to a low voltage level, data latch transistor 152 is turned off and latched data signal .about.LDATAIN is applied. While the precharge signal is at the high voltage level, data to be latched in the precharged firing cell 150 is provided and held until after the precharge signal transitions to the low voltage level. In contrast, data to be latched in the precharged firing cell 120 of FIG. 6 is provided while the select signal is at a high voltage level.

  In another embodiment, the gate of data latch transistor 152 is not electrically connected to precharge line 132 of the current firing group. Instead, the gate of data latch transistor 152 is electrically connected to the precharge line of another firing group. The data signal ~ DATAIN is received by data line 154, and the latch output data line 156 and latch output data storage node capacitance are passed through data latch transistor 152 by applying a high level voltage pulse on the precharge line of the other firing group. 158. In response to the voltage pulse on the precharge line of the other firing group transitioning from the high voltage level to the low voltage level, the data latch transistor 152 is turned off and the latched data signal ~ LDATAIN is provided. Storage node capacitance 126 is precharged via precharge transistor 128 by a high level voltage pulse on precharge line 132. A high voltage pulse on precharge line 132 occurs after the voltage pulse on the precharge line of the other firing group transitions from a high voltage level to a low voltage level.

  In one embodiment, the gate of a data latch transistor, such as data latch transistor 152, of the first precharged firing cell in the current firing group is different from the current firing group. Electrically connected to the precharge line. Also, the gate of a data latch transistor, such as data latch transistor 152, of a second precharged firing cell in the current firing group is different from the first firing group and the current firing group. Is electrically connected to the second precharge line. Data line 154 provides data during the high voltage level of the precharge signal of the first and second firing groups. The data latched in the first and second precharged firing cells is used via the precharge and selection signals of the current launch cell. In one embodiment, the data lines 154 are not electrically connected to all firing groups in the inkjet printhead firing cell array.

  In one embodiment of precharged firing cell 150, after a high level voltage pulse on precharge line 132, address signals ~ ADDRESS1 and ~ ADDRESS2 are provided on address lines 144 and 146, and first address transistor 138 and The state of the second address transistor 140 is set. When a high level voltage pulse is applied on the select line 134, the select transistor 130 is turned on, and the data transistor 136, the first address transistor 138, and / or the second address transistor 140 are on, the storage node Capacitance 126 is discharged. Alternatively, storage node capacitance 126 remains charged when data transistor 136, first address transistor 138, and second address transistor 140 are all off.

  If the address signals ~ ADDRESS1 and ~ ADDRESS2 are both low, the precharged launch cell 150 is the addressed launch cell, and if the latched data signal ~ LDATAIN is high, the storage node Capacitance 126 is discharged, and storage node capacitance 126 remains charged when the latched data signal ~ LDATAIN is low. If at least one of the address signals ~ ADDRESS1 and ~ ADDRESS2 is high, the precharged firing cell 150 is not an addressed firing cell and the storage node capacitance 126 is not latched data signal ~ LDATAIN. Discharge regardless of the voltage level. The first address transistor 136 and the second address transistor 138 constitute an address decoder, and when the precharged firing cell 150 is addressed, the data transistor 136 controls the voltage level on the storage node capacitance 126. To do.

  FIG. 10 is a circuit diagram illustrating one embodiment of a double data rate firing cell circuit 400. Double data rate firing cell circuit 400 latches two data bits from each data line at each high voltage pulse in the precharge signal. Thus, the voltage can be applied to twice as many firing resistors without increasing the firing frequency or without increasing the number of input pads. For example, by increasing the number of drop generators on the printhead and using the same number of input pads, or by using the same number of drop generators on the printhead and reducing the number of input pads, The number of droplet generators per input pad can be increased. The higher the number of drop generators in the printhead, the higher the quality and / or the faster the printing speed. Also, printheads with fewer input pads typically cost less than printheads with more input pads.

  Double data rate firing cell circuit 400 includes a plurality of firing groups, such as firing group 402, and a clock latch circuit 404. Firing group 402 comprises a plurality of precharged firing cells 150 configured to latch data and a plurality of row subgroups such as row subgroup 406. Row subgroup 406 includes precharged firing cells 150a-150m.

  Each precharged firing cell 150 in firing group 402 is electrically connected to precharge line 408 for receiving precharge signal PRECHARGE and electrically connected to select line 410 for receiving selection signal SELECT. And electrically connected to firing line 412 to receive firing signal FIRE. Each precharged firing cell 150a-150m in row subgroup 406 is electrically connected to a first address line 414 to receive a first address signal -ADDRESS1, and a second address signal -ADDRESS2 is received. It is electrically connected to the second address line 416 for receiving. The precharged firing cell 150 receives signals and operates as described in the description of FIG.

  The clock latch circuit 404 includes clock latch transistors 418a to 418n. The gate of each clock latch transistor 418a-418n is electrically connected to clock line 420 for receiving data clock signal DCLK. The drain-source path of each clock latch transistor 418a-418n has a data signal ~ D1,. . . Is electrically connected to one of the data lines 422a to 422n to receive one of. The other side of the drain-source path of each clock latch transistor 418a-418n is connected to the firing group 402 in double data rate firing cell circuit 400 and all other firing groups via corresponding clock data lines 424a-424n. Are electrically connected to the pre-charged firing cell 150. All precharged firing cells 150 in one data line group are electrically connected to only one of the clock latch transistors 418a-418n, causing the precharge signal to transition to a low voltage level, , And 420 in response to the transition of the data clock signal DCLK to a low voltage level. . . A sufficient capacitance to ensure that the charge sharing by ~ DCn is small enough to keep the minimum high voltage level in the data latched in the precharged firing cell 150 is sufficient for the clock latch output data line It exists reliably on 424a-424n.

  In other embodiments, each clock latch transistor 418a-418n and corresponding clock data line 424a-424n can be divided into multiple transistors and multiple data lines. In one embodiment, one of the plurality of transistors corresponding to one of the clock latch transistors 418a-418n and one of the plurality of data lines corresponding to one of the clock data lines 424a-424n. One is connected to the nozzle of the firing group on one side of the fluid channel. In addition, another one of a plurality of transistors corresponding to the same one of the clock latch transistors 418a to 418n and a plurality of data lines corresponding to the same one of the clock data lines 424a to 424n Another data line is connected to the firing group nozzle on the other side of the fluid channel. In one embodiment, each nozzle can be connected to an individual one of the plurality of transistors via an individual data line of the plurality of data lines.

  Clock latch transistor 418a includes a drain-source path that is electrically connected to data line 422a at one end to receive data signal ~ D1. The other end of the drain-source path of clock latch transistor 418a includes precharged firing cells 424a that include precharged firing cells 150 in firing group 402 in double data rate firing cell circuit 400 and in other firing groups. The cell 150a and all precharged firing cells 150 in the same column or data line group as the precharge firing cell 150a are electrically connected. The drain-source path of the clock latch transistor 418a is electrically connected to the data line 154 and is electrically connected to the drain-source path of the data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. Connected. Clock latch transistor 418a receives data signal ~ D1 at 422a and provides clock data signal ~ DC1 to a data line group including precharged firing cell 150a at 424a.

  Data line 422a is the same as precharged launch cell 150b and precharged launch cell 150b, including precharged launch cell 150 in launch group 402 in double data rate launch cell circuit 400 and in other launch groups. It is also electrically connected to all precharged firing cells 150 in the column or data line group. Data line 422a is electrically connected to data line 154 and electrically connected to the drain-source path of data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. The data line group including the precharged firing cell 150b receives the data signal ~ D1 at 422a.

  Clock latch transistor 418b includes a drain-source path that is electrically connected to data line 422b at one end to receive data signal ~ D2. The other end of the drain-source path of clock latch transistor 418b includes a precharged firing cell at 424b that includes precharged firing cells 150 in firing group 402 in double data rate firing cell circuit 400 and in other firing groups. The cell 150c and all precharged firing cells 150 in the same column or data line group as the precharge firing cell 150c are electrically connected. The drain-source path of clock latch transistor 418b is electrically connected to data line 154 and is electrically connected to the drain-source path of data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. Connected. Clock latch transistor 418b receives data signal ~ D2 at 422b and provides clock data signal ~ DC2 to the data line group including precharged firing cell 150c at 424b.

  Data line 422b is the same as precharged launch cell 150b and precharged launch cell 150b, including precharged launch cell 150 in launch group 402 in double data rate launch cell circuit 400 and in other launch groups. It is also electrically connected to all precharged firing cells 150 in the column or data line group. Data line 422b is electrically connected to data line 154 and electrically connected to the drain-source path of data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. The data line group including the precharged firing cell 150b receives the data signal ~ D2 at 422b.

  The remaining clock latch transistors 418 in clock latch circuit 404 are similarly up to clock latch transistor 418n including a drain-source path that is electrically connected at one end to data line 422n to receive the data signal ~ Dn. Electrically connected to precharged firing cell 150 in double data rate firing cell circuit 400. The other end of the drain-source path of clock latch transistor 418n includes precharged firing cells 424n that include precharged firing cells 150 in firing group 402 in double data rate firing cell circuit 400 and in other firing groups. It is electrically connected to cell 150m-1 and electrically connected to all precharged firing cells 150 in the same column or data line group as precharged firing cell 150m-1. The drain-source path of the clock latch transistor 418n is electrically connected to the data line 154 and is electrically connected to the drain-source path of the data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. Connected. The clock latch transistor 418n receives the data signal ~ Dn at 422n and provides the clock data signal ~ DCn to the data line group including the precharged firing cell 150m-1 at 424n.

  Data line 422n is the same as precharged launch cell 150n and precharged launch cell 150m, including precharged launch cell 150 in launch group 402 in double data rate launch cell circuit 400 and in other launch groups. It is also electrically connected to all precharged firing cells 150 in the column or data line group. Data line 422n is electrically connected to data line 154 and electrically connected to the drain-source path of data latch transistor 152 in each precharged firing cell 150 in the corresponding data line group. The data line group including the precharged firing cell 150m receives the data signal ~ Dn at 422n.

  Each of the data lines 422a-422n charges a latch output data line node via a data latch transistor 152 in a precharged firing cell 150 in a firing group that is receiving a high voltage level precharge signal. Also, data lines 422a-422n are each in a firing group that charges clock latch output data lines 424a-424n and receives a high voltage level precharge signal at each high voltage pulse in data clock signal CLK. The latch output data line node attached to the data line is charged via the data latch transistor 152 in the precharge type firing cell 150. The data node being charged via data lines 422a-422n has a capacitance that is slightly higher than the gate capacitance of the non-double data rate firing cell circuit.

  In this embodiment, approximately half of the precharged firing cells 150 are clock data signals ~ DC1,. . . ~ Electrically connected to receive DCn, approximately half of the precharged firing cells 150 are connected to the data signals ~ D1,. . . ~ Dn is electrically connected to receive. Also, every other precharged firing cell 150 in a row subgroup is connected to clock data signals ~ DC1,. . . ~ Electrically connected to receive DCn, and other launch cells are connected to the data signals ~ D1,. . . ~ Dn is electrically connected to receive. In other embodiments, any suitable percentage of precharged firing cells 150 are connected to clock data signals ~ DC1,. . . ~ DCn can be connected to receive any suitable percentage of the data signals ~ D1,. . . ~ Dn can be connected to receive. In other embodiments, the precharged firing cells 150 are connected in any suitable order or pattern, or out of order, with the clock data signal ~ DC1,. . . ~ DCn and data signals ~ D1,. . . ~ Dn can be connected to receive.

  Each data signal ~ D1,. . . ~ Dn includes the first data bit during the first half of the high voltage pulse in the precharge signal PRECHARGE and the second data bit during the other half of the high voltage pulse. The clock signal DCLK also includes a high voltage pulse in the first half of the high voltage pulse in the precharge signal PRECHARGE.

  In operation, the precharge signal PRECHARGE and the clock signal DCLK transition to a high voltage level and each data signal .about.D1,. . . ~ Dn includes a first data bit that is provided to the corresponding clock latch transistor 418a-418n during a high voltage pulse in clock signal DCLK. Clock latch transistors 418a-418n transfer the first data bit to the precharged firing cells 150a, 150c,. . . Pass to 150m-1. In response to the high voltage pulse in clock signal DCLK transitioning to a low voltage level, clock latch transistors 418a-418n latch the first data bit and clock data signals -DC1,. . . ~ DCn is given. The first data bit is stored in the corresponding data line group of precharged firing cells 150b, 150d,. . . Also given to 150m.

  Next, each data signal ~ D1,. . . ˜Dn during the other half of the high voltage pulse in the precharge signal PRECHARGE, the corresponding clock latch transistors 418a-418n, and the precharged firing cells 150b, 150d,. . . Including the second data bit given at 150m. The clock latch transistors 418a-418n are turned off by the low voltage level of the clock signal CLK, and the second data bit is sent to the precharged firing cells 150a, 150c,. . . Prevent crossing over 150m-1.

  Clock data signal to DC1,. . . ~ DCn and data signals ~ D1,. . . The second data bit in ˜Dn is received by all precharged firing cells 150 in the corresponding data line group in double data rate firing cell circuit 400. In firing group 402, clock data signals ~ DC1,. . . ~ DCn and data signals ~ D1,. . . The second data bit in ˜Dn is received by the data line 154 in the precharged firing cell 150, and the latch output data line 156 and the data latch transistor 152 and the high level voltage pulse in the precharge signal PRECHARGE Passed to latch output data storage node capacitance 158. Also, in the firing group 402, the storage node capacitance 126 is precharged through the precharge transistor 128 by a high level voltage pulse in the precharge signal PRECHARGE. Next, in the firing group 402, in response to the precharge signal PRECHARGE transitioning to a low level voltage, the data latch transistor 152 is turned off and the clock data signal ~ DC1,. . . ~ DCn and data signals ~ D1,. . . The second data bit in .about.Dn is latched and the latched data signal .about.LDATAIN is applied.

  In one embodiment of precharged firing cell 150, address signals ~ ADDRESS1 and ~ ADDRESS2 are provided to select row subgroup 406 after a high level voltage pulse in precharge signal PRECHARGE transitions to a low voltage level. Then, a high level voltage pulse is applied in the selection signal SELECT, and the selection transistor 130 is turned on. In row subgroup 406, storage node capacitance 126 is discharged when latched data signal ~ LDATAIN is high, and remains charged when latched data signal ~ LDATAIN is low. In row subgroups that are not addressed, the storage node capacitance 126 discharges regardless of the voltage level of the latched data signal ~ LDATAIN. An energy pulse is provided in the firing signal FIRE and a voltage is applied to the firing resistor 52 connected to the conductive drive switch 172 in the row subgroup 406.

  In one embodiment, applying a voltage to the precharged firing cell 150 in the double data rate firing cell circuit 400 provides a clock in the first data bit and precharges the firing cell 150 in another firing group. To be continued. The clock data signal and the second data bit are latched into the precharged firing cell 150 by the falling edge of the precharge signal and an address signal is provided to select one row subgroup. To apply a voltage to conducting precharged firing cells 150 in other firing groups, a high voltage level pulse in the selection signal and an energy pulse in the firing signal are provided. This process continues until fluid ejection is complete.

  In other embodiments, the firing cell circuit may latch any suitable number of data bits, such as three or more data bits, at each high voltage pulse in the precharge signal PRECHARGE. Any number of clock latch circuits may be included, such as clock latch circuit 404. For example, the launch cell circuit may include a second clock latch circuit that provides a clock in a third data bit via a second data clock, the launch cell circuit including a triple data The first, second, and third data bits are latched as the precharge signal PRECHARGE transitions from a high voltage level to a low voltage level so that it becomes a rate firing cell circuit.

  FIG. 11 is a timing diagram illustrating the operation of one embodiment of the double data rate firing cell circuit 400 of FIG. Double data rate firing cell circuit 400 includes a first firing group FG1, a second firing group FG2, a third firing group FG3, and other firing groups up to firing group FGn. Double data rate firing cell circuit 400 receives precharge / select signals S0, S1, S2, and other precharge / select signals up to Sn. The precharge / selection signals S0 to Sn are used as a precharge signal and / or a selection signal in the double data rate firing cell circuit 400.

  First firing group FG1 receives signal S0 as a precharge signal at 500 and receives signal S1 as a selection signal at 502. The second firing group FG2 receives the signal S1 as a precharge signal at 502 and receives the signal S2 as a selection signal at 504. The third firing group FG3 receives a signal S2 as a precharge signal and receives a signal S3 (not shown) as a selection signal at 504, and thereafter a signal Sn-1 (not shown) as a precharge signal. The same applies to the firing group FGn that receives the signal Sn as a selection signal.

  Clock latch circuit 404 receives data clock signal DCLK at 506 and data signals .about.D1,. . . ˜Dn and at 510 the clock data signal ˜DC1,. . . ~ DCn is given. Firing groups FG1-FGn receive data signals ˜D1,. . . ~ Dn, and at 510, the clock data signal ~ DC1,. . . ~ DCn is latched to provide a latched clock data signal and a latched data signal, which are used to turn on the drive switch 172 and apply a voltage to the selected firing resistor 52 . Each firing group receives a firing signal including energy pulses and applies a voltage to the selected firing resistor 52. In one embodiment, the energy pulse starts approximately midway or near the end of the high voltage pulse of the firing group selection signal and applies a voltage to the selected firing resistor 52 in the firing group.

  The first firing group FG1 receives data signals ~ D1,. . . ~ Dn, and at 510, the clock data signal ~ DC1,. . . ~ DCn is latched to provide a latched first firing group clock data signal FG1C at 512 and a latched first firing group data signal FG1D is provided at 514. The second firing group FG2 receives data signals ~ D1,. . . ~ Dn, and at 510, the clock data signal ~ DC1,. . . ~ DCn is latched to provide a latched second firing group clock data signal FG2C at 516 and a latched second firing group data signal FG2D at 518. The third firing group FG3 receives data signals ~ D1,. . . ~ Dn, and at 510, the clock data signal ~ DC1,. . . ˜DCn is latched to provide a latched third firing group clock data signal FG3C at 520 and a latched third firing group data signal FG3D at 522. Other fire groups also receive data signals ~ D1,. . . ~ Dn, and at 510, the clock data signal ~ DC1,. . . ~ DCn is latched to provide a latched clock data signal and a latched data signal similar to fire groups FG1-FG3.

  Initially, 500 signal S0 provides a high voltage pulse at 524 in the precharge signal of the first firing group FG1, and 506 data clock signal DCLK during the first half of the 524 high voltage pulse, A high voltage pulse is provided at 526. Clock latch circuit 404 receives the high voltage pulse at 526 and data signal .about.D1,. . . Through Dn, at 510, the clock data signal ~ DC1,. . . ~ DCn is given.

  During the first half of the high voltage pulse at 524, 508 data signals ~ D1,. . . ~ Dn includes a first firing group clock data signal 1C at 528, which is passed through the clock latch circuit 404 to 510 clock data signals ~ DC1,. . . Provide 530 first firing group clock data signals 1C at ~ DCn. Also, 530 first firing group clock data signal 1C is passed through data latch transistor 152 in precharged firing cell 150 of first firing group FG1, and 512 latched first firing group clocks. 532 first fire group clock data signal 1C is provided in data signal FG1C. 530 first firing group clock data signal 1C is received at 510 in response to high voltage pulse 526 transitioning to a low logic level. . . ~ Latched as DCn. The first firing group clock data signal 1C at 528 must be held until the high voltage pulse 526 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 524, the data signal ~ D1,. . . ~ Dn includes a first firing group data signal 1D at 534. The first firing group data signal 1D at 534 is passed through the data latch transistor 152 in the precharged firing cell 150 of the first firing group FG1 connected to the data line 422 and the latched first of 514. The first fire group data signal 1D of 536 is provided in the fire group data signal FG1D. The first firing group clock data signal 1C at 532 and the first firing group data signal 1D at 536 are precharged in the first firing group FG1 in response to the high voltage pulse 524 transitioning to a low logic level. Latched into the launch cell 150. The first firing group data signal 1D at 534 must be held until the high voltage pulse 524 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S1 at 502 is 538 high voltage pulses in the selection signal of the first firing group FG1 and the precharge signal of the second firing group FG2. give. The high voltage pulse at 538 turns on the select transistor 130 in the precharged firing cell 150 of the first firing group FG1. If 512 latched first firing group data FG1C and FG1D of 514 are high in the addressed row subgroup, the storage node capacitance 126 is discharged and 512 latched first firing. If the FG1D of the group data FG1C and 514 is low, it remains charged. In the row subgroup that is not addressed, the storage node capacitance 126 is discharged regardless of the voltage levels of 512 latched first firing group data FG1C and 514 FG1D. An energy pulse is provided in the firing signal of the first firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  The data clock signal DCLK at 506 provides a high voltage pulse at 540 during the first half of the 538 high voltage pulse. Clock latch circuit 404 receives the high voltage pulse at 540 and data signal .about.D1,. . . Through Dn at 510 the clock data signal ~ DC1,. . . ~ DCn is given.

  During the first half of the high voltage pulse at 538, 508 data signals ~ D1,. . . ~ Dn includes a second firing group clock data signal 2C at 542, which is passed through the clock latch circuit 404 to 510 clock data signals ~ DC1,. . . Provide 544 second firing group clock data signals 2C at ~ DCn. Also, 544 second fire group clock data signal 2C is passed through data latch transistor 152 in precharged fire cell 150 of second fire group FG2 to receive 516 latched second fire group clock. 546 second fire group clock data signal 2C is provided in data signal FG2C. 544 second firing group clock data signal 2C is generated at 510 in response to the high voltage pulse 540 transitioning to a low logic level. . . ~ Latched as DCn. The second firing group clock data signal 2C at 542 must be held until the high voltage pulse 540 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 538, the data signal ~ D1,. . . ~ Dn includes a second firing group data signal 2D at 548. The second firing group data signal 2D at 548 is passed through the data latch transistor 152 in the precharged firing cell 150 of the first firing group FG2 connected to the data line 422 and the latched second of 518. 550 second fire group data signal 2D is provided in the fire group data signal FG2D. The second firing group clock data signal 2C at 546 and the second firing group data signal 2D at 550 are precharged in the second firing group FG2 in response to the high voltage pulse 538 transitioning to a low logic level. Latched into the launch cell 150. 548 second firing group data signal 2D must be held until high voltage pulse 538 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S2 at 504 is 552 high voltage pulses in the selection signal of the second firing group FG2 and the precharge signal of the third firing group FG3. give. The high voltage pulse at 552 turns on the select transistor 130 in the precharged firing cell 150 of the second firing group FG2. In the addressed row subgroup, if the latched second firing group data, 516 FG2C and 518 FG2D are high, the storage node capacitance 126 is discharged and 516 latched second It remains charged when FG2D of fire group data FG2C and 518 is low. In the non-addressed row subgroup, the storage node capacitance 126 is discharged regardless of the voltage levels of 516 latched second firing group data FG2C and 518 FG2D. An energy pulse is provided in the firing signal of the second firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  The data clock signal DCLK at 506 provides a high voltage pulse at 554 during the first half of the 552 high voltage pulse. Clock latch circuit 404 receives the high voltage pulse at 554 and data signal ~ D1,. . . Through Dn at 510, the clock data signal ~ DC1,. . . ~ DCn is given.

  During the first half of the high voltage pulse at 552, 508 data signals ~ D1,. . . ~ Dn include a third fire group clock data signal 3C at 556, which is passed through the clock latch circuit 404 to 510 clock data signals ~ DC1,. . . A third fire group clock data signal 3C of 558 is provided at ~ DCn. Also, the 558 third fire group clock data signal 3C is passed to the data latch transistor 152 in the precharged fire cell 150 of the third fire group FG3 and 520 latched third fire group clock. 560 third fire group clock data signal 3C is provided in data signal FG3C. The third firing group clock data signal 3C of 558 includes a clock data signal ~ DC1,... At 510 in response to the high voltage pulse 554 transitioning to a low logic level. . . ~ Latched as DCn. The 556 third firing group clock data signal 3C must be held until the high voltage pulse 554 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 552, the data signal ~ D1,. . . ~ Dn includes a third fire group data signal 3D at 562; The third fire group data signal 3D at 562 is passed through the data latch transistor 152 in the precharged fire cell 150 of the first fire group FG3 connected to the data line 422 and the latched third data at 522. 564 of the third fire group data signal 3D is provided in the fire group data signal FG3D of The third firing group clock data signal 3C at 560 and the third firing group data signal 3D at 564 are precharged in the third firing group FG3 in response to the high voltage pulse 552 transitioning to a low logic level. Latched into the launch cell 150. 562 third firing group data signal 3D must be held until high voltage pulse 552 transitions below the transistor threshold.

  This process continues until the firing group FGn receives the signal Sn-1 as a precharge signal and the signal Sn as a selection signal. The process starts from the first firing group FG1 and is then repeated until the fluid ejection is complete.

  FIG. 12 is a circuit diagram illustrating one embodiment of a precharged firing cell 160 that can be used in a multiple data rate firing cell circuit. The precharged firing cell 160 is similar to the precharged firing cell 120 of FIG. 6 and includes the drive switch 172, firing resistor 52, and memory cell of the precharged firing cell 120. The components of the precharged firing cell 160 that match the components of the precharged firing cell 120 have the same numbers as the components of the precharged firing cell 120 and are described in the description of FIG. A latch output that is electrically connected to each other and to the signal line, but receives the latched data signal ~ LDATAIN instead of the gate of the data transistor 136 being connected to the data line 142 that receives the data signal ~ DATA. The difference is that it is electrically connected to the data line 166. Further, the components of the precharged firing cell 160 that match the components of the precharged firing cell 120 function and operate as described in the description of FIG.

  Precharge firing cell 160 includes a data latch transistor 162 that includes a drain-source path that is electrically connected between data line 164 and latch output data line 166. Data line 164 receives the data signal ~ DATAIN and data latch transistor 162 latches the data into precharged firing cell 160 to provide the latched data signal ~ LDATAIN. The data signal ~ DATAIN and the latched data signal ~ LDATAIN are active when low, as indicated by the waveform symbol (~) at the beginning of the signal name. The gate of the data latch transistor 162 is electrically connected to the data selection line 170 that receives the data selection signal DATASEL.

  In one embodiment, the data latch transistor 162 has a charge between the latch output data line 166 and the gate-source node of the data latch transistor 162 when the data select signal transitions from a high voltage level to a low voltage level. In order to minimize sharing, it is the smallest transistor size. This charge sharing reduces the data latched to the high voltage level. Also, in one embodiment, when the data select signal is at a low voltage level and the smallest sized transistor keeps the capacitance seen at the data line 164 low, the drain of the data latch transistor 162 reduces this capacitance. decide.

  The data latch transistor 162 passes the data from the data line 164 to the latch output data line 166 and the latch output data storage node capacitance 168 according to the high level data selection signal. Data is latched onto the latch output data line 164 and the latch output data storage node capacitance 168 as the data select signal transitions from a high voltage level to a low voltage level. The latch output data storage node capacitance 168 is shown as a dashed line because it is part of the data transistor 136. Alternatively, a capacitor separate from data transistor 136 can be used to store the latched data.

  The latch output data storage node capacitance 168 is large enough to remain generally high when the data select signal transitions from high to low. Also, the latch output data storage node capacitance 168 is generally low when an energy pulse is applied by the firing signal FIRE, a high voltage pulse is applied by the selection signal SELECT, and a high voltage pulse is applied by the precharge signal PRECHARGE. Big enough to stay. Further, the data transistor 136 is small enough to hold a low level on the latch output data storage node capacitance 168 when the gate of the drive switch 172 is discharged and before the start of the energy pulse in the firing signal FIRE. , Large enough to completely discharge the gate of the drive switch 172.

  In one embodiment of a double data rate firing cell circuit using a precharged firing cell 160, each data select line 170 is electrically connected to a precharge line, a first clock, or a second clock. In one firing group, a first clock is electrically connected to the data select line 170 in some precharged launch cells 160 and the launch group pre-populated on the data select line 170 in another precharged launch cell 160. The charge line is electrically connected. In other firing groups, a second clock is electrically connected to data selection lines 170 in some precharged firing cells 160 and firing groups are connected to data selection lines 170 in other precharged firing cells 160. The precharge line is electrically connected. The first clock includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the first clock. The second clock includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the second clock. Thus, in one fire group, the first clock and precharge signal latches two data bits during each high voltage pulse in the precharge signal, while in the other fire group, the second clock and precharge signal. Latches two data bits during each high voltage pulse in the precharge signal. In other embodiments of the multiple data rate firing cell circuit using the precharge firing cell 160, any suitable number of clock signals may be used, such as three or more data bits during the high voltage pulse of the precharge signal. A large number of data bits can be latched.

  In a multiple data rate firing cell circuit using a precharge firing cell 160, several data lines charge the latch output data line nodes in one firing group at a time, where each firing group has its firing A high voltage level is received in the group precharge signal. The other data lines charge the latch output data line nodes in the multiple firing groups, where multiple firing groups receive high voltage pulses in the clock signal.

  During operation of the precharged firing cell 160, the data signal ~ DATAIN is received by the data line 164, and a high voltage pulse is applied on the data selection line 170, thereby causing the latch output data line 166 and Latched output data storage node capacitance 168 is passed. The storage node capacitance 126 is precharged through the precharge transistor 128 by a high voltage pulse on the precharge line 132. In response to the voltage pulse on data selection line 170 transitioning from a high voltage level to a low voltage level, data latch transistor 162 is turned off and latched data signal .about.LDATAIN is applied. Data to be latched in the precharged firing cell 160 is provided while the data selection signal is at a high voltage level and is held until after the data selection signal transitions to a low voltage level. The high voltage pulse in the data selection signal occurs during the high voltage pulse in the precharge signal or is a high voltage pulse in the precharge signal. In contrast, data to be latched in the precharged firing cell 120 of FIG. 6 is provided while the select signal is at a high voltage level.

  In one embodiment of precharge firing cell 160, after applying a high level voltage pulse on data select line 170, address signals ~ ADDRESS1 and ~ ADDRESS2 are provided on address lines 144 and 146, and first address transistor 138 is provided. And the state of the second address transistor 140 is set. When a high level voltage pulse is applied on the select line 134, the select transistor 130 is turned on, and the data transistor 136, the first address transistor 138, and / or the second address transistor 140 are on, the storage Node capacitance 126 is discharged. Alternatively, storage node capacitance 126 remains charged when data transistor 136, first address transistor 138, and second address transistor 140 are all off.

  If both address signals -ADDRESS1 and -ADDRESS2 are low, the precharged firing cell 160 is the addressed firing cell, and if the latched data signal -LDATAIN is high, the storage node Capacitance 126 is discharged and remains charged when the latched data signal ~ LDATAIN is low. If at least one of the address signals ~ ADDRESS1 and ~ ADDRESS2 is high, the precharged firing cell 160 is not an addressed firing cell, and the storage node capacitance 126 is stored in the latched data signal ~ LDATAIN. Discharges regardless of voltage level. The first address transistor 136 and the second address transistor 138 constitute an address decoder, and the data transistor 136 controls the voltage level on the storage node capacitance 126 when the precharged firing cell 160 is addressed. .

  FIG. 13 is a timing diagram illustrating the operation of one embodiment of a double data rate firing cell circuit using a precharged firing cell 160. Each data selection line 170 is electrically connected to the precharge line, the first data clock, or the second data clock. The double data rate launch cell circuit includes a first launch group FG1, a second launch group FG2, a third launch group FG3, and other launch groups up to launch group FGn. The double data rate firing cell circuit receives precharge / select signals S0, S1, S2, and other precharge / select signals up to Sn. Precharge / selection signals S0,. . . Sn is used as a precharge signal and / or a selection signal in a double data rate firing cell circuit.

  The first firing group FG1 receives the signal S0 as a precharge signal at 600 and receives the signal S1 as a selection signal at 602. The second firing group FG2 receives the signal S1 as a precharge signal at 602 and the signal S2 as a selection signal at 604. The third firing group FG3 receives a signal S2 as a precharge signal and a signal S3 (not shown) as a selection signal at 604, and thereafter a signal Sn-1 (not shown) as a precharge signal. The same applies to the fire group FGn that receives the signal Sn (not shown) as a selection signal.

  The double data rate firing cell circuit receives a first data clock signal DCLK1 at 606 via a first data clock and receives a second data clock signal DCLK2 at 608 via a second data clock. . The first data clock is electrically connected to approximately half the data select lines 170 of the precharged firing cells 160 in the odd firing groups, such as the first firing group FG1 and the third firing group FG3. The The precharge line of each firing group is electrically connected to the data selection line 170 of approximately the other half of the precharged firing cells 160 in the odd number of firing groups. The second data clock is electrically connected to approximately half of the data selection lines 170 of the precharged firing cells 160 in the even number of firing groups, such as the second firing group FG2 and the fourth firing group FG4. The precharge line of each firing group is electrically connected to the data selection line 170 of approximately the other half of the precharged firing cells 160 in the even number of firing groups.

  The first data clock signal DCLK1 at 606 includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the first data clock, and the second data clock at 608 The signal DCLK2 includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the second data clock. The data lines at 610 are data signals ~ D1,. . . ~ Dn is given. However, each data line has a data signal ~ D1,. . . ~ Dn, provide a first data bit during the first half of the high voltage pulse in the precharge signal, and a second during the other half of the high voltage pulse in the precharge signal. Gives data bits. Each data line is electrically connected to a precharged firing cell 160 in every firing group. Each data line is also electrically connected to a precharged firing cell 160 in the firing group having a data select line 170 connected to the first data clock or the second data clock, and the firing group. Is electrically connected to a precharged firing cell 160 in that firing group having a data select line 170 connected to the precharged line.

  In an odd firing group, 606 first data clock signal DCLK1 and precharge signal latch two data bits during each high voltage pulse in the precharge signal. In an even firing group, 608 second data clock signal DCLK2 and precharge signal latch two data bits during each high voltage pulse in the precharge signal. In other embodiments of the multiple data rate firing cell circuit using the precharge firing cell 160, any suitable number of data clock signals can be used to generate three or more data bits during the high voltage pulse of the precharge signal. Such a large number of data bits can be latched.

  Firing groups FG1-FGn receive data signals ˜D1,. . . ~ Dn is latched to provide a latched clock data signal and a latched precharge data signal that are used to turn on the drive switch 172 and apply a voltage to the selected firing resistor 52. It is done. Each firing group receives a firing signal including energy pulses and applies a voltage to the selected firing resistor 52. In one embodiment, the energy pulse starts approximately midway or near the end of the high voltage pulse of the firing group selection signal and applies a voltage to the selected firing resistor 52 in the firing group.

  The first firing group FG1 receives data signals ~ D1,. . . ~ Dn is latched, and at 612, a latched first firing group clock data signal FG1C is provided, and at 614, a latched first firing group precharge data signal FG1P is provided. The second firing group FG2 receives data signals ~ D1,. . . ~ Dn is latched, and at 616, the latched second firing group clock data signal FG2C is provided, and at 618, the latched second firing group precharge data signal FG2P is provided. The third firing group FG3 receives data signals ~ D1,. . . ~ Dn are latched, at 620, the latched third firing group clock data signal FG3C is provided, and at 622, the latched third firing group precharge data signal FG3P is provided. Other fire groups also receive data signals ~ D1,. . . ~ Dn is latched to provide a latched clock data signal and a latched precharge data signal similar to fire groups FG1-FG3.

  Initially, a signal S0 of 600 provides a high voltage pulse at 624 in the precharge signal of the first firing group FG1. During the first half of the 624 high voltage pulse, 606 first data clock signal DCLK 1 provides a high voltage pulse at 626. 610 data signals to D1,. . . ~ Dn includes a first firing group clock data signal 1C at 628, which is passed through a data latch transistor 162 connected to the first data clock in the first firing group FG1 to 612 In the latched first firing group clock data signal FG1C, 630 first firing group clock data signals 1C are provided. The first firing group clock data signal 1C at 630 is latched in response to the high voltage pulse 626 transitioning to a low logic level. 628 first firing group clock data signal 1C must be held until after high voltage pulse 626 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 624, the data signal ~ D1,. . . ~ Dn includes a first firing group precharge data signal 1P at 632; The first firing group precharge data signal 1P at 632 is passed to the data latch transistor 162 connected to the precharge line of the first firing group FG1 to latch the first fire group precharge data at 614. A first firing group precharge data signal 1P of 634 is provided in signal FG1P. The first firing group precharge data signal 1P at 634 is latched into the precharged firing cell 160 in the first firing group FG1 in response to the high voltage pulse 624 transitioning to a low logic level. The first firing group precharge data signal 1P at 632 must be held until the high voltage pulse 624 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S1 at 602 is 636 high voltage pulses in the selection signal of the first firing group FG1 and the precharge signal of the second firing group FG2. give. The high voltage pulse at 636 turns on the select transistor 130 in the precharged firing cell 160 of the first firing group FG1. In the addressed row subgroup, if 612 latched first firing group data FG1C and 614 FG1P are high, storage node capacitance 126 is discharged and 612 latched first firing. If the FG1P of the group data FG1C and 614 is low, it remains charged. In a row subgroup that is not addressed, the storage node capacitance 126 is discharged regardless of the voltage level of 612 latched first firing group data FG1C and 614 FG1P. An energy pulse is provided in the firing signal of the first firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  During the first half of the 636 high voltage pulse, 608 the second data clock signal DCLK2 provides a high voltage pulse at 638. 610 data signals to D1,. . . ~ Dn includes a second fire group clock data signal 2C at 640 that is passed through a data latch transistor 162 connected to a second data clock in the second fire group FG2 to In latched second firing group clock data signal FG2C, 642 second firing group clock data signal 2C is provided. The second firing group clock data signal 2C at 642 is latched in response to the high voltage pulse 638 transitioning to a low logic level. The second firing group clock data signal 2C at 640 must be held until after the high voltage pulse 638 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 636, the data signal ~ D1,. . . ~ Dn includes a second firing group precharge data signal 2P at 644. The second fire group precharge data signal 2P at 644 is passed through the data latch transistor 162 connected to the precharge line of the second fire group FG2 to latch the second fire group precharge data at 618. A second fire group precharge data signal 2P of 646 is provided in signal FG2P. The second firing group precharge data signal 2P of 646 is latched in the precharged firing cell 160 in the second firing group FG2 in response to the high voltage pulse 636 transitioning to a low logic level. The second firing group precharge data signal 2P of 644 must be held until the high voltage pulse 636 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S2 at 604 is 648 high voltage pulses in the selection signal of the second firing group FG2 and the precharge signal of the third firing group FG3. give. The high voltage pulse of 648 turns on the select transistor 130 in the precharged firing cell 160 of the second firing group FG2. In the addressed row subgroup, if the latched second firing group data, 616 FG2C and 618 FG2P are high, the storage node capacitance 126 is discharged and 616 latched first It remains charged when FG2P in firing group data FG2C and 618 is low. In the row subgroup that is not addressed, the storage node capacitance 126 is discharged regardless of the voltage levels of 616 latched first firing group data FG2C and 618 FG2P. An energy pulse is provided in the firing signal of the second firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  During the first half of the 648 high voltage pulses, 606 first data clock signal DCLK1 provides a high voltage pulse at 650. 610 data signals to D1,. . . ~ Dn includes a third firing group clock data signal 3C at 652, which is passed through a data latch transistor 162 connected to the first data clock in the third firing group FG3, at 620 In the latched third firing group clock data signal FG3C, 654 third firing group clock data signal 3C is provided. The third fire group clock data signal 3C at 654 is latched in response to the high voltage pulse 650 transitioning to a low logic level. The third fire group clock data signal 3C at 652 must be held until after the high voltage pulse 650 transitions below the transistor threshold.

  During the remaining half of the high voltage pulse at 648, the data signal ˜D1,. . . ~ Dn includes a third fire group precharge data signal 3P at 656. The third fire group precharge data signal 3P at 656 is passed through the data latch transistor 162 connected to the precharge line of the third fire group FG3 to latch the third fire group precharge data at 622. A third fire group precharge data signal 3P of 658 is provided in signal FG3P. The third firing group precharge data signal 3P at 658 is latched into the precharged firing cell 160 in the third firing group FG3 in response to the high voltage pulse 648 transitioning to a low logic level. The 656 third firing group precharge data signal 3P must be held until after the high voltage pulse 648 transitions below the transistor threshold.

  This process continues until the firing group FGn which receives the signal Sn-1 as a precharge signal and receives the signal Sn as a selection signal. The process starts from the first firing group FG1, and then repeats until fluid ejection is complete.

  FIG. 14 is a circuit diagram illustrating one embodiment of a two-pass transistor precharge firing cell 180. The precharged firing cell 180 can be used with the precharged firing cell 160 of FIG. 12 in a multiple data rate firing cell circuit. In one embodiment of a multiple data rate firing cell circuit using only the precharged firing cell 160 of FIG. 12, several data lines include latch output data nodes in all firing groups that receive the data clock signal. The latch output data line connected to the data latch transistor 162 that receives the high voltage pulse in the data clock signal is charged. In these multiple data rate firing cell circuits, a two-pass transistor precharge firing cell 180 can be used instead of the precharged firing cell 160 that receives the data clock signal. The two-pass transistor precharge firing cell 180 reduces the data line capacitance so that the data line receives the high voltage pulse in the firing group's precharge signal only in one firing group latch output data line node. To charge.

  The precharged firing cell 180 is similar to the precharged firing cell 120 of FIG. 6 and includes a drive switch 172, a firing resistor 52, and a memory cell of the precharged firing cell 120. The components of the precharged firing cell 180 that match the components of the precharged firing cell 120 have the same numbers as the components of the precharged firing cell 120 and are described in the description of FIG. And latched output data for receiving the latched data signal ~ LDATAIN instead of being connected to the data line 142 for receiving the data signal ~ DATA, although the gate of the data transistor 136 is electrically connected to the signal line. The difference is that it is electrically connected to line 182. Further, the components of the precharged firing cell 180 that match the components of the precharged firing cell 120 function and operate as described in the description of FIG.

  Precharged firing cell 180 includes a clock input data latch transistor 184 and a precharge pass transistor 186. Clock input data latch transistor 184 includes a drain-source path electrically connected between the drain-source path of precharge pass transistor 186 and latch output data line 182. The drain-source path of the precharge pass transistor 186 is electrically connected between the drain-source path of the clock input data latch transistor 184 and the data line 188. The gate of the data latch transistor 184 is electrically connected to the data clock line 190 that receives the data clock signal DCLK, and the gate of the precharge pass transistor 186 is electrically connected to the precharge line 132 that receives the precharge signal PRECHARGE. Connected. The data clock signal DCLK at 190 includes a high voltage pulse in the high voltage pulse in the precharge signal PRECHARGE. Data line 188 receives the data signal ~ DATAIN, and clock input data latch transistor 184 latches the data into precharged firing cell 180 and provides the latched data signal ~ LDATAIN. The data signal ~ DATAIN and the latched data signal ~ LDATAIN are active when low, as indicated by the waveform symbol (~) at the beginning of the signal name.

  The data line 188 receives the data signal ~ DATAIN, and the precharge pass transistor 186 passes the data from the data line 188 to the clock input latch transistor 184 by the high voltage pulse in the precharge signal. Clock input latch transistor 184 passes the data to latch output data line 182 and latch output data storage node capacitance 192 by a high voltage pulse in the data clock signal. High voltage pulses in the data clock signal occur during high voltage pulses in the precharge signal.

  In response to the data clock signal transitioning from a high voltage level to a low voltage level, the data is latched onto the latch output data line 182 and the latch output data storage node capacitance 192. The latch output data storage node capacitance 192 is shown as a dashed line because it is part of the data transistor 136. Alternatively, a capacitor separate from data transistor 136 can be used to store the latched data.

  The latch output data storage node capacitance 192 is large enough to remain generally high when the data clock signal transitions from high to low. In addition, the latch output data storage node capacitance 192 is substantially low when an energy pulse is given by the firing signal FIRE, a high voltage pulse is given by the selection signal SELECT, and a high voltage pulse is given by the precharge signal PRECHARGE. Big enough to stay. Further, the data transistor 136 is small enough to hold a low level on the latch output data storage node capacitance 192 when the gate of the drive switch 172 is discharged and before the start of the energy pulse in the firing signal FIRE. , Large enough to completely discharge the gate of the drive switch 172.

  In one embodiment of a double data rate firing cell circuit using a precharged firing cell 160 and a two-pass transistor precharged firing cell 180, each firing group comprises approximately half precharged firing cell 160 and roughly half 2 A pass transistor precharged firing cell 180 is included. The data selection lines 170 of all precharged firing cells 160 in one firing group are electrically connected to the precharge line of that firing group. Also, the precharge pass transistors 186 of all precharged firing cells 180 in one firing group are electrically connected to the precharge line of that firing group. The first clock is electrically connected to all data clock lines 190 in the precharged firing cells 180 in some firing groups, and the second clock is precharged firing in other firing groups. All the data clock lines 190 in the cell 180 are electrically connected. The first clock includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the first clock. The second clock includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the second clock. Thus, in one firing group, the first clock and precharge signal latches two data bits during each high voltage pulse in the precharge signal, while in the other fire group, the second clock and precharge. The signal latches two data bits during each high voltage pulse in the precharge signal. In this multiple data rate firing cell circuit using a precharged firing cell 160 and a two pass transistor precharged firing cell 160, the data line is a latched output data line in the firing group receiving the high voltage level precharge signal. Charge the node.

  During operation of the precharged firing cell 180, the data signal ~ DATAIN is received by the data line 188 and a high voltage pulse is provided in the precharge signal, thereby providing a clock input data latch transistor 184 via the precharge pass transistor 186. Passed to. Clock input data latch transistor 184 passes data to latch output data line 182 and latch output data storage node capacitance 192 by high voltage pulses in the data clock signal. High voltage pulses in the data clock signal occur during high voltage pulses in the precharge signal.

  The storage node capacitance 126 is precharged through the precharge transistor 128 by a high voltage pulse in the precharge signal. In response to the high voltage pulse in the data clock signal transitioning from the high voltage level to the low voltage level, the clock input data latch transistor 184 is turned off and the latched data signal .about.LDATAIN is provided. The data latched in the precharged firing cell 180 is provided while the data clock signal is at a high voltage level and is held until after the data clock signal transitions to a low voltage level, which is high in the precharge signal. Occurs during a voltage pulse. In contrast, data to be latched in the precharged firing cell 120 of FIG. 6 is provided while the select signal is at a high voltage level.

  In one embodiment of precharged firing cell 180, address signals ~ ADDRESS1 and ~ ADDRESS2 are provided on address lines 144 and 146 after a high level voltage pulse in the data clock signal, and first address transistor 138 and second The state of the address transistor 140 is set. When a high voltage pulse is applied on the select line 134, the select transistor 130 is turned on, and the data transistor 136, the first address transistor 138, and / or the second address transistor 140 are on, the storage node Capacitance 126 is discharged. Alternatively, storage node capacitance 126 remains charged when data transistor 136, first address transistor 138, and second address transistor 140 are all off.

  If both address signals -ADDRESS1 and -ADDRESS2 are low, the precharged firing cell 180 is the addressed firing cell and if the latched data signal -LDATAIN is high, the storage node Capacitance 126 is discharged and remains charged when the latched data signal ~ LDATAIN is low. When at least one of the address signals ~ ADDRESS1 and ~ ADDRESS2 is high, the precharged firing cell 180 is not an addressed firing cell and the storage node capacitance 126 is stored in the latched data signal ~ LDATAIN. Discharges regardless of voltage level. The first address transistor 136 and the second address transistor 138 constitute an address decoder, and the data transistor 136 controls the voltage level on the storage node capacitance 126 when the precharged firing cell 180 is addressed. .

  FIG. 15 is a timing diagram illustrating the operation of one embodiment of a double data rate firing cell circuit using a precharged firing cell 160 and a two pass transistor precharged firing cell 180. The double data rate firing cell circuit includes a plurality of firing groups, each firing group including approximately half a precharged firing cell 160 and approximately half a two-pass transistor precharged firing cell 180.

  The double data rate launch cell circuit includes a first launch group FG1, a second launch group FG2, a third launch group FG3, and other launch groups up to launch group FGn. The double data rate firing cell circuit receives precharge / select signals S0, S1, S2, and other precharge / select signals up to Sn. The first firing group FG1 receives the signal S0 as a precharge signal at 700, and receives the signal S1 as a selection signal at 702. The second firing group FG2 receives the signal S1 as a precharge signal at 702 and the signal S2 as a selection signal at 704. The third firing group FG3 receives a signal S2 as a precharge signal and a signal S3 (not shown) as a selection signal at 704, and thereafter a signal Sn-1 (not shown) as a precharge signal. The same applies to the fire group FGn that receives the signal Sn (not shown) as a selection signal.

  The double data rate firing cell circuit receives a first data clock signal DCLK1 at 706 via a first data clock and a second data clock signal DCLK2 at 708 via a second data clock. To do. The first data clock is electrically connected to all data clock lines 190 of the precharged firing cells 180 in the odd firing groups, such as the first firing group FG1 and the third firing group FG3. . The second data clock is electrically connected to all data clock lines 190 of the precharged firing cells 180 in the even number of firing groups, such as the second firing group FG2 and the fourth firing group FG4. . The data selection lines 170 of all precharged firing cells 160 in one firing group are electrically connected to the precharge line of that firing group. Also, the precharge pass transistors 186 of all precharged firing cells 180 in one firing group are electrically connected to the precharge line of that firing group.

  The first data clock signal DCLK1 at 706 includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the first data clock, and the second data clock at 708 The signal DCLK2 includes a high voltage pulse in the first half of each high voltage pulse in the precharge signal of the firing group connected to the second data clock. The data lines at 710 are data signals ~ D1,. . . ~ Dn is given. However, each data line has a data signal ~ D1,. . . ~ Dn, provide a first data bit during the first half of the high voltage pulse in the precharge signal, and a second during the other half of the high voltage pulse in the precharge signal. Gives data bits. Each data line is electrically connected to a precharged firing cell 160 and a two-pass transistor precharged firing cell 180 in each firing group FG1-FGn.

  In an odd firing group, 706 first data clock signal DCLK1 and precharge signal latch two data bits during each high voltage pulse in the precharge signal. In an even firing group, 708 second data clock signal DCLK2 and precharge signal latch two data bits during each high voltage pulse in the precharge signal. In other embodiments of a multiple data rate firing cell circuit using precharged firing cell 160 and two pass transistor precharged firing cell 180, any suitable number of clock signals may be used to generate a high voltage pulse of the precharge signal. Inside, a plurality of data bits, such as three or more data bits, can be latched.

  Firing groups FG1-FGn receive data signals ˜D1,. . . ˜Dn is latched to provide a latched clock data signal and a latched precharge data signal, which are used to turn on the drive switch 172 and apply a voltage to the selected firing resistor 52. The Each firing group receives a firing signal including an energy pulse for applying a voltage to a selected firing resistor 52. In one embodiment, the energy pulse starts approximately midway or near the end of the high voltage pulse of the firing group selection signal and applies a voltage to the selected firing resistor 52 in the firing group.

  The first firing group FG1 receives data signals ~ D1,. . . ~ Dn is latched to provide the first fire group clock data signal FG1C latched at 712, and the latched first fire group precharge data signal FG1P is provided at 714. The second firing group FG2 receives data signals ~ D1,. . . ~ Dn is latched to provide the second fired group clock data signal FG2C latched at 716 and the second fired group precharge data signal FG2P latched at 718. The third firing group FG3 receives data signals ~ D1,. . . ~ Dn is latched to provide a third fire group clock data signal FG3C latched at 720 and a latched third fire group precharge data signal FG3P is provided at 722. Other fire groups also have data signals ~ D1,. . . ~ Dn is latched to provide a latched clock data signal and a latched precharge data signal similar to fire groups FG1-FG3.

  A signal S0 of 700 provides a high voltage pulse at 724 in the precharge signal of the first firing group FG1. During the first half of the 724 high voltage pulse, 706 data clock signal DCLK1 provides a high voltage pulse at 726. 710 of the data signal to D1,. . . ~ Dn includes 728 first firing group clock data signals IC, which are within precharge pass transistor 186 and first firing group FG1 connected to the precharge line of first firing group FG1. Is passed through the clock input data latch transistor 184 connected to the first data clock of the second to provide the first fire group clock data signal 1C of 730 in the latched first fire group clock data signal FG1C at 712. . The first firing group clock data signal 1C at 730 is latched in response to the high voltage pulse 726 transitioning to a low logic level. The first firing group clock data signal IC at 728 must be held until after the high voltage pulse 726 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 724, the data signal ~ D1,. . . ~ Dn includes a first firing group precharge data signal 1P at 732. The first firing group precharge data signal 1P at 732 is passed through the data latch transistor 162 connected to the precharge line of the first firing group FG1 to latch the first fire group precharge data at 714. A first firing group precharge data signal 1P of 734 is provided in signal FG1P. The first firing group precharge clock data signal 1P at 734 is latched into the precharged firing cell 160 in the first firing group FG1 in response to the high voltage pulse 724 transitioning to a low logic level. . The first firing group precharge data signal 1P of 732 must be held until the high voltage pulse 724 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S1 at 702 is 736 high voltage pulses in the selection signal of the first firing group FG1 and the precharge signal of the second firing group FG2. give. The high voltage pulse 736 turns on the selection transistor 130 in the precharged firing cell 160 and the selection transistor 130 in the precharged firing cell 180 of the first firing group FG1. In the addressed row subgroup, if 712 latched first firing group data FG1C and FG1P in 714 are high, storage node capacitance 126 is discharged and 712 latched first firing. If the FG1P of the group data FG1C and 714 is low, it remains charged. In the row subgroup that is not addressed, the storage node capacitance 126 is discharged regardless of the voltage level of FG1P of 712 latched first firing group data FG1C and 714. An energy pulse is provided in the firing signal of the first firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  During the first half of 736 high voltage pulses, 708 second data clock signal DCLK2 provides a high voltage pulse at 738. 710 data signals to D1,. . . ~ Dn includes a second firing group clock data signal 2C at 740, which is the precharge pass transistor 186 connected to the precharge line of the second firing group FG2 and the second firing group FG2 first. Passed through the clock data latch transistor 184 connected to the two data clocks, provides 742 second fire group clock data signal 2C in 716 latched second fire group clock data signal FG2C. The second firing group clock data signal 2C at 742 is latched in response to the high voltage pulse 738 transitioning to a low logic level. The second firing group clock data signal 2C at 740 must be held until after the high voltage pulse 738 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 736, the data signal ~ D1,. . . ~ Dn includes the second firing group data signal 2P at 744. The second firing group data signal 2P at 744 is passed through a data latch transistor 162 connected to the precharge line of the second firing group FG2, and the second fire group precharge data signal FG2P latched at 718. 746 provides a second firing group precharge data signal 2P. The second firing group precharge data signal 2P of 746 is latched in the precharged firing cell 160 in the second firing group FG2 in response to the high voltage pulse 736 transitioning to a low logic level. The second firing group precharge data signal 2P of 744 must be held until the high voltage pulse 736 transitions below the transistor threshold.

  To select one row subgroup, an address signal is provided and the signal S2 at 704 is 748 high voltage pulses in the selection signal of the second firing group FG2 and the precharge signal of the third firing group FG3. give. The high voltage pulse at 748 turns on the selection transistor 130 in the precharged firing cell 160 and the selection transistor 130 in the precharged firing cell 180 of the second firing group FG2. In the addressed row subgroup, if 716 latched second firing group data FG2C and FG2P in 718 are high, storage node capacitance 126 is discharged and 716 latched second firing. When group data FG2C and FG2P of 718 are low, they remain charged. In the row subgroup that is not addressed, the storage node capacitance 126 is discharged regardless of the voltage levels of 716 latched second firing group data FG2C and 718 FG2P. An energy pulse is provided in the firing signal of the first firing group, and a voltage is applied to firing resistor 52 connected to the conductive drive switch 172 in the addressed row subgroup.

  During the first half of the high voltage pulse at 748, the first data clock signal DCLK 1 at 706 provides a high voltage pulse at 750. This turns on the clock input data latch transistors 184 in the odd fire groups, including the clock input data latch transistors 184 in the first fire group FG1. In response to the turn-on of the clock input data latch transistor 184 in the first firing group FG1, the latched first firing group clock data signal FG1C at 712 cannot be determined at 752.

  710 of the data signal to D1,. . . ~ Dn includes a third firing group clock data signal 3C at 754, which is the precharge pass transistor 186 connected to the precharge line of the third firing group FG3 and the third firing group FG3. Passed through a clock input data latch transistor 184 connected to the first data clock, provides 756 third fire group clock data signal 3C in latched third fire group clock data signal FG3C at 720. The third firing group clock data signal 3C at 756 is latched in response to the high voltage pulse 750 transitioning to a low logic level. The third fire group clock data signal 3C at 754 must be held until after the high voltage pulse 750 transitions below the transistor threshold.

  During the other half of the high voltage pulse at 748, the data signal ~ D1,. . . ~ Dn includes a third fire group precharge data signal 3P at 758. The third fire group precharge data signal 3P at 758 is passed through the data latch transistor 162 connected to the precharge line of the third fire group FG3 to latch the third fire group precharge data at 722. A third firing group data signal 3P of 760 is provided in signal FG3P. The third firing group precharge data signal 3P of 760 is latched in the precharged firing cell 160 in the third firing group FG3 in response to the high voltage pulse 748 transitioning to a low logic level. The third firing group precharge data signal 3P of 758 must be held until the high voltage pulse 748 transitions below the transistor threshold.

  During the first half of the high voltage pulse in signal S3 (not shown), the second data clock signal DCLK2 at 708 provides the high voltage pulse shown at 762. This turns on the clock input data latch transistors 184 in the even firing groups, including the clock input data latch transistors 184 in the second firing group FG2. In response to the clock input data latch transistor 184 in the second firing group FG2 being turned on, the latched second firing group clock data signal FG2C at 716 cannot be determined at 764. This process continues until the firing group FGn which receives the signal Sn-1 as a precharge signal and receives the signal Sn as a selection signal. The process starts from the first firing group FG1, and then repeats until fluid ejection is complete.

  While specific embodiments have been illustrated and described herein, various alternatives and / or equivalents may be substituted for the specific embodiments illustrated and described without departing from the scope of the invention. One skilled in the art will appreciate that embodiments can be used. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (10)

A fluid ejection device (22/44) comprising:
A first launch line (110a-110n / 214a-214f) adapted to transmit a first energy signal comprising a first energy pulse;
A second launch line (110a-110n / 214a-214f) adapted to transmit a second energy signal comprising a second energy pulse;
Data lines (108a-108m / 208a-208h) adapted to transmit data signals representing images;
A latch circuit (152, 404/162/184, 186) configured to latch the data signal and provide a latched data signal based on at least one clock signal;
A first droplet generator (60) configured to eject fluid based on the latched data signal in response to the first energy signal;
A second droplet generator (60) configured to eject fluid based on the latched data signal in response to the second energy signal;
A fluid ejection device comprising:   One of the first energy pulses includes a start time and an end time, and one of the second energy pulses is started between the start time and the end time. The fluid ejection device according to claim 1.   The fluid ejection device of claim 1, wherein the first firing line is electrically isolated from the second firing line. A fluid ejection device (22/40) comprising:
A launch line (124) adapted to transmit an energy signal including an energy pulse;
A plurality of launch cells, and each of the launch cells (150/160/180) includes:
Firing resistor (52);
A drive switch (172) configured to allow the firing resistor to respond to the energy signal;
A first data switch (152/162/184) configured to receive a data signal representing an image, latch the data signal, and provide a latched data signal;
Receive the latched data signal and control the drive switch to heat the fluid that is to be dispensed based on the latched data signal while the firing resistor is responsive to the energy signal. A second data switch (136) configured to enable
A fluid ejection device comprising: The fluid ejection device is
A data line (422) adapted to transmit a data line data signal;
A third data switch (418a-418n) configured to receive the data line data signal, latch the data line data signal, and provide a clock data signal; Each of the launch cells receives one of the data line data signal and the clock data signal as the data signal received by the first data switch, and a first of the plurality of launch cells. A portion receives the data line data signal as the data signal at the first data switch, and a second portion of the plurality of firing cells is the clock as the data signal at the first data switch. The fluid ejection device according to claim 4, wherein the fluid ejection device receives a data signal. The plurality of firing cells are
A first group of firing cells, wherein the first data switch is configured to latch the data signal with a clock signal;
A second group of firing cells, wherein the first data switch is configured to latch the data signal by a precharge signal;
The fluid ejection device according to claim 4, further comprising: Each launch cell of the first group of launch cells is
The fluid ejection device according to claim 6, comprising a third data switch (186) configured to send the data signal to the first data switch based on the precharge signal. . A method of operating a fluid ejection device (22/40) comprising:
Transmitting a first energy signal comprising a first energy pulse via a first firing line (110a-110n / 214a-214f);
Transmitting a second energy signal comprising a second energy pulse via a second firing line (110a-110n / 214a-214f);
Transmitting data signals representing images via data lines (108a-108m / 208a-208h);
Latching the data signal based on at least one clock signal and providing a latched data signal;
Discharging fluid based on the latched data signal in response to the first energy signal; and discharging fluid based on the latched data signal in response to the second energy signal. To do,
A method of operating a fluid ejection device, comprising: Latching the data signal is
Latching the data signal by a first clock signal, providing the first clock data signal, and latching the data signal and the first clock data signal by a charge control signal in a pulse format, Providing data signals,
The method of claim 8, comprising:   The method of claim 8, comprising passing the data signal through a pass switch (186) based on the pulsed charge control signal.

Images