JP2010510646A - CMOS imager array with recessed dielectric and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS image sensor array and a manufacturing method.
A CMOS imager sensor array includes a substrate and an array of light-receiving pixel structures formed on the substrate, the “m” level conductive structure having the array formed therein. A high density logic interconnect having an "n" level conductive structure formed adjacent to the array of light receiving pixel structures and an array, each level formed in a corresponding interlayer dielectric material layer Regions, each level being formed in a corresponding interlayer dielectric material layer, and n> m, high density interconnect regions. A microlens array having a microlens and a color filter is formed above the interlayer dielectric material layer, and the microlens and each color filter are for each light receiving structure formed on the surface of the substrate. Aligned. The upper surface of the interlayer dielectric material layer under the microlens array is recessed from the upper surface of the interlayer dielectric material layer in the high density logic wiring region.
[Selection] Figure 3

Description

  The present invention relates to semiconductor optical image sensors, and more particularly to a novel CMOS (complementary metal oxide semiconductor) image sensor having a recessed dielectric, thereby exhibiting reduced reflectivity and increased photosensitivity. The present invention relates to an array structure and a process for manufacturing such an image sensor array.

  CMOS image sensors are beginning to replace conventional CCD sensors for applications that require imaging, such as digital cameras, cell phones, PDAs (personal digital assistants), personal computers, and the like. Advantageously, CMOS image sensors are manufactured at low cost by applying current CMOS manufacturing processes for semiconductor devices such as photodiodes. In addition, the CMOS image sensor can be operated with a single power supply, thereby reducing power consumption below that of a CCD sensor, and further, CMOS logic circuits and similar logic processing devices are sensor chips. The CMOS image sensor can be miniaturized because it is easily integrated into the CMOS image sensor.

  Current CMOS image sensors include an array of CMOS active pixel sensor (APS) cells that are used to collect light energy and convert it into readable electrical signals. FIG. 1 shows an array 10 of CMOS active pixel sensor (APS) cells 20 according to the prior art. As shown, the array 10 includes a plurality of microlenses 22, each of which has a hemispherical shape and is disposed on a smooth planarization layer 27, such as a spin-on polymer, for this planarization. A layer is formed on the color filter array 13 to enable the formation of a microlens array. The color filter array 13 includes independent red, green and blue filter elements 25 (primary color filters), or alternatively, cyan, magenta and yellow filter elements (complementary color filters). Each microlens 22 of the imager pixel array 10 is aligned with a corresponding color filter element 25 and constitutes an upper light receiving portion of the pixel 20. Pixel 20 includes an APS cell portion made on semiconductor substrate 15 that is used to collect light energy 14 and convert it into a readable electrical signal. The APS cell portion further comprises a photosensitive element, eg, a photosensing device 18 such as a photodiode that performs photoelectric conversion, and one or more CMOS transistors (not shown) that perform charge amplification, switching and readout. Z). Each of the pixels 20 generates a signal charge corresponding to the intensity of light received by each pixel, which is converted into a signal current by a photoelectric conversion element (for example, a photodiode) formed on the semiconductor substrate 15. In operation, a light sensing device 18, such as a photodiode, photogate, or photoconductor, overlies a doped region of the substrate for storing photogenerated charge in the underlying portion. A readout circuit is connected to each pixel cell and often includes a floating diffusion region for receiving charges from the photosensitive element during readout. Typically this is accomplished by a transistor device having a gate electrically connected to the floating diffusion region, eg, a source follower transistor circuit. The imager also includes a transistor having a transfer gate for transferring charge from the photosensitive element across the surface channel to the floating diffusion region, and a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transfer. Can be included.

The APS cell portions described above each include an organic or inorganic interlayer dielectric (ILD) material that incorporates aluminum (Al) or copper (Cu) wiring layers 35a, 35b of metallization interconnect levels M1, M2. Manufactured on the semiconductor substrate 15 below the stack including one or more interlayer dielectric material layers 30a-30c. Interlayer dielectric material, for example, may comprise a polymer or SiO _2. Since the Al metallization interconnect layers 35a, 35b do not require passivation, the respective barrier layers are not shown. It is understood that the metallization interconnect levels M1, M2 can include copper (Cu) conductors that allow for thinner interlayer dielectric stacks, which means that these metallization levels of copper are This is because each of the optical paths has a very thin barrier layer or, alternatively, is removed from the optical path of the pixel cell, thereby increasing the photosensitivity of the pixel cell.

Each APS cell 20 having conductive metallization 35a, b further includes a final metal level 36 (eg, Al) that allows wire bonding between each pixel 20 for M1 and M2 metallization. A final passivation layer 29 is formed over the wire bonding level 36, which can include SiN, SiO ₂ , or combinations thereof.

  FIG. 2 shows a prior art CMOS image sensor 10 ′ as in FIG. 1 in cross-section, but at the wafer package level that includes a bonded upper glass plate structure 11 and a chip lead structure 89. It is shown. In FIG. 2, an array structure 20 of pixels including microlenses and color filters is shown for the formed logic carrying conductors, ie copper metallization levels M1, M2. Is connected to a pixel (CMOS) processing circuit inside the chip, and further connected to a circuit outside the chip via a package lead structure 89 by connecting to a bond pad structure 88.

Juergen Leib et al., “New Wafer-Level-Packaging Technology using Silicon-Via-Contacts For Optical And Other Sensor Applications”, Electronic Components and Technology Conference, 2004, p. 843-847 I. Schweky, “CSP Optoelectronic package for Imaging and Light Detection Applications”, Proceedings of SPIE-The International Society for Optical Engineering, 1998, 3582, p. 875-881

  Thus, it is clear that CMOS imagers offer the possibility of reducing the number of chips required in the system by being integrated with logic chips. However, the requirements for wiring high density logic circuits are different from those of imagers. High density logic circuits require a large number of metal levels (typically> 4), while CMOS image sensors require a minimum number of metal levels (typically to maximize optical response). Requires <4). Therefore, there is a need for a process that simultaneously optimizes wiring in both imager arrays and logic circuits on a CMOS imager chip.

  The present invention is directed to a CMOS image sensor having a thinner pixel array sensor portion in the pixel array region compared to the logic wiring region of a higher density sensor. This allows the logic circuit to have as many metal levels as necessary to provide a high density layout, while still allowing the imager array to have a thin dielectric stack.

  Accordingly, the corresponding metal level and interlayer dielectric level height of the high density interconnect logic region for the CMOS imager device formed adjacent to the pixel array region is determined by the metallization level and interlayer dielectric level of the pixel array region. It is higher than the height of the body level.

  That is, in one embodiment, the top surface of the interlayer dielectric material layer under the microlens array is recessed relative to the top surface of the interlayer dielectric material layer in the high density logic interconnect region.

  In some designs, the corresponding metal level height of the high density logic interconnect area for CMOS imager devices can be 30% higher than the height of the imager cell array.

  A method of manufacturing a CMOS image sensor having a thinner film stack in the pixel array region compared to the high-density wiring logic region of the chip results in a pixel array with increased photosensitivity.

  Thus, according to one aspect of the present invention, a CMOS imager sensor array and manufacturing method are provided. A CMOS imager sensor array is a substrate and an array of light-receiving pixel structures formed on the substrate, each array having an “m” level conductive structure formed therein. A high density logic interconnect region formed adjacent to the array of light receiving pixel structures and having an "n" level conductive structure formed in a corresponding interlayer dielectric material layer, Each level is formed in a corresponding interlayer dielectric material layer and includes n> m high density logic interconnect regions.

  A microlens array having a microlens and a color filter is formed above the interlayer dielectric material layer, and the microlens and each color filter are for each light receiving structure formed on the surface of the substrate. Aligned.

  In one exemplary embodiment of the imager array, m = 2 and n ≧ 4.

  In another exemplary embodiment of the imager array, m ≦ 4 and n ≧ 4.

  In accordance with a further aspect of the present invention, a method of manufacturing an image sensor array of pixels is provided, the method forming a plurality of photosensitive elements in a semiconductor substrate to form a pixel array region of the sensor array. Forming a stack of “m” interlayer dielectric material layers on a substrate in both the pixel array region of the sensor array and the adjacent high density interconnect logic region of the sensor array, comprising: Each of the “m” interlayer dielectric material layers includes a respective metal interconnect level that includes a conductor structure in both the pixel array region of the sensor array and the adjacent high density interconnect logic region of the sensor array. And a step of forming a stack of additional interlayer dielectric layers on the “m” interlayer dielectric material layer on both the pixel array region and the high density logic wiring region. A stack of additional interlayer dielectric layers formed in adjacent high density logic interconnect regions includes additional metal level conductor structures formed only in adjacent high density logic interconnect regions. A total of “n” metal interconnect levels with conductive structures are formed in adjacent high density logic interconnect regions, including each additional metal interconnect level, where n> m And removing a portion of the additional interlayer dielectric layer formed on the pixel array region, whereby the surface of the additional interlayer dielectric layer in the pixel array region is added to the high-density logic wiring region. Forming a microlens array having a step recessed from the upper surface of the interlayer dielectric material layer and a microlens and a color filter on the concave surface of the interlayer dielectric material layer in the pixel array region; , Comprising the steps of microlenses and each color filter is aligned with respect to each of the photosensitive element.

  Advantageously, the pixel image sensor array formed according to the method of the present invention is readily compatible with conventional wafer level packaging in both the Schott and Shellcase package configurations.

  Objects, features and advantages of the present invention will become apparent to those skilled in the art in view of the following detailed description in conjunction with the accompanying drawings.

1 illustrates a CMOS image sensor pixel array 10 according to the prior art. A cross-sectional view of a prior art CMOS image sensor 10 'as in FIG. 1 is shown at the wafer package level including an upper glass housing and a chip lead structure. The cross-sectional view illustrates a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. A cross-sectional view illustrates a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and an upper glass housing according to the present invention. FIG. 6 illustrates an alternative process flow of a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and top glass housing according to the present invention through a cross-sectional view. FIG. 6 illustrates an alternative process flow of a method for manufacturing a CMOS image sensor array 100 having a recessed dielectric and top glass housing according to the present invention through a cross-sectional view. Fig. 4 illustrates an alternative embodiment of a CMOS image sensor array showing the packaging of wire leads bonded to the bond pad surface. The cross-sectional view shows packaging of the image sensor array in a Schott package configuration. The cross-sectional view shows the packaging of the image sensor array in the Shellcase package configuration.

  In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.

  FIG. 3 shows a cross-sectional view of a CMOS image sensor chip 100 having a recessed dielectric according to the first embodiment of the present invention. In this embodiment, the CMOS image array 100 includes a recessed dielectric structure 101 in which an array of color filters and corresponding microlens structures are formed. The recess 101 protects the lens, particularly during the process of bonding the glass plate 120 to the CMOS sensor array chip. In essence, standard devices and wiring are fabricated, however, no upper wiring layer is formed over the microlens structure of the imager array 100. Thus, as will be described later, the array 10 includes a plurality of metal wiring layers M1-M5 interconnected by vias, which were created, for example, at least five (M1-M5) metallization levels. It is formed in the high-density wiring region 98 of the peripheral circuit. This is compared to an active pixel area 97 formed between the high density interconnect areas 98 of the imager chip, where only up to two metallization levels (M1-M2) and interlayer dielectrics are formed. It is noted that conventional damascene or subtractive etching techniques can be used to form metal structures and via structures that interconnect metal level structures M1-M5 in high density interconnect region 98.

4-10 illustrate, by cross-sectional views, a process for manufacturing the CMOS image sensor array structure 100 of FIG. As described herein, standard processing results in the intermediate sensor stack structure 200 shown in FIG. In particular, Cu metallization interconnects M1, M2 are formed with the formation of a thinner stack of interlevel dielectric layers 130a-130c formed on substrate 15 in mind. The substrate 15 may be, for example, Si, SiGe, SiC, SiGeC, GaAs, InP, InAs, and other III-V compound semiconductors, bulk semiconductors including II-V compound semiconductors, or silicon-on-insulator (SOI), It can be a laminated semiconductor such as SiC on insulator (SiCOI) or silicon germanium on insulator (SGOI). Preferably, the interlayer dielectric material can be deposited by any of a number of well-known techniques, such as sputtering, spin-on or PECVD, with conventional spin and dielectric constants of about 4.2 or less. Organic or inorganic interlayer dielectric (ILD) materials can be included that can include on-organic dielectrics, spin-on inorganic dielectrics, or combinations thereof. Suitable organic dielectrics that can be used in the present invention include dielectrics containing C, O, F and / or H. Examples of some types of organic dielectrics that can be used in the present invention include aromatic thermosetting polymer resins such as those sold under the trade name SiLK® by DOW Chemical Company, Includes, but is not limited to, resins sold by Honeywell under the trade name Flare®, and similar resins sold by other suppliers, as well as other similar organic dielectrics. . The organic dielectric used as the interlayer dielectric layer may be porous or non-porous, but since the k value is small, a porous organic dielectric layer is very preferable. Suitable inorganic dielectrics that can be used as interlayer dielectrics typically contain Si, O, and H, and optionally contain C, for example, deposited by plasma enhanced chemical vapor deposition (CVD) techniques. SiO ₂ , FSG (fluorosilicate glass), SiCOH, SiOCH, carbon doped oxide (CDO), silicon oxycarbide, and organic silicate glass (OSG). Illustrative examples of some types of inorganic dielectrics that can be used include silsesquioxane HOSP (sold by Honeywell), methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MSQ-HSQ copolymer, SiO ₂ , organosilane and any others deposited using tetraethylorthosilicate (TEOS) or SiH ₄ as silicon source and using O ₂ , N ₂ O, NO etc. as oxidant The Si-containing material is included, but is not limited thereto. For purposes of discussion, assume an inorganic dielectric material and SiO _2.

Still referring to FIG. 4, the method for forming the M1 layer first includes depositing a SiO ₂ dielectric layer 130 c on a substrate that can include a capping layer (not shown), eg, about ₂ k ₂ to ₂₀ k _2. Up to a thickness in the range of up to 3 k 好 ま し く, preferably in the range of 3 kÅ to 4 kÅ, patterning trenches in the SiO ₂ layer 130c using known lithography and RIE techniques, and forming the trenches 1 Lining with metal liners such as one or more refractory metals, eg Ta, TaN, TiN, TiSiN, W, WCN, Ru. Next, the lined trench is filled with a copper material to form a Cu M1 layer 135b, which is then polished using known CMP techniques. A barrier layer (not shown) such as SiN is then deposited over the Cu M1 metallization 135b, for example, to a thickness in the range of about 20 to 2 k, preferably between 100 and 200. be able to. In this embodiment, the thickness of the nitride layer over the Cu interconnect is reduced to minimize reflectivity. It is understood that other barrier layer materials can be used including but not limited to SiON, SiC, SiCN, SiCON, SiCO materials, and the like. This process is repeated for the next Cu M2 metallization layer, so that a thin M2 dielectric layer 130b, eg, SiO ₂ , over the Cu diffusion layer is in the range between about 2 kÅ and 20 kÅ, preferably 1 is deposited to a micron thick, then M2 metallization layer, trench pattern formed in the SiO ₂ layer 130b using known lithography and RIE techniques, a metal liner such as a refractory metal formed trench And the lined trench is filled with a copper material to form a Cu M2 135a layer, which is then polished using known CMP techniques. Thereafter, a barrier such as SiN or a Cu diffusion layer (not shown) can be deposited over the Cu M2 layer 135a, for example, to a thickness in the range of about 20 to 2 k.

In the embodiment shown in FIG. 4, to minimize reflectivity, the total thickness of both the M1 diffusion barrier and the M2 diffusion barrier is preferably about 20 nm or less. In the embodiment shown in FIG. 4 further, an additional layer of material having a refractive index between SiN (1.98) and SiO ₂ (1.46), eg SiON, is applied to thin SiN. It should be understood that reflections can be further reduced by forming an equivalent thickness on the barrier layer (eg, from about 20 to 2 k). According to this first embodiment, Cu metallization and corresponding thin interlayer dielectric layers 130a-130c and a minimal diffusion barrier layer (not shown) are provided in the optical path to minimize light reflectance. Thereby allowing a greater amount of light 14 to pass through the optical path of the pixel 20 and reach the underlying photodiode 18. Although not shown, in an alternative embodiment, each pixel of the array 100 can include additional STI isolation dielectric regions formed in a substrate over a photosensitive element, eg, a photodiode. In this alternative embodiment, the bottom nitride capping layer is removed from the optical path of the pixel.

In a further embodiment, the portion of the barrier SiN layer formed in the pixel array optical path can be selectively removed to avoid refractive index mismatch problems. In this embodiment of the CMOS image sensor array 100, an opening 50 is created in the SiN barrier layer at the location of the optical path of each pixel using an additional mask (resist mask or hard mask) at each level of processing. It is done. That is, after each of the respective barrier layers is formed, additional lithographic patterning and etching steps (wet or dry etching) are performed to open the SiN at selected locations. However, it is understood that a maskless process can be performed to remove selected portions of the SiN layer, for example using cluster ion beam etching. Preferably, fluorine-based dry etching (eg, CF ₄ + oxygen plasma), but to minimize post-etching surface damage or roughness (which can cause light reflection or scattering) Wet etching is desirable. Wet etching may include “smoothing” etching with dilute HF after RIE of SiN, or it may be H ₃ PO ₄ etching to remove SiN using SiO ₂ as a hard mask. Thus, in this embodiment, process steps are performed to form an interlayer dielectric layer 130c, a Cu M1 metallization layer 135b, and a corresponding SiN barrier layer deposition, and a barrier in the optical path of the pixel array. A selective removal of the SiN layer is performed. These process steps are then repeated to form the next M2 dielectric 130b, metal layer M2 135a, and M2 Cu barrier layer. However, after the M1 SiN barrier layer is etched, the surface of the layer may not be completely flat, which may damage the M2 dielectric that is subsequently formed, and the next M2 level. It may potentially affect the lithography or polishing of the next conductor metal for 135a, such as Cu. Thus, after the ILD layer 130b (eg, SiO ₂ ) for the M2 level is patterned and deposited, an additional polishing step is performed on the surface of the SiO ₂ dielectric 130b level, and the M2 metallization 135a is patterned and formed. Before it is executed.

  Subsequently, the steps described herein with respect to the formation of ILD layers 130c and 130b and metallization levels M1, M2 are repeated to form additional interlayer dielectric layers formed over M2 Cu interconnect diffusion layers (not shown). 130a and a further corresponding metallization level M3, as well as a further interlayer dielectric layer 130 and a further corresponding metallization level M4 are obtained. However, as shown in FIG. 4, each of the M3 and M4 metallization layers is formed in the high density interconnect logic region 98 of the chip, but at each pixel between the defined active pixel sensor optical paths of the imager array. It includes M3 and M4 conductive structures 140, 145, respectively, that are not formed over existing M1 and M2 metallizations.

The next step involves forming a fifth metallization level M5 that includes a conductor 150 (eg, an aluminum conductor), which connects any logic circuit (not shown) to an external circuit and / or chip. Can be electrically coupled to the package leads used. Similar to the formation of metallization levels M3 and M4 and their respective interconnecting conductive vias, conductive structure 150 of metallization level M5 is formed in the high density interconnect logic region 98 of the chip, and imager array region. It is not directly formed on the M1 and M2 metallizations present in each pixel between the 97 defined active pixel sensor optical paths. Furthermore, a passivation layer 160 formed from one or more dielectric materials such as SiO ₂ , SiN or polyimide is formed over the final dielectric level 130 to insulate the M5 metallization conductor 150. . The passivation layer is then etched to form a pair of pads that form a protective cover, eg, a structure used to bond a glass plate over the array, typically Specifically, the thickness is 0.5 to 50 microns. Thus, considering from the intermediate structure 200 shown in FIG. 4, it is clear that the upper wiring layers, eg, layers M3-M5, are not formed on the imager array like the metallizations M1, M2. is there.

Continuing with FIG. 5, the final M5 metal level is processed and the resulting structure 200 after the trench 101 is etched into the interlevel dielectric layer stack in the imager array region 97 using conventional lithography and RIE. 'Is shown by a cross-sectional view. This can be performed using an additional mask or can be part of the final via process. For example, this may include depositing a final metal level M5 passivation, forming an opening over the bond pad and over the array, and etching the passivation over the bond pad while simultaneously forming the pixel array. Forming a recess on the top and stripping the remaining resist may be included. In particular, the passivation layer 160 and the interlayer dielectric layer 130 have a width and a length corresponding to the area of the image sensor / pixel array to be formed, i.e., aligned with respect to the optical paths of a plurality of pixels. Etched to form trenches or openings 101 that are placed on top and later provide a surface on which color filters and microlens arrays are formed. From FIG. 5, it can be seen that the sidewalls 102a, b of the trench opening 101 are inset a short distance from the formed metallization M3-M4 and are self-aligned to the edge of the passivation layer 160. FIG. This short fit defines a peripheral region 98 that is formed such that higher density logic circuitry does not interfere with the active pixel cell array in region 97. More specifically, a photolithographic mask is then patterned on the formed passivation layer 160 and then developed and etched in a subsequent single-step etching process to accommodate regions that span multiple pixels. A trench 101 is opened. Using a wet or dry etch process known in the art (eg, F-based dry etch), in the manner shown in FIG. 5, the overlying portion of the bond pad layer and metallization level M2 Trench 101 can be created by effectively removing that portion of interlevel dielectric layer 130 over the corresponding third ILD layer 130a. As shown in FIG. 5, the ILD dielectric is etched to a predetermined depth above the surface of the third ILD layer 130a. If RIE etching is used, a standard parallel plate, downstream plasma, or high density plasma chamber may be used as perfluorinated carbon (PFC) and / or as a fluorine source, as is known in the art. It can be used together with hydrofluorocarbon (HFC) gas and oxygen, hydrogen, nitrogen, argon, etc. used as diluent gas. If wet etching is used, dilute hydrofluoric acid can be used to etch ILD material (eg, SiO ₂ or similar oxide film), as known in the art, and SiN Alternatively, phosphoric acid can be used to etch a similar film or the like. The pixel of the opening 101 formed in the structure shown in FIG. 5 can have a depth of the order of about 0.2 μm-4.0 μm and a width of the order of about 1 mm-10 mm. The etched opening 101 is shown as being substantially parallel in FIG. 5, but may be slightly tapered (eg, having an upper opening wider than the bottom).

  In a more specific implementation for forming the trench 101, in a process for forming standard devices and wiring where the top wiring layer is not formed over the imager array, as shown in FIG. An M3 etch stop layer 171 is formed that is formed over the third ILD level 130a and extends substantially the entire length of the pixel array region 97. The etch stop layer 171 provides mechanical protection for the underlying layers and / or structures, but additionally provides, for example, chemical and / or ionic protection, among others. In addition, layer 171 may also be an organic polymer such as, but not limited to, copper, aluminum, silicon nitride, silicon carbide, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, polyimide, and / or One or more layers can be included, including materials such as other materials. For purposes of illustration and not limitation, layer 171 can be formed to a thickness between about 20 and about 100 nanometers. As shown in FIG. 6, an additional interlayer dielectric layer 130 is formed on the etch stop layer 171 corresponding to the metallization level M3, which may be, for example, from about 50 nanometers to about 500 nanometers. Oxide-based materials that are formed in between can be included. Next, as shown in FIG. 7, an etching process (wet etching or dry etching such as RIE) of the ILD 130 layer that stops at the etching stop layer 171 is performed by a known technique. As shown in FIG. 7, the etch stop layer 171 can be removed by conventional etching techniques to obtain the structure 200 'shown in FIG. 7 having a recessed dielectric. If the etch stop is a dielectric such as SiN, it can be left in the stack to provide protection for the underlying wiring.

  FIG. 8 illustrates a two-dimensional overlying image area 97 by etching the recesses and forming a color filter 125 and microlens array 122 disposed along the X and Y directions thereon by conventional processing. The structure obtained after forming the image sensor array of FIG. In particular, each pixel of the image sensor includes a color filter 125 of colorant material (eg, RGB (primary color filter), or cyan, magenta and yellow filters (complementary color filters)), which in one embodiment. A negative photoresist based on an acrylic polymer material containing a colored pigment, formed on the third ILD layer 130a using known techniques, may be included. In this embodiment, a protective film layer is formed on the obtained color filter layer 125 and on the exposed surface of the third interlayer dielectric film so that the topography associated with the color filter is formed. It can be flattened. This planarization layer is typically an organic material such as a resist and has a thickness ranging from 0.2 μm to 2.0 μm. Next, the microlens structure of the microlens array 122 is formed thereon by conventional techniques. Each microlens structure has a spherical surface and is regularly arranged along the X and Y directions to form a two-dimensional array aligned with the color filter. Conventional techniques for forming the microlens structure 122 can be implemented. For example, a transparent insulating material such as silicon nitride is formed and etched to form the microlens 122.

An alternative process flow (FIGS. 10 and 11) is as follows. After manufacturing the final metal layer M5, the dielectric is removed over the array using lithography and RIE. Next, one or more inorganic passivation layers 155, such as SiN or SiO ₂ / SiN, are deposited over the structure, which protects the underlying circuitry from contamination. The total thickness of the inorganic dielectric is in the range from 0.1 μm to 1 μm. Next, color filters and microlenses are formed as shown in FIG. Finally, as shown in FIG. 11, a polyimide spacer 160 is formed over the peripheral circuit, and then the glass plate 120 is attached to the polyimide 160.

  Continuing with FIG. 9, bonding the glass plate 120 to the preformed (polyimide) passivation layer 160 using a bonding cement such as an acrylic adhesive with optimized optical performance and curing properties. Is shown. As shown in FIG. 9, an air gap 190 similar in thickness to the bond pad structure 125 is created between the microlens array 122 and the packaging glass. Typically, the height of the air gap ranges from 2 μm to 50 μm to ensure that defects on the glass surface do not contact the microlens and that these defects are not imaged by the sensor. It will be appreciated that the recess 101 is deep enough that the formed lens 125 is specifically protected during the process of bonding the glass plate 120 to the CMOS sensor array chip. The glass plates to be joined can range in thickness between about 400 microns to 600 microns.

  Now, as shown in FIG. 12, in an alternative embodiment, an additional step of packaging the formed image sensor device is performed. In particular, as shown in FIG. 9, in a glass plate 120 and a passivation layer 160, for example, by a conventional etching process that exposes a final metallization level, eg, a metallization level M5 including an aluminum bonding pad 150. The step of forming the opening is shown in FIG. This step of forming openings in the glass plate for wire bonding can be performed either before or after bonding of the glass plates, as is known in the art. A conductor 199 (eg, bond wire) can then be wire bonded to the bond pad layer 150 for attachment to external circuitry.

  In an alternative embodiment, packaging an image array with a recessed dielectric portion includes forming a Schott package configuration 300 utilizing semiconductor wafer level packaging techniques known in the art. Can do. For example, as shown in FIG. 13, Schott packaging technology involves forming silicon via contacts 305 that allow direct access to contact pads and / or test pads from the back side of substrate 15. be able to. A photoresist mask applied to the backside of the silicon is used to define both the location and size of the via holes and the streets used to draw the dicing of the die with the image sensor array formed thereon. The mask design as well as the photoresist thickness is optimized for a given silicon thickness. In one embodiment, a tapered sidewall structure is etched into the underlying silicon substrate. The tapered via hole that is formed is etched by a highly customized plasma etching process. As part of this process, in the second plasma etch step, the interlayer dielectric layer underneath the contact pad allows direct electrical contact to the metallization pad, for example at the M1 level. Next, sputter deposition of Ti: W / Cu material as an adhesion layer and seed layer for plating is performed. Starting from the contact opening at the bottom of the via hole, a lead 310 is formed, which rises up the tapered sidewall and corresponds to the corresponding contact of the metal contact formed in the high density interconnect region 98 of the imager array. Reach the pad position. The lead 310 is electroplated with copper to a predetermined thickness (for example, about 5.5 μm). These leads 310 are in electrical contact with ball grid array contacts, such as solder balls 215, and conventional under bump metal (not shown) to complete the Schott package 300 for the imager array. be able to. Further details regarding Schott packaging technology that can be used for packaging of image sensor arrays having recessed dielectrics according to the present invention can be found in Non-Patent Document 1, all of its content and disclosure. Is incorporated herein by reference.

  In an alternative embodiment, as shown in FIG. 14, the packaging of an image array having a recessed dielectric portion may be performed using a Shellcase package configuration utilizing semiconductor wafer level packaging techniques known in the art. Forming 400 may be included. In particular, the substrate material between the dies is etched away from the final structure shown in FIG. 9 to obtain individual ICs that are attached to the support cover. The grooves formed between the dies are filled with an inert material and a thin cover is bonded to the backside of the silicon die to achieve a complete protective housing for each die. Next, a deep notch is formed between the dies to expose the cross section of the wire bond pad 150. Next, a metal layer 410 is formed in contact with the metal pad at its cross section. This metal layer 410 can be patterned by a lithographic process to form individual leads that contact the pad, forming a solder pad on the top surface of the package. The contacts can then be plated, for example with gold or lead tin. Finally, wafer dicing is performed to obtain individual packaged dies. Further details regarding ShellCase packaging technology that can be used for packaging of image sensor arrays with recessed dielectrics according to the present invention can be found in Non-Patent Document 2, all of its content and disclosure. Is incorporated herein by reference.

  While what has been considered as preferred embodiments of the invention has been shown and described, it will be understood that various modifications and changes in form or detail may readily be made without departing from the spirit of the invention. It will be. Accordingly, it is intended that the invention not be limited to the exact forms described and illustrated, but should be construed as covering all modifications that fall within the scope of the appended claims. The

15: Substrate 18: Photodetection device 20: Pixel cell 22, 122: Micro lens 25, 125: Color filter 30, 130: Interlayer dielectric layers 35, 135, 140, 145, 150: Conductive structure 97: Pixel Array region 98: High-density wiring region 10, 100: CMOS image sensor array 101: Recess, trench 102: Side wall 120: Glass plate 150: Bond pad 160: Passivation layer 171: Etching stop layer 190: Air gap 200: Intermediate structure 300: Schott packaging configuration 400: Shellcase package configuration

Claims (26)

A substrate,
An array of light-receiving pixel structures formed on the substrate, the array having “m” level conductive structures formed therein, each level corresponding to a corresponding interlayer dielectric material An array formed in a layer;
A high density logic interconnect region formed adjacent to the array of light receiving pixel structures and having an "n" level conductive structure, wherein each level is formed in a corresponding interlayer dielectric material layer; n> m, a high-density logic wiring region,
CMOS imager array. The array of light-receiving pixel structures is
A microlens array having a microlens and a color filter formed above the interlayer dielectric material layer, the microlens and each color filter being formed on a surface of the substrate; The imager array of claim 1, wherein the imager array is aligned with respect to the light receiving structure.   The imager array of claim 2, wherein an upper surface of the interlayer dielectric material layer under the microlens array is recessed from an upper surface of the interlayer dielectric material layer in the high-density logic wiring region.   The high-density logic wiring region is formed on two opposing sides adjacent to the pixel array region, and the high-density logic wiring region includes a passivation layer formed on an upper surface and has a final conductive structure. The imager array of claim 2.   The imager array of claim 1, wherein the “n” level conductive structures in the high density logic interconnect region are interconnected by via structures.   A protective structure mounted on an upper surface of the passivation structure at the two opposite side portions, the protective structure and the upper surface of the microlens array being separated by a gap; The imager array of claim 4, providing additional protection of the microlens array during mounting of a structure.   The imager array of claim 6 wherein the mounted protection structure includes a glass plate that covers the array of light-receiving pixel structures.   The imager array of claim 6, wherein the gap is about 10 microns or thicker.   The imager array of claim 6, further comprising a conductive element that electrically connects the final conductive structure of the high density logic interconnect region to an external conductor.   The imager array of claim 9, wherein the conductive element is a bond wire.   The imager array of claim 9, wherein the outer conductor includes solder elements formed under the substrate as part of a ball grid array structure.   The imager array of claim 11, wherein the ball grid array structure is formed as part of a Schott integrated circuit package.   The imager array of claim 11, wherein the ball grid array structure is formed as part of a Shellcase integrated circuit package.   The imager array of claim 1, wherein m = 2 and n ≧ 4.   The imager array of claim 1, wherein m ≦ 4 and n ≧ 4. A method for manufacturing an image sensor array of pixels, comprising:
Forming a plurality of photosensitive elements in a semiconductor substrate to form a pixel array region of the sensor array;
Forming a stack of "m" interlayer dielectric material layers on the substrate in both the pixel array region of the sensor array and an adjacent high density interconnect logic region of the sensor array, comprising: Each of the “m” interlayer dielectric material layers includes a conductor structure in both the pixel array region of the sensor array and the adjacent high density interconnect logic region of the sensor array. Steps, including interconnect levels;
Forming a stack of additional interlevel dielectric layers on the “m” interlevel dielectric material layer on both the pixel array region and the high density logic interconnect region, wherein Each additional stack of said additional interlayer dielectric layers formed in a density logic interconnect region includes an additional metal level conductor structure formed only in said adjacent high density logic interconnect region. A total of “n” metal interconnect levels with conductive structures are formed in the adjacent high density logic interconnect region, wherein n> m,
The portion of the additional interlayer dielectric layer formed on the pixel array region is removed, so that the surface of the additional interlayer dielectric layer in the pixel array region becomes the high-density logic wiring region. Making it recessed relative to the top surface of the additional interlayer dielectric material layer;
A microlens array having a microlens and a color filter is formed on the concave surface of the interlayer dielectric material layer in the pixel array region, and the microlens and each color filter are each photosensitive. Aligning with respect to the element.   The method of claim 16, wherein the step of removing a portion of the additional interlayer dielectric layer in the pixel array region is an etch back process. The etch back process to remove portions of the additional interlayer dielectric layer of the pixel array region;
Applying a lithographically patterned mask structure to expose only the surface of the additional interlayer dielectric layer formed over the pixels of the pixel array region;
Performing an etching process to selectively remove portions of the additional interlayer dielectric layer in the pixel array region;
The method of claim 17, comprising: Forming the additional interlayer dielectric layer stack on the “m” interlayer dielectric material layers in the pixel array region;
Forming an etch stop layer extending across the pixel array region, wherein the step of performing an etch process comprises stopping the etching of the additional interlayer dielectric layer at the etch stop layer. Item 17. The method according to Item 16.   The method of claim 16, wherein the conductor structures at the respective metal interconnect levels comprise a copper material, and each of the conductor structures comprises a barrier material layer formed over each of the conductor structures. .   The high density logic interconnect region is formed on two opposing sides adjacent to the pixel array region, and the method includes providing a passivation structure on top of each of the high density logic interconnect regions having a final conductive structure. The method of claim 16, further comprising forming.   Attaching a protective structure to the upper surface of the passivation structure at the two opposite sides, wherein the protective structure and the upper surface of the microlens array are separated by a gap; The method of claim 21, further comprising providing additional protection of the microlens array during mounting.   23. The method of claim 22, further comprising connecting a conductive element to electrically connect the final conductive structure of the high density logic interconnect region to an external conductor.   24. The method of claim 23, wherein the outer conductor includes a solder element formed under the structure as part of a ball grid array structure.   25. The method of claim 24, further comprising forming a Schott integrated circuit package to accommodate the imager sensor array.   25. The method of claim 24, further comprising forming a Shellcase integrated circuit package to accommodate the imager sensor array.

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