JP2010287798A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a layout area of each cell of a standard cell system or a gate array cell system in a semiconductor integrated circuit including an optical sensor. <P>SOLUTION: This semiconductor integrated circuit includes a plurality of cells 301, and a power line 302 extending in the horizontal direction for supplying power voltage to each of the plurality of cells, wherein the power line is included in the uppermost wiring layer in a multilayer wiring structure arranged on a semiconductor substrate; each of the plurality of cells includes a plurality of elements each having a port 308 for inputting or outputting a signal, and a power contact block 304 for supplying the power voltage to the element by connecting the power line to the semiconductor substrate through a wiring layer lower than the uppermost wiring layer in the multilayer wiring structure and a plurality of plugs; and the power contact block and the plurality of ports of the plurality of elements are laid out so that coordinates thereof in the horizontal directions are different from one another. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit.

  A semiconductor integrated circuit having an optical sensor may be mounted with an integrated circuit such as a timing generation circuit or an AD conversion circuit in addition to the optical sensor. The integrated circuit may be designed by arranging standard cells and wiring between the ports of the standard cells. In general, a plurality of wiring layers in a multilayer wiring structure are used for wiring between ports of a standard cell. Patent Document 2 describes that in the gate array, the line 122 in the lowermost wiring layer M1 and the line 121 in the wiring layer M2 thereabove are used as signal lines between input / output terminals (Patent Document). 2 (see FIG. 13). In Patent Document 3, in a solid-state imaging device (photosensor), an interlayer insulating film is not formed on the uppermost wiring layer 263, and a part of the on-chip color filter 28 enters between the uppermost wiring layers 263. (See FIG. 1 of Patent Document 3). Thereby, according to Patent Document 3, since the on-chip microlens 29 formed on the on-chip color filter 28 is close to the surface of the light receiving sensor unit 24, the light collection efficiency when the oblique light La is incident is increased. Has been.

US Patent Application Publication No. 2002/0093036 US Pat. No. 5,898,194 JP 2004-281911 A

  On the other hand, Patent Document 1 describes that both the power rails 511 and 515 and the ground rails 509 and 513 are formed by the uppermost wiring layer (layer 5) in the multilayer wiring structure (FIG. 7 of Patent Document 1). reference). Thus, according to Patent Document 1, it is assumed that connection pins (ports) of each cell can be easily connected using wiring layers (layers 1, 2, and 3) below the uppermost wiring layer. However, Patent Document 1 does not describe how a layout area can be reduced by laying out ports for inputting / outputting signals of a plurality of elements in each cell. An object of the present invention is to reduce the layout area of each standard cell type or gate array cell type cell in a semiconductor integrated circuit having an optical sensor.

  A semiconductor integrated circuit according to one aspect of the present invention is a semiconductor integrated circuit having an optical sensor, and includes a plurality of cells arranged in a horizontal direction and a vertical direction, and the plurality of cells extending in the horizontal direction. A power supply line for supplying a power supply voltage to each of the first and second power supply lines, and the power supply line is included in an uppermost wiring layer in a multilayer wiring structure disposed on a semiconductor substrate. The power supply line and the semiconductor substrate are connected via a plurality of elements each having a port for inputting or outputting a signal, a wiring layer below the uppermost wiring layer in the multilayer wiring structure, and a plurality of plugs A power contact block for supplying the power supply voltage to the element, and the power contact block and the plurality of ports in the plurality of elements Wherein the coordinate in the horizontal direction is different layout.

  According to the present invention, the layout area of each cell of a standard cell system or a gate array cell system in a semiconductor integrated circuit having an optical sensor can be reduced.

1 is a diagram illustrating a configuration of an imaging system to which a semiconductor integrated circuit according to a first embodiment is applied. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. The figure which shows the number of the metal which can be wired to the standard cell in 1st Embodiment. The figure which shows the number of the metal which can be wired to the standard cell in a comparative example. The figure which shows the structure of the semiconductor integrated circuit which concerns on 2nd Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 3rd Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 3rd Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 4th Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 4th Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 5th Embodiment. FIG. 10 is a diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment. FIG. 10 is a diagram showing a configuration of a semiconductor integrated circuit according to a sixth embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 7th Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 7th Embodiment. The figure which shows the structure of the semiconductor integrated circuit which concerns on 8th Embodiment.

  In this specification, two substantially perpendicular directions in a plane along the surface of the semiconductor substrate are expressed as “vertical direction” and “horizontal direction”, and a direction perpendicular to the surface of the semiconductor substrate is expressed as “vertical direction”. I will do it.

  An imaging system to which the semiconductor integrated circuit according to the first embodiment of the present invention is applied will be described with reference to FIG.

  As shown in FIG. 1, the imaging system 90 mainly includes an optical system, an optical sensor 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88. Here, the semiconductor integrated circuit 100 according to the first embodiment of the present invention includes an optical sensor 86 and an integrated circuit 101. The integrated circuit 101 includes an imaging signal processing circuit 95, an A / D converter 96, and a timing generation unit 98.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure. The lens 92 refracts the incident light and forms an image of the subject on the pixel array (imaging surface) of the optical sensor 86. The diaphragm 93 is provided between the lens 92 and the optical sensor 86 on the optical path, and adjusts the amount of light guided to the optical sensor 86 after passing through the lens 92. The optical sensor 86 converts the image of the subject formed in the pixel array into an image signal. The optical sensor 86 reads out the image signal from the pixel array and outputs it. The imaging signal processing circuit 95 is connected to the optical sensor 86 and processes the image signal output from the optical sensor 86. The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into an image signal (digital signal). The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like. The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97. The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89. The timing generation unit 98 is connected to the optical sensor 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. As a result, the timing signal is supplied to the optical sensor 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The optical sensor 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal. The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole. The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94. With the above configuration, if a good image signal is obtained in the optical sensor 86, a good image (image data) can be obtained.

  Next, the configuration of the integrated circuit 101 will be described with reference to FIGS. The integrated circuit 101 includes a plurality of standard cells 301 and 501 (see FIG. 5), a power supply line 302, a ground line 103, and a wiring channel 602. The plurality of standard cells 301 are arranged in the horizontal direction and the vertical direction according to the standard cell system. Each standard cell 301 is, for example, a NAND type standard cell having two input ports. Each standard cell 501 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. The power supply line 302 extends in the horizontal direction, and is the uppermost wiring layer (third wiring layer) in the multilayer wiring structure (first wiring layer to third wiring layer) disposed on the semiconductor substrate (not shown). Wiring layer). The ground line 103 extends in the horizontal direction and is included in the lowermost wiring layer (first wiring layer) in the multilayer wiring structure (first wiring layer to third wiring layer). The wiring channel 602 is arranged between the standard cells 301 and 501 adjacent in the vertical direction, and is the lowermost wiring layer (first wiring layer) in the multilayer wiring structure (first wiring layer to third wiring layer). Included. The wiring channel 602 is wiring installed for securing a place where wiring is possible. Each standard cell 301 includes a plurality of elements (EL1 to EL4), a power contact block 304, and a ground contact plug 104 as shown in FIG. The plurality of elements (EL1 to EL4) each have a port 308 for inputting or outputting a signal. The plurality of elements include, for example, NMOS transistors EL1 and EL2 and PMOS transistors EL3 and EL4. The sources and drains of the NMOS transistors EL1 and EL2 are formed in the N-type active region 306. The sources and drains of the PMOS transistors EL3 and EL4 are formed in the P-type active region 307. The power contact block 304 includes a plurality of plugs and a portion connected to the plug in a wiring layer (second wiring layer, first wiring layer) below the uppermost wiring layer in the multilayer wiring structure. In power contact block 304, a plurality of plugs are arranged in the vertical direction along normal line PL1 of the semiconductor substrate. The power contact block 304 includes a power line 302 and a P-type well in the semiconductor substrate via a wiring layer (second wiring layer, first wiring layer) below the uppermost wiring layer in the multilayer wiring structure and a plurality of plugs. Connect the area. As shown by a broken line in FIG. 2, the P-type well region is connected to the P-type active region 307 in the semiconductor substrate (for example, via a diffusion wiring). As a result, the power contact block 304 supplies a power supply voltage to the elements (PMOS transistors EL3 and EL4). The ground contact plug 104 connects the ground line 103 and the N-type well region in the semiconductor substrate. The N-type well region is connected to the N-type active region 306 in the semiconductor substrate (for example, via a diffusion wiring) as indicated by a broken line in FIG. As a result, the ground contact plug 104 supplies a ground voltage to the elements (NMOS transistors EL1, EL2).

  Here, in the pixel array of the optical sensors 86 in the semiconductor integrated circuit 100, a plurality of pixels are arrayed in a two-dimensional manner. Each pixel includes a photoelectric conversion unit, a multilayer wiring structure, a passivation film, a lower planarizing film, a color filter, an upper planarizing film, and a microlens. The photoelectric conversion unit is disposed on the semiconductor substrate. The photoelectric conversion unit generates and accumulates charges corresponding to light. The photoelectric conversion unit is, for example, a photodiode. The multilayer wiring structure is disposed on the semiconductor substrate so as to define an opening region for the photoelectric conversion portion. The multilayer wiring structure includes a plurality of interlayer insulating films and a plurality of wiring layers (first wiring layer to third wiring layer). The passivation film covers the top of the multilayer wiring structure. The lower planarization film covers the passivation film and provides a flat surface. The color filter is disposed on the flat surface of the lower planarizing film. The upper planarization film covers the color filter and provides a flat surface. The microlens is disposed on the flat surface of the upper planarization film. The distance between the microlens and the light receiving surface of the photoelectric conversion unit is used to improve the light collection characteristics according to the ratio (condensing rate) of light incident on the microlens in each pixel reaching the light receiving surface of the photoelectric conversion unit. Need to be close. As a result, the number of wiring layers may be limited to three or less. As an example, it is assumed that the semiconductor integrated circuit 100 is configured using a multilayer wiring structure from the first wiring layer to the third wiring layer. The third wiring layer, which is the uppermost wiring layer, is difficult to miniaturize compared to the first wiring layer, which is the lowermost wiring layer, and the second wiring layer, which is an intermediate wiring layer. The reason is that if the third wiring layer, which is the uppermost wiring layer, is miniaturized, the uniformity of the passivation film cannot be maintained. Therefore, the wiring pitch of the third wiring layer may be more than double that of the first wiring layer and the second wiring layer, and efficient wiring is performed in the third wiring layer. difficult. As a result, the integrated circuit 101 in the semiconductor integrated circuit 100 is also mounted on the same semiconductor substrate as the optical sensor 86 and formed by the same process, so that the number of wiring layers may be limited to three or less. is there.

  When the number of wiring layers is limited to three or less, the uppermost wiring layer (third wiring layer) cannot be freely used for signal wiring in a cell or signal wiring between cells. Accordingly, it is necessary to form the signal wiring with a plurality of wiring layers (first wiring layer, second wiring layer). At this time, suppose that the power supply line is included in the lowermost wiring layer (first wiring layer). In this case, it is necessary to lay out signal wiring between a port in the cell and a port adjacent to the cell on the power line side so as to bypass the power line at least in the vertical direction. That is, it is necessary to connect the ports of adjacent cells in the vertical direction via the first wiring layer, the via plug, the second wiring layer, the via plug, and the first wiring layer so as to straddle the power supply line in the vertical direction. Occurs. Thereby, the layout efficiency at least in the vertical direction is lowered.

  On the other hand, in the present embodiment, since the power supply line 302 is included in the uppermost wiring layer (third wiring layer), the first cell is connected between the ports of adjacent cells on the power supply line 302 side in the vertical direction. Connection can be made efficiently with the wiring 601 in the wiring layer (see FIG. 5). Alternatively, the cell port and the wiring channel 602 adjacent to the cell can be efficiently connected by the wiring 603 of the first wiring layer (see FIG. 5). This improves the layout efficiency at least in the vertical direction. Therefore, the layout area of each standard cell cell in the semiconductor integrated circuit 100 having the optical sensor 86 can be reduced. FIG. 5 is a diagram in which a standard cell 301 and a standard cell 501 of a logic circuit having arbitrary five input ports and one output port are arranged and wiring is laid out. The standard cell 501 also follows the standard cell system.

  Further, suppose that a contact plug connected to a semiconductor substrate from a power supply line or a ground line and a plurality of ports in a plurality of elements are laid out in the cell so that coordinates in the horizontal direction overlap. It is necessary to lay out the signal wiring so as to bypass the contact plug when the signal wiring of the first wiring layer is connected to the port of the cell adjacent in the vertical direction from the port where the coordinate in the horizontal direction overlaps with the contact plug Occurs. As a result, the layout efficiency in the horizontal and vertical directions decreases. In addition, for example, since the second wiring layer cannot be used for the second signal wiring at the location where the second wiring layer is used as the first signal wiring, the first signal wiring is bypassed. It is necessary to lay out the second signal wiring. As described above, the layout efficiency of the wiring in the horizontal direction and the vertical direction is lowered, and as a result, the layout area of each cell may be increased. As the layout area of each cell increases, the semiconductor integrated circuit 100 increases in size. Patent Documents 1 to 3 do not describe how a layout area can be reduced by laying out ports for inputting / outputting signals of a plurality of elements in each cell.

  In contrast, in the present embodiment, the power contact block 304 and the plurality of ports 308 in the plurality of elements (EL1 to EL4) are laid out so that the coordinates in the horizontal direction are different (see FIGS. 3 and 4). Thus, for example, the first wiring is not used between the port 308 connected to the gates of the PMOS transistors EL3 and EL4 shown in FIG. 3 and the port of the cell adjacent in the vertical direction without using the second wiring layer. The wiring can be efficiently connected with the wiring 3081 of the layer. Alternatively, for example, between the port 308 connected to the gate or drain of the PMOS transistor shown in FIG. 4 and the port of the cell adjacent in the vertical direction, without using the second wiring layer, the first wiring layer Connection can be made efficiently with the wiring 3082. In this manner, the wiring 3081 of the first wiring layer can be efficiently laid out without bypassing the power contact block 304, so that the layout efficiency in the horizontal direction and the vertical direction can be improved. Therefore, the layout area of each standard cell cell in the semiconductor integrated circuit 100 having the optical sensor 86 can be reduced. As a result, the semiconductor integrated circuit 100 can be reduced in size.

  Next, in order to clarify the effect of the semiconductor integrated circuit 100 according to the first embodiment of the present invention, with respect to the number of wirings that can be connected to the standard cell, the comparative example (FIG. 7) and the first embodiment (FIG. 6). And will be described. As a premise, the number of wiring layers in the multilayer wiring structure is three (first wiring layer to third wiring layer), and the wiring pitch of the third wiring layer is the first wiring layer and the second wiring layer. It will be doubled compared to. That is, it is assumed that the relative ratio of the wiring pitch is 1 for the first wiring layer and the second wiring layer and 2 for the third wiring layer. The auxiliary lines in FIGS. 7 and 6 are drawn in units of wiring pitch with respect to the first wiring layer and the second wiring layer. As shown in FIG. 7, the comparative example is different from the first embodiment (see FIG. 6) in that the power supply line 102 is included in the lowermost wiring layer (first wiring layer) in the multilayer wiring structure. Yes. In the comparative example, 11 first wiring layers and 7 third wiring layers can be connected in the horizontal direction from the right, and the same applies from the left. Therefore, 22 first wiring layers and 14 third wiring layers can be connected from the left and right. From the bottom, 17 second wiring layers can be connected in the vertical direction, and the same applies from the top. Therefore, 34 second wiring layers can be connected from above and below. Therefore, in the comparative example, the total number of wires connectable from the left and right and from the top and bottom is 70. On the other hand, in the first embodiment, as shown in FIG. 6, twelve first wiring layers and six third wiring layers can be connected in the horizontal direction from the right, and the same applies from the left. Therefore, 24 first wiring layers and 12 third wiring layers can be connected from the left and right. From the bottom, 17 second wiring layers can be connected in the vertical direction. From the top, 15 second wiring layers can be connected in the vertical direction while avoiding the two power contact blocks 304, and 15 first wiring layers can also be connected. Therefore, 15 first wiring layers and 32 second wiring layers can be connected from above and below. Therefore, the total number of wires connectable from the left and right and from the top and bottom is 83. Thus, according to the first embodiment, the number of wires connectable to the standard cell can be increased as compared with the comparative example. Thus, according to the first embodiment, the layout efficiency can be improved, so that the semiconductor integrated circuit can be reduced in size.

  Next, an integrated circuit 101i in the semiconductor integrated circuit 100i according to the second embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different point from 1st Embodiment. As shown in FIG. 8, the integrated circuit 101 i includes a plurality of standard cells 901, a power supply line 102, and a ground line 902. Each standard cell 901 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. The power supply line 102 is included in the lowermost wiring layer (first wiring layer) in the multilayer wiring structure. The ground line 902 is included in the uppermost wiring layer (third wiring layer) in the multilayer wiring structure. Each standard cell 901 includes a power contact plug 204 and a ground contact block 903. The power contact plug 204 connects the power line 102 and the P-type well region in the semiconductor substrate. The ground contact block 903 includes a plurality of plugs and a portion connected to the plug in a wiring layer (second wiring layer, first wiring layer) below the uppermost wiring layer in the multilayer wiring structure. In the ground contact block 903, a plurality of plugs are arranged in the vertical direction along the normal line PL2 of the semiconductor substrate. The ground contact block 903 is connected to the ground line 903 and an N-type well in the semiconductor substrate via a wiring layer (second wiring layer, first wiring layer) below the uppermost wiring layer in the multilayer wiring structure and a plurality of plugs. Connect the area. In the present embodiment, the ground contact block 903 and the plurality of ports 308i in the plurality of elements are laid out so that the coordinates in the horizontal direction are different. Thereby, for example, the port 308i connected to the gate of the PMOS transistor shown in FIG. 8 can be efficiently connected by the wiring 3083i of the first wiring layer without using the second wiring layer. As described above, the wiring 3083i of the first wiring layer can be efficiently laid out without bypassing the ground contact block 903, so that the layout efficiency in the horizontal direction and the vertical direction can be improved. Therefore, the layout area of each standard cell cell in the semiconductor integrated circuit 100i having the photosensor 86 can be reduced. As a result, the semiconductor integrated circuit 100i can be reduced in size.

  Next, an integrated circuit 101j in the semiconductor integrated circuit 100j according to the third embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different point from 1st Embodiment. As shown in FIG. 9, the integrated circuit 101 j includes a plurality of standard cells 1001 and 1101 (see FIG. 10) and a ground line 902. Each standard cell 1001 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. Each standard cell 1101 is, for example, a NAND type standard cell having two input ports. The ground line 902 is included in the uppermost wiring layer (third wiring layer) in the multilayer wiring structure. Each standard cell 1001 includes a ground contact block 903. The ground contact block 903 is the same as the ground contact block 903 in the second embodiment. In the present embodiment, the ground line 902 is included in the uppermost wiring layer (third wiring layer) in addition to the power supply line 302. Accordingly, the ports of adjacent cells on both sides of the power supply line 302 side and the ground line 902 side in the vertical direction can be efficiently connected by the wirings 3082j and 3083j of the first wiring layer. The power contact block 304 and the plurality of ports 308 in the plurality of elements are laid out so that the coordinates in the horizontal direction are different. Thus, for example, the first wiring layer is not used between the port 308j connected to the gate or drain of the PMOS transistor shown in FIG. 9 and the port of the cell adjacent in the vertical direction without using the second wiring layer. The wiring 3082j can be connected efficiently. In addition, the ground contact block 903 and the plurality of ports 308j in the plurality of elements are laid out so that the coordinates in the horizontal direction are different. Thereby, for example, the first wiring layer is not used between the port 308j connected to the gate or drain of the NMOS transistor shown in FIG. 9 and the port of the cell adjacent in the vertical direction without using the second wiring layer. The wiring 3083j can be connected efficiently. As described above, the wirings 3082j and 3083j of the first wiring layer can be efficiently laid out without bypassing the power contact block 302 and the ground contact block 903, so that the layout efficiency in the horizontal direction and the vertical direction is improved. be able to. Therefore, the layout area of each standard cell cell in the semiconductor integrated circuit 100j having the optical sensor 86 can be reduced. As a result, the semiconductor integrated circuit 100j can be reduced in size.

  For example, the first wiring layer drawn out from the port 308j to the power supply line side does not overlap the first wiring layer included in the power supply contact block 304, and passes under the power supply line 302 of the third wiring layer. It is possible to connect to other ports and wiring channels. Similarly, the first wiring layer drawn out from the port 308j to the ground line side does not overlap the first wiring layer included in the ground contact block 903, and passes below the ground line 902 of the third wiring layer. It is possible to connect to other ports and wiring channels. Further, for example, as shown in FIG. 10, it is possible to use the wiring 601 of the first wiring layer for connection between the ports 308j of the cells adjacent in the vertical direction. In addition, in a place where a wiring channel is provided for securing a place where wiring is possible, the wiring 603 of the first wiring layer can be used for connection between the wiring channel 602 and the port 308j.

  Next, an integrated circuit 101k in a semiconductor integrated circuit 100k according to a fourth embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different point from 1st Embodiment. As shown in FIG. 11, the integrated circuit 101 k includes a plurality of standard cells 1201 and 1301 (see FIG. 12) and a power supply line 1202. Each standard cell 1201 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. Each standard cell 1301 is, for example, a NAND type standard cell having two input ports. The power line 1202 shields at least a plurality of elements included in each standard cell 1201. For example, the power supply line 1202 extends mainly in the horizontal direction, but may extend from the outside of the area AR1k where the plurality of ports 308k of the plurality of elements are arranged so as to cover the area AR1k. The power supply line 1202 may shield the entire area of each standard cell 1201 (the entire surface of the cell). For example, the power supply line 1202 may extend from the outside of the area AR1k where the plurality of ports 308k in the plurality of elements are arranged so as to cover the area AR1k and the ground line 103. When the power supply line 1202 shields the entire area of each standard cell 1201, the possibility of obliquely incident light reaching the elements in each standard cell 1201 can be reduced. In addition, when the power supply line 1202 shields the entire area of each standard cell 1201, the possibility that light with high illuminance incident perpendicularly to the surface of the semiconductor substrate is converted into electric charge in the semiconductor substrate and flows into the element is reduced. it can. Thereby, the noise mixed in the signal transmitted by the element can be reduced. Further, as shown in FIG. 12, the power supply line 1202 may extend above the wiring channel 602 arranged between the standard cells 1201 and 1301 adjacent in the vertical direction. When the power supply line 1202 shields the wiring channel 602 in addition to the entire area of each standard cell 1201, the possibility that obliquely incident light reaches the element in each standard cell 1201 can be further reduced. Further, when the power supply line 1202 shields the wiring channel 602 in addition to the entire area of each standard cell 1201, light with high illuminance perpendicularly incident on the surface of the semiconductor substrate is converted into electric charge in the semiconductor substrate and flows into the element. The possibility of being lost can be further reduced. As described above, since the power supply line of the third wiring layer can also be used as the light shielding film during light shielding, it is not necessary to separately configure the power supply line and the light shielding film, layout efficiency can be improved, and the integrated circuit can be downsized. Becomes easier.

  Next, an integrated circuit 101n in a semiconductor integrated circuit 100n according to a fifth embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different point from 2nd Embodiment (refer FIG. 8). As shown in FIG. 13, the integrated circuit 101 n includes a plurality of standard cells 1401 and a ground line 1402. Each standard cell 1401 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. The ground line 1402 shields at least a plurality of elements included in each standard cell 1201. For example, the power supply line 1402 may extend so as to cover the area AR1n from the outside of the area AR1n where the plurality of ports 308n in the plurality of elements are arranged. The ground line 1402 may shield the entire area of each standard cell 1401 (the entire surface of the cell). For example, the ground line 1402 may extend from the outside of the area AR1n where the plurality of ports 308n of the plurality of elements are arranged so as to cover the area AR1n and the power line 102. When the ground line 1402 shields the entire area of each standard cell 1401, the possibility that obliquely incident light reaches the element in each standard cell 1401 can be reduced. In addition, when the ground line 1402 shields the entire area of each standard cell 1401, the possibility that light with high illuminance incident perpendicularly to the surface of the semiconductor substrate is converted into electric charge in the semiconductor substrate and flows into the element is reduced. it can. Thereby, the noise mixed in the signal transmitted by the element can be reduced.

  Next, an integrated circuit 101p in a semiconductor integrated circuit 100p according to a sixth embodiment of the present invention will be described with reference to FIGS. Below, it demonstrates centering on a different point from 3rd Embodiment (refer FIG. 9). As shown in FIG. 14, the integrated circuit 101p includes a plurality of standard cells 1501, a power supply line 1202p, and a ground line 1402p. Each standard cell 1501 is, for example, a logic circuit type standard cell having 5 input ports and 1 output port. The power line 1202p shields light from the elements arranged on the power line 1202p side in the plurality of elements included in each standard cell 1501. For example, the power supply line 1202p may extend from the outside of the region AR1p where the plurality of ports 308p in the plurality of elements are arranged so as to cover the region AR1p1 on the power supply line 1202p side in the region AR1p. The ground line 1402p shields light from the elements arranged on the ground line 1402p side of the plurality of elements included in each standard cell 1201. For example, the ground line 1402p may extend from the outside of the region AR1p so as to cover the region AR1p2 on the ground line 1402p side in the region AR1p. Further, as shown in FIG. 15, the power supply line 1202p may extend above the wiring channel 602 disposed between the adjacent standard cells 1201 and 1301. Alternatively, although not shown, the ground line 1402p may extend to above the wiring channel 602 disposed between the adjacent standard cells 1201 and 1301. When the power supply line 1202p or the ground line 1402p shields the wiring channel 602 in addition to the entire area of each standard cell 1201, the possibility of obliquely incident light reaching the elements in each standard cell 1201 can be further reduced. In addition, when the power line 1202p or the ground line 1402p shields the wiring channel 602 in addition to the entire area of each standard cell 1201, light with high illuminance incident perpendicularly to the surface of the semiconductor substrate is converted into electric charges in the semiconductor substrate. Thus, the possibility of flowing into the device can be further reduced. As described above, since the power supply line or the ground line of the third wiring layer can be used as the light shielding film at the time of light shielding, it is not necessary to separately configure the power supply line and the light shielding film, layout efficiency can be improved, and the integrated circuit can be downsized. It becomes easy to make.

  Next, an integrated circuit 101q in a semiconductor integrated circuit 100q according to a seventh embodiment of the present invention will be described with reference to FIGS. Below, it demonstrates centering on a different point from 5th Embodiment (refer FIG. 13). As shown in FIG. 16, the integrated circuit 101q includes a plurality of standard cells 1701, 1801 (see FIG. 17), and a ground line 1702. Each standard cell 1701 is a logic circuit type standard cell having, for example, 5 input ports and 1 output port. Each standard cell 1801 is, for example, a NAND type standard cell having two input ports. As shown in FIG. 16, the ground line 1702 may extend above the wiring channel disposed between the adjacent standard cells 1401. For example, the ground line 1702 may extend from the outside of the area AR1q where the plurality of ports 308n of the plurality of elements are arranged so as to cover the area AR1q and the area AR2q where the wiring channel 602 is arranged. When the ground line 1702 shields the wiring channel in addition to the entire area of each standard cell 1701, the possibility that light incident obliquely reaches the element in each standard cell 1701 can be further reduced. In addition, when the ground line 1702 shields the wiring channel in addition to the entire area of each standard cell 1701, the light with high illuminance perpendicularly incident on the surface of the semiconductor substrate is converted into electric charge in the semiconductor substrate and flows into the element. This can further reduce the possibility of As described above, since the ground line of the third wiring layer can also be used as a light shielding film during light shielding, it is not necessary to separately configure the ground line and the light shielding film, layout efficiency can be improved, and the integrated circuit can be downsized. Becomes easier.

  Next, an integrated circuit 101r in a semiconductor integrated circuit 100r according to an eighth embodiment of the present invention will be described with reference to FIG. Below, it demonstrates centering on a different point from 1st Embodiment (refer FIG. 2) and 3rd Embodiment (FIG. 14). As shown in FIG. 18, the integrated circuit 101r includes a plurality of gate array cells 1901, a power supply line 1202r, and a ground line 1402r. The plurality of gate array cells 1901 are arranged in the horizontal direction and the vertical direction in accordance with the gate array cell system. Each gate array cell 1901 includes a plurality of elements (EL1r to EL4r), a power contact block 304, and a ground contact block 903, as shown in FIG. Each of the plurality of elements (EL1r to EL4r) has a port 308r for inputting or outputting a signal. FIG. 18 illustrates the case where each gate array cell 1901 includes one basic gate array cell, but each gate array cell 1901 may include a plurality of basic gate array cells. The power supply line 1202r shields the elements EL3r and EL4r arranged on the power supply line 1202r side of the plurality of elements included in each gate array cell 1901. The ground line 1402r shields light from the elements EL1r and EL2r arranged on the ground line 1402r side of the plurality of elements included in each gate array cell 1901.

Claims (7)

A semiconductor integrated circuit having an optical sensor,
A plurality of cells arranged horizontally and vertically;
A power supply line extending in the horizontal direction and supplying a power supply voltage to each of the plurality of cells;
With
The power line is included in the uppermost wiring layer in the multilayer wiring structure disposed on the semiconductor substrate,
Each of the plurality of cells is
A plurality of elements each having a port for inputting or outputting a signal;
A power supply contact block for supplying the power supply voltage to the element by connecting the power supply line and the semiconductor substrate via a wiring layer below the uppermost wiring layer and a plurality of plugs in the multilayer wiring structure; ,
Including
The semiconductor integrated circuit, wherein the power contact block and the plurality of ports in the plurality of elements are laid out so that the coordinates in the horizontal direction are different. The semiconductor integrated circuit according to claim 1, wherein the power supply line shields light from the entire surface of the cell. The wiring layer is included in a wiring layer below the uppermost wiring layer, and further includes a wiring channel disposed between adjacent cells,
The semiconductor integrated circuit according to claim 2, wherein the power supply line extends to above the wiring channel. A ground line extending in the horizontal direction and supplying a ground voltage to each of the plurality of cells;
The ground line is included in the uppermost wiring layer,
Each of the plurality of cells is
A ground contact block that supplies the ground voltage to the element by connecting the ground line and the semiconductor substrate via a wiring layer below the uppermost wiring layer and a plurality of plugs in the multilayer wiring structure. In addition,
2. The semiconductor integrated circuit according to claim 1, wherein the ground contact block and the plurality of ports in the plurality of elements are laid out so that coordinates in the horizontal direction are different. 5. The semiconductor integrated circuit according to claim 4, wherein the ground line shields light from the entire surface of the cell. The wiring layer is included in a wiring layer below the uppermost wiring layer, and further includes a wiring channel disposed between adjacent cells,
6. The semiconductor integrated circuit according to claim 5, wherein the ground line extends to above the wiring channel. A semiconductor integrated circuit having an optical sensor,
A plurality of cells arranged horizontally and vertically;
A ground line extending in the horizontal direction and supplying a ground voltage to each of the plurality of cells;
With
The ground line is included in the uppermost wiring layer in the multilayer wiring structure disposed on the semiconductor substrate,
Each of the plurality of cells is
A plurality of elements each having a port for inputting or outputting a signal;
A ground contact block for supplying the ground voltage to the element by connecting the ground line and the semiconductor substrate via a plurality of plugs and a wiring layer below the uppermost wiring layer in the multilayer wiring structure; ,
Including
The semiconductor integrated circuit, wherein the ground contact block and the plurality of ports in the plurality of elements are laid out so that the coordinates in the horizontal direction are different.

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