JP2010283628A - Synchronization signal generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization signal generation circuit generating synchronization signals synchronized with PWM (pulse width modulated) signals from the PWM signals. <P>SOLUTION: A triangular wave generation circuit 101 is a means for generating triangular wave signals in parallel with the generation of triangular wave signals, started in advance each time detecting each of the rising edge and falling edge of the PWM signals PWMIN; changes the triangular wave signals from a reference level with a fixed temporal gradient, after detecting the rising edge or the falling edge; and thereafter changes the triangular wave signals with the temporal gradient of the same size, in the opposite direction after the edge of the same kind is detected. A synchronization signal generating part 160 is a means for generating the synchronization signals SYNC, synchronized with the PWM signals PWMIN, on the basis of the triangular wave signals TRIA, TRIB and TRIC generated by the triangular-wave generating circuit 101, inverts the level of the synchronization signals SYNC, when the size relation of the two triangular wave signals whose generation is started in tandem is reversed, and initializes the triangular wave signals whose generation is started, in advance, to the reference level. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a synchronization signal generation circuit that generates a synchronization signal synchronized with a PWM (Pulse Width Modulation) signal.

  The class D amplifier is an amplifier that generates a PWM signal that is pulse-width modulated in accordance with an input signal, and drives a load by the PWM signal (see, for example, Patent Document 1). This class D amplifier has an advantage of high energy efficiency, and is often used as a power amplifier for driving a speaker in audio equipment or the like.

JP 2007-124625 A

  By the way, it may be necessary to uniformly adjust the individual pulse widths of the PWM signal in accordance with the power supply voltage of the circuit that drives the load (for example, to increase the pulse width by k times) for reasons such as keeping the gain constant. is there. As a means for coping with such a request, for example, a PWM signal (hereinafter referred to as an input PWM signal) is returned to an analog signal before modulation, and this analog signal is converted into a PWM signal (hereinafter referred to as an output PWM signal). A means of performing again is conceivable. However, when this means is adopted, a synchronization signal that indicates the generation timing of the output PWM signal is required to perform conversion from the analog signal to the output PWM signal. Here, the analog signal obtained from the input PWM signal includes a noise component synchronized with the original input PWM signal. For this reason, if the synchronization signal used to obtain the output PWM signal from the analog signal is not synchronized with the original input PWM signal, a beat occurs in the output PWM signal. In order to prevent the occurrence of such a beat, the synchronization signal used to generate the input PWM signal is obtained from the circuit that is the source of the input PWM signal, and the analog signal is converted to the output PWM signal using this synchronization signal. Conversion may be performed. However, there are cases where such a synchronization signal cannot be obtained from the circuit that is the source of the input PWM signal.

  The present invention has been made in view of the circumstances described above, and an object thereof is to provide a synchronization signal generation circuit capable of generating a synchronization signal synchronized with the PWM signal from the PWM signal.

  The present invention is a means for generating a triangular wave signal in parallel with the generation of a triangular wave signal started in advance each time a rising edge and a falling edge of an input pulse width modulation signal are detected. After detecting an edge or falling edge, change the triangular wave signal with a constant time gradient from the reference level, and then change the triangular wave signal with a reverse time gradient of the same magnitude after the same type of edge is detected Generating means, and means for generating a synchronizing signal synchronized with the pulse width modulation signal based on the triangular wave signal generated by the triangular wave generating means, wherein the triangular wave generating means When the magnitude relation of the triangular wave signal is reversed, the level of the synchronizing signal is reversed and the two triangular wave signals that have started to be generated before and after the above are synchronized. The preceding triangular wave signal that initiated the generated is initialized to the reference level to provide a synchronizing signal generating circuit, characterized by comprising a synchronizing signal generator means for stopping.

  According to this invention, two triangular wave signals generated in succession intersect with each other in a time gradient in opposite directions at the center between adjacent different edges in the pulse width modulation signal, and this intersection is the boundary. The magnitude relationship between the two triangular wave signals is switched. Accordingly, when the magnitude relationship between two triangular wave signals generated before and after the switching, the level of the synchronization signal is inverted to obtain a synchronization signal synchronized with the pulse width modulation signal. In addition, since the triangular wave signal generated in advance is initialized to the reference level when the level of the synchronization signal is inverted, the triangular wave signal generated when the edge of the pulse width modulation signal is detected always starts changing from the reference level. . Therefore, a stable synchronization signal can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a class D amplifier including a synchronization signal generating circuit according to a first embodiment of the present invention. It is a figure which shows the signal waveform of each part of the embodiment. It is a figure which shows the signal waveform of each part of the embodiment. FIG. 3 is a circuit diagram illustrating a specific configuration example of a timing generation unit in the same embodiment. It is a circuit diagram which shows the specific structural example of the synchronizing signal generation part in the embodiment. It is a figure which shows the signal waveform of each part of the same timing generation part. It is a circuit diagram which shows the structure of the class D amplifier provided with the synchronizing signal generation circuit which is 2nd Embodiment of this invention. It is a figure which shows the signal waveform of each part of the embodiment. FIG. 3 is a circuit diagram illustrating a specific configuration example of a timing generation unit in the same embodiment. It is a circuit diagram which shows the specific structural example of the synchronizing signal generation part in the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a class D amplifier constituted by a synchronizing signal generation circuit 100 and a remodulation circuit 200 according to the first embodiment of the present invention. The class D amplifier receives a PWM signal PWMIN output from a PWM circuit (not shown). The PWM signal PWMIN is a train of pulses that are pulse-width modulated in accordance with an input signal, and each pulse in the train of pulses has the same time before and after sampling points arranged at regular time intervals on the time axis. The pulse is swollen by the width. The synchronization signal generation circuit 100 according to the present embodiment is a circuit that generates a synchronization signal SYNC synchronized with the sampling point of the PWM signal PWMIN from the PWM signal PWMIN. Further, the remodulation circuit 200 is based on the PWM signal PWMIN and the synchronization signal SYNC and is synchronized with the synchronization signal SYNC and has a pulse width having a pulse width obtained by multiplying the pulse width of the original PWM signal PWMIN by a specified magnification. This circuit generates and outputs PWMOUT.

  The re-modulation circuit 200 may have various configurations. For example, as shown in the figure, a demodulation circuit 201 such as a low-pass filter that generates a modulation signal (analog signal) corresponding to the pulse width of the PWM signal PWMIN; You may comprise by the triangular wave generation circuit 202 which generate | occur | produces the triangular wave signal synchronizing with the synchronizing signal SYNC, and the PWM circuit 203 which generate | occur | produces the PWM signal PWMOUT by the level comparison with this triangular wave signal and an analog signal.

  As shown in FIG. 1, the synchronization signal generation circuit 100 according to the present embodiment includes a triangular wave generation circuit 101 and a synchronization signal generation unit 160. The triangular wave generating circuit 101 is a means for generating a triangular wave signal TRIA, TRIB or TRIC in parallel with the generation of the triangular wave signal started in advance every time when each of the rising edge and the falling edge of the PWM signal PWMIN is detected. After the rising edge or falling edge is detected, the triangular wave signal is changed from the reference level with a constant time gradient, and after the same type of edge is detected, the triangular wave signal is detected with the same time gradient in the reverse direction. It is a circuit to change.

  In the illustrated example, the triangular wave generation circuit 101 includes a timing generation unit 102 and triangular wave generation units 110A, 110B, and 110C. Here, the timing generator 102 is a circuit that generates pulses PA, PB, and PC by detecting the rising and falling edges of the PWM signal PWMIN. More specifically, in the PWM signal PWMIN, a period between adjacent different types of edges (for example, a period between a rising edge and a subsequent falling edge) is a period between one different type of edge, and a period between consecutive same types of edges. Assuming that a period between the rising edge and the next rising edge (for example, a period between the same kind of edges) is referred to as a period between the same kind of edges, The operation of setting the pulse PA to the H level only during the period between different edges is repeated. In addition, the timing generation unit 102 generates a pulse PB in a manner similar to the pulse PA with a delay of one period between different kinds of edges with respect to the pulse PA, and with a delay of one period between different kinds of edges with respect to the pulse PB. The pulse PC is generated in the same manner as the pulse PA.

  Triangular wave generators 110A, 110B, and 110C are circuits that generate triangular wave signals TRIA, TRIB, and TRIC based on pulses PA, PB, and PC output from timing generator 102, respectively. Of these, the triangular wave generator 110A includes a switch 111, constant current sources 112 and 113, a switch 114, and a common connection point of the constant current sources 112 and 113 that are inserted in series between the power supply VDD and the ground as shown in the figure. The capacitor 115 interposed between the ground and the switch 116 connected in parallel to the capacitor 115 is provided. In this configuration, the switch 111 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the switch 114 is an N-channel MOSFET, and a pulse is applied to the gate of each MOSFET. PA is supplied. The switch 116 is an N-channel MOSFET, and a reset pulse RA is supplied from the synchronization signal generator 160 to the gate of the MOSFET.

  When the reset pulse RA becomes an active level (H level), the switch 116 is turned on, so that the capacitor 115 is discharged through the switch 116 and the triangular wave signal TRIA is fixed at 0V. In a state where the reset pulse RA is in an inactive level (L level), when the pulse PA becomes L level, the switch 111 is turned on and the switch 114 is turned off, so that the capacitor 115 is charged by the constant current source 112, The triangular wave signal TRIA rises linearly from 0 V with a constant time gradient determined by the current value of the constant current source 112 and the capacitance value of the capacitor 115. Thereafter, when the pulse PA becomes H level, the switch 111 is turned off and the switch 114 is turned on, so that the capacitor 115 is discharged by the constant current source 113, and the triangular wave signal TRIA is the current value of the constant current source 113 and the capacitor 115. Decreases linearly with a constant time gradient determined by the capacitance value. Here, the constant current sources 112 and 113 are constant current sources having the same current value. Therefore, the time gradient when the triangular wave signal TRIA rises and the time gradient when the triangular wave signal TRIA falls are gradients having the same magnitude but different signs.

  The triangular wave generators 110B and 110C have the same configuration as the triangular wave generator 110A. The triangular wave generator 110B linearly increases the triangular wave signal TRIB with a constant time gradient during a period when the pulse PB is at L level, and linearly increases the triangular wave signal TRIB with a constant time gradient during a period when the pulse PB is at H level. To lower. Further, the triangular wave generator 110C linearly increases the triangular wave signal TRIC with a constant time gradient during a period when the pulse PC is at the L level, and the triangular wave signal TRIC with a constant time gradient during the period when the pulse PC is at the H level. Decrease linearly. The triangular wave signal TRIB generated by the triangular wave generation unit 110B is the same as the triangular wave signal TRIC generated by the triangular wave generation unit 110C when the synchronization signal generation unit 160 sets the reset pulse RB to the active level (H level). When 160 sets the reset pulse RC to the active level (H level), each is fixed to 0V. In the triangular wave generators 110A, 110B, and 110C, the current value of the constant current source 112, the current value of the constant current source 113, and the capacitance value of the capacitor 115 are the same. For this reason, the absolute value of the time gradient when the triangular wave signals TRIA, TRIB, and TRIC rise, and the absolute value of the time gradient when these fall are all the same.

  The synchronization signal generator 160 is means for generating a synchronization signal SYNC synchronized with the PWM signal PWMIN based on the triangular wave signals TRIA, TRIB and TRIC generated by the triangular wave generation circuit 101. The synchronization signal generator 160 is in a state where the magnitude relationship between two triangular wave signals (for example, the triangular wave signals TRIA and TRIB) that the triangular wave generating circuit 101 has started to generate is reversed (for example, a state of TRIA> TRIB). When switching from TRIA <TRIB to the state of TRIA), the level of the synchronization signal SYNC is inverted, and the triangular wave signal that has started to be generated first is generated among the two triangular wave signals that have been generated in succession (this example Then, a reset pulse (in this example, a reset pulse RA) is generated for fixing and stopping the triangular wave signal TRIA) at a reference level.

  FIG. 2 is a diagram showing signal waveforms of respective parts when a PWM signal PWMIN having a duty ratio smaller than 50% is given to the synchronization signal generating circuit 100, and FIG. 3 shows a duty ratio larger than 50%. FIG. 6 is a diagram showing signal waveforms of respective parts when a PWM signal PWMIN having the same is given to a synchronization signal generating circuit 100; The operation of this embodiment will be described below with reference to these drawings.

  2 and 3, each downward arrow arranged in the uppermost row indicates a sampling point of the PWM signal PWMIN. As shown in the figure, the PWM signal PWMIN is a train of pulses that swells by the same time before and after the sampling point.

  In the example shown in the figure, the timing generator 102 sets the pulse PA to the L level over the period between the same kind of edges (t1 to t3) starting from the first rising edge (time t1) of the PWM signal PWMIN, and then one kind of the difference. The pulse PA is set to the H level over the inter-edge period (t3-t4). Hereinafter, the same applies, and the timing generation unit 102 performs an operation of setting the pulse PA to the L level over the period between the same kind of edges and then setting the pulse PA to the H level over the period between the different kinds of edges. repeat.

  In one inter-edge period (t1-t3) in which the pulse PA maintains the L level, the triangular wave signal TRIA rises linearly from 0 V with a constant time gradient. In addition, the timing generation unit 102 sets the pulse PB to the L level during the period between the same kind of edges (t2 to t4) starting from a time point delayed by one period between different kinds of edges from the falling edge of the pulse PA. During this time, the triangular wave signal TRIB rises linearly from 0 V with a constant time gradient.

  Here, since the lengths of the same-type inter-edge period (t1-t3) and the same-type inter-edge period (t2-t4) coincide with the period of the PWM signal PWMIN, both are equal. In addition, the time gradient of the triangular wave signal TRIA in the same-type edge period (t1-t3) is equal to the time gradient of the triangular wave signal TRIB in the same-type edge period (t2-t4). Therefore, triangular wave signals TRIA and TRIB reach the same voltage VP at times t3 and t4, respectively.

  On the other hand, the timing generation unit 102 sets the pulse PA to the L level over the period between the same kind of edges (t1-t3), and then sets the pulse PA to the H level over the period between the different kinds of edges (t3-t4). And In the period between the different kinds of edges (t3 to t4) in which the pulse PA is at the H level, the triangular wave signal TRIA has a voltage VP with a reverse time gradient having the same absolute value as the time gradient of the triangular wave signals TRIA and TRIB at the time of rising. Begins to decline linearly from.

  Here, paying attention to the period between one different edge (t3-t4) in which the pulse PA is at the H level, the triangular wave signal TRIA drops from the voltage VP at a constant time gradient at the start point t3 of the synchronization period (t3-t4). Initially, at the end point t4 during the same period (t3-t4), the triangular wave signal TIRB reaches the voltage VP with a time gradient equal to the absolute value in the opposite direction to the triangular wave signal TRIA. For this reason, the triangular wave signals TRIA and TRIB intersect at the sampling point at the center of the period between one different edge (t3 to t4) in which the pulse PA is at the H level, and the relationship between the triangular wave signals TRIA and TRIB is the boundary at this sampling point. TRIA> TRIB is switched to TRIA <TRIB.

Therefore, the synchronization signal generator 160 detects that the relationship between the triangular wave signals TRIA and TRIB switches from TRIA> TRIB to TRIA <TRIB, and inverts the level of the synchronization signal SYNC (in the illustrated example, from the L level). The reset pulse RA is set to the active level (H level) in order to initialize the level of the triangular wave signal TRIA that has started to be generated to 0V.
The same operation as described above is also performed for triangular wave signals TRIB and TRIC that are generated in succession, and is also performed for triangular wave signals TRIC and TRIA that are generated in succession. That is, it is as follows.

  First, the triangular wave signal TRIB rises from 0 V to VP in the period between the same kind of edges (t2 to t4) in which the pulse PB becomes the L level, but the triangular wave signal TRIC starts from the period between the one kind of edges (t2 to t4). In one inter-edge period (t3-t5) delayed by one different edge period, the pulse PC rises from 0V to the voltage VP because the pulse PC becomes L level. Further, since the triangular wave signal TRIB is in the period between one different kind of edges (t4-t5) after the period between one homogeneous edge (t2-t4), the pulse PB becomes H level, and therefore from the voltage VP with a constant time gradient. It begins to decline.

  Here, paying attention to the period between the different kinds of edges (t4 to t5) in which the pulse PB is at the H level, the triangular wave signal TRIB decreases from the voltage VP with a constant time gradient at the start point t4 of the synchronization period (t4 to t5). First, at the end point t5 during the same period (t4-t5), the triangular wave signal TRIC reaches the voltage VP with a time gradient equal to the absolute value in the opposite direction to the triangular wave signal TRIB. For this reason, the triangular wave signals TRIB and TRIC intersect at the sampling point at the center of the period between one different edge (t4 to t5) in which the pulse PB is at the H level, and the relationship between the triangular wave signals TRIB and TRIC is the boundary at this sampling point. It switches from TRIB> TRIC to TRIB <TRIC.

  Therefore, the synchronization signal generator 160 detects that the relationship between the triangular wave signals TRIB and TRIC switches from TRIB> TRIC to TRIB <TRIC, and inverts the level of the synchronization signal SYNC (in the illustrated example, from the H level). Then, the reset pulse RB is set to the active level (H level) in order to initialize the level of the triangular wave signal TRIB that has been generated in advance to 0V.

  Next, the triangular wave signal TRIC rises from 0 V to VP in the period between the same kind of edges (t3 to t5) in which the pulse PC becomes the L level, but the triangular wave signal TRIA has the period between the one kind of edges (t3 to t5). Since the pulse PA becomes L level in the period between one kind of edges (t4 to t6) delayed by one period between different kinds of edges, the voltage rises from 0V to the voltage VP. In addition, since the triangular wave signal TRIC is in the period between one different edge (t5 to t6) after the period between one homogeneous edge (t3 to t5), the pulse PC becomes H level, so that the voltage VP has a constant time gradient. It begins to decline.

  Here, focusing on one inter-edge period (t5-t6) in which the pulse PC is at the H level, the triangular wave signal TRIC drops from the voltage VP at a constant time gradient at the start point t5 during the synchronization period (t5-t6). First, at the end point t6 during the same period (t5-t6), the triangular wave signal TRIA reaches the voltage VP with a time gradient equal to the absolute value in the opposite direction to the triangular wave signal TRIC. For this reason, the triangular wave signals TRIC and TRIA intersect at the sampling point at the center of the period between one different edge (t5 to t6) in which the pulse PC is at the H level, and the relationship between the triangular wave signals TRIC and TRIA is the boundary at this sampling point. TRIC> TRIA is switched to TRIC <TRIA.

Therefore, the synchronization signal generator 160 detects that the relationship between the triangular wave signals TRIC and TRIA switches from TRIC> TRIA to TRIC <TRIA, and inverts the level of the synchronization signal SYNC (in the example of FIG. The reset pulse RC is set to the active level (H level) so as to initialize the level of the triangular wave signal TRIC that has been generated in advance to 0V.
Thereafter, the same operation is performed.

  Thus, according to the present embodiment, regardless of the duty ratio of the PWM signal PWMIN, the sampling point at the center of the period in which the PWM signal PWMIN maintains the H level and the sampling point at the center of the period of maintaining the L level. A synchronization signal SYNC whose level is inverted in synchronization is obtained. In the present embodiment, the synchronization signal SYNC is supplied to the triangular wave generation circuit 202 of the remodulation circuit 200.

  In the remodulation circuit 200, the analog signal used by the PWM circuit 203 for level comparison with the triangular wave signal from the triangular wave generating circuit 202 includes noise having a frequency corresponding to the interval at the sampling point of the PWM signal PWMIN. Therefore, if the triangular wave signal used by the PWM circuit 203 to generate the PWM signal PWMOUT is not synchronized with the PWM signal PWMIN, a beat is generated in the PWM signal PWMOUT. However, in this embodiment, the synchronization signal generation circuit 100 outputs the synchronization signal SYNC synchronized with the sampling point of the PWM signal PWMIN. Then, the triangular wave generation circuit 202 of the remodulation circuit 200 generates a triangular wave signal that peaks at the edge of the synchronization signal SYNC synchronized with the sampling point of the PWM signal PWMIN, for example, with the same configuration as the triangular wave generation unit 110A and the like. The circuit 203 generates a PWM signal PWMOUT using this triangular wave signal. Therefore, it is possible to prevent a beat from occurring in the PWM signal PWMOUT.

  As described above, according to the present embodiment, the synchronization signal SYNC can be generated from the PWM signal PWMIN even in a situation where the synchronization signal of the PWM signal PWMIN is not supplied from the preceding PWM circuit. Therefore, it is possible to perform operations such as uniformly expanding or reducing the pulse width of the PWM signal PWMIN without causing the problem of occurrence of beats. In the present embodiment, the triangular wave signals TRIA, TRIB and TRIC used for generating the synchronization signal SYNC always start to rise from 0 V which is the reference level. Therefore, a synchronization signal SYNC that is always accurately synchronized with the sampling point is obtained.

  Next, the present embodiment will be described in more detail with specific examples. 4 is a circuit diagram showing a specific configuration example of the timing generation unit 102 in the present embodiment, FIG. 5 is a circuit diagram showing a specific configuration example of the synchronization signal generation unit 160 in the present embodiment, and FIG. 6 is shown in FIG. FIG. 4 is a diagram illustrating waveforms of respective units of the timing generation unit 102.

First, the timing generator 102 shown in FIG. 4 will be described.
In FIG. 4, flip-flops 121 to 124 constitute a shift register, and this shift register and the NOR gate 125 constitute a ring counter. Here, the flip-flops 121 and 123 located in the first stage and the third stage of the shift register are positive edge driving flip-flops that take in and output input data at the rising edge of the PWM signal PWMIN. The flip-flops 122 and 124 located in the four stages are negative edge-driven flip-flops that take in and output input data at the falling edge of the PWM signal PWMIN.

  In the ring counter configured in this way, as shown in FIG. 6, when the PWM signal PWMIN rises at time t11 when the output signal Da of the NOR gate 125 is at the H level, the signal Da at the H level becomes the level of the PWM signal PWMIN. The signal is taken into the flip-flop 121 by the rising edge, and the positive logic output signal (Q output signal) Db of the flip-flop 121 becomes H level. As a result, the output signal Da of the NOR gate 125 becomes L level.

  Next, when the PWM signal PWMIN falls at time t12, the H level signal Db is taken into the flip-flop 121 by the falling edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Dc of the flip-flop 122 is H. Become a level. Next, when the PWM signal PWMIN rises at time t13, the H level signal Dc is taken into the flip-flop 123 by the rising edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Dd of the flip-flop 123 becomes H level. Become. Further, the L level signal Da is taken into the flip-flop 121 at the rising edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Db of the flip-flop 121 becomes L level.

  Next, when the PWM signal PWMIN falls at time t14, the H level signal Dd is taken into the flip-flop 124 by the falling edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) De of the flip-flop 124 is H. Become a level. Further, the L level signal Db is taken into the flip-flop 122 at the falling edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Dc of the flip-flop 122 becomes L level. Next, when the PWM signal PWMIN rises at time t15, the L level signal Dc is taken into the flip-flop 123 by the rising edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Dd of the flip-flop 123 becomes H level. Become. Next, when the PWM signal PWMIN falls at time t16, the L level signal Dd is taken into the flip-flop 124 by the falling edge of the PWM signal PWMIN, and the positive logic output signal (Q output signal) Dd of the flip-flop 124 becomes L Become a level. As a result, all of the signals Da to Dd are set to the L level, so that the output signal Da of the NOR gate 125 is set to the H level. As described above, the timing generation unit 102 shown in FIG. 4 sets the operation while the level of the PWM signal PWMIN is inverted six times as one cycle, and repeats the operation for one cycle.

  In FIG. 4, the NAND gate 131 is a period in which both the positive logic output signal Db of the first-stage flip-flop 121 of the shift register and the negative logic output signal Dc ′ of the second-stage flip-flop 122 are at the H level. As shown in FIG. 6, the state signal S0 is set to the active level (L level) only in the first inter-edge period (t11-t12) until the PWM signal PWMIN rises first and then falls within the one period. And The NAND gate 132 is a period during which both the positive logic output signal Dc of the second-stage flip-flop 122 of the shift register and the negative logic output signal Dd ′ of the third-stage flip-flop 123 are at the H level, that is, FIG. As shown in FIG. 6, the state signal S1 is set to the active level (L level) only in the second inter-edge period (t12-t13) in the one cycle.

  The NAND gate 133 is a period during which both the positive logic output signal Dd of the third-stage flip-flop 123 of the shift register and the negative logic output signal De ′ of the fourth-stage flip-flop 124 are at the H level, that is, FIG. As shown in FIG. 6, the state signal S2 is set to the active level (L level) only in the third inter-edge period (t13-t14) in one period. The NAND gate 134 is a period in which both the positive logic output signal De of the fourth-stage flip-flop 124 of the shift register and the positive logic output signal Dd of the third-stage flip-flop 123 are at the H level, that is, FIG. As shown in FIG. 5, the state signal S3 is set to the active level (L level) only during the fourth inter-edge period (t14-t15) in the one period.

  The NAND gate 135 is a period during which both the positive logic output signal De of the fourth-stage flip-flop 124 of the shift register and the negative logic output signal Dd ′ of the third-stage flip-flop 123 are at the H level, that is, FIG. As shown in FIG. 6, the state signal S4 is set to the active level (L level) only in the fifth inter-edge period (t15-t16) in the one period. Then, the inverter 136 is in the state only during the period when the output signal Da of the NOR gate 125 is at the H level, that is, as shown in FIG. 6, the last inter-edge period (t16−t11 of the next period) in the one period. The signal S5 is set to an active level (L level).

  The low active NOR gate 137A sets the pulse PA to the L level during the period when any of the state signals S0, S1, S3, S4 is the active level (L level), and sets the pulse PA to the H level during the other periods. To do. Further, the low active NOR gate 137B sets the pulse PB to the L level during the period when any of the state signals S1, S2, S4, S5 is the active level (L level), and sets the pulse PB to the H level during the other periods. To do. The low active NOR gate 137C sets the pulse PC to the L level during the period when any of the state signals S2, S3, S5, S0 is the active level (L level), and sets the pulse PC to the H level during the other periods. To do.

Therefore, as shown in FIG. 6, the pulse PA is maintained at the L level over the period between the same kind of edges (t11-t13) and is at the H level over the period between the different kinds of edges (t13-t14). And maintaining the L level over the period between the same kind of edges (t14-t16) and maintaining the H level over the period between the different kinds of edges (t16-t11 of the next cycle). Is repeated periodically. Further, the pulse PB repeats the same periodic change as the pulse PA with a delay of one inter-edge period from the pulse PA, and the pulse PC has the same period as the pulse PA with a delay of one inter-edge period from the pulse PB. Repeat the change. When comparing the PWM signal PWMIN and the pulses PA, PB, and PC in FIG. 6, FIG. 2 and FIG. 3, the times t11 to t16 in FIG. 6 correspond to the times t1 to t6 in FIG. It will be understood that the pulses PA, PB and PC shown in FIGS. 2 and 3 are generated by the timing generator 102 shown in FIG.
The above is the details of the timing generator 102 shown in FIG.

Next, the synchronization signal generator 160 shown in FIG. 5 will be described.
In FIG. 5, the comparator 161A raises its output signal when the relationship between the triangular wave signals TRIA and TRIB is switched from TRIA> TRIB to TRIA <TRIB. Further, the comparator 161B raises its output signal when the relationship between the triangular wave signals TRIB and TRIC switches from TRIB> TRIC to TRIB <TRIC. The comparator 161C raises its output signal when the relationship between the triangular wave signals TRIC and TRIA is switched from TRIC> TRIA to TRIC <TRIA. The low active OR-AND gate 162A passes the output signal of the comparator 161A only when the state signal S2 or S5 is L level, and the low active OR-AND gate 162B is the comparator only when the state signal S3 or S0 is L level. The output signal of 161B is allowed to pass, and the low active OR-AND gate 162C passes the output signal of the comparator 161C only when the state signal S4 or S1 is at the L level.

  The output signals of the low active OR-AND gates 162A, 162B and 162C are supplied to the clock input terminal C of the toggle flip-flop 166 via the OR gate 165. The toggle flip-flop 166 inverts the level of the signal at the positive logic output terminal Q every time the input signal to the clock input terminal C rises because the signal at the negative logic output terminal is fed back to the data input terminal D. In this example, the signal at the positive logic output terminal Q of the toggle flip-flop 166 is the synchronization signal SYNC.

  In the set-reset flip-flop 163A, the output signal of the low active OR-AND gate 162A is given to the set terminal S, and the pulse PA output from the timing generator 102 is inverted by the inverter 164A and given to the reset terminal R. The output signal of the set-reset flip-flop 163A is supplied as a reset pulse RA to the triangular wave generator 110A in FIG. In the set / reset flip-flop 163B, the output signal of the low active OR-AND gate 162B is applied to the set terminal S, and the pulse PB output from the timing generator 102 is inverted by the inverter 164B and applied to the reset terminal R. . The output signal of the set / reset flip-flop 163B is supplied as a reset pulse RB to the triangular wave generator 110B in FIG. In the set / reset flip-flop 163C, the output signal of the low active OR-AND gate 162C is applied to the set terminal S, and the pulse PC output from the timing generator 102 is inverted by the inverter 164C and applied to the reset terminal R. . The output signal of the set / reset flip-flop 163C is supplied as a reset pulse RC to the triangular wave generator 110C in FIG.

  In such a configuration, in the period between different edges (t13 to t14) in which the state signal S2 is at the L level and the pulse PA is at the H level in FIG. 6, the triangular wave signal TRIA decreases from the voltage VP with a constant time gradient. The signal TRIB rises with a constant time gradient toward the voltage VB (see between t3 and t4 in FIGS. 2 and 3). When the relationship between the triangular wave signals TRIA and TRIB is switched from TRIA <TRIB to TRIA> TRIB at the sampling point at the center of the period between different edges (t13-t14), the output signal of the comparator 161A rises. At this time, since the state signal S2 is at the L level, the rising edge of the output signal of the comparator 161A passes through the low active OR-AND gate 162A and passes through the OR gate 165 to the clock input terminal C of the toggle flip-flop 166. Given to. As a result, the level of the synchronization signal SYNC is inverted. The rising edge of the output signal of the comparator 161A is given to the set input terminal S of the set / reset flip-flop 163A. As a result, the reset pulse RA becomes H level, and the triangular wave signal TRIA is initialized to 0V. After that, when the state signal S2 becomes H level, the state signal S3 becomes L level, and the pulse PA becomes L level, the set input terminal S of the set / reset flip-flop 163A becomes L level and the reset input terminal R becomes H level, The reset pulse RA for the triangular wave generator 110A becomes L level. As a result, the triangular wave signal TRIA starts to rise at a constant time gradient from 0V.

  Next, in the period between different edges (t14-t15) in which the state signal S3 is at L level and the pulse PB is at H level in FIG. 6, the triangular wave signal TRIB decreases from the voltage VP with a constant time gradient, and the triangular wave signal TRIC is It rises at a constant time gradient toward the voltage VB (see between t4 and t5 in FIGS. 2 and 3). When the relationship between the triangular wave signals TRIB and TRIC switches from TRIB <TRIC> TRIB> TRIC at the center sampling point in the period between different edges (t14-t15), the output signal of the comparator 161B rises. At this time, since the state signal S3 is at the L level, the rising edge of the output signal of the comparator 161B passes through the low active OR-AND gate 162B and passes through the OR gate 165 to the clock input terminal C of the toggle flip-flop 166. Given to. As a result, the level of the synchronization signal SYNC is inverted. The rising edge of the output signal of the comparator 161B is given to the set input terminal S of the set / reset flip-flop 163B. As a result, the reset pulse RB becomes H level, and the triangular wave signal TRIB is initialized to 0V. After that, when the state signal S3 becomes H level, the state signal S4 becomes L level, and the pulse PB becomes L level, the set input terminal S of the set / reset flip-flop 163B becomes L level and the reset input terminal R becomes H level, The reset pulse RB for the triangular wave generator 110B becomes L level. As a result, the triangular wave signal TRIB starts to rise at a constant time gradient from 0V.

The operations of the comparator 161C, the low active OR-AND gate 162C, the set / reset flip-flop 163C, and the inverter 164C related to the triangular wave signals TRIC and TRIA are the same as above.
The above is the details of the synchronization signal generator 160 shown in FIG.

<Second Embodiment>
FIG. 7 is a circuit diagram showing a configuration of a synchronization signal generating circuit 100A according to the second embodiment of the present invention. This synchronization signal generating circuit 100A generates a triangular wave generation circuit 101A that generates triangular wave signals TRIA, TRIB, TRIC, and TRID from the PWM signal PWMIN, and generates a synchronization signal SYNC based on these triangular wave signals TRIA, TRIB, TRIC, and TRID. It is comprised by the synchronizing signal generation part 160A. The triangular wave generation circuit 101A includes a timing generation unit 102A and four triangular wave generation units 110A, 110B, 110C, and 110D. Here, the timing generation unit 102A detects the rising edge and the falling edge of the PWM signal PWMIN, maintains the L level over the period between the same kind of edges, and over the period between the same kind of edges thereafter. A pulse PA that repeats the change of maintaining the H level is output. In addition, the timing generation unit 102A outputs a pulse PB that repeats the same change as the pulse PA with a delay of a period between one different edge from the pulse PA. In addition, the timing generation unit 102A outputs a pulse PC that repeats the same change as the pulse PA with a delay of one inter-different edge period from the pulse PB. Further, the timing generation unit 102A outputs a pulse PD that repeats the same change as the pulse PA with a delay of one inter-edge period from the pulse PC. The triangular wave generators 110A, 110B, 110C and 110D are circuits similar to the triangular wave generator 110A of the first embodiment, and based on the pulses PA, PB, PC and PD, respectively, the triangular wave signals TRIA, TRIB, TRIC and TRID. Is generated. Triangular wave signals TRIA, TRIB, TRIC, and TRID are given to synchronization signal generator 160A. The synchronization signal generator 160A inverts the level of the synchronization signal SYNC and is generated in advance when the magnitude relationship of two triangular wave signals (for example, the triangular wave signals TRIA and TRIB) generated before and after switching. A reset pulse for initializing the triangular wave signal (triangular wave signal TRIA in this example) to 0V is output.

  FIG. 8 is a diagram showing signal waveforms at various parts of the synchronization signal generating circuit 100A. As illustrated in FIG. 8, the timing generation unit 102A sets the pulse PA to the L level over one homogeneous edge period (for example, t21-t23), and spans the one homogeneous edge period (for example, t23-t25). The operation of setting the pulse PA to the H level is repeated. Further, the timing generator 102A changes the pulse PB in the same manner as the pulse PA with a delay from the pulse PA by one period between different types of edges, and delays the pulse PC from the pulse PB by a period between one different types of edges as the pulse PA. Further, the pulse PD is changed in the same manner as the pulse PA with a delay from the pulse PC by a period between one different edge.

  The triangular wave signal TRIA rises from 0 V to the voltage VP at a constant time gradient in the period between the same kind of edges (t21 to t23) in which the pulse PA maintains the L level, and then the period between the different kinds of edges (t23 to t24). Then, since the pulse PA becomes the H level, the voltage PA starts to decrease from the voltage VB with the same time gradient as that at the time of increase. On the other hand, the pulse PB becomes L level in one inter-edge period (t22 to t24) delayed by one inter-edge period from the pulse PA. In one inter-edge period (t22 to t24) in which the pulse PB maintains the L level, the triangular wave signal TRIB rises from 0 V to the voltage VP at the same constant time gradient as the rising triangular wave signal TRIA. Therefore, the triangular wave signals TRIA and TRIB intersect at the sampling point at the center of the period between one different edge (t23-t24) immediately after the pulse PA becomes H level, and the triangular wave signals TRIA and TRIB The relationship of TRIB switches from TRIA> TRIB to TRIA <TRIB. As a result, the synchronization signal generator 160A inverts the level of the synchronization signal SYNC at the sampling point, and initializes the triangular wave signal TRIA to 0 V by setting the reset pulse RA to H level.

  In the period between one different edge (t24-t25), since the pulse PB becomes H level, the triangular wave signal TRIB starts to decrease from the voltage VP with the same time-wise reverse time gradient as that when rising. On the other hand, the pulse PC becomes L level in one inter-edge period (t23 to t25) that is delayed by one inter-edge period from the pulse PB. In one inter-edge period (t23 to t25) in which the pulse PC maintains the L level, the triangular wave signal TRIC rises from 0 V to the voltage VP at the same constant time gradient as the rising triangular wave signal TRIB. Therefore, the triangular wave signals TRIB and TRIC intersect at the sampling point in the center of the period between one different edge (t24-t25) immediately after the pulse PB becomes H level, and the triangular wave signals TRIB and TRIC The relationship of TRIC is switched from TRIB> TRIC to TRIB <TRIC. As a result, the synchronization signal generator 160A inverts the level of the synchronization signal SYNC at the sampling point, and sets the reset pulse RB to H level to initialize the triangular wave signal TRIB to 0V.

  The same applies to the following, and in the period between one different edge (t25-t26) after the period between one different edge (t24-t25), the falling triangular wave signal TRIC and the rising triangular wave signal TRID cross and synchronize at the sampling point. The level of the signal SYNC is inverted, and in the subsequent period between different kinds of edges (t26 to t27), the falling triangular wave signal TRID and the rising triangular wave signal TRIA intersect at the sampling point, and the level of the synchronizing signal SYNC is inverted.

  FIG. 9 is a circuit diagram showing a specific configuration example of the timing generator 102A in the present embodiment. As shown in FIG. 9, the timing generation unit 102A includes a toggle flip-flop 126 that inverts the level by using the rising edge of the PWM signal PWMIN as a trigger, a toggle flip-flop 127 that inverts the level by using the falling edge of the PWM signal PWMIN, It is composed of four NAND gates 128A, 128B, 128C and 128D. Here, the positive logic output signal (Q output signal) of the toggle flip-flop 126 is pulse PA and the negative logic output signal is pulse PC, and the positive logic output signal (Q output signal) of the toggle flip-flop 127 is the pulse PB and negative logic. The output signal becomes pulse PD. With such a configuration, the pulses PA, PB, PC, and PD shown in FIG. 8 are obtained from the PWM signal PWMIN. The NAND gate 128A sets the state signal S0 to L level only during the period when the pulses PB and PC are at the H level, and the NAND gate 128B sets the state signal S1 to L level only during the period when the pulses PC and PD are at the H level. 128C sets the state signal S2 to L level only during the period when the pulses PD and PA are at H level, and the NAND gate 128D sets the state signal S3 to L level only during the period when the pulses PA and PB are at H level.

FIG. 10 is a circuit diagram showing a specific configuration example of the synchronization signal generator 160A in the present embodiment. In addition, in each part shown in FIG. 10, the same code | symbol is used for the part corresponding to above-mentioned FIG. In FIG. 10, comparators 161 </ b> A to 161 </ b> D are means for detecting switching of the magnitude relationship of the triangular wave signals TRIA to TRID. More specifically, the comparator 161A raises an output signal when switching from TRIA> TRIB to TRIA <TRIB, and the comparator 161B raises an output signal when switching from TRIB> TRIC to TRIB <TRIC. 161C raises an output signal when switching from TRIC> TRID to TRIC <TRID, and the comparator 161D raises an output signal when switching from TRID> TRIA to TRID <TRIA.
The AND gate 167A passes the output signal of the comparator 161A only during the period when the state signal S2 is at the L level, and the AND gate 167B passes the output signal of the comparator 161B only during the period when the state signal S3 is at the L level. 167C passes the output signal of the comparator 161C only during the period when the state signal S0 is at the L level, and the AND gate 167D passes the output signal of the comparator 161D only during the period when the state signal S1 is at the L level.

  The output signals of the AND gates 167A, 167B, 167C, and 167D are supplied to the clock input terminal C of the toggle flip-flop 166 via the OR gate 168. The signal at the positive logic output terminal Q of the toggle flip-flop 166 becomes the synchronization signal SYNC.

  In the set-reset flip-flop 163A, the output signal of the AND gate 167A is supplied to the set terminal S, and the pulse PA output from the timing generator 102A is inverted by the inverter 164A and supplied to the reset terminal R. The output signal of the set / reset flip-flop 163A is supplied as a reset pulse RA to the triangular wave generator 110A in FIG. In the set-reset flip-flop 163B, the output signal of the AND gate 167B is given to the set terminal S, and the pulse PB output from the timing generator 102A is inverted by the inverter 164B and given to the reset terminal R. Then, the output signal of the set-reset flip-flop 163B is supplied as a reset pulse RB to the triangular wave generator 110B in FIG. In the set-reset flip-flop 163C, the output signal of the AND gate 167C is given to the set terminal S, and the pulse PC output from the timing generator 102A is inverted by the inverter 164C and given to the reset terminal R. The output signal of the set / reset flip-flop 163C is supplied as a reset pulse RC to the triangular wave generator 110C in FIG. In the set-reset flip-flop 163D, the output signal of the AND gate 167D is given to the set terminal S, and the pulse PD output from the timing generator 102A is inverted by the inverter 164D and given to the reset terminal R. The output signal of the set / reset flip-flop 163D is supplied as a reset pulse RD to the triangular wave generator 110D in FIG.

  In such a configuration, as shown in FIG. 8, in the period between different edges (t23 to t24) in which the pulse PA is at the H level, the triangular wave signal TRIA decreases from the voltage VP with a constant time gradient, and the triangular wave signal TRIB It rises with a constant time gradient toward VB. Then, switching from TRIA <TRIB to TRIA> TRIB occurs at the sampling point at the center of the period between different edges (t23 to t24), and the output signal of the comparator 161A rises. At this time, since the pulses PA and PD are at the H level and the state signal S2 is at the L level, the rising edge of the output signal of the comparator 161A passes through the AND gate 167A and is toggled through the OR gate 165. 166 to the clock input terminal C. As a result, the level of the synchronization signal SYNC is inverted. The rising edge of the output signal of the comparator 161A is given to the set input terminal S of the set / reset flip-flop 163A. As a result, the reset pulse RA becomes H level, and the triangular wave signal TRIA is initialized to 0V. Thereafter, when the pulse PA becomes L level, the set input terminal S of the set-reset flip-flop 163A becomes L level, the reset input terminal R becomes H level, and the reset pulse RA for the triangular wave generator 110A becomes L level. As a result, the triangular wave signal TRIA starts to rise at a constant time gradient from 0V.

  Next, as shown in FIG. 8, in the period between different edges (t24-t25) in which the pulse PB is at the H level, the triangular wave signal TRIB decreases from the voltage VP with a constant time gradient, and the triangular wave signal TRIC is directed toward the voltage VB. Rise with a certain time gradient. Then, at the center sampling point of the period between different edges (t24-t25), switching from TRIB <TRIC to TRIB> TRIC occurs, and the output signal of the comparator 161B rises. At this time, since the pulses PA and PB are at the H level and the state signal S3 is at the L level, the rising edge of the output signal of the comparator 161B passes through the AND gate 167B and is toggled through the OR gate 165. 166 to the clock input terminal C. As a result, the level of the synchronization signal SYNC is inverted. The rising edge of the output signal of the comparator 161B is given to the set input terminal S of the set / reset flip-flop 163B. As a result, the reset pulse RB becomes H level, and the triangular wave signal TRIB is initialized to 0V. Thereafter, when the pulse PB becomes L level, the set input terminal S of the set-reset flip-flop 163B becomes L level, the reset input terminal R becomes H level, and the reset pulse RB for the triangular wave generator 110B becomes L level. As a result, the triangular wave signal TRIB starts to rise at a constant time gradient from 0V.

  The operations of the comparator 161C, the AND gate 167C, the set / reset flip-flop 163C, and the inverter 164C related to the triangular wave signals TRIC and TRID are the same as described above. The operations of the comparator 161D, the AND gate 167D, the set / reset flip-flop 163D, and the inverter 164D related to the triangular wave signals TRID and TRIA are the same as described above.

  Also in this embodiment, the same effect as the first embodiment can be obtained. Further, as can be seen from a comparison between FIG. 4 and FIG. 9, the present embodiment has an advantage that the configuration of the timing generator 102A can be simplified as compared with the first embodiment.

<Other embodiments>
While the first and second embodiments of the present invention have been described above, various other embodiments are conceivable for the present invention. For example:
(1) In each of the above embodiments, when the magnitude relationship between two triangular wave signals generated in succession is switched, the level of the synchronization signal SYNC is inverted and the triangular wave signal generated in advance is initialized to 0V. However, the triangular wave signal may be initialized to a reference level other than 0V.
(2) In the above embodiment, in accordance with the sequential detection of edges from the PWM signal PWMIN, the triangular wave signal starting from the positive time gradient is sequentially generated, and the negative time gradient section in the preceding triangular wave signal and the subsequent The level of the synchronization signal SYNC was inverted at the point where the positive time gradient section of the triangular wave signal intersects. However, as the edges are sequentially detected from the PWM signal PWMIN, a triangular wave signal starting from a negative time gradient is sequentially generated, and the positive time gradient section in the preceding triangular wave signal and the negative time of the subsequent triangular wave signal are generated. The level of the synchronization signal SYNC may be inverted at the point where the gradient section intersects.
(3) The above embodiment is based on the premise that the period between similar edges generated in the PWM signal PWMIN is synchronized with the sampling period of the PWM signal PWMIN. In a situation where the waveform of the analog signal used to generate the PWM signal PWMIN does not change suddenly, this premise is almost satisfied, so that a synchronization signal SYNC accurately synchronized with the PWM signal PWMIN is obtained. However, when an abrupt change occurs in the waveform of the analog signal used to generate the PWM signal PWMIN, the period between the same types of edges of the PWM signal PWMIN generated as a result is temporarily with respect to the sampling period of the PWM signal PWMIN. It may cause synchronization loss. In order to compensate for such a temporary synchronization shift, for example, the synchronization signal SYNC is given to a PLL (Phase Locked Loop), and a synchronization signal in which the period variation of the synchronization signal SYNC is relaxed is generated by the PLL and regenerated. It may be supplied to the modulation circuit 200.

DESCRIPTION OF SYMBOLS 100,100A ... Synchronization signal generation circuit, 101, 101A ... Triangle wave generation circuit, 102, 102A ... Timing generation unit, 110A, 110B, 110C, 110D ... Triangle wave generation unit, 160, 160A ... Synchronization signal generation unit , 111, 114, 116... Switch, 112, 113 .. constant current source, 115... Capacitor, 121-124 .. flip-flop, 125 .. NOR gate, 131-135, 128A, 128B, 128C, 128D. ... NAND gate, 136, 164A, 164B, 164C, 164D ... Inverter, 137A, 137B, 137C ... Low active NOR gate, 161A, 161B, 161C, 161D ... Comparator, 162A, 162B, 162C ... Low active OA -AND gate 163A, 163B, 163C, 163D ... set reset flip-flop, 165 ... OR gate, 166, 126, 127 ... toggle flip-flop, 167A, 167B, 167C, 167D ... AND gate, 200 ... remodulation circuit, 201... Demodulation circuit 202... Triangular wave generation circuit 203.

Claims (1)

A means for generating a triangular wave signal in parallel with the generation of a triangular wave signal that has been started in advance each time a rising edge and a falling edge of the input pulse width modulation signal are detected. After detecting the edge, the triangular wave signal is changed with a constant time gradient from the reference level, and then, after the same kind of edge is detected, the triangular wave generating means for changing the triangular wave signal with the same time reverse gradient,
A means for generating a synchronizing signal synchronized with the pulse width modulation signal based on a triangular wave signal generated by the triangular wave generating means, the magnitude of two triangular wave signals started to be generated before and after the triangular wave generating means When the relationship is reversed, the level of the synchronization signal is reversed, and among the two triangular wave signals that have been generated before and after the phase, the triangular wave signal that has been generated in advance is initialized to a reference level and stopped. And a signal generation means.

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