JP2010283518A - Image processor, and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform burst transfer of a progressive image without including unnecessary data when performing IP (Interlace Progressive) conversion. <P>SOLUTION: A frame buffer controller 91 reads from a frame buffer memory 92 image data composing a progressive image and unnecessary data in units of blocks having a prescribed data size by line. A PCI-e memory controller 93 extracts only image data composing the read block and writes them to a PCI-e memory 94 in units of blocks. The frame buffer controller 91 reads a block composed of only image data or a block composed of image data and unnecessary data as a block by line. The invention is applicable to, for example, an image processor, such as a video card for converting an interlaced image into a progressive image. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method, and in particular, an image processing apparatus capable of transferring a progressive image obtained by, for example, IP (interlace progressive) conversion without including unnecessary data that is substantially unnecessary, and The present invention relates to an image processing method.

  Conventionally, there is an IP conversion processing technique for converting an interlaced image into a progressive image (see, for example, Patent Document 1).

  As an image processing apparatus that converts an interlaced image into a progressive image by IP conversion processing technology, for example, when an interlaced image such as an image of a television broadcast program is captured and stored in a personal computer, it is input. A video card (graphic card) that converts an interlaced image into a progressive image can be mentioned.

  In a conventional video card, for example, when an interlaced image is transferred to a personal computer, an odd field and an even field are alternately switched on a line-by-line basis as the interlaced image field. The progressive image is transferred to a personal computer.

  However, in this case, the video card needs to operate with a high-speed clock in order to switch the odd field and the even field alternately in line units.

  For this reason, when the video card is composed of a substrate using an FPGA (field programmable gate array), it is difficult to operate the video card with a high-speed clock. The method of switching and transferring with is not realistic.

  Therefore, there is a video card in which the odd field and the even field are combined on a memory built in the video card to generate a progressive image of a corresponding frame and then transferred to a personal computer.

[Configuration Example of Conventional Image Processing Apparatus 1]
FIG. 1 shows an example of the configuration of a conventional image processing apparatus 1 as a video card for synthesizing input interlaced images on a built-in memory and transferring the resulting progressive images to a personal computer.

  The image processing apparatus 1 is connected to a personal computer 2. The image processing apparatus 1 includes SDI (serial digital interface) 21 and 22, a frame buffer controller 23, a frame buffer memory 24, a codec 25, a PCI-e (peripheral components interconnect bus express) memory controller 26, and a PCI-e memory 27. And the PCI-e interface 28.

  The SDI 21 is an interface conforming to the SDI standard, and supplies an interlaced image supplied from a video switcher or a video transmitter (not shown) to the frame buffer controller 23.

  The SDI 22 outputs the interlaced image or progressive image supplied from the frame buffer controller 23 to a monitor or the like (not shown).

  The frame buffer controller 23 is disturbed, for example, by part of the image data constituting the interlaced image from the SDI 21 being lost due to image switching by the video switcher connected to the SDI 21 or insertion / removal of the connector of the SDI 21. Determine if it has occurred. The frame buffer controller 23 supplies the interlaced image to the frame buffer memory 24 and temporarily stores it only when it is determined that the interlaced image from the SDI 21 is not disturbed.

  In addition, the frame buffer controller 23 reads the interlaced image stored in the frame buffer memory 24 and without any disturbance, and supplies the interlaced image to the codec 25 and the PCI-e memory controller 26.

  Thereby, for example, it is possible to prevent the interlaced image in which the disturbance has occurred from being supplied from the frame buffer controller 23 to the codec 25. For this reason, due to the fact that the interlaced image in which the disturbance has occurred is supplied to the codec 25, the encoding process of the interlaced image by the codec 25 cannot be performed normally, and the encoding process is interrupted. It is possible to prevent such as.

  The frame buffer controller 23 determines whether or not the interlaced image from the SDI 21 is disturbed, and supplies the interlaced image from the SDI 21 together with the determination result to the frame buffer memory 24 to temporarily. You may make it memorize | store.

  In this case, the frame buffer controller 23 reads only the interlaced image in which no disturbance has occurred based on the determination result stored in the frame buffer memory 24, and supplies it to the codec 25 and the PCI-e memory controller 26.

  Further, the frame buffer controller 23 supplies the interlaced image from the codec 25 and the interlaced image from the PCI-e memory controller 26 to the SDI 22.

  The frame buffer memory 24 temporarily stores (holds) an interlaced image from the frame buffer controller 23 that is not disturbed.

  The codec 25 encodes the interlaced image supplied from the frame buffer controller 23 and supplies the encoded data obtained as a result to the PCI-e memory controller 26. The codec 25 decodes the encoded data supplied from the PCI-e memory controller 26 and supplies an interlaced image obtained as a result to the frame buffer controller 23.

  The PCI-e memory controller 26 supplies the encoded data from the codec 25 to the PCI-e memory 27 for storage. Further, the PCI-e memory controller 26 reads the encoded data stored in the PCI-e memory 27 and supplies it to the codec 25.

  Further, the PCI-e memory controller 26 generates a progressive image of the frame obtained by synthesizing the odd and even fields of the interlaced image supplied from the frame buffer controller 23 in the storage area of the PCI-e memory 27. To do.

  That is, for example, the PCI-e memory controller 26 converts the lines constituting the interlaced image of the odd field supplied from the frame buffer controller 23 into the odd-numbered lines (odd-numbered lines) among the plurality of lines constituting the progressive image. ) In the storage area of the PCI-e memory 27.

  Further, the PCI-e memory controller 26 sets the lines constituting the even-field interlaced image supplied from the frame buffer controller 23 as even-numbered lines (even-numbered lines) among the plurality of lines constituting the progressive image. And stored in the storage area of the PCI-e memory 27.

  As a result, a corresponding progressive image is generated in the storage area of the PCI-e memory 27.

  Also, the PCI-e memory controller 26 transfers the image data constituting the progressive image generated in the storage area of the PCI-e memory 27 by one burst transfer for each line from the head to the end of the line. Data is read out in units of burst transfer size representing the data size that can be transferred, and burst transferred to the PCI-e interface 28 as a transfer block.

  Here, burst transfer refers to batch transfer for each transfer block having a burst transfer size.

  The burst transfer performed by the PCI-e memory controller 26 will be described later with reference to FIG.

  Further, the PCI-e memory controller 26 reads one of the two fields of interlaced images arranged as a progressive image from the PCI-e memory 27 and supplies it to the frame buffer controller 23.

  In addition, the PCI-e memory controller 26 can display the progressive image stored in the PCI-e memory according to the input speed of the interlaced image input from the SDI 21 to the frame buffer controller 23 without excess or deficiency. It is necessary to output to the personal computer 2 via

  Therefore, the PCI-e memory controller 26 operates with a clock that is faster than a clock that is required only for outputting a progressive image to the personal computer 2 via the PCI-e interface 28, and for data transfer. Burst transfer is employed to improve transfer efficiency.

  The PCI-e memory 27 stores the odd field and even field from the PCI-e memory controller 26 as a progressive image of the corresponding frame. The PCI-e memory 27 stores the encoded data from the PCI-e memory controller 26.

  The PCI-e interface 28 outputs a progressive image burst-transferred by the PCI-e memory controller 26 to the personal computer 2.

[Description of burst transfer performed by PCI-e memory controller 26]
Next, details of a process in which the PCI-e memory controller 26 performs burst transfer of a progressive image stored in the PCI-e memory 27 will be described.

  FIG. 2 shows an example of a progressive image stored in the storage area of the PCI-e memory 27.

  The progressive image is composed of first field data representing odd fields and second field data representing even fields.

  The PCI-e memory controller 26 reads out the image data constituting the progressive image generated in the storage area of the PCI-e memory 27 in units of burst transfer size in order from the head of the line for each line. Burst transfer to the PCI-e interface 28 is performed.

  Incidentally, for example, in FIG. 2, the data size of the image data constituting one line of each of the first field data and the second field data is aX + Y bits, and the burst transfer size is X bits. Therefore, the data size aX + Y of the image data constituting one line of each of the first field data and the second field data is a data size that cannot be divided by the burst transfer size X.

  Therefore, when image data constituting one line is divided into transfer blocks of burst transfer size X, a remainder block of data size Y (<X) less than the burst transfer size is generated at the end of the line. Become.

  The PCI-e memory controller 26 performs burst transfer of a transfer blocks of a burst transfer size X out of the image data constituting one line as it is.

  In addition, the PCI-e memory controller 26 uses the extra blocks of less than the burst transfer size in the image data constituting one line as the data irrelevant to the surplus blocks, and the data of the extra blocks from the burst transfer size X. Along with unnecessary data 52 representing data having a data size XY obtained by subtracting the size Y, burst transfer is performed as a transfer block having a burst transfer size.

  The reason why the surplus block is burst-transferred as a transfer block together with the unnecessary data 52 having the data size X-Y is that the data size Y of the surplus block is less than the burst transfer size X required for burst transfer.

  As a result, a transfer block including unnecessary data 52 is output from the PCI-e memory controller 26 to the personal computer 2 via the PCI-e interface 28.

JP 2003-179886 A

  As described above, the transfer block including the unnecessary data 52 is burst transferred to the personal computer 2, and the personal computer 2 reconstructs the transfer block and acquires the progressive image to acquire the progressive image. Processing to remove unnecessary data 52 from the transfer block including 52 is necessary.

  The present invention has been made in view of such a situation, and enables a progressive image to be burst-transferred without including unnecessary data that is substantially unnecessary during IP conversion.

  An image processing apparatus according to an aspect of the present invention is an image processing apparatus that converts an interlaced image into a progressive image, and holds image data in units of lines constituting the progressive image with unnecessary data added thereto. The progressive image is constituted by a first holding means, a second holding means for holding image data constituting the progressive image in units of blocks having a predetermined data size, and the first holding means. Reading means for reading out the image data and the unnecessary data in units of the block for each line, and extracting only the image data constituting the read block, and the second unit in units of the blocks. First writing means for writing to the holding means, and the reading means is the block for each line. , Block composed only by the image data, or reads the block constituted by the image data and the required data.

  Corresponding means for associating a data valid flag indicating whether or not the data is the unnecessary data with respect to the data constituting the read block can be further provided. In the first writing means, Based on the data valid flag, only the image data constituting the block can be extracted and written to the second holding unit in units of the block.

  Corresponding means for associating a data valid flag indicating whether or not the unnecessary data is included in the block may be further provided for the read block, and the first writing means may include the data valid flag. Based on the flag, only the image data constituting the block can be extracted and written in the second holding unit in units of the block.

  The first writing unit may convert the extracted image data according to a predetermined format and write the converted image data to the second holding unit in units of the block.

  In the reading unit, the image data and the unnecessary data constituting the progressive image are read from the first holding unit in units of the block having a burst transfer size capable of burst transfer for each line. can do.

  Transfer means for reading out the block having the burst transfer size from the second holding means and performing burst transfer can be further provided.

  When the line-unit image data constituting the interlaced image of the odd field and the even field corresponding to the frame of the progressive image is divided in the unit of the block, there is a surplus block less than the data size of the block. An adding means for adding the unnecessary data corresponding to the data size obtained by subtracting the data size of the remainder block from the data size of the block to the image data in units of lines constituting each of the interlaced images. The image data for each line constituting each of the interlaced images to which the unnecessary data is added is written in the second holding means as the image data for each line constituting the progressive image to which the unnecessary data is added. Second writing means and more It can be provided.

  The first writing unit can also serve as the second writing unit.

  The first holding means can also serve as the second holding means.

  An image processing method according to one aspect of the present invention is an image processing method of an image processing apparatus that converts an interlaced image into a progressive image, and the image processing apparatus includes a first holding unit, a second holding unit, A first reading unit; a first writing unit, wherein the reading unit holds the image data in units of lines constituting the progressive image in a state where unnecessary data is added; The image data constituting the progressive image and the unnecessary data are read in units of the block for each line, and the first writing means extracts only the image data constituting the read block. The image data constituting the progressive image is held in units of blocks having a predetermined data size in units of the blocks. A step of writing in the second holding unit, wherein the reading unit is a block configured by only the image data or a block configured by the image data and the unnecessary data for each line as the block. Is read.

  In the present invention, the image data and the unnecessary data constituting the progressive image are read from the first holding unit for each line in the unit of the block, and the read block is constituted. Only the image data is extracted and written to the second holding unit in units of the block.

  According to the present invention, a progressive image can be burst-transferred without including unnecessary data that is substantially unnecessary during IP conversion.

It is a block diagram which shows the structural example of the conventional image processing apparatus. It is a figure which shows an example of the progressive image memorize | stored in the PCI-e memory. It is a block diagram which shows the structural example of the image processing apparatus which is this Embodiment. It is a block diagram which shows the structural example of a frame buffer controller. It is a figure which shows an example of a DPX format. It is a figure which shows an example of the interlace image for 1 line. It is a figure which shows an example of a transfer block. It is a block diagram which shows the structural example of a PCI-e memory controller. It is a figure for demonstrating the process which a PCI-e memory controller performs. FIG. 10 is another diagram for explaining processing performed by the PCI-e memory controller. It is a flowchart for demonstrating a write-in process. It is a flowchart for demonstrating odd line generation processing. It is a flowchart for demonstrating even line production | generation processing. It is a flowchart for demonstrating a read-out process. It is a flowchart for demonstrating an unnecessary data removal process. FIG. 10 is a block diagram showing another configuration example of the PCI-e memory controller. It is a block diagram which shows the structural example of a computer.

Hereinafter, modes for carrying out the invention (hereinafter referred to as the present embodiment) will be described. The description will be given in the following order.
1. Embodiment (example of removing unnecessary data from a progressive image)
2. Modified example

<1. Embodiment>
[Configuration Example of Image Processing Device 71]
FIG. 3 shows a configuration example of the image processing apparatus 71 according to this embodiment.

  The image processing device 71 corresponds to, for example, a video card connected to the personal computer 2. In the image processing apparatus 71, the same reference numerals are given to the same components as those of the image processing apparatus 1 in FIG.

  That is, the image processing apparatus 71 is replaced with the frame buffer controller 23, the frame buffer memory 24, the PCI-e memory controller 26, and the PCI-e memory 27 provided in the image processing apparatus 1 of FIG. 91, except that a frame buffer memory 92, a PCI-e memory controller 93, and a PCI-e memory 94 are provided.

  An interlaced image is supplied from the SDI 21 to the frame buffer controller 91. The frame buffer controller 91 generates a corresponding progressive image in the storage area of the frame buffer memory 92 based on the first field data and the second field data of the interlaced image supplied from the SDI 21.

  Further, the frame buffer controller 91 reads out image data constituting the progressive image generated in the storage area of the frame buffer memory 92 for each transfer block in units of one line.

  Then, the frame buffer controller 91 associates the read transfer block with a data valid flag indicating whether or not unnecessary data is included, and supplies it to the PCI-e memory controller 93.

  Note that the data valid flag is set to true when unnecessary data is not included in the transfer block, and is set to false when unnecessary data is included in the transfer block.

  The frame buffer memory 92 stores the first field data and the second field data from the frame buffer controller 91 as a progressive image of the corresponding frame.

  The PCI-e memory controller 93 determines whether or not unnecessary data is included in the transfer block based on the data valid flag associated with the transfer block from the frame buffer controller 91.

  If the PCI-e memory controller 93 determines that unnecessary data is included in the transfer block based on the data valid flag associated with the transfer block from the frame buffer controller 91, the image constituting the transfer block Among data and unnecessary data, unnecessary data is discarded (ignored) and image data is acquired (extracted).

  Note that the PCI-e memory controller 93 distinguishes unnecessary data and image data constituting a transfer block based on, for example, the data size of one line constituting a progressive image, the burst transfer size, etc., and only image data. Is getting.

  If the PCI-e memory controller 93 determines that unnecessary data is not included in the transfer block based on the data valid flag associated with the transfer block from the frame buffer controller 91, the PCI-e memory controller 93 configures the transfer block. Acquire image data.

  Further, when the PCI-e memory controller 93 acquires the image data for the burst transfer size, the PCI-e memory controller 93 converts the image data for the burst transfer size in units of the burst transfer size (as a transfer block of the burst transfer size). The data is supplied to the memory 94 and stored.

  The PCI-e memory controller 93 reads a transfer block having a burst transfer size from the PCI-e memory 94 and performs burst transfer to the personal computer 2 via the PCI-e interface 28.

  Note that the PCI-e memory controller 93 displays the progressive image stored in the PCI-e memory 94 according to the input speed of the interlaced image input from the SDI 21 to the frame buffer controller 91. It is necessary to output it to the personal computer 2 via 28.

  Accordingly, the PCI-e memory controller 93 is operated by a clock faster than a clock required for simply outputting a progressive image to the personal computer 2 via the PCI-e interface 28, and data Burst transfer is employed to improve transfer efficiency.

  The PCI-e memory 94 stores the image data supplied in burst transfer size from the PCI-e memory controller 93 as a transfer block of burst transfer size.

[Configuration Example of Frame Buffer Controller 91]
Next, FIG. 4 shows a configuration example of the frame buffer controller 91.

  The frame buffer controller 91 mainly includes an input port 111 incorporating a FIFO (first in first out) memory 111a, a monitoring unit 112, an arbiter memory controller 113, an output port 114 incorporating a FIFO memory 114a, and a FIFO memory 115a. Output port 115.

  The same interlaced image (first field data or second field data) is input (supplied) from the SDI 21 to the input port 111 and the monitoring unit 112, respectively.

  The input port 111 inputs and stores the interlaced image from the SDI 21 into the built-in FIFO memory 111a in the order supplied from the SDI 21.

  Further, the input port 111 causes the arbiter memory controller 113 to output the interlaced images that are input and stored in the FIFO memory 111a in the input order.

  The monitoring unit 112 determines whether or not there is a disturbance in the interlaced image from the SDI 21 (the same interlaced image input from the FIFO memory 111a to the arbiter memory controller 113), and the determination result is used as the arbiter. This is supplied to the memory controller 113.

  The arbiter memory controller 113 has an arbiter function that controls writing and reading of data with respect to the input port 111, the output ports 114 and 115, and the frame buffer memory 92.

  That is, for example, when the arbiter memory controller 113 obtains the determination result that the interlaced image from the FIFO memory 111a is not disturbed from the monitoring unit 112, the arbiter memory controller 113 outputs the interlaced image from the FIFO memory 111a to the output port. The data is input to and stored in the FIFO memory 114 a 114 and supplied to the frame buffer memory 92 for storage.

  Further, the arbiter memory controller 113 reads the progressive image stored in the frame buffer memory 92 as a transfer block in units of burst transfer size for each line.

  The arbiter memory controller 113 may supply the interlaced image from the FIFO memory 111a to the frame buffer memory 92 in association with the determination result from the monitoring unit 112 for storage.

  In this case, based on the determination result stored in the frame buffer memory 92, the arbiter memory controller 113 transfers only the progressive image corresponding to the uninterrupted interlaced image in units of burst transfer size for each line. Read as a block.

  The arbiter memory controller 113 associates the read transfer block with the corresponding data valid flag, and inputs the transfer block associated with the data valid flag obtained as a result to the FIFO memory 115a of the output port 115. To remember.

  Further, the arbiter memory controller 113 performs a refresh operation on the frame buffer memory 92 in addition to writing and reading data by the arbiter function.

  The output port 114 reads out the interlaced images that are input and stored in the FIFO memory 114 a in the input order, and outputs them to the codec 25.

  The output port 115 reads the transfer blocks input and stored in the FIFO memory 115a in the order of input to the FIFO memory 115a, and sequentially outputs them to the PCI-e memory controller 93.

[Description of processing performed by frame buffer controller 91]
Next, details of processing performed by the frame buffer controller 91 will be described with reference to FIGS. 5 to 7.

  In the frame buffer controller 91, the arbiter memory controller 113 converts the first field data and the second field data of the interlaced image supplied from the SDI 21 via the input port 111 and the FIFO memory 111 a to a file in the personal computer 2, for example. It is converted into a predetermined format such as DPX (digital picture exchange) format that can be easily converted.

  FIG. 5 shows the data structure of DPX storage data, which is an example of the DPX format.

  The DPX storage data shown in FIG. 5 includes, for example, three 10-bit data representing the image data constituting the first field data and the second field data, and the 2-bit data representing the control data “00”.

  The arbiter memory controller 113 converts, for example, first field data and second field data from the FIFO memory 111a of the input port 111 into a plurality of DPX storage data for each line.

  Next, the details of the process in which the arbiter memory controller 113 converts one line of the first field data into a plurality of DPX storage data will be described with reference to FIG. Since one line in the second field data is also converted into a plurality of DPX storage data as in the case of the first field data, one line in the second field data is converted into a plurality of DPX storage data. The description of the processing to be performed is omitted below.

  FIG. 6 shows an example of first field data for one line that is converted into a plurality of DPX storage data by the arbiter memory controller 113.

  In FIG. 6, the first field data for one line indicated by diagonal lines is converted into a plurality of DPX storage data by the arbiter memory controller 113, and the first image data constituting the progressive image indicated by the largest rectangle in FIG. The data is stored in the frame buffer memory 92 as a line.

  In the first field data, it is assumed that the Y component, Cb component, and Cr component are sampled at a ratio of Y: Cb: Cr = 4: 2: 2. In this case, the number of Y component, Cb component, and Cr component (representing data) for one line is 2048 Y data representing Y component, 1024 Cb data representing Cb component, and Cr component, respectively. The total number of Cr data that represents 1024 is 4096.

  If the number of bits representing one pixel is 10 bits, the first field data for one line is represented by 4096 10-bit data.

  Therefore, in this case, the arbiter memory controller 113 converts 4096 pieces of 10-bit data into a plurality of DPX storage data according to the DPX format.

  Next, FIG. 7 shows an example of converted DPX storage data and a transfer block constituted by the DPX storage data.

In FIG. 7, DPX stored data 51 ₁ through 51 _1366, the arbiter memory controller 113, the 4096 10-bit data P1-1 to P1-4096, shows an example of a DPX storing data converted in accordance with DPX format Yes.

  The 10-bit data P1-1 to P1-4096 represent 4096 10-bit data in the first field data for one line indicated by hatching in FIG.

  As described above, there are 4096 pieces of 10-bit data P1-1 to P1-4096, and DPX storage data is data composed of three pieces of 10-bit data and 2-bit data representing “00”.

Therefore, the arbiter memory controller 113, for example, 1365 (= 4095/3) based on 4095 pieces of 10-bit data P1-1 to P1-4095 out of 4096 pieces of 10-bit data P1-1 to P1-4096. Pieces of DPX storage data 51 _{1 to} 51 ₁₃₆₅ are generated.

In addition, the arbiter memory controller 113 selects 10-bit data P1-4096, 20-bit unnecessary data 52 based on the remaining 10-bit data P1-4096 out of 4096 10-bit data P1-1 to P1-4096. And DPX storage data 51 ₁₃₆₆ composed of 2-bit data representing “00”.

The arbiter memory controller 113 supplies the generated 1366 pieces of DPX storage data 51 _{1 to} 51 ₁₃₆₆ to the frame buffer memory 92 for storage.

Further, the arbiter memory controller 113, the DPX stored data 51 ₁ to 51 ₁₃₆₆ stored in the storage area of the frame buffer memory 92, as the burst transfer size, for example, reads a 64-bit transfer block.

  The burst transfer size refers to the type of frame buffer memory 92 (for example, single data rate or double data rate), the number of memories constituting the frame buffer memory 92, and the connection between the arbiter memory controller 113 and the frame buffer memory 92. The optimum value is determined by the bus width (transfer rate) of the bus to be used.

The arbiter memory controller 113 is composed of transfer blocks (for example, DPX storage data 51 ₁ and 51 ₂ ) composed only of image data (for example, 10-bit data P1-1 to P1-6) among the read transfer blocks. Transfer block) is associated with a true data valid flag and input to the FIFO memory 115a of the output port 115.

The arbiter memory controller 113 also includes a transfer block (for example, 10-bit data P1-4093 to P1-4096) and unnecessary data (for example, unnecessary data 52) among the read transfer blocks. For the transfer block composed of DPX storage data 51 ₁₃₆₅ and 51 ₁₃₆₆ ), the data valid flag set to false is associated with each other and input to the FIFO memory 115a of the output port 115.

  Note that the arbiter memory controller 113 sets the position on the storage area of the frame buffer memory 92 where the transfer block constituted only by image data and the transfer block constituted by image data and unnecessary data are stored in one line. Therefore, the corresponding data valid flag can be associated with the read transfer block.

[Configuration example of PCI-e memory controller 93]
Next, FIG. 8 shows a configuration example of the PCI-e memory controller 93.

PCI-e memory controller 93, RFIFO (natural number of _n from 1 to N) input and output ports 131 n incorporating the memory 131a _n and WFIFO memory 131b _n, and constituted by the arbiter memory controller 132.

For example, a transfer block associated with a data valid flag is supplied from the frame buffer controller 91 to the input / output port 131 _n .

The input / output port 131 _n inputs and stores the transfer block from the frame buffer controller 91 in the built-in WFIFO memory 131b _n .

The input / output port 131 _n reads out the transfer blocks from the WFIFO memory 131 b _n in the order of input, and outputs them to the arbiter memory controller 132.

Furthermore, the input-output port 131 _n is in RFIFO memory 131a _n, the transfer block input from the arbiter memory controller 132 reads the order they are entered, burst transfers to PCI-e interface 28.

The RFIFO memory 131a _n and the WFIFO memory 131b _n have a memory capacity capable of storing a plurality of transfer blocks. Therefore, the input / output port 131 _n can perform burst transfer with a high-speed clock using the RFIFO memory 131a _n and the WFIFO memory 131b _n capable of storing a plurality of transfer blocks.

The arbiter memory controller 132 has an arbiter function that controls writing and reading of data with respect to the input / output port 131 _n and the PCI-e memory 94.

That is, for example, when the data valid flag associated with the transfer block from the WFIFO memory 131b _n is true, the arbiter memory controller 132 acquires the image data constituting the transfer block.

Further, for example, when the data valid flag associated with the transfer block from the WFIFO memory 131b _n is false, the arbiter memory controller 132 ignores unnecessary data among the image data and unnecessary data constituting the transfer block. In addition, image data is acquired.

  The arbiter memory controller 132 obtains only image data by distinguishing unnecessary data and image data constituting a transfer block based on, for example, the data size of one line constituting a progressive image and the burst transfer size. is doing.

  Then, the arbiter memory controller 132 supplies the image data for the burst transfer size to the PCI-e memory 94 as a transfer block of the burst transfer size in response to the acquisition of the image data for the burst transfer size. Let

Further, for example, arbiter memory controller 132 reads the transfer block which is stored in the PCI-e memory 94, and stores enter the RFIFO memory 131a _n.

  Furthermore, the arbiter memory controller 132 performs a refresh operation on the PCI-e memory 94 in addition to writing and reading data by the arbiter function.

[Description of processing performed by the PCI-e memory controller 93]
Next, details of processing performed by the PCI-e memory controller 93 will be described with reference to FIGS. 9 and 10.

  FIG. 9 shows an example of a progressive image stored in the storage area of the PCI-e memory 94.

  The PCI-e memory controller 93 acquires image data constituting a transfer block whose data validity flag is true among the transfer blocks supplied from the frame buffer controller 91.

  Further, the PCI-e memory controller 93 ignores unnecessary data among the image data and unnecessary data constituting the transfer block whose data valid flag is false among the transfer blocks supplied from the frame buffer controller 91, Get image data.

  In response to the acquisition of the image data for the burst transfer size, the PCI-e memory controller 93 converts the acquired image data for the burst transfer size as a transfer block of the burst transfer size as shown in FIG. It is supplied to the PCI-e memory 94 and stored.

  Next, referring to FIG. 10, in response to the PCI-e memory controller 93 acquiring image data for the burst transfer size, the acquired image data is transferred in units of transfer blocks of burst transfer size. Details of processing to be supplied to and stored in the PCI-e memory 94 will be described.

  FIG. 10 shows an example of a transfer block stored in the PCI-e memory 94 and DPX storage data constituting the transfer block.

  In FIG. 10, 10-bit data P1-1 to P1-4096 represent 10-bit data constituting the first line from the top among a plurality of lines constituting the progressive image.

  Further, 10-bit data P2-1 to P2-4096 represent 10-bit data constituting the second line from the top among the plurality of lines constituting the progressive image.

The arbiter memory controller 132 is supplied with a transfer block associated with a data valid flag from the frame buffer controller 91 via the input / output port 131 _n and the WFIFO memory 131b _n .

The arbiter memory controller 132 acquires the image data included in the transfer block based on the data valid flag associated with the transfer block from the WFIFO memory 131b _n . Then, the arbiter memory controller 132 converts the image data for the burst transfer size into a plurality of DPXs in response to the acquisition of the image data for the burst transfer size (image data transferred in batch in the burst transfer). The data is converted into stored data and supplied to the PCI-e memory 94 as a transfer block for storage.

In this case, for example, the arbiter memory controller 132 acquires the acquired image data as the DPX storage data 151 in response to the acquisition of the 10-bit data P1-1 to P1-6 as the image data for the burst transfer size. ₁ and 151 ₂ , and supplied to the PCI-e memory 94 as a transfer block for storage.

Similarly, the PCI-e memory controller 93 converts the 10-bit data P1-7 to P1-4092 into DPX stored data 151 _{3 to} 151 ₁₃₆₄ , and a combination of the DPX stored data 151 _2n-1 and 151 _2n (n Is a natural number from 2 to 682) as a transfer block and supplied to the PCI-e memory 94 for storage.

Further, the PCI-e memory controller 93 converts the acquired 10-bit data P1-4093 to P1-4095 for the burst transfer size into DPX storage data 151 ₁₃₆₅ . Also, the PCI-e memory controller 93 generates 10-bit data P1-4096 and 10-bit data P2-1 to P2-4096 as 10-bit data corresponding to the acquired burst transfer size. P2-2 is converted into DPX storage data 151 ₁₃₆₆ in accordance with the DPX format.

Then, the PCI-e memory controller 93 supplies the combination of the DPX storage data 151 ₁₃₆₅ and 151 _{1366 to} the PCI-e memory 94 as a transfer block and stores it.

The PCI-e memory controller 93 similarly applies the DPX storage data 151 _{1367 for the} 10th bit data P2-3 to P2-4096 and the third and subsequent lines from among the plurality of lines constituting the progressive image. and converted to DPX storing data such as 151 _1368, a combination of DPX storing data, and supplies the PCI-e memory 94 is stored as a transfer block.

  In this way, the PCI-e memory controller 93 generates DPX storage data that does not include the unnecessary data 52, and uses the combination of the two DPX storage data as a transfer block having a burst transfer size. To be stored.

[Description of write processing operation]
Next, a writing process in which the frame buffer controller 91 generates the progressive image of the corresponding frame by writing the first field data and the second field data from the SDI 21 in the recording area of the frame buffer memory 92 will be described.

  FIG. 11 is a flowchart for explaining the writing process.

  In step S1, the input port 111 repeats the process of determining whether or not the first field data is input from the SDI 21 among the fields of the interlaced image until it is determined that the first field data is input.

  When the input port 111 determines that the first field data is input, the input port 111 inputs the first field data from the SDI 21 into the built-in FIFO memory 111a and stores it.

  The input port 111 outputs the first field data input and stored in the FIFO memory 111a to the arbiter memory controller 113 in the input order, and the process proceeds to step S2.

  In step S2, the monitoring unit 112 determines whether or not there is a disturbance in the first field data from the SDI 21 (the same first field data that is input from the FIFO memory 111a to the arbiter memory controller 113). The determination result is supplied to the arbiter memory controller 113.

  In step S3, when the monitoring unit 112 determines that there is no disturbance in the same first field data input from the FIFO memory 111a to the arbiter memory controller 113, the process proceeds to step S4.

  In step S4, the arbiter memory controller 113 receives the determination result that the first field data from the FIFO memory 111a is not disturbed from the monitoring unit 112 in response to the first result from the FIFO memory 111a. An odd line generation process for storing the field data in the frame buffer memory 92 as an odd line of a plurality of lines constituting the progressive image is performed.

  The details of the odd line generation processing will be described later with reference to the flowchart of FIG.

  In step S5, the input port 111 repeats the process of determining whether or not the second field data is input from the field of the interlaced image from the SDI 21 until it is determined that the second field data is input.

  When the input port 111 determines that the second field data has been input, the input port 111 inputs and stores the second field data from the SDI 21 into the built-in FIFO memory 111a.

  The input port 111 outputs the second field data input and stored in the FIFO memory 111a to the arbiter memory controller 113 in the input order, and the process proceeds to step S6.

  In step S6, the monitoring unit 112 determines whether or not there is a disturbance in the second field data from the SDI 21 (the same second field data that is input from the FIFO memory 111a to the arbiter memory controller 113). The determination result is supplied to the arbiter memory controller 113.

  If the monitoring unit 112 determines in step S7 that there is no disturbance in the second field data that is the same as that input from the FIFO memory 111a to the arbiter memory controller 113, the process proceeds to step S8.

  In step S8, the arbiter memory controller 113 receives the determination result that the second field data from the FIFO memory 111a is not disturbed from the monitoring unit 112, and the second field data from the FIFO memory 111a. An even line generation process is performed for storing the field data in the frame buffer memory 92 as an even line among a plurality of lines constituting the progressive image.

  The details of the even line generation processing will be described later with reference to the flowchart of FIG.

  In step S9, the arbiter memory controller 113 corresponds to the progressive image stored in the frame buffer memory 92 in response to the generation of the progressive image by the odd line generation processing in step S4 and the even line generation processing in step S8. A read flag indicating whether or not to permit reading is set to one that permits reading.

  Note that in response to the read flag being set to permit reading, a read process for reading a progressive image written by the write process is started. Details of the reading process will be described later with reference to FIG.

  This completes the writing process.

  In addition, when the monitoring unit 112 determines in step S3 that the first field data is disturbed or in step S7, it is determined that the second field data is disturbed. Processing is terminated.

  Even when the monitoring unit 112 determines in step S3 that the first field data is disturbed, or in step S7, it is determined that the second field data is disturbed. The odd line generation process and the even line generation process may be performed, and in step S9, the read flag may be set to a value that does not permit reading.

[Explanation of odd line generation processing]
Next, an odd line generation process in which the frame buffer controller 91 stores the lines constituting the interlaced image of the first field data in the storage area of the frame buffer memory 92 as the odd lines of the corresponding progressive image will be described.

  FIG. 12 is a flowchart for explaining odd-number line generation processing in step S4 of FIG.

  In step S31, the arbiter memory controller 113 sets a plurality of lines constituting the first field data (interlaced image thereof) input from the FIFO memory 111a in order from the top as attention lines.

  In step S <b> 32, the arbiter memory controller 113 generates a start address of a storage area on the frame buffer memory 92 that stores the target line.

  In step S33, the arbiter memory controller 113 converts the image data (for example, the 10-bit data P1-1 to P1-4096 in FIG. 7) constituting the line of interest into a plurality of DPX storage data, and is equivalent to the burst transfer size. The combination of DPX stored data is stored in the frame buffer memory 92 as a transfer block.

  That is, for example, the arbiter memory controller 113 can generate a transfer block in units of burst transfer size for the image data (for example, 10-bit data P1-1 to P1-4096 in FIG. 7) constituting the target line. Received from the FIFO memory 111a in units of 60-bit data (for example, 10-bit data P1-1 to P1-6).

In step S33, the arbiter memory controller 113 converts the received 60-bit data (for example, 10-bit data P1-1 to P1-6) into a combination of DPX storage data (for example, the transfer block) according to the DPX format (for example, It is converted to DPX stored data 51 ₁ and 51 _2).

In step S33, the arbiter memory controller 113 receives the image data (for example, 10-bit data P1-1 to P1-4096 in FIG. 7) constituting the target line in a unit less than the burst transfer size unit. That is, when the end of the target line (for example, 10-bit data P1-4093 to P1-4096) is received from the FIFO memory 111a, the end of the target line is transferred together with the unnecessary data 52 according to the DPX format. converted to a combination of DPX storing data constituting the (e.g., DPX stored data 51 ₁₃₆₅ and 51 _1366).

  After the process of step S33 is completed, the process proceeds to step S34, and the arbiter memory controller 113 stores the step S33 in the storage area on the frame buffer memory 92 specified by the head address of the target line generated by the process of step S32. Each combination of DPX storage data obtained by the above process is stored as a transfer block.

  In step S <b> 35, the arbiter memory controller 113 determines whether or not all the lines constituting the first field data are stored in the frame buffer memory 92 based on the number of times that the target line is stored in the frame buffer memory 92. judge.

  If the arbiter memory controller 113 determines in step S35 that all the plurality of lines constituting the first field data have not yet been stored in the frame buffer memory 92, the process returns to step S31.

  In step S31, the arbiter memory controller 113 sets the line that exists next to the current attention line among the plurality of lines constituting the first field data input from the FIFO memory 111a as the attention line. The process proceeds to step S32.

  In step S32, the arbiter memory controller 113 stores the storage area (for example, line 1 in FIG. 2) in which the previous attention line is stored as the start address of the storage area on the frame buffer memory 92 in which the attention line is stored. Storage area (for example, line 3 in FIG. 2) is stored in a position skipped by the storage area (for example, storage area for storing line 2 in FIG. 2) where even lines of the progressive image are stored. Storage address) is generated.

  And after completion | finish of the process of step S32, a process is advanced to step S33 and the same process is performed after that.

  In step S35, if the arbiter memory controller 113 determines that all the plurality of lines constituting the first field data have been stored in the frame buffer memory 92 as the odd lines of the progressive image, the odd line generation process ends. Then, the process returns to step S4 in FIG.

[Explanation of even line generation processing]
Next, an even line generation process in which the frame buffer controller 91 stores the lines constituting the interlaced image of the second field data in the storage area of the frame buffer memory 92 as the even lines of the corresponding progressive image will be described.

  FIG. 13 is a flowchart for explaining the even line generation processing in step S8 of FIG.

  In step S51, the arbiter memory controller 113 sets a plurality of lines constituting the second field data (interlaced image thereof) input from the FIFO memory 111a as attention lines in order from the top.

  In step S52, the arbiter memory controller 113 generates the start address of the storage area on the frame buffer memory 92 that stores the line of interest.

  In step S53, the arbiter memory controller 113 converts the image data constituting the target line into a plurality of DPX storage data, and the combination of DPX storage data corresponding to the burst transfer size is transferred to the frame buffer memory 92 as a transfer block. Remember.

  That is, for example, the arbiter memory controller 113 receives the image data constituting the target line from the FIFO memory 111a in units of 60-bit data capable of generating a transfer block in burst transfer size units.

  In step S53, the arbiter memory controller 113 converts the received 60-bit data into a combination of DPX storage data constituting the transfer block according to the DPX format.

  In step S53, the arbiter memory controller 113 receives the image data constituting the target line in a unit that is less than the burst transfer size unit, that is, the end of the target line is received from the FIFO memory 111a. The end of the line of interest is converted into a combination of DPX storage data constituting a transfer block according to the DPX format together with unnecessary data.

  After the process of step S53 is completed, the process proceeds to step S54, and the arbiter memory controller 113 stores the storage area on the frame buffer memory 92 specified by the head address of the target line generated in the process of step S52, in step S53. Each combination of DPX storage data obtained by the above process is stored as a transfer block.

  In step S55, the arbiter memory controller 113 determines whether or not all of the plurality of lines constituting the second field data are stored in the frame buffer memory 92 based on the number of times that the target line is stored in the frame buffer memory 92. judge.

  In step S55, if the arbiter memory controller 113 determines that all the plurality of lines constituting the second field data have not yet been stored in the frame buffer memory 92, the process returns to step S51.

  In step S51, the arbiter memory controller 113 sets the line existing next to the current line of interest among the plurality of lines constituting the second field data input from the FIFO memory 111a as the line of interest. The process proceeds to step S52.

  In step S52, the arbiter memory controller 113 stores the storage area (for example, line 2 in FIG. 2) in which the previous attention line is stored as the start address of the storage area on the frame buffer memory 92 in which the attention line is stored. Storage area (for example, line 4 in FIG. 2) is stored at a position skipped by the storage area (for example, storage area for storing line 3 in FIG. 2) where the odd lines of the progressive image are stored. Storage address) is generated.

  And after completion | finish of the process of step S52, a process is advanced to step S53 and the same process is performed after that.

  In step S55, if the arbiter memory controller 113 determines that all the plurality of lines constituting the second field data have been stored in the frame buffer memory 92 as even lines of the progressive image, the even line generation process ends. Then, the process returns to step S8 in FIG.

[Description of read processing operation]
Next, the frame buffer controller 91 reads the DPX stored data from the frame buffer memory 92 in units of transfer blocks, associates the corresponding data valid flags with the read transfer blocks, and outputs them to the PCI-e memory controller 93. A reading process to be performed will be described.

  FIG. 14 is a flowchart for explaining the reading process. This reading process is started in response to, for example, the reading flag being set to permit reading of the progressive image stored in the frame buffer memory 92 by the process of step S9 in the writing process.

  In step S71, the arbiter memory controller 113 sets a plurality of lines constituting the progressive image generated in the storage area of the frame buffer memory 92 as a target line in order from the top by the writing process.

  In step S72, the arbiter memory controller 113 uses the head address generated in step S32 of the odd line generation process or step S52 of the even line generation process as the head address on the storage area of the frame buffer memory 92 where the target line is stored. Generates the same start address as the address.

In step S73, the arbiter memory controller 113 converts the DPX storage data (for example, DPX storage data 51 _{1 to} 51 _{1366 in} FIG. 7) constituting the attention line based on the head address generated by the processing in step S72. The data is read in units of burst transfer size (for example, 64 bits) in order from the head of the line of interest.

Then, the arbiter memory controller 113 reads DPX store data (e.g., transport block constituted by a combination of DPX storing data 51 ₁ and 51 ₂ in FIG. 7), and sets the data of interest.

  In step S74, the arbiter memory controller 113 determines whether or not the attention data exists at the end of the attention line based on the number of times the attention data is read, that is, the attention data includes unnecessary data. It is determined whether or not.

  If the arbiter memory controller 113 determines in step S74 that unnecessary data is not included in the data of interest, the process proceeds to step S75.

  In step S75, the arbiter memory controller 113 associates the true data valid flag with the data of interest, and the process proceeds to step S77.

  In step S74, if the arbiter memory controller 113 determines that unnecessary data is included in the data of interest, the process proceeds to step S76.

  In step S76, the arbiter memory controller 113 associates the data valid flag set to false with the data of interest, and the process proceeds to step S77.

  In step S77, the arbiter memory controller 113 inputs and stores the data of interest associated with the data valid flag in the FIFO memory 115a of the output port 115. The output port 115 reads the attention data input and stored in the FIFO memory 115 a by the arbiter memory controller 113 in the input order, and outputs it to the PCI-e memory controller 93.

  In step S78, the arbiter memory controller 113 determines whether or not all DPX storage data constituting the target line has been read based on the number of times of reading the target data.

  If the arbiter memory controller 113 determines in step S78 that the DPX storage data constituting the target line has not yet been read, the process returns to step S73.

  In step S73, the arbiter memory controller 113 sets DPX storage data (combination) that has not yet been set as the attention data among the DPX storage data constituting the attention line as the attention data, and thereafter the same processing is repeated. It is.

  On the other hand, if the arbiter memory controller 113 determines in step S78 that all DPX storage data constituting the target line has been read, the process proceeds to step S79.

  In step S79, the arbiter memory controller 113 determines whether or not all the lines constituting the progressive image stored in the frame buffer memory 92 have been read based on the number of times the target line has been read from the frame buffer memory 92. judge.

  In step S79, if the arbiter memory controller 113 determines that all of the plurality of lines constituting the progressive image stored in the frame buffer memory 92 have not been read yet, the process returns to step S71.

  In step S71, the arbiter memory controller 113 sets a line that has not yet been set as the attention line among the plurality of lines constituting the progressive image stored in the frame buffer memory 92 as the attention line. The process proceeds to S72, and thereafter the same processing is repeated.

  In step S79, the arbiter memory controller 113 determines that all the plurality of lines constituting the progressive image stored in the frame buffer memory 92 have been read based on the number of times the target line has been read from the frame buffer memory 92. If so, the reading process is terminated.

  As described above, in the read processing, the arbiter memory controller 113 corresponds to the transfer block (target block) read from the frame buffer memory 92 with a data valid flag indicating whether or not the transfer block includes unnecessary data. In addition, the data is output to the PCI-e memory controller 93.

  Therefore, the PCI-e memory controller 93 is configured by only a transfer block including unnecessary data and image data not including unnecessary data based on the data valid flag associated with the transfer block from the arbiter memory controller 113. Transfer block can be identified.

  For this reason, the PCI-e memory controller 93 obtains image data from a transfer block composed only of image data, and for the transfer block including unnecessary data, the data transfer size and the data of one line of the progressive image. Only image data can be acquired from the transfer block based on the size or the like.

  Therefore, the PCI-e memory controller 93 can acquire only image data from the transfer block from the arbiter memory controller 113 (frame buffer controller 91) and store it in the PCI-e memory 94 in units of burst transfer size. .

  For this reason, the PCI-e memory controller 93 reads image data from the PCI-e memory 94 in units of burst transfer size, and outputs it to the personal computer 2 via the PCI-e interface 28 as a transfer block of burst transfer size. be able to.

  Thereby, in the personal computer 2, since the transfer block from the PCI-e interface 28 does not include unnecessary data, it is not necessary to remove unnecessary data, and the load on the CPU (central processing unit) of the personal computer 2 is reduced. It becomes possible to reduce.

[Explanation of unnecessary data removal process]

  Next, the unnecessary data removal processing in which the PCI-e memory controller 93 stores in the PCI-e memory 94 the data obtained by removing unnecessary data from the progressive image including unnecessary data supplied from the frame buffer controller 91 will be described. To do.

  FIG. 15 is a flowchart for explaining the unnecessary data removal processing.

In step S101, the arbiter memory controller 132 determines whether or not the data valid flag associated with the transfer block input from the frame buffer controller 91 via the input / output port 131 _n and the WFIFO 131b _n is true.

  If the arbiter memory controller 132 determines in step S101 that the data valid flag is true, that is, if it is determined that unnecessary data is not included in the transfer block associated with the data valid flag, the process proceeds to step S101. The process proceeds to S102.

In step S102, the arbiter memory controller 132 acquires the image data constituting the transport block from WFIFO131b _n, processing proceeds to step S105.

  In step S101, the arbiter memory controller 132 determines that the data valid flag is not true (false), that is, determines that unnecessary data is included in the transfer block associated with the data valid flag. If so, the process proceeds to step S103.

In step S103, the arbiter memory controller 132, and the burst transfer size, based on the data size or the like of the lines constituting the progressive image, to distinguish the image data and unnecessary data constituting the transport block from WFIFO131b _n, the image data only In step S104, unnecessary data is discarded (ignored).

  After the process of step S104 ends, the process proceeds to step S105, and the arbiter memory controller 132 determines whether image data for the burst transfer size has been acquired.

  If the arbiter memory controller 132 determines in step S105 that image data for the burst transfer size has not yet been acquired, the process returns to step S101, and the subsequent processing is performed.

  If the arbiter memory controller 132 determines in step S105 that image data equivalent to the burst transfer size has been acquired, the process proceeds to step S106. Then, the arbiter memory controller 132 supplies the image data for the acquired burst transfer size to the PCI-e memory 94 as a transfer block having the burst transfer size and stores it.

In step S107, the arbiter memory controller 132 determines whether all transfer blocks input from the frame buffer controller 91 via the input / output port 131 _n and the WFIFO 131b _n have been processed based on the number of times unnecessary data has been discarded. To do.

  If the arbiter memory controller 132 determines in step S107 that all the transfer blocks have not yet been processed, the process returns to step S101, and the same processing is performed thereafter.

  In step S107, if the arbiter memory controller 132 determines that all the transfer blocks have been processed, the unnecessary data removal processing ends.

As described above, in the unnecessary data removal process, the arbiter memory controller 132 is based on the data valid flag associated with the transfer block input from the frame buffer controller 91 via the input / output port 131 _n and the WFIFO 131b _n. Only the image data included in the transfer block is acquired and stored in the PCI-e memory 94 in units of burst transfer size.

  For this reason, the PCI-e memory controller 93 reads a transfer block including only image data, which does not include unnecessary data, from the PCI-e memory 94 and performs burst transfer to the personal computer 2 via the PCI-e interface 28. can do.

  In the present embodiment, the above-described diagram is used by using hardware resources such as the PCI-e memory controller 93 similar to those provided in the conventional image processing apparatus 1 that converts an interlaced image into a progressive image. The processing described with reference to FIGS. 11 to 15 can be performed.

  Therefore, it is not necessary to provide a new circuit or the like for carrying out the present invention, and the manufacturing cost can be suppressed.

<2. Modification>
In this embodiment, the frame buffer controller 91 stores the first field data and the second field data of the interlaced image in the frame buffer memory 92, thereby generating a progressive image including unnecessary data, and PCI -e The memory controller 93 is configured to store the PCI-e memory 94 after removing unnecessary data from the progressive image including the unnecessary data. However, the present invention is not limited to this.

  That is, for example, the PCI-e memory controller 93 generates a progressive image including unnecessary data in the first storage area on the PCI-e memory 94 based on the first field data and the second field data of the interlaced image. In addition, it is possible to configure a progressive image including unnecessary data from which unnecessary data is removed and stored in a second storage area different from the first storage area on the PCI-e memory 94. .

[Configuration example of PCI-e memory controller 171]
FIG. 16 shows a PCI-e memory controller 171 and a PCI-e memory 172 that generate a progressive image including unnecessary data and remove unnecessary data from the generated progressive image including unnecessary data.

The PCI-e memory controller 171 includes an input / output port 191 _m (m is a natural number from 1 to 3) configured similarly to the input / output port 131 _{n of} FIG. 8 and an arbiter memory controller 192.

Incidentally, the input and output ports 191 ₁ from SDI21, the first field data and second field data are supplied.

The arbiter memory controller 192 stores the first field data and the second field data supplied from the input / output port 191 ₁ and the WFIFO memory 191b ₁ in the first storage on the PCI-e memory 172, as indicated by an arrow 211. By writing in the area, a progressive image of the corresponding frame is generated.

Further, the arbiter memory controller 192 reads the generated progressive image from the first storage area on the PCI-e memory 172 in units of transfer blocks as indicated by an arrow 212, and sets a data valid flag to the read transfer blocks. After the association, the data is supplied to the input / output port 191 ₃ via the RFIFO memory 191a ₂ and the input / output port 191 ₂ .

The input / output port 191 ₃ supplies the transfer block associated with the data valid flag from the input / output port 191 ₂ to the arbiter memory controller 192 via the WFIFO memory 191b ₃ .

Furthermore, the arbiter memory controller 192, as indicated by arrow 213, of the transport block supplied from WFIFO memory 191b _3, acquires the image data constituting the transport block associated with the true data valid flag .

Further, the arbiter memory controller 192, as indicated by arrow 213, of the transport block supplied from WFIFO memory 191b _3, the image data and unnecessary data constituting the transport block associated with the false data valid flag of Among them, unnecessary data is discarded and only image data is acquired.

  Then, in response to the acquisition of the image data for the burst transfer size, the arbiter memory controller 192 stores the image data for the burst transfer size in the second storage area on the PCI-e memory 172 as a transfer block. Remember.

  As a result, a transfer block having a burst transfer size is stored in the second storage area on the PCI-e memory 172 as a progressive image from which unnecessary data has been removed.

  In the present embodiment, the frame buffer controller 91 synthesizes interlaced images (first field data and second field data) supplied from, for example, a video switcher or a video transmitter via the SDI 21 to generate a frame buffer memory. Although progressive images are generated in 92 storage areas, interlaced images to be synthesized are not limited to this.

  That is, for example, the interlaced image to be synthesized is a partial interlaced image obtained by cutting out a predetermined area of the interlaced image, or an interlaced image obtained by enlarging or reducing the interlaced image. Can be adopted.

  Therefore, it is possible to remove unnecessary data from a progressive image to which unnecessary data is added, which is obtained from an interlaced image that has been processed such as cutting, enlargement, or reduction of a predetermined area.

  In the present embodiment, in the odd line generation process and the even line generation process, the image data constituting the target line is converted to DPX storage data, and the DPX storage data corresponding to the burst transfer size is stored as a transfer block. However, it is not limited to this.

  That is, for example, in the odd line generation process and the even line generation process, the frame buffer controller 91 may store the image data constituting the target line in the frame buffer memory 92 in units of burst transfer size.

  In this case, the frame buffer memory 92 includes, as shown in FIG. 2, a transfer block configured only by image data as a transfer block that configures a progressive image including unnecessary data, and image data and unnecessary data. The configured transfer block is stored.

  Then, in the reading process, the frame buffer controller 91 reads the transfer block from the frame buffer memory 92, associates the data valid flag, and supplies it to the PCI-e memory controller 93.

  In the unnecessary data removal process, the PCI-e memory controller 93 converts only the image data in the corresponding transfer block for the burst transfer size based on the data valid flag associated with the transfer block from the frame buffer controller 91. Each time it is received, it is stored as a transfer block that does not contain unnecessary data.

  In the unnecessary data removal processing, the PCI-e memory controller 93 sets a transfer block that does not include unnecessary data every time it receives only the image data of the transfer block from the frame buffer controller 91 by the burst transfer size. In addition to storing, only the image data in the transfer block from the frame buffer controller 91 is converted into a plurality of DPX storage data in accordance with the DPX format, and the converted plurality of DPX storage data is converted for each burst transfer size. Alternatively, it may be stored as a transfer block that does not include unnecessary data.

  In this embodiment, the frame buffer controller 91 associates the data valid flag with each transfer block. However, for example, whether or not there is unnecessary data for each minimum unit of data constituting the transfer block. A data valid flag can be associated with the flag indicating the above.

  In this case, in the unnecessary data removal process, whether or not the minimum unit data is unnecessary data is determined for each minimum unit data constituting the transfer block based only on the data valid flag.

  Therefore, for example, in a transfer block associated with a fake data valid flag (including unnecessary data), from where to where data is unnecessary data, the data size of a line constituting a progressive image, and Since it is not necessary to make a determination based on the data size or the like of the transfer block, it is possible to reduce the scale of the circuit used for the process of determining whether or not the data is unnecessary.

  Next, the series of processes described above can be executed by dedicated hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software can execute various functions by installing a so-called embedded computer or various programs. For example, it is installed from a recording medium in a general-purpose computer or the like.

[Computer configuration example]
FIG. 17 shows a configuration example of a computer that executes the above-described series of processing by a program.

  A CPU (central processing unit) 231 executes various processes according to a program stored in a ROM (read only memory) 232 or a storage unit 238. A RAM (random access memory) 233 appropriately stores programs executed by the CPU 231 and data. The CPU 231, ROM 232, and RAM 233 are connected to each other via a bus 234.

  An input / output interface 235 is also connected to the CPU 231 via the bus 234. The input / output interface 235 is connected to an input unit 236 composed of a keyboard, mouse, microphone, and the like, and an output unit 237 composed of a display, a speaker, and the like. The CPU 231 executes various processes in response to commands input from the input unit 236. Then, the CPU 231 outputs the processing result to the output unit 237.

  The storage unit 238 connected to the input / output interface 235 includes, for example, a hard disk, and stores programs executed by the CPU 231 and various data. The communication unit 239 communicates with an external device via a network such as the Internet or a local area network.

  Further, a program may be acquired via the communication unit 239 and stored in the storage unit 238.

  The drive 240 connected to the input / output interface 235 drives a removable medium 241 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives programs and data recorded therein. Get etc. The acquired program and data are transferred to and stored in the storage unit 238 as necessary.

  As shown in FIG. 17, a recording medium that records a program that is installed in a computer and can be executed by the computer includes a magnetic disk (including a flexible disk), an optical disk (CD-ROM (compact disc-read only). memory), DVD (including digital versatile disc)), magneto-optical disc (including MD (mini-disc)), or removable media 241, which is a package media consisting of semiconductor memory, etc., or the program is temporary or permanent ROM 232 recorded in the memory, a hard disk constituting the storage unit 238, and the like. Recording of a program on a recording medium is performed using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 239 that is an interface such as a router or a modem as necessary. Is called.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  Further, the present embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

71 image processing apparatus, 91 frame buffer controller, 92 frame buffer memory, 93 PCI-e memory controller, 94 PCI-e memory, 111 input port, 111a FIFO memory, 112 monitoring unit, 113 arbiter memory controller, 114 output port, 114a FIFO memory, 115 output port, 115a FIFO memory, 131 _{1 to} 131 _N input / output port, 131a _{1 to} 131a _N RFIFO memory, 131b _{1 to} 131b _N WFIFO memory, 132 arbiter memory controller, 171 PCI-e memory controller, 172 PCI -e memory, 191 _{1 to} 191 _{3 I} / O ports, 191a _{1 to} 191a ₃ RFIFO memory, 191b _{1 to} 191b ₃ WFIFO memory, 192 arbiter memory controller

Claims (10)

In an image processing apparatus that converts an interlaced image into a progressive image,
First holding means for holding image data in units of lines constituting the progressive image with unnecessary data added thereto;
Second holding means for holding the image data constituting the progressive image in units of blocks having a predetermined data size;
Reading means for reading out the image data and the unnecessary data constituting the progressive image from the first holding means in units of the blocks for each line;
Extracting only the image data constituting the read block, and writing to the second holding unit in units of the block, and first writing means,
The image reading apparatus is configured to read, for each line, a block constituted only by the image data or a block constituted by the image data and the unnecessary data as the block for each line. Further comprising association means for associating a data valid flag indicating whether or not the data is the unnecessary data with respect to the data constituting the read block,
The image according to claim 1, wherein the first writing unit extracts only the image data constituting the block based on the data validity flag, and writes the extracted image data in the second holding unit in units of the block. Processing equipment. An association means for associating a data valid flag indicating whether or not the unnecessary data is included in the block with the read block;
The image according to claim 1, wherein the first writing unit extracts only the image data constituting the block based on the data validity flag, and writes the extracted image data in the second holding unit in units of the block. Processing equipment. The image processing apparatus according to claim 1, wherein the first writing unit converts the extracted image data in a predetermined format, and writes the converted image data in the second holding unit in units of the blocks. The reading means includes
The image according to claim 1, wherein the image data and the unnecessary data constituting the progressive image are read from the first holding unit in units of the blocks having a burst transfer size capable of burst transfer for each line. Processing equipment. The image processing apparatus according to claim 5, further comprising a transfer unit that reads out the block having the burst transfer size from the second holding unit and performs burst transfer. When the line-unit image data constituting the interlaced image of the odd field and the even field corresponding to the frame of the progressive image is divided in the unit of the block, there is a surplus block less than the data size of the block. An adding means for adding the unnecessary data corresponding to the data size obtained by subtracting the data size of the remainder block from the data size of the block to the image data in units of lines constituting each of the interlaced images.
The image data for each line constituting each of the interlaced images to which the unnecessary data is added is written in the second holding means as the image data for each line constituting the progressive image to which the unnecessary data is added. The image processing apparatus according to claim 1, further comprising second writing means. The image processing apparatus according to claim 7, wherein the first writing unit also serves as the second writing unit. The image processing apparatus according to claim 8, wherein the first holding unit also serves as the second holding unit. In an image processing method of an image processing apparatus for converting an interlaced image into a progressive image,
The image processing apparatus includes:
First holding means;
A second holding means;
Reading means;
First writing means, and
The reading means holds the image data and the unnecessary data constituting the progressive image from the first holding means for holding the image data in units of lines constituting the progressive image in a state where unnecessary data is added. For each line, read in units of the block,
The first writing means extracts only the image data constituting the read block, and the image data constituting the progressive image is a block unit having a predetermined data size in the block unit. Writing to the second holding means held by
The image reading method is an image processing method for reading, for each line, a block constituted only by the image data or a block constituted by the image data and the unnecessary data as the block for each line.

Images