JP2010283086A - Semiconductor device and method of manufacturing the same, solid-state image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure which enables manufacturing with proper productivity and high yield. <P>SOLUTION: The semiconductor device is constituted to include a vertical NMOS transistor containing a gate electrode 21 which is a laminated structure of an electrode layer 15, to which an n-type impurity is introduced, and an electrode layer 17 thereon, to which no impurity is introduced; a planar NMOS transistor, containing gate electrodes 22, 23 which are a laminated structure of the electrode layer 15 and an electrode layer 16 thereon; a planar PMOS transistor, containing a gate electrode 24 which is a laminated structure of the electrode layer 15 and the electrode layer 17 thereon, to which p-type impurity is introduced and which is p-type electrode; and other circuit elements, such as, a photodiode formed under the vertical NMOS transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a vertical transistor in which a gate electrode and a gate insulating film are embedded in a semiconductor substrate, and a manufacturing method thereof. Further, the present invention relates to a solid-state imaging device having a vertical transistor in a pixel portion.

  In a solid-state imaging device, a circuit is highly integrated in order to improve sensitivity, and various techniques for ensuring the area of a photodiode have been proposed.

For example, a structure has been proposed in which a trench is formed on a photodiode formed on the back side of a silicon substrate and a transfer gate is provided inside the trench to form a vertical transistor (see, for example, Patent Document 1). ).
In the vertical transistor formed in the trench, the electrode material of the gate electrode is embedded in the trench covered with the gate insulating film, and the side wall portion and the bottom surface portion of the trench become the channel portion.
With this structure, the area of the photodiode can be increased as compared with a structure in which the photodiode and the transfer gate are individually formed on the surface side of the substrate, so that sensitivity can be improved.

  In a solid-state imaging device using a vertical transistor as a transfer gate, a vertical transistor, a normal planar transistor, a transistor in a pixel portion (amplification, selection, reset) and a transistor in a logic portion are mixedly mounted. Become. This complicates the electrode formation process.

  In the manufacturing process of a conventional solid-state imaging device composed only of a planar transistor, after forming a single-layer polycrystalline silicon layer, patterning by a photomask (photolithography) and ion implantation are performed to form an NMOS portion and a PMOS portion. Different electrodes are made. That is, such a simple process can be employed.

However, in a solid-state image pickup device having a vertical transistor, when an electrode layer of a vertical transistor with a depth of several μm embedded in the trench is formed, the trench is deep, so that impurities introduced by ion implantation are present at the bottom of the vertical hole. Do not spread until.
Therefore, it is impossible to apply the above-described simple process in which electrodes are separately formed by photolithography and ion implantation.

Japanese Patent Laying-Open No. 2005-223084

  Therefore, instead of introducing impurities by ion implantation after forming the electrode layer, it is conceivable to introduce impurities simultaneously when forming the electrode layer. By forming the electrode layer of the vertical transistor in this way, it is possible to manufacture electrodes separately even in a solid-state imaging device having a vertical transistor.

  A method for manufacturing a solid-state imaging device having a vertical transistor in the case where impurities are simultaneously introduced at the time of forming an electrode layer will be described with reference to FIGS. Here, a columnar vertical transistor having a depth of 1 μm and a diameter of 0.2 μm is assumed.

As shown in FIG. 6A, after forming a vertical hole in the silicon substrate 101, a gate insulating film 102 is formed, and then the vertical hole of the silicon substrate 101 is filled to form an electrode layer 103 to be a gate electrode. As the electrode layer 103, a semiconductor layer containing n-type impurities, for example, PDAS (amorphous silicon doped with phosphorus) is formed.
Next, as shown in FIG. 6B, a photoresist 106 corresponding to the pattern of the gate electrode of the vertical transistor and the NMOS transistor in the pixel portion is formed on the electrode layer 103.
Next, by processing the electrode layer 103 using the photoresist 106 as a mask, as shown in FIG. 6C, an n-type gate electrode 103a of the vertical transistor and an n-type gate electrode 103b of the NMOS transistor of the pixel portion are formed. To do.
Next, as illustrated in FIG. 7D, an oxide film 109 serving as an etching stop film is formed so as to cover the gate electrode 103 a and the gate electrode 103 b, and then an electrode layer 107 is formed over the entire surface.
Next, as shown in FIGS. 7E to 7F, the electrode layer 107 is processed by lithography and dry etching to form the gate electrode 107a of the NMOS transistor in the logic portion and the gate electrode 107b of the PMOS transistor in the logic portion. To do.
Next, as shown in FIG. 8G, a photoresist 110 is formed to cover the pixel portion including the vertical transistor and the NMOS transistor in the logic portion. Then, using this photoresist 110 as a mask, boron (B) is ion-implanted to make the gate electrode 107b of the PMOS transistor in the logic portion p-type.
In this way, as shown in FIG. 8H, the gate electrodes 103a, 103b, 107a, and 107b of the vertical transistor, the NMOS transistor of the pixel portion, the logic NMOS transistor, and the PMOS transistor can be formed.

  In the manufacturing method described above, in each of the vertical transistor, the pixel transistor, and the logic portion transistor, the gate electrode layers are separately formed by the NMOS transistor and the PMOS transistor, so that depletion of the gate electrode of each transistor can be suppressed. Thereby, favorable electrode characteristics can be obtained.

  However, in the manufacturing method described above, the number of processes increases because processing and lithography are frequently used. Therefore, productivity becomes low. In addition, since the number of etching steps increases, the residue remaining after the etching process and the occurrence of divots in the trench isolation layer (STI) increase, resulting in a decrease in manufacturing yield.

Further, the vertical transistor is not limited to the solid-state imaging device, and can be applied to other semiconductor devices. For example, in a semiconductor device having a transistor and other circuit elements (resistors, capacitors, photodiodes), it is conceivable to employ a vertical transistor to form the other circuit elements and transistors vertically. As a result, the area of the entire semiconductor device can be reduced, and the area of other circuit elements can be increased.
Also in such a semiconductor device, when the gate electrode layer is separately formed by the NMOS transistor and the PMOS transistor, problems of productivity and manufacturing yield occur as in the case of the solid-state imaging device.

  In order to solve the above-described problems, the present invention provides a semiconductor device having a structure capable of being manufactured with high productivity and high yield, a manufacturing method thereof, and a solid-state imaging device.

The semiconductor device of the present invention has a vertical first conductivity type channel MOS transistor formed by embedding a gate electrode in a semiconductor substrate. Furthermore, the semiconductor device of the present invention includes a planar first conductivity type channel MOS transistor having a gate electrode formed on a semiconductor substrate, and a planar type second conductivity type channel MOS transistor.
And a vertical first-conductivity-type channel MOS transistor including a gate electrode having a stacked structure of an electrode layer into which the first-conductivity-type impurity is introduced and an electrode layer on which the impurity is not introduced. .
In addition, the semiconductor device includes a planar first conductivity type channel MOS transistor including a gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which an impurity is not introduced thereon. .
A stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer into which an impurity of the second conductivity type is introduced thereon, including a gate electrode that is an electrode of the second conductivity type; A planar type second conductivity type channel MOS transistor is included.
Further, it includes other circuit elements other than the transistors formed below or above the vertical first conductivity type channel MOS transistor.

A method of manufacturing a semiconductor device of the present invention includes a vertical first conductivity type channel MOS transistor, a planar first conductivity type channel MOS transistor, and a planar type second conductivity type channel MOS transistor. A method of manufacturing a semiconductor device.
Then, a step of forming a hole in the semiconductor substrate, filling the inside of the hole and forming an electrode layer into which the first conductivity type impurity is introduced over the entire surface, and an upper surface of the electrode layer into which the first conductivity type impurity is introduced Forming an electrode layer into which impurities are not introduced.
In addition, the electrode layer in which the two layers are stacked is divided into a vertical first conductivity type channel MOS transistor, a planar type first conductivity type channel MOS transistor, and a planar type second conductivity type channel MOS transistor. Patterning the gate electrode pattern.
Further, the method includes a step of ion-implanting a second conductivity type impurity into the gate electrode of the planar second conductivity type channel MOS transistor.

The solid-state imaging device of the present invention includes a photodiode formed for each pixel in a semiconductor substrate and a vertical first conductivity type channel MOS transistor formed by embedding a gate electrode in the semiconductor substrate. Further, the solid-state imaging device of the present invention includes a planar first conductivity type channel MOS transistor having a gate electrode formed on a semiconductor substrate, and a planar type second conductivity type channel MOS transistor.
In addition, a transfer gate including a gate electrode having a stacked structure of an electrode layer into which impurities of the first conductivity type are introduced and an electrode layer on which impurities are not introduced thereon is formed and becomes a transfer gate formed on the photodiode. A vertical first-conductivity-type channel MOS transistor is included.
In addition, the semiconductor device includes a planar first conductivity type channel MOS transistor including a gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which an impurity is not introduced thereon. .
And a stacked structure of an electrode layer into which the first conductivity type impurity is introduced and an electrode layer into which the second conductivity type impurity is introduced thereon, and includes a gate electrode that is a second conductivity type electrode. And a planar second conductivity type channel MOS transistor.

According to the above-described configuration of the semiconductor device of the present invention, each gate electrode has a two-layer stacked structure, and the first conductivity type impurity is introduced into the lower electrode layer. Therefore, in the vertical first conductivity type channel MOS transistor, the concentration of the first conductivity type impurity in the portion of the gate electrode embedded in the semiconductor substrate can be increased. On the other hand, the gate electrode of the planar second-conductivity-type channel MOS transistor is the second-conductivity-type electrode by introducing the second-conductivity-type impurity into the upper electrode layer. It can be used as the gate electrode of a channel MOS transistor.
The gate electrode of each transistor has a two-layer structure in which the lower electrode layers are the same, and can be formed simultaneously by patterning the two electrode layers.

According to the semiconductor device manufacturing method of the present invention described above, it is possible to simultaneously form each gate electrode by patterning an electrode layer in which two layers are stacked into a pattern of each gate electrode of each MOS transistor. Become. This eliminates the need to form the gate electrode in two steps as in the manufacturing method shown in FIGS. The oxide film 109 shown in FIG. 7D is also unnecessary.
Further, since the second conductivity type impurity is ion-implanted into the gate electrode of the planar second conductivity type channel MOS transistor, the gate electrode can be changed from the first conductivity type to the second conductivity type electrode. . Thereby, it can be used as the gate electrode of the MOS transistor of the second conductivity type channel.
Also, a hole is formed in the semiconductor substrate, and an electrode layer into which the first conductivity type impurity is introduced is formed on the entire surface by filling the inside of the hole. As a result, the gate electrode of the vertical first-conductivity-type channel MOS transistor can be filled with the first-conductivity-type high-impurity electrode layer into which the first conductivity-type impurity is introduced.
Furthermore, since the electrode layer into which the impurity is not introduced is formed on the electrode layer into which the first conductivity type impurity is introduced, in the planar MOS transistor, the first conductivity type impurity concentration of the gate electrode is relatively low. can do. In the MOS transistor of the second conductivity type channel, the gate electrode can be changed from the first conductivity type to the second conductivity type relatively easily by ion implantation of the second conductivity type impurity.

According to the above-described configuration of the solid-state imaging device of the present invention, each gate electrode has a two-layer structure, and the first conductivity type impurity is introduced into the lower electrode layer. Therefore, in the vertical first conductivity type channel MOS transistor, the concentration of the first conductivity type impurity in the portion of the gate electrode embedded in the semiconductor substrate can be increased. On the other hand, the gate electrode of the planar second-conductivity-type channel MOS transistor is the second-conductivity-type electrode by introducing the second-conductivity-type impurity into the upper electrode layer. It can be used as the gate electrode of a channel MOS transistor.
The gate electrode of each transistor has a two-layer structure in which the lower electrode layers are the same, and can be formed simultaneously by patterning the two electrode layers.

According to the above-described present invention, the gate electrode of each transistor can be simultaneously formed by patterning the two electrode layers, so that the manufacturing process can be simplified. Thereby, productivity can be improved.
In addition, since the number of etching steps is reduced, residues generated after the etching process and divots in the trench element isolation layer (STI) can be reduced, and the manufacturing yield can be improved.
Therefore, according to the present invention, a semiconductor device including a vertical transistor and a solid-state imaging element can be manufactured with high productivity and high yield.

And by using a vertical transistor, it becomes possible to form other circuit elements of a semiconductor device, a photodiode of a solid-state imaging device, and a vertical transistor vertically, thereby reducing the overall area. Can do.
This makes it possible to reduce the size of the semiconductor device, the size of the solid-state image sensor, and the number of pixels.
In the solid-state imaging device of the present invention, the area of the photodiode of each pixel can be increased to improve sensitivity.

  Further, in the vertical transistor, the first conductivity type impurity concentration of the portion embedded in the hole of the gate electrode can be increased. In the planar transistor, the first conductivity type impurity concentration of the gate electrode can be increased. Can be lowered. Accordingly, it is possible to achieve desired characteristics in each transistor by adjusting the impurity concentration of each gate electrode between the vertical transistor and the planar transistor.

1A and 1B are schematic configuration diagrams (cross-sectional views) of a first embodiment (solid-state imaging device) of a semiconductor device of the present invention. FIG. 2 is a cross-sectional view of the entire vertical transistor portion of the pixel portion of FIG. 1. FIG. 3 is an equivalent circuit diagram of one pixel in the pixel unit illustrated in FIGS. 1 and 2. FIGS. 2A to 2C are process diagrams showing a manufacturing process of the semiconductor device (solid-state imaging device) of FIG. D and E are process diagrams showing manufacturing steps of the semiconductor device (solid-state imaging device) of FIG. It is process drawing which shows the manufacturing process of the structure which has AC vertical transistor. DF is a process diagram showing a manufacturing process of a configuration having a vertical transistor. It is process drawing which shows the manufacturing process of the structure which has a G and H vertical transistor.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
The description will be given in the following order.
1. First Embodiment 2. FIG. Modified example

<1. First Embodiment>
As a first embodiment of a semiconductor device of the present invention, schematic configuration diagrams (cross-sectional views) of a solid-state imaging device are shown in FIGS. 1A and 1B. 1A is a cross-sectional view of a pixel portion, and FIG. 1B is a cross-sectional view of a logic portion. In this embodiment, the present invention is applied to a CMOS solid-state imaging device (CMOS image sensor).

  The solid-state imaging device 1 includes a transfer transistor formed of a vertical transistor, another transistor of a pixel unit formed of a planar transistor, and a logic unit transistor (NMOS transistor, PMOS transistor).

In the pixel portion shown in FIG. 1A, a transfer transistor composed of a vertical NMOS transistor and other transistors (reset, amplification, selection, etc.) composed of a planar NMOS transistor are formed.
Below the vertical NMOS transistor, an n-type impurity region 2 constituting a photodiode of the light receiving unit is formed below the semiconductor substrate 11 such as a silicon substrate (on the back side). The n-type impurity region 2 is composed of a lower low-concentration n-type impurity region 2B and an upper high-concentration n-type impurity region (n ⁺ ) 2A.
Near the surface of the semiconductor substrate 11 above the n-type impurity region 2, an n-type high concentration (n ⁺ ) impurity region 3 is formed.

In the transfer transistor composed of a vertical NMOS transistor, the gate electrode 21 embedded in the hole formed in the semiconductor substrate 11 becomes the transfer gate TG. A gate insulating film 12 is formed along a hole formed in the semiconductor substrate 11, and a gate electrode 21 is embedded in the hole formed in the semiconductor substrate 11 through the gate insulating film 12. The high-concentration n-type impurity region 2A of the photodiode and the n-type high-concentration impurity region 3 near the surface of the semiconductor substrate 11 serve as source / drain regions. The vicinity of the gate insulating film 12 in the p-type semiconductor region of the semiconductor substrate 11 between these impurity regions 2A and 3 in the source / drain region becomes a channel region.
The n-type high-concentration impurity region 3 in the vicinity of the surface of the semiconductor substrate 11 is used to read out signal charges from the photodiode by the operation of the transfer gate TG, and is used as a so-called floating diffusion (FD).

In a planar NMOS transistor, n-type high concentration (n ⁺ ) source / drain regions 4 are formed in a region isolated by an element isolation layer 13 near the surface of a semiconductor substrate 11, and the gate insulating film 12 A gate electrode 22 is formed thereon.

In the logic portion shown in FIG. 1B, an NMOS transistor and a PMOS transistor, which are planar transistors, are formed.
In the NMOS transistor of the logic part, a p-type well region 5 is formed in a region separated by a trench element isolation layer 14 made of an insulating layer embedded in a semiconductor substrate 11. Near the surface of the p-type well region 5, n-type high concentration (n ⁺ ) source / drain regions 6 are formed, and a gate electrode 23 is formed on the gate insulating film 12.
In the PMOS transistor of the logic part, an n-type well region 7 is formed in a region isolated by the trench element isolation layer 14. A p-type high concentration (p ⁺ ) source / drain region 8 is formed near the surface of the n-type well region 7, and a gate electrode 24 is formed on the gate insulating film 12.

In the solid-state imaging device 1 of the present embodiment, in particular, the gate electrodes 21, 22, 23, and 24 of each MOS transistor have a two-layer structure. Specifically, the gate electrodes 21, 22, 23, and 24 are constituted by the electrode layer 15 into which an n-type impurity (for example, phosphorus) is introduced and the electrode layers 16 and 17 thereon.
In the vertical NMOS transistor, the NMOS transistor in the pixel portion, and the NMOS transistor in the logic portion, the upper electrode layer of each gate electrode 21, 22, 23 is an electrode layer 16 into which no impurity is introduced. .
In the PMOS transistor of the logic part, the upper electrode layer of the gate electrode 24 is an electrode layer 17 into which a p-type impurity (for example, boron) is introduced.

  As a material of each electrode layer 15, 16, 17, for example, a polycrystalline silicon layer can be used, and a p-type impurity or an n-type impurity is introduced corresponding to each electrode layer 15, 16, 17. Or do not introduce impurities. The polycrystalline silicon layer may be formed as an amorphous silicon layer first, and then crystallized by subsequent annealing or the like to form a polycrystalline silicon layer.

  1A and 1B show cross-sectional views in the vicinity of each transistor, but FIG. 2 shows an overall cross-sectional view of the vertical transistor portion of the pixel portion. 2 shows a cross-sectional view different from that in FIG. 1, the n-type high-concentration impurity region 3 of the floating diffusion does not appear.

As shown in FIG. 2, n-type impurity regions 2 (2 </ b> A and 2 </ b> B) constituting a photodiode serving as a light receiving portion are formed for each pixel 20 in a portion below the semiconductor substrate 11.
A color filter 9 and an on-chip lens 10 are formed on the back surface of the semiconductor substrate 11 corresponding to each pixel 20.
An insulating layer 19 is formed on the surface of the semiconductor substrate 11 so as to cover the gate insulating film 12 and the gate electrode 21. A wiring layer 18 is formed inside the insulating layer 19. Although not shown, the wiring layer 18 and the insulating layer 19 are also formed above other transistors in the pixel portion and above the transistors in the logic portion.

Here, an equivalent circuit diagram of one pixel 20 in the pixel portion is shown in FIG.
As shown in FIG. 3, the photodiode including the n-type impurity region 2 is connected to the n-type high-concentration impurity region 3 that is a floating diffusion through a transfer gate TG formed by the gate electrode 21. The floating diffusion (3) is connected to one source / drain region of the reset transistor RST and the gate of the amplification transistor Amp. One source / drain region of the selection transistor SEL is connected to one source / drain region of the amplification transistor Amp. A power supply potential VDD is connected to the other source / drain region of the reset transistor RST and the other source / drain region of the amplification transistor Amp. A signal line 25 is connected to the other source / drain region of the selection transistor SEL.
That is, the equivalent circuit diagram of each pixel is the same as the conventional configuration using a planar transistor as the transfer transistor.

Then, the manufacturing method of the solid-state image sensor 1 of this Embodiment is demonstrated with reference to FIG. 4A-FIG. 5E. 4A to 5E, illustration of some components such as the trench element isolation layer 14 between the NMOS transistor and the PMOS transistor in FIG. 1B is omitted.
First, after a hole for a gate electrode of a vertical transistor is formed in the semiconductor substrate 11 by dry etching, a gate insulating film 12 is formed by, for example, a thin silicon oxide film. At this time, as the gate insulating film 12, it is preferable to form a silicon oxide film by employing a radical oxidation process which has low dependency on the plane orientation of silicon and is effective in rounding corners and reducing roughness of silicon. In radical oxidation, for example, treatment is performed at 800 ° C. to 1100 ° C. using H ₂ or O ₂ as a source gas.
Thereafter, a hole for the trench element isolation layer 14 is formed in the semiconductor substrate 11, and the trench element isolation layer 14 is formed by filling the hole with, for example, a silicon oxide layer. Further, the element isolation layer 13 of the pixel portion is formed by, for example, a silicon oxide layer.
Further, an electrode layer 15 into which an n-type impurity is introduced is formed on the entire surface. For example, PDAS (amorphous silicon layer containing phosphorus) is formed by a CVD method (chemical vapor deposition method) at 500 to 600 ° C. using SiH ₄ gas, H ₂ gas, and PH ₃ gas. The phosphorus concentration of PDAS is preferably 0.12-0.25 wt%.
The film thickness of the electrode layer 15 is at least half that of the hole for the gate electrode 21 of the vertical transistor. For example, when the hole diameter is 200 nm, the thickness of the electrode layer 15 is set to 100 nm or more. As a result, the inside of the hole is filled with only the electrode layer 15.
Further, an electrode layer 16 into which impurities are not introduced is formed on the electrode layer 15 (see FIG. 4A above). For example, the amorphous silicon layer is formed with a film thickness of 80 nm with respect to the film thickness of the electrode layer 15 of 100 nm.

Next, as shown in FIG. 4B, a resist 31 corresponding to the pattern of the gate electrodes 21, 22, 23, 24 of each transistor is formed on the electrode layer 16.
Next, as shown in FIG. 4C, the electrode 31 and the electrode layer 16 are patterned using the resist 31 as a mask, and the resist 31 is removed. Thereby, the gate electrodes 21, 22, 23, and 24 of the respective transistors are formed.

Next, as shown in FIG. 5D, a portion other than the PMOS transistor portion of the logic portion is covered with a resist 32. Then, as shown by the arrow in FIG. 5D, boron, which is a p-type impurity, is ion-implanted into the PMOS transistor portion of the logic portion. The injection amount is, for example, 7 × 10 ¹⁵ atms / cm ² .
Subsequently, as shown in FIG. 5E, the resist 32 is removed. The electrode layer 16 is changed to the electrode layer 17 into which the p-type impurity is introduced by ion implantation of the p-type impurity. At this time, since the p-type impurity is also implanted into the electrode layer 15 into which the n-type impurity is introduced, the electrode layer 15 changes to a configuration having the n-type impurity and the p-type impurity, but the sign remains the same. It is said.

Thereafter, annealing (heat treatment) is performed to crystallize the amorphous silicon of the electrode layers 15, 16, and 17 to form a polycrystalline silicon layer. At this time, ion-implanted p-type impurity boron diffuses in the interface of the crystal grains, accumulates in the vicinity of the interface with the gate insulating film 12, and is activated. In this way, the entire gate electrode 24 of the PMOS transistor in the logic portion changes from n-type to p-type. Boron near the interface with the gate insulating film 12 contributes to the p-type polarity of the gate electrode 24 of the PMOS transistor.
Since the n-type impurities in the electrode layer 15 are diffused into the non-doped electrode layer 16 by annealing, the boundary between the final n-type layer and the non-doped layer in the stacked electrode layer slightly changes from the time of film formation. .

Thereafter, the insulating layer 19 is formed so as to cover the gate electrodes 21, 22, 23, and 24, and the wiring layer 18 and the insulating layer 19 are repeatedly formed.
In this way, the solid-state imaging device 1 of the present embodiment can be manufactured.

Here, for example, consider a case where the gate electrodes 21, 22, 23, and 24 are formed in a laminated structure of PDAS containing 0.25 wt% phosphorus and amorphous silicon. Since the vertical transistor is filled with PDAS, the concentration of phosphorus in the vicinity of the interface with the gate insulating film 12 is 0.25 wt%.
On the other hand, in the PDAS / amorphous silicon laminated portion of the gate electrode of the planar transistor, the concentration of phosphorus is 0.14 to 0 from the original 0.25 wt% due to diffusion of phosphorus in the amorphous silicon direction by annealing in a later step. Decrease to 15 wt%.
That is, the concentration of phosphorus near the interface between the gate electrode 21 of the vertical transistor and the gate insulating film 12 is higher than the concentration of phosphorus near the interface between the gate electrodes 22 and 23 of the planar NMOS transistor and the gate insulating film 12. Get higher.
Therefore, by controlling the film thickness of each electrode layer 15 and 16 in the laminated structure and controlling the phosphorus concentration of PDAS (electrode layer 15), the gate electrodes 22, 23, and 24 are set to a desired phosphorus concentration in the planar transistor. Can be formed.

Furthermore, the smaller the crystal grains and the greater the grain boundaries, the more boron diffusion is promoted and the boron concentration near the interface increases.
Since the size of the crystal grain depends on the phosphorus concentration of PDAS, if the phosphorus concentration is reduced, the crystal grain becomes smaller and good p-type characteristics can be obtained in the gate electrode 24 into which boron is implanted.

Further, increasing the acceleration voltage at the time of boron ion implantation and controlling the boron profile close to the interface with the gate insulating film 12 in advance also provides a means for obtaining good p-type characteristics.
For example, the acceleration voltage may be controlled to about 15 eV to 22 keV. This makes it possible to control the boron profile closer to the interface with the gate insulating film 12 while suppressing boron from penetrating into the semiconductor substrate 11.

In the PMOS transistor of the logic portion, the boron concentration in the vicinity of the interface with the gate insulating film 12 in the gate electrode 24 is preferably 2 × 10 ²⁰ atms / cm ² or more. With such a boron concentration, good characteristics can be obtained as a p-type electrode.
Moreover, it is preferable that the distribution of phosphorus in the gate electrode 24 of the PMOS transistor in the logic portion has a profile that monotonously decreases from a specific depth of the gate electrode 24 toward the surface.

According to the configuration of the solid-state imaging device 1 of the present embodiment described above, the vertical NMOS transistor is formed on the photodiode formed of the n-type impurity region 2, so that the area of the pixel portion is reduced. Can do. As a result, the solid-state imaging device 1 can be reduced in size or increased in number of pixels.
In addition, since the area of the photodiode can be increased, the sensitivity of the solid-state imaging device 1 can be improved.
Therefore, in a device such as a camera provided with the solid-state imaging device 1, the device can be downsized or have a large number of pixels, or the sensitivity can be improved and an image can be obtained even at low illuminance.

According to the configuration of the present embodiment, by patterning the two electrode layers 15 and 16, it becomes possible to simultaneously form the gate electrodes 21, 22, 23, and 24 of each transistor. It can be simplified. Thereby, productivity can be improved. Further, since the number of etching steps is reduced, it is possible to reduce the residue remaining after the etching process and the occurrence of divots in the trench element isolation layer 14. As a result, the manufacturing yield can be improved.
That is, the solid-state imaging device 1 including the vertical transistor can be manufactured with high productivity and high yield.

Furthermore, the gate electrodes 21, 22, 23, and 24 are formed in a laminated structure of the electrode layer 15 introduced with phosphorus and the electrode layer 16 or 17 not introduced with phosphorus thereon. Thereby, in the vertical transistor, the concentration of phosphorus in the portion embedded in the hole of the semiconductor substrate 11 of the gate electrode 21 can be increased, and in the planar transistor, the phosphorus of the gate electrodes 22, 23, and 24 is increased. The concentration of can be lowered.
In the vertical transistor, it is desirable that the phosphorus concentration in the gate electrode is high, and in the planar transistor, it is desirable that the phosphorus concentration in the gate electrode is low. According to the present embodiment, it is possible to easily realize the conflicting characteristics. That is, it is possible to achieve desirable characteristics in each transistor by adjusting the impurity concentration of each gate electrode between the vertical transistor and the planar transistor.
In the planar type PMOS transistor, since the phosphorus concentration of the gate electrode 24 is low, the gate electrode 24 can be easily changed from n-type to p-type by boron ion implantation.

<2. Modification>
In the above-described embodiment, phosphorus (P) is introduced as the n-type impurity, and boron (B) is introduced as the p-type impurity.
The present invention is not limited to the combination of these impurity elements, and other elements may be used for the n-type impurity or the p-type impurity.

In the above-described embodiment, an amorphous silicon layer is formed as the electrode layers 15 and 16 and crystallized by subsequent annealing to form a polycrystalline silicon layer.
The present invention is not limited to such a formation method and configuration.
For example, the electrode layers 15 and 16 may be formed of an amorphous silicon layer, and the gate electrode may be formed without being crystallized as it is. In this case, the gate electrode finally formed is an amorphous silicon layer.
For example, the electrode layers 15 and 16 may be formed of a polycrystalline silicon layer, and the gate electrode may be formed as it is. In this case, the gate electrode finally formed is a polycrystalline silicon layer. Even when a polycrystalline silicon layer is formed, it is formed by a CVD method (chemical vapor deposition method) using SiH ₄ gas, H ₂ gas, and PH ₃ gas, as in the case of forming an amorphous silicon layer. Can do. However, the CVD method conditions (temperature, etc.) are slightly different from those in the case of forming an amorphous silicon layer.

In the above embodiment, the semiconductor substrate 11 is described as a silicon substrate. However, in the present invention, other silicon layers such as a silicon epitaxial layer on a silicon substrate and a silicon layer formed on another substrate are used as the semiconductor substrate 11. May be used as
Further, a semiconductor other than silicon may be used for the semiconductor substrate 11.

The above-described embodiment is a case where the present invention is applied to a solid-state imaging device, but the present invention can be similarly applied to a semiconductor device having a transistor and other circuit elements.
Examples of other circuit elements include resistors, capacitors, memory elements, and photodiodes. As a semiconductor device having a photodiode, unlike a solid-state imaging device having a photodiode for each pixel, a semiconductor device having a light receiving element made up of a single photodiode, for example, an infrared sensor or a device for receiving and detecting laser light Is mentioned.
Further, the other circuit elements are not limited to be formed below the vertical transistor, and may be formed above the gate electrode of the vertical transistor.

In the above-described embodiment, the vertical transistor is an NMOS transistor. On the other hand, in the solid-state imaging device or semiconductor device, even when the vertical transistor is a PMOS transistor, the present invention is similarly applied if each layer has a conductivity type opposite to that of the above-described embodiment. can do.
That is, in the present invention, when the vertical transistor is a MOS transistor of the first conductivity type channel, in order to make the gate electrode of the vertical transistor the first conductivity type, the upper layer of the first conductivity type impurity is introduced. Then, an electrode layer into which impurities are not introduced is formed. On the other hand, in the planar MOS transistor of the second conductivity type channel, the second conductivity type impurity is ion-implanted into the stacked structure of the electrode layer to make the gate electrode the second conductivity type.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 1 Solid-state image sensor, 2 n-type impurity region, 3 n-type high concentration impurity region, 4, 6, 8 Source / drain region, 5 p-type well region, 7 n-type well region, 9 Color filter, 10 On-chip Lens, 11 Semiconductor substrate, 12 Gate insulating film, 13 Element isolation layer, 14 Trench element isolation layer, 15 (N-type impurity introduced) electrode layer, 16 (No impurity introduced) electrode layer, 17 (p Electrode layer, 18 wiring layer, 19 insulating layer, 20 pixels, 21, 22, 23, 24 gate electrode, 25 signal lines, 31, 32 resist, RST reset transistor, Amp amplification transistor, SEL selection Transistor

Claims (15)

A vertical first conductivity type channel MOS transistor formed by embedding a gate electrode in a semiconductor substrate; a planar first conductivity type channel MOS transistor having a gate electrode formed on the semiconductor substrate; A semiconductor device having a planar second conductivity type channel MOS transistor having a gate electrode formed on a semiconductor substrate,
A vertical first conductivity type channel MOS transistor including the gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which an impurity is not introduced; ,
A planar first conductivity type channel MOS transistor including the gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which an impurity is not introduced; ,
A stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer into which an impurity of the second conductivity type is introduced thereon, including the gate electrode that is an electrode of the second conductivity type; A planar second conductivity type channel MOS transistor;
A circuit element other than the transistor formed below or on the vertical first-conductivity-type channel MOS transistor,
Semiconductor device.   2. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The semiconductor device according to claim 2, wherein the first conductivity type impurity is phosphorus, and the second conductivity type impurity is boron.   4. The semiconductor device according to claim 3, wherein a concentration of phosphorus in the vicinity of an interface between the gate electrode and the gate insulating film of the vertical first conductivity type channel MOS transistor is 0.15 to 0.25 wt%.   The concentration of the first conductivity type impurity in the vicinity of the interface between the gate electrode and the gate insulating film of the vertical first conductivity type channel MOS transistor is the gate of the planar first conductivity type channel MOS transistor. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the vicinity of an interface between the electrode and the gate insulating film is higher. A vertical first conductivity type channel MOS transistor formed by embedding a gate electrode in a semiconductor substrate; a planar first conductivity type channel MOS transistor having a gate electrode formed on the semiconductor substrate; A method of manufacturing a semiconductor device having a planar second conductivity type channel MOS transistor having a gate electrode formed on a semiconductor substrate,
Forming a hole in the semiconductor substrate, filling the inside of the hole, and forming an electrode layer into which the first conductivity type impurity is introduced over the entire surface;
Forming an electrode layer into which impurities are not introduced on the electrode layer into which the first conductivity type impurities are introduced;
The electrode layer in which two layers are stacked includes a vertical first conductivity type channel MOS transistor, a planar first conductivity type channel MOS transistor, and a planar type second conductivity type channel MOS transistor. Patterning each gate electrode pattern;
And a step of ion-implanting a second conductivity type impurity into the gate electrode of the planar second conductivity type channel MOS transistor.   The method of manufacturing a semiconductor device according to claim 6, wherein the first conductivity type is n-type and the second conductivity type is p-type.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first conductivity type impurity is phosphorus, and the second conductivity type impurity is boron.   The method for manufacturing a semiconductor device according to claim 6, wherein a thickness of the electrode layer into which the first conductivity type impurity is introduced is equal to or larger than a radius of the hole formed in the semiconductor substrate. The electrode layer obtained by introducing the _phosphorus, SiH _4, the H 2, PH CVD method using ₃ gas to form as an amorphous silicon layer, a method of manufacturing a semiconductor device according to claim 8. The method for manufacturing a semiconductor device according to claim 8, wherein the electrode layer into which the phosphorus is introduced is formed as a polycrystalline silicon layer by a CVD method using SiH ₄ , H ₂ , and PH ₃ gas. A photodiode formed for each pixel in a semiconductor substrate, a vertical first conductivity type channel MOS transistor formed by embedding a gate electrode in the semiconductor substrate, and a gate electrode formed on the semiconductor substrate. A solid-state imaging device having a planar first conductivity type channel MOS transistor and a planar second conductivity type channel MOS transistor having a gate electrode formed on the semiconductor substrate,
The photodiode;
A transfer gate including the gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which the impurity is not introduced, and formed on the photodiode; The vertical first-conductivity-type channel MOS transistor,
A planar first conductivity type channel MOS transistor including the gate electrode having a stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer on which an impurity is not introduced; ,
A stacked structure of an electrode layer into which an impurity of the first conductivity type is introduced and an electrode layer into which an impurity of the second conductivity type is introduced thereon, including the gate electrode that is an electrode of the second conductivity type; A planar second-conductivity-type channel MOS transistor;
Solid-state image sensor.   A pixel portion having a photodiode, the vertical first conductivity type channel MOS transistor, and the planar first conductivity type channel MOS transistor, the planar first conductivity type channel MOS transistor, and the planar type The solid-state imaging device according to claim 12, further comprising: a logic unit including a second conductivity type channel MOS transistor.   The solid-state imaging device according to claim 12, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The solid-state imaging device according to claim 14, wherein the first conductivity type impurity is phosphorus, and the second conductivity type impurity is boron.

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