JP2010278393A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that when a silicon mixed crystal layer is formed in a p-type source drain region, there may be a risk of a decrease in carrier mobility of an N-type MIS transistor. <P>SOLUTION: An active region 10a and an active region 10b are isolated by an element isolation region 11, a first transistor of a first conductivity type is provided on the active region 10a, and a second transistor of a second conductivity type is provided on the active region 10b. In the active region 10b, the silicon mixed crystal layer 21 having first stress is provided. A recessed part 22 is provided on an upper surface of a part of the element isolation region 11 sandwiched between the active region 10a and active region 10b. A stress insulating film 24 is provided in the recessed part 23, and has second stress in the opposite direction from the first stress. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a silicon mixed crystal layer is provided in an active region and a manufacturing method thereof.

  In recent years, with the development of information communication equipment, semiconductor devices such as system LSI (large scale integration) are required to have high processing capability. Therefore, the operation speed of the transistor is increased. For example, CMIS (Complementary Metal Insulator Semiconductor) transistors composed of an N-type MIS (Metal Insulator Semiconductor) transistor and a P-type MIS transistor are widely used because of their low power consumption. It is planned by That is, the increase in the speed of the CMIS transistor has been supported by the advancement of lithography technology for processing semiconductor elements. However, recently, the minimum required processing dimension is less than the wavelength of light used for lithography, and it is becoming difficult to further refine the CMIS transistor.

  Therefore, there is a demand for a technique for improving the performance of the transistor without reducing the structure of the transistor. As one of the techniques, there is a strained silicon technique in which carrier mobility is improved by distorting a silicon crystal. In a transistor using strained silicon technology, there is a possibility that a large carrier mobility can be obtained as compared with a transistor composed of bulk silicon. Therefore, in a transistor using strained silicon technology, performance can be improved without miniaturization of the structure.

  It is known that the current drive capability of the CMIS transistor is improved by using this strained silicon technology, and the following technologies are attracting attention. That is, if a material having a lattice constant larger than that of silicon (the substrate is made of silicon) is embedded in the source / drain region of the P-type MIS transistor formation region in the CMIS transistor, compressive stress is applied to the channel region of the P-type MIS transistor. The carrier mobility in the P-type MIS transistor can be improved. Specifically, a source / drain region of a P-type MIS transistor formation region in the CMIS transistor is formed of a silicon mixed crystal such as silicon germanium (SiGe) having a lattice constant larger than that of silicon. Then, since compressive stress is applied to the silicon crystal in the channel region of the P-type MIS transistor, carrier mobility (hole mobility) increases in the P-type MIS transistor. Thereby, the current drive capability of the P-type MIS transistor in the CMIS transistor can be improved. This is disclosed in Patent Document 1 and the like.

  Hereinafter, the configuration of a semiconductor device having a P-type MIS transistor manufactured using strained silicon technology will be described with reference to FIGS. 9 and 10A to 10D. FIG. 9 is a plan view of a conventional semiconductor device. FIGS. 10A to 10D are cross-sectional views taken along lines AA ′, BB ′, CC ′, and DD ′ shown in FIG. 9, respectively. In FIG. 9, FIG. 10A, FIG. 10C, and FIG. 10D, “NTr” indicates an N-type MIS transistor formation region NTr in which an N-type MIS transistor is formed, and “PTr”. Indicates a P-type MIS transistor formation region PTr in which a P-type MIS transistor is formed. In FIG. 9, the silicide layer 122 is not shown.

  In the semiconductor device shown in FIG. 9 and FIGS. 10A to 10D, the first active region 110 a and the second active region 110 b have a channel width across the element isolation region 111 on the semiconductor substrate 110. They are arranged side by side. A p-type well region 112a is formed in the first active region 110a, and an n-type well region 112b is formed in the second active region 110b. An N-type MIS transistor is provided on the first active region 110a, and a P-type MIS transistor is provided on the second active region 110b.

  The N-type MIS transistor has the following configuration. A gate insulating film 113 and a gate electrode 114 are provided in this order on the first active region 110 a, and a sidewall 118 is provided on the side surface of the gate electrode 114. The side wall 118 includes an inner side wall 116 and an outer side wall 117, the inner side wall 116 is provided on the side surface of the gate electrode 114, and the outer side wall 117 is interposed via the inner side wall 116. It is provided on the side surface of the gate electrode 114. In the first active region 110 a, an n-type extension region 115 a is provided below the side of the gate electrode 114, and an n-type source / drain region 119 a is provided below the side wall 118. A silicide layer 122 is formed on the upper surface of the gate electrode 114 and the upper surface of the n-type source / drain region 119a.

  The P-type MIS transistor has the following configuration. A gate insulating film 113 and a gate electrode 114 are provided in this order on the second active region 110 b, and a sidewall 118 is provided on the side surface of the gate electrode 114. The sidewall 118 in the P-type MIS transistor formation region PTr has the same configuration as the sidewall 118 in the N-type MIS transistor formation region NTr. In the second active region 110 b, a p-type extension region 115 b is provided below the side of the gate electrode 114, and a p-type source / drain region 119 b is provided below the side wall 118. A SiGe layer 121 is formed in the p-type source / drain region 119b. A silicide layer 122 is formed on the upper surface of the gate electrode 114 and the upper surface of the p-type source / drain region 119b.

JP 2007-227565 A

  The CMIS transistor includes an N-type MIS transistor and a P-type MIS transistor. Therefore, in the CMIS transistor, it is desirable that both the N-type MIS transistor and the P-type MIS transistor exhibit high current drive capability.

  By the way, in many CMIS transistors, an N-type MIS transistor is located next to a P-type MIS transistor. Therefore, the compressive stress from the SiGe layer of the P-type MIS transistor may be applied to the channel region of the N-type MIS transistor located adjacent to the P-type MIS transistor through the element isolation region. When compressive stress is applied to the channel region of the N-type MIS transistor, the carrier mobility (electron mobility) is reduced in the N-type MIS transistor, so that the current driving capability is reduced.

  The present invention has been made to solve the above-described problems, and in a semiconductor device including a first conductivity type first transistor and a second conductivity type second transistor, and a method of manufacturing the same, It is an object of the present invention to suppress a decrease in current driving capability of the other transistor even when the transistor has a silicon mixed crystal layer in the active region.

  The semiconductor device of the present invention includes a first conductivity type first transistor and a second conductivity type second transistor. The first transistor is provided on the first active region in the semiconductor region, and the second transistor is provided on the second active region in the semiconductor region, and the first active region and the second active region are provided. The region is separated by an element isolation region. A silicon mixed crystal layer is provided in the first active region of such a semiconductor device, and the silicon mixed crystal layer has a first stress. In addition, a recess is provided on the upper surface of a portion of the element isolation region sandwiched between the first active region and the second active region, and the recess is formed on the upper surface of the element isolation region, the first active region, and the first active region. The upper surface of the element isolation region only needs to be positioned below the upper surface of the channel region of the second transistor in the second active region. A stress insulating film is provided in the recess, and the stress insulating film has a second stress in a direction opposite to the first stress.

  In such a semiconductor device, the first stress is applied from the silicon mixed crystal layer to the channel region of the first transistor. Thereby, the current drive capability of the first transistor can be improved.

  In the semiconductor device, at least a part of the first stress from the silicon mixed crystal layer can be offset by the second stress from the stress insulating film. Thereby, the fall of the current drive capability of a 2nd transistor can be suppressed.

  In the semiconductor device of the present invention, the thickness of the stress insulating film is preferably equal to or greater than the depth of the recess. This further prevents the first stress from the silicon mixed crystal layer from being applied to the channel region of the second transistor.

  In the semiconductor device of the present invention, it is preferable that the bottom surface of the recess is located below the upper surface of the silicon mixed crystal layer and above the lower surface of the silicon mixed crystal layer. This further prevents the first stress from the silicon mixed crystal layer from being applied to the channel region of the second transistor through the element isolation region.

  In the semiconductor device of the present invention, it is preferable that the silicon mixed crystal layer is not provided in the second active region. Thereby, it can suppress that the 1st stress is applied to the 2nd active region.

  In a preferred embodiment described below, the first stress generates a compressive stress in the gate width direction, and the second stress generates a tensile stress in the gate width direction.

  When the silicon mixed crystal layer has compressive stress and the stress insulating film has tensile stress, the tensile stress is preferably 1 GPa or more. This further prevents the first stress from the silicon mixed crystal layer from being applied to the channel region of the second transistor.

  When the silicon mixed crystal layer has a compressive stress and the stress insulating film has a tensile stress, the first transistor is a P-type MIS transistor and the second transistor is an N-type MIS transistor. The silicon mixed crystal layer is a SiGe layer, and the stress insulating film is a silicon nitride film.

  When the second transistor is an N-type MIS transistor, the stress insulating film preferably covers the second active region and generates a tensile stress in the gate length direction. Accordingly, since the second stress is applied to the channel region of the second transistor, the current driving capability of the second transistor can be improved.

  In the first transistor of such a semiconductor device, the first gate insulating film is provided on the first active region, the first gate electrode is provided on the first gate insulating film, The first sidewall is provided on the side surface of the first gate electrode, and the first source / drain region is provided in a portion of the first active region located below the side of the first sidewall. The silicon mixed crystal layer is provided in the first source / drain region.

  In the first method for manufacturing a semiconductor device of the present invention, an element isolation region is formed between the first active region and the second active region, and then the first active region has a first stress. A silicon mixed crystal layer is provided, and then a portion of the element isolation region sandwiched between the first active region and the second active region is etched to form a recess, and a second stress (first stress) is formed in the recess. A stress insulating film having a stress in a direction opposite to the stress 1) is provided.

  A second semiconductor device of the present invention includes a first conductivity type first transistor and a second conductivity type second transistor. The first transistor is provided on the first active region in the semiconductor region, and the second transistor is provided on the second active region in the semiconductor region, and the first active region and the second active region are provided. The region is separated by an element isolation region. A silicon mixed crystal layer is provided in the first active region of such a semiconductor device, and the silicon mixed crystal layer has a first stress. In addition, a cavity portion formed in a portion sandwiched between the first active region and the second active region in the element isolation region is provided.

  In such a semiconductor device, the first stress is applied from the silicon mixed crystal layer to the channel region of the first transistor. Thereby, the current drive capability of the first transistor can be improved.

  Further, the first stress from the silicon mixed crystal layer is relaxed in the cavity. Therefore, it is possible to prevent the first stress from the silicon mixed crystal layer from being applied to the channel region of the second transistor through the element isolation region. Thereby, the fall of the current drive capability of a 2nd transistor can be suppressed.

  In the second semiconductor device of the present invention, the silicon mixed crystal layer may be an SiGe layer, and therefore, the first transistor may be a P-type MIS transistor and the second transistor is an N-type MIS transistor. good.

  In the first method for manufacturing a semiconductor device of the present invention, an element isolation region having a cavity is formed between the first active region and the second active region, and then, in the first active region, A silicon mixed crystal layer having a compressive stress is provided.

  According to the present invention, in a semiconductor device including a first conductivity type first transistor and a second conductivity type second transistor and a method of manufacturing the same, one transistor has a silicon mixed crystal layer in an active region. Even if it is provided, a decrease in the current drive capability of the other transistor can be suppressed.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. (A)-(d) is sectional drawing in the AA 'line | wire, BB' line | wire, CC 'line, and DD' line shown in FIG. 1, respectively. (A1)-(d1) and (a2)-(d2) are sectional drawings which show the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in order of a process, (a1)-(d1) is FIG. And (d2) are cross-sectional views taken along the line DD ′ shown in FIG. 1. (A1)-(b1) and (a2)-(b2) are sectional drawings which show the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in order of a process, (a1)-(b1) is FIG. And (b2) are cross-sectional views taken along the line DD ′ shown in FIG. (A1)-(b1) and (a2)-(b2) are sectional drawings which show a part of manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in order of a process, (a1) and (b1) are It is sectional drawing in the AA 'line shown in FIG. 1, (a2) and (b2) are sectional drawings in the BB' line shown in FIG. It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention. (A)-(d) is sectional drawing in the AA 'line | wire, BB' line | wire, CC 'line, and DD' line shown in FIG. 6, respectively. (A1) to (c1) and (a2) to (c2) are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps, and (a1) to (c1) are FIG. FIG. 7 is a cross-sectional view taken along the line AA ′ shown in FIG. It is a top view of the conventional semiconductor device. (A)-(d) is sectional drawing in the AA 'line | wire, BB' line | wire, CC 'line, and DD' line shown in FIG. 9, respectively.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. For example, the material is not limited to the following materials, the film thickness, the concentration, and the like are not limited to the following numerical values, and the film formation method, the etching method, and the like are not limited to the following methods. Moreover, the same code | symbol may be attached | subjected with respect to the same member, and description may be abbreviate | omitted.

<< First Embodiment >>
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  First, the structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 2A to 2D. FIG. 1 is a plan view of the semiconductor device according to the present embodiment. 2A to 2D are cross-sectional views taken along lines AA ′, BB ′, CC ′, and DD ′ shown in FIG. 1, respectively. In FIG. 1, FIG. 2A, FIG. 2C, and FIG. 2D, “NTr” indicates an N-type MIS transistor formation region NTr in which an N-type MIS transistor is formed. "Indicates a P-type MIS transistor formation region PTr in which a P-type MIS transistor is formed. In FIG. 1, the silicide layer 22 and the stress insulating film 24 are not shown.

  As shown in FIG. 1 and FIGS. 2A to 2D, an active region 10 a and an active region 10 b are surrounded by an element isolation region 11 on an upper portion (semiconductor region) of a semiconductor substrate 10 made of silicon, In addition, they are arranged side by side in the channel width direction (gate width direction) with the element isolation region 11 interposed therebetween. The active region 10a is formed in the N-type MIS transistor formation region NTr, and the p-type well region 12a is formed in the active region 10a. The active region 10b is formed in the P-type MIS transistor formation region PTr, and the n-type well region 12b is formed in the active region 10b. In the semiconductor device according to the present embodiment, an N-type MIS transistor is formed on the active region 10a, and a P-type MIS transistor is formed on the active region 10b.

  The configuration of the N-type MIS transistor is as follows. A gate insulating film 13 and a gate electrode 14 are provided in this order on the active region 10a. A side wall 18 is provided on the side surface of the gate electrode 14, and the side wall 18 has an inner side wall 16 and an outer side wall 17. The inner sidewall 16 is provided on the side surface of the gate electrode 14 and has an L-shaped cross-sectional shape. The outer sidewall 17 is provided on the side surface of the gate electrode 14 via the inner sidewall 16.

  An n-type extension region 15a is formed below the side of the gate electrode 14 in the active region 10a. An n-type source / drain region 19a is formed below the side wall 18 in the active region 10a, and the n-type source / drain region 19a has a deeper junction depth than the n-type extension region 15a. A silicide layer 22 is provided on the upper surface of the gate electrode 14 and the upper surface of the n-type source / drain region 19a.

Here, the gate insulating film 13 is a silicon oxide film, for example, and has a thickness of 2 to 4 nm. The gate electrode 14 is a polysilicon film, for example, and has a thickness of 50 to 100 nm. The inner side wall 16 is, for example, a silicon oxide film, and the outer side wall 17 is, for example, a silicon nitride film. An n-type impurity such as arsenic is implanted into the n-type extension region 15a, and the dose is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . An n-type impurity such as arsenic is implanted into the n-type source / drain region 19a, and the dose is about 1 × 10 ¹⁶ / cm ² . The silicide layer 22 is made of, for example, NiSi and has a thickness of about 20 nm.

  The configuration of the P-type MIS transistor is as follows. A gate insulating film 13 and a gate electrode 14 are provided in this order on the active region 10b. A side wall 18 is provided on the side surface of the gate electrode 14, and the side wall 18 has an inner side wall 16 and an outer side wall 17. The inner sidewall 16 is provided on the side surface of the gate electrode 14 and has an L-shaped cross-sectional shape. The outer sidewall 17 is provided on the side surface of the gate electrode 14 via the inner sidewall 16.

  A p-type extension region 15b is formed below the side of the gate electrode 14 in the active region 10b. A p-type source / drain region 19b is formed below the side wall 18 in the active region 10b. The p-type source / drain region 19b has a junction depth larger than that of the p-type extension region 15b. A silicide layer 22 is provided on the upper surface of the gate electrode 14 and the upper surface of the p-type source / drain region 19b.

Here, the gate insulating film 13, the gate electrode 14, the sidewall 18 and the silicide layer 22 provided in the P-type MIS transistor forming region PTr are respectively formed in the gate insulating film 13 provided in the N-type MIS transistor forming region NTr, It is the same as the gate electrode 14, the sidewall 18 and the silicide layer 22. A p-type impurity such as boron is implanted into the p-type extension region 15b, and the dose is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . A p-type impurity such as boron is implanted into the p-type source / drain region 19b, and the dose is, for example, 1 × 10 ¹⁶ / cm ² .

Further, a silicon mixed crystal layer 21 is formed in the p-type source / drain region 19b. The silicon mixed crystal layer 21 is made of a silicon mixed crystal (for example, SiGe) having a lattice constant larger than that of silicon, and generates compressive stress (first stress) in the gate length direction and the gate width direction. The silicon mixed crystal layer 21 has a film thickness of about 60 nm and contains about 20 to 30% Ge with respect to silicon in terms of atomic ratio. The silicon mixed crystal layer 21 is also implanted with, for example, 1 × 10 ¹⁶ / cm ² of a p-type impurity such as boron. That is, the concentration of the p-type impurity in the silicon mixed crystal layer 21 is preferably the same as the concentration of the p-type impurity in the p-type source / drain region 19b. Since the silicon mixed crystal layer 21 is thus formed in the p-type source / drain region 19b, a compressive stress is applied in the gate length direction in the channel region of the P-type MIS transistor. Therefore, carrier mobility (hole mobility) in the P-type MIS transistor can be improved. Therefore, in this embodiment, the current drive capability of the P-type MIS transistor can be improved. The silicon mixed crystal layer 21 is formed only in the p-type source / drain region 19b and not in the n-type source / drain region 19a. The silicon mixed crystal layer 21 is a part of the active region 10b in the present embodiment and the second embodiment described below.

  The semiconductor device according to the present embodiment further includes the following configuration.

  As shown in FIGS. 2A to 2D, in the semiconductor device according to this embodiment, the recess 23 is formed on the entire upper surface of the element isolation region 11, and the stress insulating film 24 is formed on the entire upper surface of the semiconductor substrate 10. Covering. In other words, in the semiconductor device according to the present embodiment, the upper surface of the element isolation region 11 is located below the upper surface of the active region 10a and the upper surface of the active region 10b, and the stress insulating film 24 is formed in the element isolation region. 11, the entire upper surface of the active region 10a, and the entire upper surface of the active region 10b. However, in the final structure after the contact is formed, the entire upper surface of the active region 10a and the entire upper surface of the active region 10b covered by the stress insulating film 24 mean a region excluding the region where the contact is formed.

  The stress insulating film 24 is an insulating film that generates tensile stress (second stress) in the gate width direction, and is produced, for example, by irradiating an insulating film containing hydrogen (for example, a silicon nitride film) with ultraviolet rays. It is an insulating film. When the insulating film containing hydrogen is irradiated with ultraviolet rays, hydrogen is released from the insulating film. Since the insulating film irradiated with ultraviolet rays contracts due to the release of hydrogen, tensile stress is generated. That is, the stress insulating film 24 causes tensile stress in the gate width direction by contracting itself. The tensile stress may be 1 GPa or more, preferably 1 GPa or more and 1.9 GPa or less, and more preferably 1.7 GPa or more and 1.9 GPa or less. Incidentally, the tensile stress of the silicon nitride film formed by CVD (Chemical Vapor Deposition) method is less than 0.1 GPa, and the tensile of the silicon nitride film containing hydrogen (silicon nitride film before being irradiated with ultraviolet rays) The stress is about 0.3 GPa. In such a semiconductor device, compressive stress from the silicon mixed crystal layer 21 formed in the p-type source / drain region 19b of the P-type MIS transistor is applied to the channel region of the N-type MIS transistor through the element isolation region 11. Can be suppressed. This will be described below in comparison with the semiconductor device shown in FIGS. 9 and 10A to 10D.

  In the semiconductor device shown in FIG. 9 and FIGS. 10A to 10D, the SiGe layer 121 is formed in the p-type source / drain region 119b of the P-type MIS transistor. A compressive stress is applied, so that the carrier mobility of the P-type MIS transistor can be improved. However, the compressive stress from the SiGe layer 121 is applied to the channel region of the N-type MIS transistor via the element isolation region 111 located between the first active region 110a and the second active region 110b. For this reason, the carrier mobility (electron mobility) of the N-type MIS transistor is lowered, and the drive current capability of the N-type MIS transistor is lowered.

  The semiconductor device according to the present embodiment has the silicon mixed crystal layer 21 in the p-type source / drain region 19b of the P-type MIS transistor, similarly to the semiconductor devices shown in FIGS. 9 and 10A to 10D. Yes. However, in the semiconductor device according to the present embodiment, the recess 23 is formed on the entire upper surface of the element isolation region 11. Therefore, in the semiconductor device according to the present embodiment, the portion of the element isolation region 11 located between the active region 10a and the active region 10b is more than the semiconductor device shown in FIGS. 9 and 10A to 10D. Can be narrowed. In other words, the element isolation region 11 that causes the compressive stress from the silicon mixed crystal layer 21 to be applied to the channel region of the N-type MIS transistor is shown in FIGS. 9 and 10A to 10D. It can be made narrower than the device. In addition, in the semiconductor device according to the present embodiment, the stress insulating film 24 is provided on the entire top surface of the semiconductor substrate 10. Therefore, at least a part of the compressive stress from the silicon mixed crystal layer 21 can be offset by the tensile stress from the stress insulating film 24. From these things, it can suppress that the compressive stress from the silicon mixed crystal layer 21 is applied to the channel region of the N-type MIS transistor. Therefore, in the semiconductor device according to the present embodiment, not only can the current drive capability of the P-type MIS transistor be improved, but also a decrease in the current drive capability of the N-type MIS transistor can be suppressed.

  Here, when the semiconductor device has the recess 23 but does not have the stress insulating film 24, it is difficult to cancel the compressive stress from the silicon mixed crystal layer with the tensile stress from the stress insulating film. Further, when the semiconductor device has the stress insulating film 24 but does not have the recess 23, the element isolation region that causes the compressive stress from the silicon mixed crystal layer to be applied to the channel region of the N-type MIS transistor. In other words, it is difficult to make the portion of the element isolation region 11 located between the active region 10a and the active region 10b narrower than the semiconductor device shown in FIGS. 9 and 10A to 10D. For these reasons, if the semiconductor device does not have both the recess 23 and the stress insulating film 24, the compressive stress from the silicon mixed crystal layer 21 is suppressed from being applied to the channel region of the N-type MIS transistor. It ’s difficult.

  In the present embodiment, the bottom surface of the recess 23 (the upper surface of the element isolation region 11) is located below the upper surface of the silicon mixed crystal layer 21 and more than the upper surface of the channel region immediately below the gate insulating film 13 in the active region 10a. Preferably it is located below. When the bottom surface of the recess 23 is located above the top surface of the silicon mixed crystal layer 21, or the bottom surface of the recess 23 is flush with the top surface of the silicon mixed crystal layer 21, and immediately below the gate insulating film 13 in the active region 10a. If it is located above the upper surface of the channel region, the compressive stress from the silicon mixed crystal layer 21 may be applied to the channel region of the N-type MIS transistor through the element isolation region 11. Therefore, the bottom surface of the recess 23 is preferably located below the top surface of the silicon mixed crystal layer 21 and below the top surface of the channel region immediately below the gate insulating film 13 in the active region 10a. Furthermore, the bottom surface of the recess 23 is lower than the upper surface of the silicon mixed crystal layer 21 and lower than the upper surface of the channel region immediately below the gate insulating film 13 in the active region 10a and the lower surface of the silicon mixed crystal layer 21. It is preferable that it is located above. Considering that the thickness of the silicide layer 22 is about 20 nm and the thickness of the silicon mixed crystal layer 21 is about 60 nm, the depth of the recess 23 may be about 20 to 60 nm. Thereby, compressive stress from the silicon mixed crystal layer 21 can be prevented from being applied to the channel region of the N-type MIS transistor while ensuring insulation between the active region 10a and the active region 10b.

  The thickness of the stress insulating film 24 in this embodiment is preferably equal to or greater than the depth of the recess 23. Thereby, since the stress insulating film 24 having a sufficient thickness is provided in the recess 23, it is possible to sufficiently suppress the compressive stress from the silicon mixed crystal layer 21 being applied to the channel region of the N-type MIS transistor. . Since the depth of the recess 23 is preferably about 20 to 60 nm, the thickness of the stress insulating film 24 is preferably about 20 to 100 nm. Incidentally, the depth of the element isolation region 11 is about 200 to 300 nm.

  In summary, in the semiconductor device according to the present embodiment, the silicon mixed crystal layer 21 is formed in the p-type source / drain region 19b of the P-type MIS transistor. A recess 23 is formed on the entire upper surface of the element isolation region 11, and a stress insulating film 24 covers the entire upper surface of the semiconductor substrate 10. For these reasons, it is possible to suppress a decrease in the drive current capability of the N-type MIS transistor while improving the drive current capability of the P-type MIS transistor.

  By the way, in order to suppress the compressive stress from the silicon mixed crystal layer 21 being applied to the channel region of the N-type MIS transistor, the recess 23 is sandwiched between the active region 10a and the active region 10b in the element isolation region 11. The stress insulating film 24 is provided in the recess 23 formed in the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b. Just do it. In this case, the recess 23 is formed on the upper surface of the element isolation region 11 sandwiched between the active region 10a and the active region 10b and the side surface of the active region 10a (specifically, the side surface of the n-type source / drain region 19a). The upper portion) and the side surface of the active region 10b (specifically, the upper portion of the side surface of the p-type source / drain region 19b, that is, the upper portion of the side surface of the silicon mixed crystal layer 21).

  However, if the recess 23 is formed not only on the upper surface of the element isolation region 11 between the active region 10a and the active region 10b but also on the entire upper surface of the element isolation region 11, the formation of the recess 23 is simplified. A new effect that it can be achieved can be obtained. Further, since the stress insulating film 24 contracts itself to generate a tensile stress, the stress insulating film 24 generates a tensile stress not only in the gate width direction but also in the gate length direction. Therefore, the stress insulating film 24 is not only provided in the recess 23 formed in the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b, but also covers the upper surface of the active region 10a. If so, tensile stress is applied to the channel region of the N-type MIS transistor, so that the carrier mobility of the N-type MIS transistor can be improved. Therefore, a new effect that the drive current capability of the N-type MIS transistor can be improved can be obtained. Further, if the stress insulating film 24 is provided so as to cover the entire upper surface of the semiconductor substrate 10, a new effect that the formation of the stress insulating film 24 can be simplified can be obtained.

  The method for manufacturing the semiconductor device according to this embodiment will be described below. 3 (a1) to (d1), FIGS. 3 (a2) to (d2), FIGS. 4 (a1) to (b1) and FIGS. 4 (a2) to (b2) are diagrams illustrating the manufacture of the semiconductor device according to this embodiment. It is sectional drawing which shows a method in process order. 3 (a1) to (d1) and FIGS. 4 (a1) to (b1) are cross-sectional views taken along the line CC ′ shown in FIG. 1, and FIGS. 3 (a2) to (d2) and FIG. 4 (a2). (B2) is sectional drawing in the DD 'line shown in FIG. FIGS. 5A1 to 5B1 and FIGS. 5A2 to 5B2 are cross-sectional views illustrating a part of the method of manufacturing the semiconductor device according to this embodiment in the order of steps, and FIGS. ) Is a cross-sectional view taken along the line AA ′ shown in FIG. 1, and FIGS. 5A2 and 5B2 are cross-sectional views taken along the line BB ′ shown in FIG. In FIG. 3A1, FIG. 3A2, FIG. 4A1, FIG. 4A2, and FIG. 5A1, “NTr” is an N-type MIS in which an N-type MIS transistor is formed. A transistor formation region NTr is shown, and “PTr” indicates a P-type MIS transistor formation region PTr in which a P-type MIS transistor is formed.

  First, in the steps shown in FIGS. 3A1 and 3A2, a trench (not shown) is formed in a portion of the semiconductor substrate 10 where the element isolation region 11 is formed using, for example, a resist mask (not shown). To do. The depth of the trench is preferably about 200 to 300 nm. Next, a silicon oxide film (not shown) having a film thickness of 100 nm to 150 nm is formed on the semiconductor substrate 10 by setting the deposition temperature to 800 ° C. to 900 ° C. using, for example, the CVD method. Subsequently, for example, annealing at 900 ° C. to 1000 ° C. is performed as necessary, and then a planarization process is performed on the silicon oxide film. By this planarization process, the N-type MIS transistor formation region NTr and the P-type MIS transistor formation region PTr on the upper surface of the semiconductor substrate 10 are exposed, while the silicon oxide film provided in the trench remains. Thereby, the element isolation region 11 is formed (step (a)). Further, an active region 10 a made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the N-type MIS transistor formation region NTr, and the P-type MIS transistor formation region PTr is surrounded by the element isolation region 11. An active region 10b made of the semiconductor substrate 10 is formed.

  Next, in the steps shown in FIGS. 3B1 and 3B2, the p-type well region 12a is formed in the N-type MIS transistor formation region NTr in the semiconductor substrate 10, while the P-type MIS transistor formation in the semiconductor substrate 10 is performed. An n-type well region 12b is formed in the region PTr.

  Thereafter, a silicon oxide film and a polysilicon film (both not shown) are sequentially formed on the entire upper surface of the semiconductor substrate 10 by using, for example, a thermal oxidation method. The thickness of the silicon oxide film is 2 to 4 nm, and the thickness of the polysilicon film is 50 to 100 nm. Subsequently, the silicon oxide film and the polysilicon film are patterned using a photolithography method and a dry etching method. Thereby, the gate insulating film 13 made of a silicon oxide film and the gate electrode 14 made of a polysilicon film are formed in this order on the active region 10a and the active region 10b.

Subsequently, in the process shown in FIGS. 3C1 and 3C2, a first mask (not shown) is formed so as to cover the active region 10b, and then the first mask and the N-type MIS transistor are formed. Using the gate electrode 14 in the formation region NTr, an n-type impurity such as arsenic is implanted below the side of the gate electrode 14 in the active region 10a. As a result, an n-type extension region 15a is formed below the side of the gate electrode 14 in the active region 10a. Thereafter, the first mask is removed. Then, after forming a second mask (not shown) so as to cover the active region 10a, the gate of the active region 10b is formed using the second mask and the gate electrode 14 in the P-type MIS transistor formation region PTr. A p-type impurity such as boron is implanted under the side of the electrode 14. As a result, a p-type extension region 15b is formed below the side of the gate electrode 14 in the active region 10b. Thereafter, the second mask is removed. At this time, irrespective of the conductivity type of the implanted impurity, the implantation energy is, for example, 2 to 5 keV, and the dose amount is, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² .

  Thereafter, for example, a silicon oxide film and a silicon nitride film (both not shown) are sequentially deposited on the entire upper surface of the semiconductor substrate 10. At this time, the thickness of the silicon oxide film is, for example, 10 nm, and the thickness of the silicon nitride film is, for example, 50 nm. Then, anisotropic etching is performed on the silicon nitride film and the silicon oxide film. Thereby, the sidewall 18 is formed on the side surface of the gate electrode 14. That is, the inner sidewall 16 made of a silicon oxide film and having an L-shaped cross section is formed on the side surface of the gate electrode 14, and the outer sidewall 17 made of a silicon nitride film is interposed through the inner sidewall 16. Formed on the side of the.

Then, after forming a third mask (not shown) so as to cover the active region 10b, the active region is formed using the third mask, the gate electrode 14 and the sidewall 18 in the N-type MIS transistor formation region NTr. An n-type impurity such as arsenic is implanted below the side wall 18 of 10a. As a result, the n-type source / drain region 19a is formed at a position below the side wall 18 in the active region 10a and at a junction depth deeper than that of the n-type extension region 15a. Thereafter, the third mask is removed. Then, after forming a fourth mask (not shown) so as to cover the active region 10a, the active region is formed using the fourth mask and the gate electrode 14 and the sidewall 18 in the P-type MIS transistor formation region PTr. A p-type impurity such as boron is implanted below the side of the gate electrode 14 in 10b. As a result, the p-type source / drain region 19b is formed in the active region 10b below the side wall 18 and at a position where the junction depth is deeper than the p-type extension region 15b. At this time, regardless of the conductivity type of the implanted impurity, the implantation energy is, for example, 30 keV, and the dose amount is, for example, 1 × 10 ¹⁶ / cm ² .

Subsequently, in the steps shown in FIGS. 3D1 and 3D2, the fourth mask and the gate electrode 14 and the sidewalls 18 in the P-type MIS transistor formation region PTr are used as an etching mask, and for example, HBr is used as an etching gas. Then, dry etching is performed on the upper surface of the p-type source / drain region 19b. As a result, a recess (recess for forming a silicon mixed crystal) is formed on the upper surface of the p-type source / drain region 19b. The depth of the recess is, for example, 60 nm. Thereafter, a silicon mixed crystal (for example, SiGe) is epitaxially grown in the recess portion by using, for example, a low pressure thermal CVD method. When the silicon mixed crystal is SiGe, GeH ₄ or the like can be used as a Ge source gas. At this time, it is preferable to epitaxially grow the silicon mixed crystal while implanting a p-type impurity such as boron. Thereby, the silicon mixed crystal layer 21 is formed in the recess portion (step (b)), and the formed silicon mixed crystal layer 21 becomes a part of the active region 10b. The formed silicon mixed crystal layer 21 has a thickness of about 60 nm, and the Ge concentration in the silicon mixed crystal layer 21 is about 20 to 30 atomic%. Thereafter, after removing the fourth mask, a spike RTA of 1000 ° C. is performed on the semiconductor substrate 10. By this heat treatment, the n-type impurity and the p-type impurity implanted into the semiconductor substrate 10 in the steps shown in FIGS. 3C1, 3C2, 3D1, and 3D2 are activated.

  Thereafter, a nickel film having a thickness of about 20 nm is formed on the upper surface of the semiconductor substrate 10. Then, heat treatment is performed in a nitrogen atmosphere at 500 ° C. for 10 seconds. As a result, nickel silicide is formed on the upper portion of the n-type source / drain region 19a, the upper portion of the p-type source / drain region 19b, and the upper portion of the gate electrode. Then, after removing the nickel film remaining in an unreacted state, heat treatment for stabilizing the silicide is performed. Thereby, a silicide layer 22 having a thickness of about 20 nm is formed on the n-type source / drain region 19a, the p-type source / drain region 19b, and the gate electrode 14.

  Subsequently, in the process shown in FIGS. 4A1 and 4A2, wet etching is performed on the semiconductor substrate 10 using, for example, hydrofluoric acid. By this wet etching, the upper portion of the element isolation region 11 is removed. Thus, as shown in FIGS. 4A1, 4A2, 5A1, and 5A2, the upper surface of the element isolation region 11 is the upper surface of the active region 10a and the upper surface of the active region 10b. Located below. At this time, the upper surface of the element isolation region 11 is lower than the upper surface of the silicon mixed crystal layer 21 and lower than the upper surface of the channel region immediately below the gate insulating film 13 in the active region 10a and the silicon mixed crystal layer 21. It is preferable that it is located above the lower surface of. In other words, a recess 23 composed of the side surface of the active region 10a and the side surface of the silicon mixed crystal layer 21 in the active region 10b is formed on the entire upper surface of the element isolation region 11. At this time, it is preferable to perform wet etching so that the depth of the recess 23 is about 20 to 60 nm.

  Here, if this wet etching is performed before the silicide layer 22 is formed, a portion of the silicide layer 22 that is in contact with the element isolation region 11 may be formed at a deep position in the semiconductor substrate 10. May increase. Therefore, it is preferable to perform this wet etching after forming the silicide layer 22.

  Further, as described above, the recess 23 may be formed on the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b. Therefore, the recess 23 may be formed only on the upper surface of the element isolation region 11 sandwiched between the active region 10a and the active region 10b (step (c)). Specifically, after covering the upper surface of the portion of the element isolation region 11 where the recess 23 is not formed (the portion other than the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b) with a mask, Wet etching may be performed on the element isolation region 11.

  Then, in the process shown in FIGS. 4B1 and 4B2, the stress insulating film 24 is provided on the entire top surface of the semiconductor substrate 10. Specifically, first, a silicon nitride film (not shown) containing hydrogen is provided on the entire top surface of the semiconductor substrate 10. Next, the silicon nitride film containing hydrogen is irradiated with ultraviolet rays. Then, hydrogen is released from the silicon nitride film, and as a result, the silicon nitride film itself contracts. As a result, as shown in FIGS. 4B1, 4B2, 5B1, and 5B2, the stress insulating film 24 in the present embodiment is formed on the entire upper surface of the semiconductor substrate 10. . In this manner, the semiconductor device according to this embodiment can be manufactured.

  Here, as described above, the stress insulating film 24 may be provided in the recess 23 formed on the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b. Therefore, in this step, the stress insulating film 24 may be provided only in the recess 23 formed on the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b (step (d)). ). Specifically, one of the following methods may be selected. In the first method, a silicon nitride film containing hydrogen is formed only in the recess 23 (the recess 23 formed on the upper surface of the portion of the element isolation region 11 sandwiched between the active region 10a and the active region 10b). Thereafter, the silicon nitride film is irradiated with ultraviolet rays. In the second method, a silicon nitride film containing hydrogen is provided over the entire upper surface of the semiconductor substrate 10 and then irradiated with ultraviolet rays. Thereafter, the insulating film irradiated with the ultraviolet rays is formed in the recess 23 (in the element isolation region 11). The insulating film irradiated with ultraviolet rays is removed so as to remain only in the recesses 23) formed on the upper surface of the portion sandwiched between the active region 10a and the active region 10b.

  As described above, in the method for manufacturing the semiconductor device according to the present embodiment, the silicon mixed crystal layer 21 is formed in the p-type source / drain region 19b in the steps shown in FIGS. 3 (d1) and 3 (d2). The As a result, compressive stress is applied to the channel region of the P-type MIS transistor, so that the carrier mobility of the P-type MIS transistor can be improved, and thus the drive current capability of the P-type MIS transistor can be improved. .

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, the recess 23 is formed on the entire upper surface of the element isolation region 11 in the steps shown in FIGS. 4A1 and 4A2, and FIGS. In the step shown in 4 (b2), the stress insulating film 24 is formed on the entire upper surface of the semiconductor substrate 10. As a result, it is possible to suppress the compressive stress from the silicon mixed crystal layer 21 being applied to the channel region of the N-type MIS transistor, and thus it is possible to suppress a decrease in drive current capability of the N-type MIS transistor.

<< Second Embodiment >>
In the second embodiment of the present invention, the compressive stress from the silicon mixed crystal layer is applied to the channel region of the N-type MIS transistor by using means different from the means described in the first embodiment. Suppress. In the following, the semiconductor device and the manufacturing method thereof according to the present embodiment will be described with a focus on differences from the first embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be described with reference to FIGS. 6 and 7A to 7D. FIG. 6 is a plan view of the semiconductor device according to the present embodiment. 7A to 7D are cross-sectional views taken along lines AA ′, BB ′, CC ′, and DD ′ shown in FIG. 6, respectively. In FIG. 6, FIG. 7A, FIG. 7C, and FIG. 7D, “NTr” indicates an N-type MIS transistor formation region NTr in which an N-type MIS transistor is formed. "Indicates a P-type MIS transistor formation region PTr in which a P-type MIS transistor is formed. In FIG. 6, illustration of the silicide layer 22 and the stress insulating film 24 is omitted.

  The semiconductor device according to the present embodiment has a cavity 26 in a portion sandwiched between the active region 10a and the active region 10b in the element isolation region 11 while having no recess in the first embodiment. Except for this, the semiconductor device has the same configuration as that of the semiconductor device according to the first embodiment.

  Specifically, the semiconductor device according to the present embodiment has the silicon mixed crystal layer 21 in the p-type source / drain region 19b as in the semiconductor device according to the first embodiment. Thereby, compressive stress is applied to the channel region of the P-type MIS transistor.

  In addition, the semiconductor device according to the present embodiment does not have the recess in the first embodiment, but the cavity 26 is formed in the element isolation region 11 between the active region 10a and the active region 10b. have. Thereby, the compressive stress from the silicon mixed crystal layer 21 can be relaxed in the cavity 26. Therefore, in the semiconductor device according to the present embodiment, not only can the current driving capability of the P-type MIS transistor be improved, but also the current driving capability of the N-type MIS transistor, as in the semiconductor device according to the first embodiment. The decrease can be suppressed.

  In the present embodiment, the lower end of the cavity 26 is preferably located below the lower surface of the silicon mixed crystal layer 21. Thereby, the compressive stress from the silicon mixed crystal layer 21 can be sufficiently relieved in the cavity portion 26 as compared with the case where the lower end of the cavity portion 26 is located above the lower surface of the silicon mixed crystal layer 21. it can. The upper end of the cavity 26 is preferably located below the upper surface of the element isolation region 11. If the cavity is open on the upper surface of the element isolation region, the material of the film may be mixed into the cavity when a film is formed on the upper surface of the semiconductor substrate. Therefore, it is preferable that the upper end of the cavity portion 26 is located below the upper surface of the element isolation region 11. As described above, the cavity 26 is preferably formed from a position below the upper surface of the element isolation region 11 to a position below the lower surface of the silicon mixed crystal layer 21. Considering that the thickness of the element isolation region 11 is about 200 to 300 nm and the thickness of the silicon mixed crystal layer 21 is about 60 nm, the length of the cavity 26 in the thickness direction of the semiconductor device is about 60 to 100 nm. It is preferable.

In order to form such a cavity portion 26 in the element isolation region 11, the width W _{1 of the} portion where the cavity portion 26 is formed in the element isolation region 11 is formed, and the cavity portion 26 is formed in the element isolation region 11. it may be narrower than the width W ₂ of the portion which is not. In other words, the width W ₁ of the portion sandwiched by the active region 10a and the active region 10b of the element isolation region 11 is not sandwiched between the active region 10a and the active region 10b of the element isolation region 11 it may be narrower than the width W ₂ of the part. Since the width _{W 2} is about 80 nm, the width _{W 1} may be narrower than 80 nm, it is sufficient, for example 70 nm.

  In summary, in the semiconductor device according to the present embodiment, the silicon mixed crystal layer 21 is formed in the p-type source / drain region 19b of the P-type MIS transistor. In the semiconductor device according to the present embodiment, the cavity 26 is formed in the element isolation region 11 between the active region 10a and the active region 10b. For these reasons, it is possible to suppress a decrease in the drive current capability of the N-type MIS transistor while improving the drive current capability of the P-type MIS transistor.

  In the semiconductor device according to the present embodiment, even if the stress insulating film 24 in the first embodiment is formed over the entire upper surface of the semiconductor substrate 10 as shown in FIGS. The stress insulating film 24 in the first embodiment may not be formed at all. However, if the stress insulating film 24 in the first embodiment covers at least the upper surface of the active region 10a, tensile stress is applied to the channel region of the N-type MIS transistor, so that the driving current of the N-type MIS transistor is reduced. Ability can be improved. Therefore, in the semiconductor device according to the present embodiment, it is preferable that the stress insulating film 24 in the first embodiment covers at least the upper surface of the active region 10a.

  In the semiconductor device according to the present embodiment, not the stress insulating film 24 in the first embodiment but an insulating film having a tensile stress of 0.1 GPa or less (for example, a silicon nitride film formed using a CVD method or the like). May be formed over the entire top surface of the semiconductor substrate 10. Thereby, this insulating film having a tensile stress of 0.1 GPa or less can function as an etching stopper when forming a contact hole or the like.

  The method for manufacturing the semiconductor device according to this embodiment will be described below. 8A1 to 8C1 and 8A2 to 8C2 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to this embodiment in the order of steps, and FIGS. 8A1 to 8C1 are diagrams. 6 is a cross-sectional view taken along line AA ′ shown in FIG. 6, and FIGS. 8A to 8C2 are cross-sectional views taken along line BB ′ shown in FIG. 6.

  First, as shown in FIGS. 8A1 and 8A2, a trench (not shown) is formed in a portion of the semiconductor substrate 10 where the element isolation region 11 is to be formed using, for example, a resist mask (not shown). To do. The depth of the trench is preferably about 200 to 300 nm. At this time, the width of the portion sandwiched between the region to be the active region 10a and the region to be the active region 10b in the trench is made smaller than the width of the other portion of the trench. For example, the width of the portion sandwiched between the region that becomes the active region 10a and the region that becomes the active region 10b in the trench is made smaller than 80 nm, and the width of the other portion of the trench is made about 80 nm.

  Next, a silicon oxide film (not shown) having a film thickness of 100 nm to 150 nm is formed on the semiconductor substrate 10 by setting the deposition temperature to 800 ° C. to 900 ° C. using, for example, the CVD method. At this time, since the width of the portion sandwiched between the region to be the active region 10a and the region to be the active region 10b in the trench is narrower than the width of the other portion of the trench, the active region 10a of the silicon oxide film A cavity 26 is formed in a portion sandwiched between the region to be formed and the region to be the active region 10b. At this time, if the upper end of the formed cavity 26 is closed in the trench, the material constituting the film remains in the cavity 26 even if a film is formed on the upper surface of the semiconductor substrate in the subsequent process. Can be prevented. Therefore, it is preferable that the upper end of the formed cavity 26 is closed in the trench.

  Thereafter, for example, annealing is performed from 900 ° C. to 1000 ° C. as necessary, and then the silicon oxide film is planarized. By this planarization process, the N-type MIS transistor formation region NTr and the P-type MIS transistor formation region PTr on the upper surface of the semiconductor substrate 10 are exposed, while the silicon oxide film provided in the trench remains. Thereby, the element isolation region 11 is formed (step (a)). Further, an active region 10 a made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the N-type MIS transistor formation region NTr, and the P-type MIS transistor formation region PTr is surrounded by the element isolation region 11. An active region 10b made of the semiconductor substrate 10 is formed. Thereafter, as described in the first embodiment, the gate insulating film 13, the gate electrode 14, the n-type and p-type extension regions 15a and 15b, the sidewall 18, the n-type and p-type source / drain regions 19a and 19b. Then, the silicon mixed crystal layer 21 and the silicide layer 22 are formed. As a result, the structure shown in FIGS. 8B1 and 8B2 can be obtained.

  Thereafter, as shown in FIGS. 8C1 and 8C2, a stress insulating film 24 is provided on the entire top surface of the semiconductor substrate 10 in accordance with the method described in the first embodiment. Thereby, the semiconductor device in this embodiment can be manufactured.

  As described above, in the semiconductor device manufacturing method according to the present embodiment, the silicon mixed crystal layer 21 is formed in the p-type source / drain region 19b as in the first embodiment, although details are omitted. As a result, compressive stress is applied to the channel region of the P-type MIS transistor, so that the carrier mobility of the P-type MIS transistor can be improved, and thus the drive current capability of the P-type MIS transistor can be improved. .

  Further, in the method of manufacturing the semiconductor device according to the present embodiment, in the step shown in FIGS. 8A1 and 8A2, a portion sandwiched between the active region 10 a and the active region 10 b in the element isolation region 11. A cavity 26 is formed. Thereby, since the compressive stress from the silicon mixed crystal layer 21 is relieved in the cavity 26, it is possible to suppress a decrease in the drive current capability of the N-type MIS transistor.

  Note that the method for manufacturing a semiconductor device according to the present embodiment may not include the steps shown in FIGS. 8C1 and 8C2. Further, in FIGS. 8C1 and 8C2, a silicon nitride film is formed on the entire upper surface of the semiconductor substrate using a CVD method or the like instead of forming a stress insulating film over the entire upper surface of the semiconductor substrate. You may do it. Thereby, the silicon nitride film formed by using the CVD method or the like is a contact hole forming step (steps subsequent to the steps shown in FIGS. 8C1 and 8C2 and is not mentioned in this specification. ) To function as an etching stopper layer.

<< Other Embodiments >>
The first and second embodiments may have the following configuration.

  The gate insulating film is a silicon oxide film, but may be a high dielectric film (for example, HfSiON) having a relative dielectric constant larger than that of the silicon nitride film.

  Although the gate electrode is made of a polysilicon film, it may be a laminate of a metal film (for example, an electrode made of TiN) and a polysilicon film.

  The silicon mixed crystal layer in the p-type source / drain region is not limited to the SiGe mixed crystal layer, and may be a SiGeC mixed crystal layer.

  Needless to say, the first embodiment and the second embodiment can be combined. That is, in the semiconductor device, the recess is formed on the entire upper surface of the element isolation region, and the cavity is formed in a portion of the element isolation region sandwiched between the first active region and the second active region. The stress insulating film may be provided on the entire top surface of the semiconductor substrate. In this case, as described in the first embodiment, the recess only needs to be formed on the upper surface of the portion of the element isolation region sandwiched between the first active region and the second active region, The stress insulating film may be provided in the recess formed in the upper surface of the portion of the element isolation region sandwiched between the first active region and the second active region.

  As described above, the present invention is useful for a semiconductor device such as a system LSI.

10 Semiconductor substrate
10a Active region (second active region)
10b Active region (first active region)
11 Device isolation region
12a p-type well region
12b n-type well region
13 Gate insulation film
14 Gate electrode
15a n-type extension region
15b p-type extension region (first extension region)
16 Inside sidewall
17 Outside sidewall
18 sidewall
19a n-type source / drain region
19b p-type source / drain region (first source / drain region)
21 Silicon mixed crystal layer
22 Silicide layer
23 recess
24 Stress insulation film

Claims (16)

A first transistor of the first conductivity type provided on the first active region in the semiconductor region and a second active region in the semiconductor region separated from the first active region by an element isolation region A semiconductor device comprising a second transistor of the second conductivity type provided,
A silicon mixed crystal layer having a first stress provided in the first active region;
A recess provided on an upper surface of a portion sandwiched between the first active region and the second active region in the element isolation region;
A semiconductor device comprising: a stress insulating film provided in the recess and having a second stress in a direction opposite to the first stress. The semiconductor device according to claim 1,
The thickness of the said stress insulating film is a semiconductor device which is more than the depth of the said recessed part. The semiconductor device according to claim 1 or 2,
The recess is composed of an upper surface of the element isolation region and side surfaces of the first active region and the second active region,
The upper surface of the element isolation region is located below the upper surface of the channel region of the second transistor in the second active region. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device, wherein a bottom surface of the recess is located below the upper surface of the silicon mixed crystal layer and above the lower surface of the silicon mixed crystal layer. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device in which the silicon mixed crystal layer is not provided in the second active region. The semiconductor device according to any one of claims 1 to 5,
The first stress generates a compressive stress in the gate width direction,
The semiconductor device in which the second stress generates a tensile stress in the gate width direction. The semiconductor device according to claim 6.
The semiconductor device, wherein the tensile stress of the stress insulating film is 1 GPa or more. The semiconductor device according to claim 6.
The first transistor is a P-type MIS transistor,
The second transistor is an N-type MIS transistor,
The silicon mixed crystal layer is a SiGe layer,
The semiconductor device, wherein the stress insulating film is a silicon nitride film. The semiconductor device according to claim 8,
The stress insulating film covers the second active region and generates a tensile stress in the gate length direction. The semiconductor device according to any one of claims 1 to 9,
The first transistor of the first conductivity type is
A first gate insulating film provided on the first active region;
A first gate electrode provided on the first gate insulating film;
A first sidewall provided on a side surface of the first gate electrode;
A first source / drain region provided in a portion of the first active region located on a side lower side of the first sidewall;
The semiconductor device in which the silicon mixed crystal layer is provided in the first source / drain region. A first transistor of the first conductivity type provided on the first active region in the semiconductor region and a second active region in the semiconductor region separated from the first active region by an element isolation region A semiconductor device comprising a second transistor of the second conductivity type provided,
A silicon mixed crystal layer provided in the first active region and having a first stress;
A semiconductor device comprising: a cavity formed in a portion sandwiched between the first active region and the second active region in the element isolation region. The semiconductor device according to claim 11,
The first transistor is a P-type MIS transistor,
The second transistor is an N-type MIS transistor,
The semiconductor device wherein the silicon mixed crystal layer is a SiGe layer. A first transistor of the first conductivity type provided on the first active region in the semiconductor region and a second active region in the semiconductor region separated from the first active region by an element isolation region A method for manufacturing a semiconductor device comprising a second transistor of the second conductivity type provided,
Forming the element isolation region between the first active region and the second active region (a);
After the step (a), a step (b) of providing a silicon mixed crystal layer having a first stress in the first active region;
After the step (b), a step (c) of forming a recess by etching a portion of the element isolation region sandwiched between the first active region and the second active region;
And (d) providing a stress insulating film having a second stress in a direction opposite to the first stress in the recess. In the manufacturing method of the semiconductor device according to claim 13,
The first transistor is a P-type MIS transistor,
The second transistor is an N-type MIS transistor,
The silicon mixed crystal layer is a SiGe layer,
The method for manufacturing a semiconductor device, wherein the stress insulating film is a silicon nitride film. A first transistor of the first conductivity type provided on the first active region in the semiconductor region and a second active region in the semiconductor region separated from the first active region by an element isolation region A method for manufacturing a semiconductor device comprising a second transistor of the second conductivity type provided,
Forming the element isolation region having a cavity between the first active region and the second active region (a);
A method of manufacturing a semiconductor device comprising: (b) a step of providing a silicon mixed crystal layer having a first stress in the first active region after the step (a). In the manufacturing method of the semiconductor device according to claim 15,
The first transistor is a P-type MIS transistor,
The second transistor is an N-type MIS transistor,
The method for manufacturing a semiconductor device, wherein the silicon mixed crystal layer is a SiGe layer.

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