JP2010278345A

JP2010278345A - Semiconductor device and method of manufacturing the same

Info

Publication number: JP2010278345A
Application number: JP2009130985A
Authority: JP
Inventors: Ryohei Osawa; 良平大澤; Masaru Takizawa; 勝滝沢; Tomoya Sato; 朋弥佐藤; Ryuji Suemoto; 竜二末本; Akihiro Nakamura; 明弘中村
Original assignee: Shindengen Electric Manufacturing Co Ltd
Current assignee: Shindengen Electric Manufacturing Co Ltd
Priority date: 2009-05-29
Filing date: 2009-05-29
Publication date: 2010-12-09

Abstract

<P>PROBLEM TO BE SOLVED: To prevent cracks from occurring on a semiconductor substrate due to the difference in thermal expansion coefficient caused by a change in temperature between a semiconductor substrate and a metal layer. <P>SOLUTION: An insulator coating 20 is formed in a ring so as to cover the boundary between the outer circumferential edge of a P-type diffusion layer 12 and an N-type semiconductor on a semiconductor substrate 11, a contact metal layer 15 is laminated on the surface of the semiconductor substrate 11 inside the insulator coating 20, and a stress relaxing intermediate layer 30, a cushion electrode layer 16 and a lead-out layer 17 are formed so as to cover the surfaces of the contact metal layer 15 and the insulator coating 20. The insulator coating 20 is made of a silicon dioxide coating 13 and a nitride coating 14 having an etching rate smaller than that of the silicon dioxide coating 13. The stress relaxing intermediate layer 30 has a linear expansion coefficient more approximate to the semiconductor substrate 11 than to the stress relaxing metal layer 16. The extraction electrode layer 17 (e.g. Ni) has a smaller etching rate for a surface treatment agent than that of the cushion electrode layer 16 (e.g. Al). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は半導体素子の分野に関し、特に半導体基板と金属層が接触する構造を有する半導体素子の構造とその製造方法に関する。 The present invention relates to the field of semiconductor devices, and more particularly to a structure of a semiconductor device having a structure in which a semiconductor substrate and a metal layer are in contact with each other and a method for manufacturing the same.

半導体を用いた素子として、金属層と他の材料層とを、それぞれ半導体基板（例えばＳｉ）の上面に接触させて形成した構造を有しているものがある。そして、上記他の材料層が、例えば積層構造であって、半導体基板上に形成された第１の材料層の上に第２の材料層が形成され、上記金属層が第１の金属層と、その上に形成された第２の金属層とからなるような場合がある。 An element using a semiconductor has a structure in which a metal layer and another material layer are formed in contact with the upper surface of a semiconductor substrate (for example, Si), respectively. The other material layer has a laminated structure, for example, and a second material layer is formed on the first material layer formed on the semiconductor substrate, and the metal layer is formed with the first metal layer. And a second metal layer formed thereon.

また、このような構造を有する半導体素子の一例として、ショットキーバリアダイオードが挙げられる。ショットキーバリアダイオードとは、ショットキーバリア形構造を形成したダイオードを指す。この構造は、一般的に、半導体基板と金属層が接触する構造を有している。例えば、特許文献１、２には、ショットキーバリアダイオードの構造およびその製造方法が記載されている。このようなショットキーバリアダイオードの一般的な製造方法を、断面図である図６を用いて説明すると以下のようになる。 An example of a semiconductor element having such a structure is a Schottky barrier diode. A Schottky barrier diode refers to a diode having a Schottky barrier structure. This structure generally has a structure in which a semiconductor substrate and a metal layer are in contact with each other. For example, Patent Documents 1 and 2 describe a structure of a Schottky barrier diode and a manufacturing method thereof. A general manufacturing method of such a Schottky barrier diode will be described below with reference to FIG.

まず、第１の導電型（例えばＮ型）の半導体の表層に、いわゆるガードリングと称されるショットキーバリアダイオードの順逆方向電圧−電流特性等の電気的特性改善のための第２の導電型（例えばＰ型）拡散層１０２をリング状に設け、半導体基板１０１を形成する（図６（ａ））。なお、ここでは、簡単のため、第１の導電型がＮ型、第２の導電型がＰ型であるとして説明する。また、図６では、上記Ｐ型拡散層１０２のリングの片方の断面のみを示しており、実際には、断面で見た場合に紙面左方に同様のＰ型拡散層の断面が存在し、そして、図で示すＰ型拡散層１０２と紙面左方に存在するＰ型拡散層との中間にリングの中心が存在することになる。次に、図６（ａ）に示すように、半導体基板１０１全体に絶縁体被膜１２０（パシベーション膜）として、二酸化珪素被膜１０３（酸化膜）および窒化被膜１０４を形成する。絶縁体被膜１２０としては半導体基板１０１表面に形成された二酸化珪素被膜１０３（ＳｉＯ_２）と、この二酸化珪素被膜１０３に積層された窒化被膜１０４（具体的にはＳｉ_３Ｎ_４）とからなる積層膜を採用する。 First, a second conductivity type for improving electrical characteristics such as forward-reverse voltage-current characteristics of a Schottky barrier diode called a so-called guard ring is formed on a surface layer of a first conductivity type (for example, N-type) semiconductor. A (for example, P-type) diffusion layer 102 is provided in a ring shape to form the semiconductor substrate 101 (FIG. 6A). Here, for the sake of simplicity, the description will be made assuming that the first conductivity type is N-type and the second conductivity type is P-type. Further, FIG. 6 shows only a cross section of one side of the ring of the P-type diffusion layer 102. Actually, when viewed in a cross-section, there is a similar cross-section of the P-type diffusion layer on the left side of the page, The center of the ring exists between the P-type diffusion layer 102 shown in the figure and the P-type diffusion layer existing on the left side of the drawing. Next, as shown in FIG. 6A, a silicon dioxide film 103 (oxide film) and a nitride film 104 are formed as an insulator film 120 (passivation film) on the entire semiconductor substrate 101. As the insulator film 120, a laminated layer composed of a silicon dioxide film 103 (SiO ₂ ) formed on the surface of the semiconductor substrate 101 and a nitride film 104 (specifically, Si ₃ N ₄ ) laminated on the silicon dioxide film 103. Adopt a membrane.

次に、二酸化珪素被膜１０３および窒化被膜１０４をパターニングする。図６（ｂ）に示すように、レジスト膜１０４Ａをリング状のＰ型拡散層１０２の外縁を覆うように外側に形成し、まず窒化被膜１０４、続いて二酸化珪素被膜１０３をエッチング（ウェットエッチングまたはドライエッチング等）によりパターニングする。そして、レジスト膜１０４Ａを除去し、リング中央部分に絶縁体被膜の窓穴１５０を形成する。 Next, the silicon dioxide film 103 and the nitride film 104 are patterned. As shown in FIG. 6B, a resist film 104A is formed on the outer side so as to cover the outer edge of the ring-shaped P-type diffusion layer 102, and the nitride film 104 and then the silicon dioxide film 103 are etched (wet etching or Patterning by dry etching). Then, the resist film 104A is removed, and an insulating coating window hole 150 is formed at the center of the ring.

次に、図６（ｃ）に示すように、電位障壁（ショットキーバリア）を形成するために接触金属層１０５、例えばモリブデン／パラジウム等を蒸着等の手段により絶縁体被膜の窓穴１５０に露出させた半導体基板１０１の表面に形成する。そして、この接触金属層１０５および絶縁体被膜１２０（二酸化珪素被膜１０３および窒化被膜１０４）の表面を覆うようにクッション用（応力緩和用）電極層１０６（例えばＡｌ）および半田等とのぬれの良い引出し電極層１０７（例えばＮｉ）を形成する。その後、ショットキーバリア電極側と反対側の半導体基板表面に引出し電極層を形成し、チップ化する。 Next, as shown in FIG. 6C, in order to form a potential barrier (Schottky barrier), a contact metal layer 105 such as molybdenum / palladium is exposed to the window hole 150 of the insulating film by means such as vapor deposition. The semiconductor substrate 101 is formed on the surface. The contact metal layer 105 and the insulator coating 120 (silicon dioxide coating 103 and nitride coating 104) cover the surfaces of the cushioning (stress relaxation) electrode layer 106 (for example, Al) and solder, etc. An extraction electrode layer 107 (for example, Ni) is formed. Thereafter, an extraction electrode layer is formed on the surface of the semiconductor substrate opposite to the Schottky barrier electrode side to form a chip.

特開２００１−１５７７１号公報JP 2001-15771 A 特開２００１−３６０６７号公報JP 2001-36067 A

上記のような第１および第２の材料層と、第１および第２の金属層とを、それぞれ半導体基板の上面に接触させて形成した構造を有する半導体素子において、第２の材料層が第１の材料層よりもエッチングレートが小さく、第２の金属層が第１の金属層よりもエッチングレートが小さい場合、まず第１および第２の材料層をエッチングするとエッチングレートの大きい第１の材料層の方が多くエッチングされてしまい、第２の材料層がひさしのようになってその下に空間ができる。さらにこの場合、半導体装置の表面処理液やエッチング液等によって第１の金属層がより多くエッチングされ、第１の金属層の上で第２の金属層がひさしのようになり、第１の金属層の下側には、半導体基板との接触端面（エッジ）ができる。この状態で、製造工程中の蒸着やエッチング処理や熱処理時における熱膨張係数の差に起因して、第２の金属層に応力がかかると、第２の金属層のひさしの張り出し部分が力点に、そして第１の金属層の半導体との接触端面が作用点となって、てこの原理によって半導体基板の第１の金属層との接触端面付近に過大な力がかかってクラックが入る恐れがある。 In a semiconductor element having a structure in which the first and second material layers and the first and second metal layers as described above are formed in contact with the upper surface of the semiconductor substrate, the second material layer is the first material layer. When the etching rate is lower than that of the first material layer and the second metal layer has an etching rate lower than that of the first metal layer, the first material having a higher etching rate is first etched when the first and second material layers are etched. The layer is etched more, and the second material layer becomes like an eave, creating a space below it. Further, in this case, the first metal layer is more etched by the surface treatment liquid or the etching liquid of the semiconductor device, and the second metal layer becomes eaves on the first metal layer. A contact end face (edge) with the semiconductor substrate is formed below the layer. In this state, when the stress is applied to the second metal layer due to the difference in thermal expansion coefficient during the vapor deposition, etching process or heat treatment during the manufacturing process, the projecting portion of the eaves of the second metal layer becomes the main point. Then, the contact end face of the first metal layer with the semiconductor becomes an action point, and there is a risk that an excessive force is applied to the vicinity of the contact end face of the semiconductor substrate with the first metal layer by the lever principle to cause a crack. .

また、半導体素子の一例として挙げた従来のショットキーバリアダイオードにあっては、窒化被膜１０４のエッチングレートが二酸化珪素被膜１０３のエッチングレートに比べて小さいことに起因して、二酸化珪素被膜１０３が窒化被膜１０４より多くエッチングされ、これによって窒化被膜１０４に二酸化珪素被膜１０３よりも窓穴１５０の中央部側に張り出された部分（以下、窒化被膜ひさし１０４ａという）が形成される。これが原因となって窒化被膜ひさし１０４ａの下の半導体基板１０１側に空間が空く。この状態でクッション用電極層１０６および引出し電極層１０７をこの上に積層すると、窒化被膜ひさし１０４ａおよびその下に開いた空間の影響によって引き出し電極層１０７やクッション用電極層１０６に段切れ１６０が生じることがある（図６（ｃ）参照）。 Further, in the conventional Schottky barrier diode mentioned as an example of the semiconductor element, the silicon dioxide film 103 is nitrided because the etching rate of the nitride film 104 is smaller than the etching rate of the silicon dioxide film 103. Etching is performed more than the coating 104, thereby forming a portion (hereinafter referred to as a nitride coating eaves 104 a) that protrudes from the silicon dioxide coating 103 toward the center of the window hole 150. This causes a space on the semiconductor substrate 101 side under the nitride film eaves 104a. When the cushion electrode layer 106 and the lead electrode layer 107 are laminated thereon in this state, a step 160 occurs in the lead electrode layer 107 and the cushion electrode layer 106 due to the influence of the nitride film eaves 104a and the space opened therebelow. (See FIG. 6C).

ショットキーバリアダイオードなどの半導体素子の製造過程では、裏面の付着物などの除去、洗浄のために例えばフッ酸等の表面処理液を使うことがあるが、段切れ１６０が生じた状態でこの表面処理液にさらすと、段切れ１６０にも表面処理液が浸入する。ここで、引出し電極層１０７の表面処理液に対するエッチングレートはクッション用電極層１０６の表面処理液に対するエッチングレートよりも小さいため、両者のエッチングレートの違いに起因してクッション用電極層１０６の方がより多くエッチングされ、段切れ１６０の空洞が広がる（図６（ｄ）参照）。このため，引出し電極層１０７にクッション用電極層１０６よりも張り出された部分（以下、金属層ひさし１０７ａという）が形成される。また、クッション用電極層１０６がエッチングされることにより、クッション用電極層１０６の下側には、半導体基板１０１との接触端面（エッジ）ができる。 In the process of manufacturing a semiconductor device such as a Schottky barrier diode, a surface treatment solution such as hydrofluoric acid may be used for removing or cleaning the adhered matter on the back surface. When exposed to the treatment liquid, the surface treatment liquid also enters the step 160. Here, the etching rate of the extraction electrode layer 107 with respect to the surface treatment solution is smaller than the etching rate of the cushion electrode layer 106 with respect to the surface treatment solution. More etching is performed, and the cavity of the step 160 is expanded (see FIG. 6D). For this reason, a portion (hereinafter referred to as a metal layer eave 107a) that protrudes from the cushion electrode layer 106 is formed on the extraction electrode layer 107. Further, by etching the cushion electrode layer 106, a contact end surface (edge) with the semiconductor substrate 101 is formed below the cushion electrode layer 106.

この状態で、製造時や検査時において温度が変化すると、引出し電極層１０７（例えばＮｉ）の熱膨張係数よりもクッション用電極層１０６（例えばＡｌ）の熱膨張係数が大きいために、引出し電極層１０７に応力がかかることになる。また、半導体基板１０１の熱膨張係数はクッション用電極層１０６の熱膨張係数よりも小さい。従って、引出し電極層１０７の金属層ひさし１０７ａの張り出し部分が力点に、そしてクッション用電極層１０６の半導体との接触端面が作用点となって、てこの原理によって半導体基板１０１のクッション用電極層１０６との接触端面付近に過大な力がかかってクラック１７０が入る恐れがある（図６（ｄ）参照）。なお、この時の支点は、例えば引出し電極層１０７と半導体基板１０１との間に存在すると考えられる。 In this state, if the temperature changes during manufacturing or inspection, the thermal expansion coefficient of the cushion electrode layer 106 (for example, Al) is larger than the thermal expansion coefficient of the extraction electrode layer 107 (for example, Ni). 107 is stressed. The thermal expansion coefficient of the semiconductor substrate 101 is smaller than the thermal expansion coefficient of the cushion electrode layer 106. Therefore, the protruding portion of the metal layer eaves 107a of the extraction electrode layer 107 serves as a force point, and the contact end surface of the cushion electrode layer 106 with the semiconductor serves as an action point. There is a possibility that an excessive force is applied in the vicinity of the contact end face with the crack 170 to enter (see FIG. 6D). The fulcrum at this time is considered to exist between the extraction electrode layer 107 and the semiconductor substrate 101, for example.

従って、本発明の目的は、温度変化による半導体基板および金属層の熱膨張係数の差に起因して半導体基板にクラックが生じることを防止することができる半導体素子およびその製造方法を提供することである。 Accordingly, an object of the present invention is to provide a semiconductor element capable of preventing the semiconductor substrate from being cracked due to a difference in thermal expansion coefficient between the semiconductor substrate and the metal layer due to temperature change, and a method for manufacturing the same. is there.

上述した課題を解決するために、本発明の半導体素子は、半導体基板と、該半導体基板の表面上に形成された第１の材料層と、該第１の材料層の表面上に形成され、前記第１の材料層よりもエッチングレートの小さい第２の材料層と、前記半導体基板の表面上および前記第２の材料層の表面上に形成された応力緩和中間層と、前記応力緩和中間層の表面上に形成された第１の金属層と、該第１の金属層の表面上に形成され、前記第１の金属層よりもエッチングレートの小さい第２の金属層と、を有し、前記応力緩和中間層は線膨張係数が前記第１の金属層よりも前記半導体基板に近いことを特徴とする。 In order to solve the above-described problems, a semiconductor element of the present invention is formed on a semiconductor substrate, a first material layer formed on the surface of the semiconductor substrate, and a surface of the first material layer, A second material layer having an etching rate lower than that of the first material layer; a stress relaxation intermediate layer formed on the surface of the semiconductor substrate and on the surface of the second material layer; and the stress relaxation intermediate layer A first metal layer formed on the surface of the first metal layer, and a second metal layer formed on the surface of the first metal layer and having a lower etching rate than the first metal layer, The stress relaxation intermediate layer has a linear expansion coefficient closer to the semiconductor substrate than the first metal layer.

上記のような構成を有する本発明の半導体素子においては、半導体基板の表面と第１の金属層との間には応力緩和中間層が位置するため、第１の金属層のエッジが半導体基板に直接接することがない。これにより、製造時や検査時の熱による熱膨張係数の差に起因して、第２の金属層に応力がかかっても、てこの原理によって過大な力がかかるのは応力緩和中間層のみに限られ、半導体基板には何らの影響を及ぼすことがない。しかも応力緩和中間層の線膨張係数が第１の金属層よりも半導体基板に近いため、半導体基板が応力緩和中間層のエッジから受ける変形の影響が小さくなる。従って、半導体基板にクラックが入ることを防止することができる。 In the semiconductor element of the present invention having the above configuration, since the stress relaxation intermediate layer is located between the surface of the semiconductor substrate and the first metal layer, the edge of the first metal layer is formed on the semiconductor substrate. There is no direct contact. As a result, even if stress is applied to the second metal layer due to the difference in thermal expansion coefficient due to heat during manufacturing or inspection, only the stress relaxation intermediate layer is subjected to excessive force by the lever principle. It is limited and does not affect the semiconductor substrate. In addition, since the linear expansion coefficient of the stress relaxation intermediate layer is closer to that of the semiconductor substrate than the first metal layer, the influence of the deformation that the semiconductor substrate receives from the edge of the stress relaxation intermediate layer is reduced. Therefore, cracks can be prevented from entering the semiconductor substrate.

上記半導体素子において、望ましくは、前記応力緩和中間層は前記第１の金属層よりもエッチングレートが小さいことを特徴とする。 In the semiconductor element, preferably, the stress relaxation intermediate layer has an etching rate smaller than that of the first metal layer.

また、本発明のショットキーバリアダイオードとして使用される半導体素子は、第１の導電型の半導体の表層に第２の導電型拡散層がリング状に形成されてなる半導体基板と、該半導体基板の前記第２の導電型拡散層の外周縁と前記半導体基板との境界を覆うリング状に形成された絶縁体被膜と、該絶縁体被膜の内側の前記半導体基板表面に積層された接触金属層と、該接触金属層および前記絶縁体被膜の表面を覆うように形成された応力緩和用電極層と、この応力緩和用電極層に積層され、前記応力緩和用電極層よりもエッチングレートの小さい引き出し電極層とを具備し、前記絶縁体被膜は積層膜であり、前記絶縁体被膜を形成する複数の膜は、互いに隣り合う膜のうち半導体基板よりも遠い側に位置する膜のエッチングレートが半導体基板側に位置する膜のエッチングレートよりも小さく形成され、さらに、前記接触金属層と前記応力緩和用電極層との間に、線膨張係数が前記応力緩和金属層よりも前記半導体基板に近い材料からなる応力緩和中間層を有することを特徴とする。 The semiconductor element used as the Schottky barrier diode of the present invention includes a semiconductor substrate in which a second conductivity type diffusion layer is formed in a ring shape on the surface layer of the first conductivity type semiconductor, and the semiconductor substrate. An insulating coating formed in a ring shape covering the boundary between the outer peripheral edge of the second conductivity type diffusion layer and the semiconductor substrate, and a contact metal layer laminated on the surface of the semiconductor substrate inside the insulating coating; A stress relieving electrode layer formed so as to cover the contact metal layer and the surface of the insulator coating, and a lead electrode laminated on the stress relieving electrode layer and having a lower etching rate than the stress relieving electrode layer And the insulating film is a laminated film, and the plurality of films forming the insulating film has a semiconductor with an etching rate of a film located on a side farther than the semiconductor substrate among adjacent films. A material formed smaller than the etching rate of the film located on the plate side, and further, a material whose linear expansion coefficient is closer to the semiconductor substrate than the stress relaxation metal layer between the contact metal layer and the stress relaxation electrode layer It has the stress relaxation intermediate | middle layer which consists of.

上記のような構成を有する本発明のショットキーバリアダイオードとして使用される半導体素子においては、接触金属層と応力緩和用電極層との間に、線膨張係数が接触金属応力緩和用電極層よりも半導体基板に近い材料からなる応力緩和中間層が配置されるため、応力緩和用電極層のエッジが半導体基板に直接接することがない。そして、応力緩和用電極層および引き出し電極層に段切れが生じ、この段切れに表面処理液が浸入して段切れの空洞が広がり、引出し電極層に金属層ひさしが形成されたとしても、応力緩和用電極層のエッジは半導体基板ではなく応力緩和中間層の上面に形成されることになる。これにより、製造時や検査時の熱による熱膨張係数の差に起因して、引出し電極層に応力がかかっても、この原理によって過大な力がかかるのは上記応力緩和中間層のみに限られ、半導体基板には何らの影響を及ぼすことがない。しかも応力緩和中間層の線膨張係数が応力緩和用電極層よりも半導体基板に近いため、半導体基板が応力緩和中間層のエッジから受ける変形の影響が小さくなる。従って、半導体基板にクラックが入ることを防止することができる。また、半導体基板に歪みが与えられることが防止されるため、逆方向電流の増加が防止される。 In the semiconductor device used as the Schottky barrier diode of the present invention having the above-described configuration, the linear expansion coefficient is larger than that of the contact metal stress relaxation electrode layer between the contact metal layer and the stress relaxation electrode layer. Since the stress relaxation intermediate layer made of a material close to the semiconductor substrate is disposed, the edge of the stress relaxation electrode layer does not directly contact the semiconductor substrate. Even if a step breakage occurs in the stress relaxation electrode layer and the extraction electrode layer, and the surface treatment liquid enters the step breakage to expand the step breakage cavities and the metal layer eaves are formed in the extraction electrode layer, The edge of the relaxation electrode layer is formed not on the semiconductor substrate but on the upper surface of the stress relaxation intermediate layer. As a result, even if stress is applied to the extraction electrode layer due to the difference in thermal expansion coefficient due to heat during manufacturing or inspection, the excessive force is applied only to the stress relaxation intermediate layer by this principle. There is no effect on the semiconductor substrate. In addition, since the linear expansion coefficient of the stress relaxation intermediate layer is closer to that of the semiconductor substrate than the stress relaxation electrode layer, the influence of the deformation that the semiconductor substrate receives from the edge of the stress relaxation intermediate layer is reduced. Therefore, cracks can be prevented from entering the semiconductor substrate. In addition, since the semiconductor substrate is prevented from being distorted, an increase in reverse current is prevented.

上記のような構成において、望ましくは、前記応力緩和用電極層と前記引き出し電極層とのエッチングレートの差は、表面処理液に対するエッチングレートの差であり、前記絶縁体被膜を形成する複数の膜のエッチングレートの差は、リング状の形態を形成する際のエッチング液に対するエッチングレートの差であり、さらに前記応力緩和中間層は前記応力緩和用電極層よりも表面処理液に対するエッチングレートが小さい。 In the above-described configuration, desirably, the difference in etching rate between the stress relaxation electrode layer and the lead electrode layer is a difference in etching rate with respect to the surface treatment liquid, and a plurality of films forming the insulator film The difference in the etching rate is the difference in the etching rate with respect to the etching solution when forming the ring-shaped form, and the stress relaxation intermediate layer has a lower etching rate with respect to the surface treatment solution than the stress relaxation electrode layer.

また、本発明の半導体素子の製造方法は、半導体基板上に第１の材料層を形成し、該第１の材料層上よりもエッチングレートの小さい第２の材料層を前記第１の材料層上に形成する材料層形成工程と、マスクを使用して前記第１および２の材料層をエッチングするエッチング工程と、前記半導体基板上および前記第２の材料層上に応力緩和中間層を形成する応力緩和中間層形成工程と、前記応力緩和中間層に第１の金属層を形成する金属層形成工程と、前記第１の金属層の表面上に、該第１の金属層よりもエッチングレートの小さい第２の金属層を形成する第１の金属形成工程と、を有し、前記応力緩和中間層は線膨張係数が前記第１の金属層よりも前記半導体基板に近いことを特徴とする。 In the method for manufacturing a semiconductor element of the present invention, a first material layer is formed on a semiconductor substrate, and a second material layer having an etching rate smaller than that on the first material layer is used as the first material layer. A material layer forming step to be formed thereon, an etching step in which the first and second material layers are etched using a mask, and a stress relaxation intermediate layer is formed on the semiconductor substrate and on the second material layer A stress relaxation intermediate layer forming step, a metal layer forming step of forming a first metal layer on the stress relaxation intermediate layer, and an etching rate higher than that of the first metal layer on the surface of the first metal layer. A first metal forming step of forming a small second metal layer, wherein the stress relaxation intermediate layer has a linear expansion coefficient closer to the semiconductor substrate than the first metal layer.

上記のような構成を有する本発明の半導体素子の製造方法においては、応力緩和中間層形成工程において形成される応力緩和中間層が半導体基板の表面と金属層との間に位置するため、金属層のエッジが半導体基板に直接接することがない。これにより、製造時や検査時の熱による熱膨張係数の差に起因して、第２の金属層に応力がかかっても、てこの原理によって過大な力がかかるのは応力緩和中間層のみに限られ、半導体基板には何らの影響を及ぼすことがない。しかも応力緩和中間層の線膨張係数が第１の金属層よりも半導体基板に近いため、半導体基板が応力緩和中間層のエッジから受ける変形の影響が小さくなる。従って、半導体基板にクラックが入ることを防止することができる。 In the method of manufacturing a semiconductor element of the present invention having the above-described configuration, the stress relaxation intermediate layer formed in the stress relaxation intermediate layer forming step is located between the surface of the semiconductor substrate and the metal layer. The edge of the substrate does not directly contact the semiconductor substrate. As a result, even if stress is applied to the second metal layer due to the difference in thermal expansion coefficient due to heat during manufacturing or inspection, only the stress relaxation intermediate layer is subjected to excessive force by the lever principle. It is limited and does not affect the semiconductor substrate. In addition, since the linear expansion coefficient of the stress relaxation intermediate layer is closer to that of the semiconductor substrate than the first metal layer, the influence of the deformation that the semiconductor substrate receives from the edge of the stress relaxation intermediate layer is reduced. Therefore, cracks can be prevented from entering the semiconductor substrate.

上記半導体素子の製造方法において、望ましくは、前記応力緩和中間層は前記第１の金属層よりもエッチングレートが小さい。 In the semiconductor device manufacturing method, preferably, the stress relaxation intermediate layer has an etching rate lower than that of the first metal layer.

また、本発明のショットキーバリアダイオードとして使用される半導体素子の製造方法は、第１の導電型の半導体の表層に第２の導電型拡散層がリング状に形成されてなる半導体基板の表面に絶縁体被膜を積層して形成する絶縁体被膜形成工程と、該絶縁体被膜形成工程にて形成した前記絶縁体被膜にエッチングによって窓穴を形成する窓穴形成工程と、前記窓穴に露出させた半導体基板の表面に接触金属層を形成する接触金属層形成工程と、前記接触金属層および前記絶縁体被膜の表面に応力緩和用電極層を形成した後、該応力緩和用電極層の表面に、前記応力緩和用電極層よりもエッチングレートの小さい引き出し電極層を形成する電極層形成工程とを具備し、前記絶縁体被膜形成工程では、互いに隣り合う膜のうち半導体基板よりも遠い側に位置する膜を半導体基板側に位置する膜よりもエッチングレートの小さい材料で形成し、さらに、前記接触金属層形成工程の後で前記応力緩和用電極層形成工程の前に、線膨張係数が前記応力緩和金属層よりも前記半導体基板に近い材料からなる応力緩和中間層を前記接触金属層および前記絶縁被膜の表面に形成する応力緩和中間層形成工程を具備し、前記応力緩和用電極層形成工程では、前記応力緩和用電極層を前記応力緩和中間層の表面に形成することを特徴とする。 In addition, a method of manufacturing a semiconductor device used as a Schottky barrier diode according to the present invention is provided on a surface of a semiconductor substrate in which a second conductive diffusion layer is formed in a ring shape on a surface layer of a first conductive semiconductor. Insulator film forming step of laminating and forming an insulator film, a window hole forming step of forming a window hole by etching in the insulator film formed in the insulator film forming step, and exposing to the window hole Forming a contact metal layer on the surface of the semiconductor substrate, and forming a stress relaxation electrode layer on the surfaces of the contact metal layer and the insulator coating; And an electrode layer forming step of forming an extraction electrode layer having an etching rate smaller than that of the stress relaxation electrode layer. In the insulator film forming step, the insulating film forming step is farther from the semiconductor substrate than the semiconductor substrate. The film located on the side is formed of a material having a lower etching rate than the film located on the semiconductor substrate side, and further, after the contact metal layer forming step and before the stress relaxation electrode layer forming step, the linear expansion coefficient A stress relaxation intermediate layer forming step of forming a stress relaxation intermediate layer made of a material closer to the semiconductor substrate than the stress relaxation metal layer on the surfaces of the contact metal layer and the insulating coating, and the electrode layer for stress relaxation In the forming step, the stress relaxation electrode layer is formed on a surface of the stress relaxation intermediate layer.

上記のような構成を有する本発明のショットキーバリアダイオードとして使用される半導体素子の製造方法においては、応力緩和中間層形成工程において形成される応力緩和中間層が接触金属層と応力緩和用電極層との間に配置されるため、応力緩和用電極層のエッジが半導体基板に直接接することがない。そして、応力緩和用電極層および引き出し電極層に段切れが生じ、この段切れに表面処理液が浸入して段切れの空洞が広がり、引出し電極層に金属層ひさしが形成されたとしても、応力緩和用電極層のエッジは半導体基板ではなく応力緩和中間層の上面に形成されることになる。これにより、製造時や検査時の熱による熱膨張係数の差に起因して、引出し電極層に応力がかかっても、てこの原理によって過大な力がかかるのは上記応力緩和中間層のみに限られ、半導体基板には何らの影響を及ぼすことがない。しかも応力緩和中間層の線膨張係数が応力緩和用電極層よりも半導体基板に近いため、半導体基板が応力緩和中間層のエッジから受ける変形の影響が小さくなる。従って、半導体基板にクラックが入ることを防止することができる。また、半導体基板に歪みが与えられることが防止されるため、逆方向電流の増加が防止される。 In the method for manufacturing a semiconductor device used as the Schottky barrier diode of the present invention having the above-described configuration, the stress relaxation intermediate layer formed in the stress relaxation intermediate layer forming step includes a contact metal layer and a stress relaxation electrode layer. Therefore, the edge of the stress relaxation electrode layer does not directly contact the semiconductor substrate. Even if a step breakage occurs in the stress relaxation electrode layer and the extraction electrode layer, and the surface treatment liquid enters the step breakage to widen the step breakage cavity, and the metal layer eaves are formed in the extraction electrode layer, The edge of the relaxation electrode layer is formed not on the semiconductor substrate but on the upper surface of the stress relaxation intermediate layer. As a result, even if stress is applied to the extraction electrode layer due to the difference in thermal expansion coefficient due to heat during manufacturing or inspection, excessive force is applied only to the stress relaxation intermediate layer due to the lever principle. The semiconductor substrate is not affected at all. In addition, since the linear expansion coefficient of the stress relaxation intermediate layer is closer to that of the semiconductor substrate than the stress relaxation electrode layer, the influence of the deformation that the semiconductor substrate receives from the edge of the stress relaxation intermediate layer is reduced. Therefore, cracks can be prevented from entering the semiconductor substrate. In addition, since the semiconductor substrate is prevented from being distorted, an increase in reverse current is prevented.

本発明によれば、半導体基板と金属層が接触する構造を有する半導体素子において、温度変化による半導体基板および金属層の熱膨張係数の差に起因して半導体基板にクラックが生じることを防止することができる。 According to the present invention, in a semiconductor element having a structure in which a semiconductor substrate and a metal layer are in contact with each other, it is possible to prevent the semiconductor substrate from being cracked due to a difference in thermal expansion coefficient between the semiconductor substrate and the metal layer due to temperature change. Can do.

本発明の第１の実施形態による半導体素子の基本的な構成を示す概略断面図である。1 is a schematic cross-sectional view showing a basic configuration of a semiconductor element according to a first embodiment of the present invention. 図１に示した半導体素子の製造方法を示す概略断面図であって、（ａ）は半導体基板上に第１の材料層および第２の材料層を形成する工程を説明する図、（ｂ）はレジスト膜を形成して第１の材料層および第２の材料層をエッチングによりパターニングする工程を説明する図、（ｃ）は応力緩和中間層および第１及び第２の金属層を形成する工程を説明する図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor element shown in FIG. 1, (a) is a figure explaining the process of forming the 1st material layer and the 2nd material layer on a semiconductor substrate, (b). FIG. 4 is a diagram for explaining a process of forming a resist film and patterning the first material layer and the second material layer by etching, and (c) a process of forming a stress relaxation intermediate layer and first and second metal layers. FIG. 本発明の第２の実施形態による半導体素子の製造方法を示す概略断面図であって、（ａ）は第１の導電型（Ｎ型）の半導体に第２の導電型（Ｐ型）拡散層をリング状に設け、二酸化珪素被膜（酸化膜）および窒化被膜を形成する工程を説明する図、（ｂ）はレジスト膜を形成する工程を説明する図、（ｃ）は窒化被膜をエッチングによりパターニングする工程を説明する図、（ｄ）は二酸化珪素被膜をエッチングによりパターニングする工程を説明する図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor element by the 2nd Embodiment of this invention, Comprising: (a) is a 2nd conductivity type (P type) diffused layer in the 1st conductivity type (N type) semiconductor. Is a diagram for explaining a process of forming a silicon dioxide film (oxide film) and a nitride film, (b) is a diagram for explaining a process of forming a resist film, and (c) is a patterning of the nitride film by etching. The figure explaining the process to do, (d) is a figure explaining the process of patterning a silicon dioxide film by an etching. 本発明の第２の実施形態による半導体素子の製造方法を示す概略断面図であって、（ａ）はレジスト膜を除去する工程を説明する図、（ｂ）は電位障壁（ショットキーバリア）を形成するための接触金属層を形成する工程を説明する図、（ｃ）は応力緩和中間層、クッション用電極層および引出し電極層を形成する工程を説明する図、（ｄ）はレジスト膜を形成する工程を説明する図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention, (a) is a figure explaining the process of removing a resist film, (b) is a potential barrier (Schottky barrier). The figure explaining the process of forming the contact metal layer for forming, (c) is the figure explaining the process of forming the stress relaxation intermediate | middle layer, the electrode layer for cushions, and the lead-out electrode layer, (d) forms a resist film It is a figure explaining the process to do. 本発明の第２の実施形態による半導体素子の製造方法を示す概略断面図であって、（ａ）は応力緩和中間層、クッション用電極層および引き出し電極層をエッチングによりパターニングする工程を説明する図、（ｂ）はレジスト膜を除去する工程を説明する図、（ｃ）は本発明の第２の実施形態による半導体素子に発生した段切れの空洞が広がる状況を示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor element by the 2nd Embodiment of this invention, (a) is a figure explaining the process of patterning a stress relaxation intermediate | middle layer, the electrode layer for cushions, and the extraction electrode layer by an etching. (B) is a figure explaining the process of removing a resist film, (c) is a schematic sectional drawing which shows the condition where the cavity of the step which generate | occur | produced in the semiconductor element by the 2nd Embodiment of this invention spreads. ショットキーバリアダイオードとして使用される従来の半導体素子の製造方法を示す概略断面図であって、（ａ）は第１の導電型（Ｎ型）の半導体に第２の導電型（Ｐ型）拡散層をリング状に設け、二酸化珪素被膜（酸化膜）および窒化被膜を形成する工程を説明する図、（ｂ）は窒化被膜および二酸化珪素被膜をエッチングによりパターニングする工程を説明する図、（ｃ）は電位障壁（ショットキーバリア）を形成するための接触金属層、クッション用電極層、および引出し電極層を形成する工程を説明する図、（ｄ）は半導体素子に発生した段切れ部分から空洞が広がり、半導体基板にクラックが入る状況を示す図である。It is a schematic sectional drawing which shows the manufacturing method of the conventional semiconductor device used as a Schottky barrier diode, Comprising: (a) is 2nd conductivity type (P type) diffusion to the semiconductor of 1st conductivity type (N type). The figure explaining the process of providing a layer in a ring shape and forming a silicon dioxide film (oxide film) and a nitride film, (b) is the figure explaining the process of patterning a nitride film and a silicon dioxide film by etching, (c) FIG. 4 is a diagram illustrating a process of forming a contact metal layer, a cushion electrode layer, and a lead electrode layer for forming a potential barrier (Schottky barrier), and FIG. It is a figure which shows the condition which spreads and a crack enters into a semiconductor substrate.

以下、本発明を実施するための形態を詳細に説明する。なお、以下の説明で使用する図面においては、説明をわかり易くするために、各層の厚みを実際の縮尺通りには示していない。 Hereinafter, embodiments for carrying out the present invention will be described in detail. In the drawings used in the following description, the thickness of each layer is not shown to an actual scale for easy understanding.

図１は本発明の第１の実施形態による半導体素子の基本的な構成を示す概略断面図である。図１に示すように、本発明の半導体素子は、半導体基板１と、半導体基板１の表面上に形成された第１の材料層２ａと、第１の材料層２ａの表面上に形成され、第１の材料層２ａよりもエッチングレートの小さい第２の材料層２ｂと、半導体基板１の表面上および第２の材料層２ｂの表面上に形成された応力緩和中間層５と、応力緩和中間層５の表面上に形成された第１の金属層３ａと、第１の金属層３ａの表面上に形成され、第１の金属層３ａよりもエッチングレートの小さい第２の金属層３ｂとを有する。ここで、応力緩和中間層５は、線膨張係数が金属層３よりも半導体基板１に近い材料で形成されている。また、応力緩和中間層５は金属層３よりもエッチングレートが小さいことが望ましい。 FIG. 1 is a schematic sectional view showing a basic configuration of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor element of the present invention is formed on a surface of a semiconductor substrate 1, a first material layer 2a formed on the surface of the semiconductor substrate 1, and a first material layer 2a. A second material layer 2b having an etching rate lower than that of the first material layer 2a; a stress relaxation intermediate layer 5 formed on the surface of the semiconductor substrate 1 and on the surface of the second material layer 2b; A first metal layer 3a formed on the surface of the layer 5, and a second metal layer 3b formed on the surface of the first metal layer 3a and having an etching rate smaller than that of the first metal layer 3a. Have. Here, the stress relaxation intermediate layer 5 is formed of a material whose linear expansion coefficient is closer to the semiconductor substrate 1 than the metal layer 3. The stress relaxation intermediate layer 5 desirably has a lower etching rate than the metal layer 3.

次に、図１のような基本的な構成を有する半導体素子の製造方法について、以下で説明する。
まず、図２（ａ）に示すように、半導体基板１の上に第１の材料層２ａを形成し、第１の材料層２ａよりもエッチングレートの小さい第２の材料層２ｂを第１の材料層２ａ上に形成する。次に、図２（ｂ）に示すように、レジスト膜４を形成し、第２の材料層２ｂおよび第１の材料層２ａをエッチングする。この時、第２の材料層２ｂのエッチングレートが第１の材料層２ａのエッチングレートに比べて小さいことに起因して、第１の材料層２ａが第２の材料層２ｂより多くエッチングされる。次に、図２（ｃ）に示すように、半導体基板１および第２の材料層２ｂの上に応力緩和中間層５を形成し、さらに応力緩和中間層５の上に第１の金属層３ａおよび第２の金属層３ｂを形成する。なお、図１および図２（ｃ）においては、第１の材料層２ａが第２の材料層２ｂより多くエッチングされることの影響を受けて、応力緩和中間層５、第１の金属層３ａ、および第２の金属層３ｂが段切れしている例を示す。 Next, a method for manufacturing a semiconductor element having the basic configuration as shown in FIG. 1 will be described below.
First, as shown in FIG. 2A, a first material layer 2a is formed on a semiconductor substrate 1, and a second material layer 2b having an etching rate lower than that of the first material layer 2a is formed on the first material layer 2a. It is formed on the material layer 2a. Next, as shown in FIG. 2B, a resist film 4 is formed, and the second material layer 2b and the first material layer 2a are etched. At this time, the first material layer 2a is etched more than the second material layer 2b because the etching rate of the second material layer 2b is smaller than the etching rate of the first material layer 2a. . Next, as shown in FIG. 2C, the stress relaxation intermediate layer 5 is formed on the semiconductor substrate 1 and the second material layer 2b, and the first metal layer 3a is further formed on the stress relaxation intermediate layer 5. And the 2nd metal layer 3b is formed. In FIG. 1 and FIG. 2C, the stress relaxation intermediate layer 5 and the first metal layer 3a are affected by the fact that the first material layer 2a is etched more than the second material layer 2b. And an example in which the second metal layer 3b is disconnected.

ここで、例えば、製造工程中のエッチング処理や洗浄処理等のための薬液に半導体素子がさらされた場合、第２の金属層３ｂのエッチングレートが第１の金属層３ａのエッチングレートよりも小さいため、図１に示すように、第１の金属層３ａが多くエッチングされエッチバックされるが、第１の金属層３ａのエッジは半導体基板１ではなく応力緩和中間層５の上面で接している。さらに、第１の金属層３ａの上で第２の金属層３ｂがひさしのようになる。 Here, for example, when the semiconductor element is exposed to a chemical solution for etching or cleaning during the manufacturing process, the etching rate of the second metal layer 3b is lower than the etching rate of the first metal layer 3a. Therefore, as shown in FIG. 1, the first metal layer 3a is etched and etched back, but the edge of the first metal layer 3a is in contact with the upper surface of the stress relaxation intermediate layer 5 instead of the semiconductor substrate 1. . Further, the second metal layer 3b becomes eaves on the first metal layer 3a.

本実施形態によれば、製造時や検査時の熱による熱膨張係数の差に起因して、第２の金属層３ｂに応力がかかっても、てこの原理によって第１の金属層３ａを介して過大な力がかかるのは応力緩和中間層５のみに限られ、半導体基板１には何らの影響を及ぼすことがない。従って、半導体基板１にクラックが入ることを防止することができる。 According to the present embodiment, even if stress is applied to the second metal layer 3b due to a difference in thermal expansion coefficient due to heat at the time of manufacturing or inspection, the first metal layer 3a is interposed by the principle of leverage. Therefore, an excessive force is applied only to the stress relaxation intermediate layer 5 and does not affect the semiconductor substrate 1 at all. Therefore, cracks can be prevented from entering the semiconductor substrate 1.

次に、本発明の第２の実施形態を、さらに具体的な例によって説明する。図３〜５は本発明の第２の実施形態による半導体素子の基本的な構成、およびその製造方法を示す概略断面図である。 Next, the second embodiment of the present invention will be described with a more specific example. 3 to 5 are schematic cross-sectional views showing a basic configuration of a semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same.

まず、本発明の第２の実施形態による半導体素子の基本的な構成について、図５（ｃ）により説明する。
本実施形態の半導体素子は、ショットキーバリアダイオードとして使用されるものである。図５（ｃ）に示すように、第１の導電型（例えばＮ型）の半導体の表層に、いわゆるガードリングと称されるショットキーバリアダイオードの順逆方向電圧−電流特性等の電気的特性改善のための第２の導電型（例えばＰ型）拡散層１２がリング状に形成され、半導体基板１１が形成されている。なお、以下では、簡単のため、第１の導電型がＮ型、第２の導電型がＰ型であるとして説明するが、第１の導電型がＰ型、第２の導電型がＮ型であってもよい。 First, the basic structure of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.
The semiconductor element of this embodiment is used as a Schottky barrier diode. As shown in FIG. 5C, the electrical characteristics such as forward-reverse voltage-current characteristics of a Schottky barrier diode called a guard ring are improved on the surface layer of the first conductivity type (for example, N type) semiconductor. A second conductive type (for example, P-type) diffusion layer 12 for forming a semiconductor substrate 11 is formed in a ring shape. In the following description, for the sake of simplicity, the first conductivity type is described as N-type and the second conductivity type is defined as P-type. However, the first conductivity type is P-type and the second conductivity type is N-type. It may be.

半導体基板１１上には、Ｐ型拡散層１２の外周縁とＮ型半導体との境界を覆うように絶縁体被膜２０がリング状に形成され、絶縁体被膜２０の内側の半導体基板１１表面には接触金属層１５が積層されている。絶縁体被膜２０は積層膜であって、二酸化珪素被膜１３（酸化膜）と窒化被膜１４とからなり、窒化被膜１４のパターニング時のエッチングレートは二酸化珪素被膜１３のパターニング時のエッチングレートよりも小さい。接触金属層１５および絶縁体被膜２０の表面を覆うように、応力緩和中間層３０が形成され、応力緩和中間層３０の表面を覆うようにクッション用（応力緩和用）電極層１６が形成され、さらにクッション用電極層１６には引き出し電極層１７が積層されている。また、引出し電極層１７（例えばＮｉ）の表面処理液（半導体素子の裏面の付着物などの除去、洗浄のための表面処理液）に対するエッチングレートはクッション用電極層１６（例えばＡｌ）の表面処理液に対するエッチングレートよりも小さい。さらに、応力緩和中間層３０、クッション用電極層１６および引き出し電極層１７の外周部は除去されている。 On the semiconductor substrate 11, an insulator coating 20 is formed in a ring shape so as to cover the boundary between the outer peripheral edge of the P-type diffusion layer 12 and the N-type semiconductor, and on the surface of the semiconductor substrate 11 inside the insulator coating 20. A contact metal layer 15 is laminated. The insulating film 20 is a laminated film, and includes a silicon dioxide film 13 (oxide film) and a nitride film 14, and the etching rate when patterning the nitride film 14 is smaller than the etching rate when patterning the silicon dioxide film 13. . A stress relaxation intermediate layer 30 is formed so as to cover the surfaces of the contact metal layer 15 and the insulator coating 20, and a cushion (stress relaxation) electrode layer 16 is formed so as to cover the surface of the stress relaxation intermediate layer 30, Further, a lead electrode layer 17 is laminated on the cushion electrode layer 16. The etching rate for the surface treatment liquid of the extraction electrode layer 17 (for example, Ni) (surface treatment liquid for removal and cleaning of deposits on the back surface of the semiconductor element) is the surface treatment of the electrode layer for cushion 16 (for example, Al). It is smaller than the etching rate for the liquid. Further, the outer peripheral portions of the stress relaxation intermediate layer 30, the cushion electrode layer 16, and the lead electrode layer 17 are removed.

応力緩和中間層３０は、線膨張係数がクッション用電極層１６よりも半導体基板１１に近い材料からなる。応力緩和中間層３０はクッション用電極層１６よりもエッチングレートが小さいことが望ましい。また、応力緩和中間層３０の材料としては、例えばＭｏが望ましい。さらに、少なくとも接触金属層１５の表面と応力緩和中間層３０との間にＴｉ層を介在させてもよく、これにより接触金属層１５と応力緩和中間層３０との間の密着性が向上する。また、窒化被膜１４と応力緩和中間層３０の間に、Ｔｉ層を介在させてもよく、これにより窒化被膜１４と応力緩和中間層３０との間の密着性を向上させることができる。 The stress relaxation intermediate layer 30 is made of a material having a linear expansion coefficient closer to the semiconductor substrate 11 than the cushion electrode layer 16. The stress relaxation intermediate layer 30 preferably has a lower etching rate than the cushion electrode layer 16. Moreover, as a material of the stress relaxation intermediate layer 30, for example, Mo is desirable. Furthermore, a Ti layer may be interposed at least between the surface of the contact metal layer 15 and the stress relaxation intermediate layer 30, thereby improving the adhesion between the contact metal layer 15 and the stress relaxation intermediate layer 30. Further, a Ti layer may be interposed between the nitride film 14 and the stress relaxation intermediate layer 30, whereby the adhesion between the nitride film 14 and the stress relaxation intermediate layer 30 can be improved.

次に、上記のような構成を有する本実施形態の半導体素子の製造方法について、図３〜５を用いて以下で説明する。 Next, a method for manufacturing the semiconductor element of the present embodiment having the above configuration will be described below with reference to FIGS.

まず、Ｎ型の半導体の表層にＰ型拡散層１２をリング状に設け、半導体基板１１を形成する（図３（ａ））。なお、図３では、上記Ｐ型拡散層１２のリングの片方の断面のみを示しており、実際には、断面で見た場合に紙面左方に同様のＰ型拡散層の断面が存在し、そして、図で示すＰ型拡散層１２と紙面左方に存在するＰ型拡散層との中間にリングの中心が存在することになる（以下、図４および５においても同様である）。次に、図３（ａ）に示すように、半導体基板１１全体に絶縁体被膜２０（パシベーション膜）として、二酸化珪素被膜１３および窒化被膜１４を形成する。絶縁体被膜２０としては半導体基板１１表面に形成された二酸化珪素被膜１３（ＳｉＯ_２）と、この二酸化珪素被膜１３に積層された窒化被膜１４（具体的にはＳｉ_３Ｎ_４）とからなる積層膜を採用する。 First, a P-type diffusion layer 12 is provided in a ring shape on the surface layer of an N-type semiconductor to form a semiconductor substrate 11 (FIG. 3A). Note that FIG. 3 shows only a cross section of one side of the ring of the P-type diffusion layer 12, and actually there is a similar cross-section of the P-type diffusion layer on the left side of the paper when viewed in cross section. Then, the center of the ring exists between the P-type diffusion layer 12 shown in the drawing and the P-type diffusion layer existing on the left side of the drawing (the same applies to FIGS. 4 and 5 below). Next, as shown in FIG. 3A, a silicon dioxide film 13 and a nitride film 14 are formed as an insulator film 20 (passivation film) on the entire semiconductor substrate 11. As the insulator film 20, a laminate composed of a silicon dioxide film 13 (SiO ₂ ) formed on the surface of the semiconductor substrate 11 and a nitride film 14 (specifically, Si ₃ N ₄ ) laminated on the silicon dioxide film 13. Adopt a membrane.

次に、二酸化珪素被膜１３および窒化被膜１４をパターニングする。図３（ｂ）に示すように、レジスト膜１４Ａを、リング状のＰ型拡散層１２の外縁を覆うように外側に形成し、まず窒化被膜１４をエッチング（ウェットエッチングまたはドライエッチング等）によりパターニングし（図３（ｃ））、続いて二酸化珪素被膜１３をエッチングによりパターニングする（図３（ｄ））、そして、レジスト膜１４Ａを除去する（図４（ａ））。これにより、Ｐ型拡散層１２の外縁とＮ型半導体との境界を覆うようにその表面に二酸化珪素被膜１３および窒化被膜１４からなる絶縁体被膜（パシベーション膜）が形成され、リング中央部分に絶縁体被膜の窓穴５０が形成される。この時、窒化被膜１４のエッチングレートが二酸化珪素被膜１３のエッチングレートに比べて小さいことに起因して、二酸化珪素被膜１３が窒化被膜１４より多くエッチングされ、これによって窒化被膜１４に二酸化珪素被膜１３よりも窓穴５０の中央部側に張り出された部分（以下、窒化被膜ひさし１４ａという）が形成される（図４（ａ）参照）。 Next, the silicon dioxide film 13 and the nitride film 14 are patterned. As shown in FIG. 3B, a resist film 14A is formed on the outside so as to cover the outer edge of the ring-shaped P-type diffusion layer 12, and the nitride film 14 is first patterned by etching (wet etching or dry etching). Then, the silicon dioxide film 13 is patterned by etching (FIG. 3D), and the resist film 14A is removed (FIG. 4A). As a result, an insulator film (passivation film) composed of the silicon dioxide film 13 and the nitride film 14 is formed on the surface so as to cover the boundary between the outer edge of the P-type diffusion layer 12 and the N-type semiconductor, and insulation is provided at the center of the ring. A body coating window hole 50 is formed. At this time, the silicon dioxide film 13 is etched more than the nitride film 14 because the etching rate of the nitride film 14 is smaller than the etching rate of the silicon dioxide film 13. As a result, a portion (hereinafter referred to as a nitride film eaves 14a) that protrudes toward the center of the window hole 50 is formed (see FIG. 4A).

次に、電位障壁（ショットキーバリア）を形成するために接触金属層１５、例えばモリブデン／パラジウム等を蒸着等の手段により絶縁体被膜の窓穴５０に露出させた半導体基板１１の表面に形成する（図４（ｂ））。そして、この接触金属層１５および絶縁体被膜２０（二酸化珪素被膜１３および窒化被膜１４）の表面を覆うように、クッション用電極層１６と引き出し電極層１７とからなる電極層よりもエッチングレートが小さく、かつ線膨張係数がクッション用電極層１６よりも半導体基板１１に近い、例えばＭｏ等の材料により応力緩和中間層３０を形成する。 Next, in order to form a potential barrier (Schottky barrier), a contact metal layer 15, such as molybdenum / palladium, is formed on the surface of the semiconductor substrate 11 exposed in the window hole 50 of the insulating film by means such as vapor deposition. (FIG. 4B). The etching rate is smaller than that of the electrode layer made up of the cushion electrode layer 16 and the lead electrode layer 17 so as to cover the surfaces of the contact metal layer 15 and the insulator coating 20 (silicon dioxide coating 13 and nitride coating 14). In addition, the stress relaxation intermediate layer 30 is formed of a material such as Mo whose linear expansion coefficient is closer to the semiconductor substrate 11 than the electrode layer 16 for cushion.

さらに、応力緩和中間層３０の表面を覆うようにクッション用（応力緩和用）電極層１６および半田等とのぬれの良い引出し電極層１７を形成する（図４（ｃ）参照）。この時、窒化被膜ひさし１４ａは不安定であり、その下には空間が空いているため、それが原因となって応力緩和中間層３０や引き出し電極層１７やクッション用電極層１６に段切れ６０が生じることがある（図４（ｃ））。但し、段切れ６０は、必ずしもリング状の形状の全周にわたって形成されるとは限らず、リング状の形状の少なくとも一部では段切れができずに電極層（クッション用電極層１６および引出し電極層１７）はつながっているものと考えられる。電極層（クッション用電極層１６および引出し電極層１７）を絶縁体被膜２０（二酸化珪素被膜１３および窒化被膜１４）の上に形成するのは、絶縁体被膜によって電極層のコーナ領域でのブレークダウン耐圧の低下を防止することができるからである（フィールドプレート効果）。 Further, the electrode layer 16 for cushioning (for stress relaxation) and the extraction electrode layer 17 having good wettability with solder or the like are formed so as to cover the surface of the stress relaxation intermediate layer 30 (see FIG. 4C). At this time, the nitride film eaves 14a is unstable, and a space is formed below the nitride film eaves 14a. As a result, the stress relief intermediate layer 30, the lead electrode layer 17 and the cushion electrode layer 16 are disconnected 60. May occur (FIG. 4C). However, the step break 60 is not necessarily formed over the entire circumference of the ring shape, and the electrode layer (the cushion electrode layer 16 and the extraction electrode) cannot be cut at least at a part of the ring shape. Layer 17) is considered connected. The electrode layers (cushion electrode layer 16 and extraction electrode layer 17) are formed on the insulator coating 20 (silicon dioxide coating 13 and nitride coating 14) because of the breakdown in the corner region of the electrode layer by the insulator coating. This is because the breakdown voltage can be prevented from decreasing (field plate effect).

次に、応力緩和中間層３０、クッション用電極層１６および引き出し電極層１７の外周部を除去する。図４（ｄ）に示すように、レジスト膜１８をリング状のＰ型拡散層１２の外縁よりも大きな範囲に形成し、引き出し電極層１７、クッション用電極層１６および応力緩和中間層３０をエッチング（ウェットエッチングまたはドライエッチング等）によりパターニングし（図５（ａ））、続いてレジスト膜１８を除去する（図５（ｂ））。これにより、応力緩和中間層３０、クッション用電極層１６および引き出し電極層１７の外周部が除去される。その後、ショットキーバリア電極側と反対側の半導体基板表面に引出し電極層を形成し、チップ化する。 Next, the outer peripheral portions of the stress relaxation intermediate layer 30, the cushion electrode layer 16, and the lead electrode layer 17 are removed. As shown in FIG. 4D, a resist film 18 is formed in a range larger than the outer edge of the ring-shaped P-type diffusion layer 12, and the lead electrode layer 17, the cushion electrode layer 16, and the stress relaxation intermediate layer 30 are etched. Patterning is performed by (wet etching or dry etching) (FIG. 5A), and then the resist film 18 is removed (FIG. 5B). Thereby, the outer peripheral portions of the stress relaxation intermediate layer 30, the cushion electrode layer 16, and the lead electrode layer 17 are removed. Thereafter, an extraction electrode layer is formed on the surface of the semiconductor substrate opposite to the Schottky barrier electrode side to form a chip.

本実施形態によれば、接触金属層１５および絶縁体被膜２０とクッション用電極層１６との間に応力緩和中間層３０が配置されることにより、半導体基板１１がクッション用電極層１６のエッジに起因する変形の影響を直接受けることがない。従って、製造時や検査時の熱による熱膨張係数の差に起因して、引出し電極層１７に応力がかかっても、てこの原理によって過大な力がかかるのは上記応力緩和中間層３０のみに限られ、半導体基板１１には何らの影響を及ぼすことがない。しかも応力緩和中間層３０の線膨張係数がクッション用電極層１６よりも半導体基板１１に近いため、半導体基板１１が応力緩和中間層３０のエッジから受ける変形の影響が小さくなる。従って、半導体基板１１にクラックが入ることを防止することができる。また、半導体基板に歪みが与えられることが防止されるため、逆方向電流の増加が防止される。 According to the present embodiment, the stress relaxation intermediate layer 30 is disposed between the contact metal layer 15 and the insulator coating 20 and the cushion electrode layer 16, so that the semiconductor substrate 11 is placed on the edge of the cushion electrode layer 16. It is not directly affected by the resulting deformation. Therefore, even if stress is applied to the extraction electrode layer 17 due to the difference in thermal expansion coefficient due to heat at the time of manufacturing or inspection, only the stress relaxation intermediate layer 30 is subjected to excessive force by the lever principle. However, the semiconductor substrate 11 is not affected. In addition, since the linear expansion coefficient of the stress relaxation intermediate layer 30 is closer to the semiconductor substrate 11 than the cushion electrode layer 16, the influence of the deformation that the semiconductor substrate 11 receives from the edge of the stress relaxation intermediate layer 30 is reduced. Therefore, it is possible to prevent the semiconductor substrate 11 from cracking. In addition, since the semiconductor substrate is prevented from being distorted, an increase in reverse current is prevented.

１半導体基板
２ａ第１の材料層
２ｂ第２の材料層
３ａ第１の金属層
３ｂ第２の金属層
４レジスト膜
５応力緩和中間層
１１半導体基板
１２Ｐ型拡散層
１３二酸化珪素被膜
１４窒化被膜
１４ａ窒化被膜ひさし
１４Ａレジスト膜
１５接触金属層
１６クッション用（応力緩和用）電極層
１７電極層
１８レジスト膜
２０絶縁体被膜
３０応力緩和中間層
５０窓穴
６０段切れ DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a 1st material layer 2b 2nd material layer 3a 1st metal layer 3b 2nd metal layer 4 Resist film 5 Stress relaxation intermediate | middle layer 11 Semiconductor substrate 12 P-type diffused layer 13 Silicon dioxide film 14 Nitride film 14a Nitride coating eaves 14A Resist film 15 Contact metal layer 16 Electrode layer for cushion (for stress relaxation) 17 Electrode layer 18 Resist film 20 Insulator coating 30 Stress relaxation intermediate layer 50 Window hole 60 Step break

Claims

A semiconductor substrate, a first material layer formed on the surface of the semiconductor substrate, and a second material formed on the surface of the first material layer and having an etching rate smaller than that of the first material layer A layer, a stress relaxation intermediate layer formed on the surface of the semiconductor substrate and on the surface of the second material layer, a first metal layer formed on the surface of the stress relaxation intermediate layer,
A second metal layer formed on the surface of the first metal layer and having a lower etching rate than the first metal layer,
The stress relaxation intermediate layer has a linear expansion coefficient closer to the semiconductor substrate than the first metal layer.

The semiconductor element according to claim 1, wherein the stress relaxation intermediate layer has an etching rate smaller than that of the first metal layer.

A semiconductor element used as a Schottky barrier diode,
A semiconductor substrate in which a second conductivity type diffusion layer is formed in a ring shape on a surface layer of a semiconductor of the first conductivity type, an outer periphery of the second conductivity type diffusion layer of the semiconductor substrate, and the semiconductor substrate An insulator coating formed in a ring shape covering the boundary, a contact metal layer laminated on the surface of the semiconductor substrate inside the insulator coating, and formed so as to cover the surface of the contact metal layer and the insulator coating A stress relieving electrode layer, and a lead electrode layer laminated on the stress relieving electrode layer and having a smaller etching rate than the stress relieving electrode layer,
The insulator film is a laminated film, and the plurality of films forming the insulator film are films having an etching rate of a film located on the side farther than the semiconductor substrate among films adjacent to each other on the semiconductor substrate side. Formed smaller than the etching rate,
And a stress relaxation intermediate layer having a linear expansion coefficient made of a material closer to the semiconductor substrate than the stress relaxation metal layer between the contact metal layer and the stress relaxation electrode layer. .

The difference in etching rate between the stress relaxation electrode layer and the extraction electrode layer is the difference in etching rate with respect to the surface treatment liquid, and the difference in etching rate between the plurality of films forming the insulator coating is a ring-like shape. The etching rate difference with respect to the etching solution when forming the shape, and further, the stress relaxation intermediate layer has a lower etching rate with respect to the surface treatment solution than the stress relaxation electrode layer. Semiconductor element.

Forming a first material layer on the semiconductor substrate, and forming a second material layer having a lower etching rate on the first material layer than on the first material layer; and
An etching step of etching the first and second material layers using a mask;
A stress relaxation intermediate layer forming step of forming a stress relaxation intermediate layer on the semiconductor substrate and on the second material layer;
A metal layer forming step of forming a first metal layer on the stress relaxation intermediate layer;
Forming a second metal layer having an etching rate smaller than that of the first metal layer on the surface of the first metal layer, and
The method of manufacturing a semiconductor device, wherein the stress relaxation intermediate layer has a linear expansion coefficient closer to the semiconductor substrate than the first metal layer.

6. The method of manufacturing a semiconductor element according to claim 5, wherein the stress relaxation intermediate layer has an etching rate smaller than that of the first metal layer.

A method of manufacturing a semiconductor device used as a Schottky barrier diode,
An insulator film forming step of forming an insulator film on the surface of a semiconductor substrate in which a second conductivity type diffusion layer is formed in a ring shape on the surface layer of the first conductivity type semiconductor; and the insulator film A window hole forming step of forming a window hole by etching in the insulator film formed in the forming step, a contact metal layer forming step of forming a contact metal layer on the surface of the semiconductor substrate exposed in the window hole, and An electrode in which an electrode layer for stress relaxation is formed on the surface of the contact metal layer and the insulator coating, and then an extraction electrode layer having an etching rate smaller than that of the electrode layer for stress relaxation is formed on the surface of the electrode layer for stress relaxation A layer forming step,
In the insulator coating forming step, a film located on a side farther than the semiconductor substrate among adjacent films is formed of a material having a smaller etching rate than a film located on the semiconductor substrate side,
Further, after the contact metal layer formation step and before the stress relaxation electrode layer formation step, a stress relaxation intermediate layer made of a material whose linear expansion coefficient is closer to the semiconductor substrate than the stress relaxation metal layer is formed on the contact metal. A stress relaxation intermediate layer forming step to be formed on the surface of the layer and the insulating coating,
In the stress relaxation electrode layer forming step, the stress relaxation electrode layer is formed on the surface of the stress relaxation intermediate layer.

The difference in etching rate between the stress relaxation electrode layer and the extraction electrode layer is the difference in etching rate with respect to the surface treatment liquid, and the difference in etching rate between the plurality of films forming the insulator coating is a ring-like shape. The etching rate difference with respect to the etching solution when forming the form, and further, the stress relaxation intermediate layer has a lower etching rate with respect to the surface treatment solution than the stress relaxation electrode layer. A method for manufacturing a semiconductor device.