JP2010278243A - Semiconductor protection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that there is a need for increasing the width W of resistance R and reducing a capacity of pn-junction at the lower part of a pad in the case of maintaining EMI filter characteristics of a semiconductor protection device to separate the pad in the semiconductor protection device with the resistance and a diode formed in the same n-type impurity region, but ESD resistance is deteriorated by reduction in the capacity of pn-junction at the lower part of the pad in this case. <P>SOLUTION: An n-type impurity region which becomes the resistance of a semiconductor protection device is separated from the n-type impurity region which becomes a diode, and the area of the n-type impurity region which becomes the resistance is made to be the minimum area that is required for EMI filter characteristics. Thereby, the total area of the n-type impurity region which becomes the diode can be secured to the maximum. Thereby, the pads can be separated from each other while improving the ESD resistance more than that of a conventional one. Moreover, an area of both ends of the n-type impurity region which becomes the resistance of the semiconductor protection device is increased more than the width of the resistance. The other n-type impurity region having an area equivalent to that of both ends of the n-type impurity region which is separated therefrom to be the resistance is provided to form the diode, so that improvement can be made in the ESD resistance. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor protection device having both a protection circuit for protecting an electronic device from electrostatic discharge and an EMI (electro magnetic interference) filter.

  When a memory card with built-in flash memory is installed in a mobile phone, for example, the radio waves generated in the signal line from the memory card slot to the integrated circuit element affect the radio frequency of the mobile phone communication frequency. It will deteriorate. When the memory card is set in the slot at the same time, there is a possibility that the integrated circuit element is destroyed by electrostatic discharge due to human contact.

  Therefore, a semiconductor protection device having a protection circuit for preventing the leakage of radio waves generated from the signal line and improving the interference with the radio waves at the communication frequency and the electronic equipment from electrostatic discharge is used. .

  4A and 4B are diagrams showing an example of a conventional semiconductor protection device 510, where FIG. 4A is a circuit diagram and FIG. 4B is a cross-sectional view. The semiconductor protection device 510 shown in FIG. 4A is obtained by connecting the low voltage side of two diodes D51 and D52, and connecting a resistor R in series between one end of the two diodes D51 and D52 on the high voltage side. . The input terminal Vi ′ of the semiconductor protection device 510 is connected to an input signal terminal, and the output terminal Vo ′ is connected to an integrated circuit element (not shown).

  This circuit is a low-pass filter (LPF) in which a pn junction capacitance of two diodes D51 and D52 is connected to a ladder and a resistor R is connected between them. By connecting between the input signal terminal and the integrated circuit element, unnecessary radio waves generated from the signal line are blocked by the LPF, so that the influence on the peripheral system can be extremely reduced. At the same time, since the two diodes D51 and D52 can release electrostatic discharge from the high voltage side to the low voltage side, the integrated circuit element can be protected from the electrostatic discharge applied from the input signal terminal.

  4B is a cross-sectional view illustrating an example of the structure of the semiconductor protective device 510 in FIG.

  In the semiconductor protection device 510, n-type layers 505 and 506 spaced apart from each other are provided on the surface of a p-type semiconductor substrate 507, and an insulating layer 504 is provided on the p-type semiconductor substrate 507. On the p-type semiconductor substrate between the n-type layers 505 and 506, a resistor R made of polysilicon 503 is provided via an insulating layer 504. Aluminum wirings 501 and 502 having one ends contacting n-type layers 505 and 506 are provided on insulating layer 504. The other ends of the aluminum wirings 501 and 502 are connected to both ends of the resistor R, respectively. The aluminum wiring on the n-type layers 505 and 506 becomes a pad portion to which the bonding wire is fixed. The n-type layers 505 and 506 in contact with the aluminum wirings 501 and 502 form the p-type semiconductor substrate 507 and the pn junction diodes D51 and D52, and the semiconductor protection device 510 is configured by the pn junction capacitance and the resistance R of the polysilicon 503. Is formed.

  FIG. 5 shows a semiconductor protection device 520 in which an n-type layer 524 is formed on the surface of a p-type semiconductor substrate 507 by a diffusion method, an ion implantation method, or the like. FIG. 5A is a cross-sectional view, and FIG. Is a plan view, and FIG. 5C is a plan view. FIG. 5A is a cross-sectional view taken along the line cc of FIG. However, in FIG. 5B, the external electrodes 521 and 522 and the insulating layer 504 over the semiconductor substrate 507 are omitted.

  At both ends of the n-type layer 524, external electrodes 521 and 522 serving as pad portions to which bonding wires are fixed are provided through openings in the insulating layer 504. In this configuration, diodes D51 and D52 are formed by the n-type layer 524 and the p-type semiconductor substrate 507, and the n-type layer 524 also functions as a resistor R. Therefore, the same semiconductor protection as the circuit configuration shown in FIG. A device 520 is realized.

Japanese Patent Publication No. 2005-167906

  In the semiconductor protection device 510 shown in FIG. 4, the resistor R is formed of polysilicon 503, and the n-type impurity regions of the diodes D51 and D52 are formed of diffusion regions. Since these are separate processes, there is a problem that the number of manufacturing processes increases.

  On the other hand, as shown in FIG. 5, the semiconductor protection device 520 in which the resistor R is formed in the impurity region (n-type layer) can share the diodes D51 and D52 and the resistor R in the impurity region, thereby avoiding an increase in the number of manufacturing steps.

  In FIG. 5A, external electrodes 521 and 522 are provided above both ends of the resistor R (n-type layer 524), and serve as a pad portion to which a bonding wire is fixed as described above. The n-type layer 524 has a large area so that the area of both ends overlaps with the pad portion (FIG. 5B), and functions as the diodes D51 and D52.

  When the semiconductor protection device 520 is flip-chip mounted, for example, a bump electrode or the like is provided on the pad portion and mounted on the mounting substrate. Further, the position of the bump electrode may be limited by the wiring of the mounting substrate. For example, the pad portions (external electrodes 521 and 522) are arranged most distant (for example, about 500 μm) in the chip.

  Accordingly, it is necessary to extend the length L of the n-type layer 524 whose both ends are connected to the pad portion to the length L ′ (see FIGS. 5A and 5C). The EMI filter characteristic (cut-off frequency fc) of the semiconductor protection device is determined by the resistance value of the resistor R and the pn junction capacitances of the diodes D51 and D52. That is, the pattern of the n-type layer 524 affects the filter characteristics.

  Specifically, when the resistor R is formed by an impurity region (n-type layer), the pn junction formed by this and the p-type semiconductor substrate 507 is also a capacitance component of the semiconductor protection device 520. Accordingly, when the pad portions are separated from each other, if the pattern of the n-type layer 524 is extended and the width W of the resistor R is increased to the width W ′ in order to maintain the resistance value of the resistor R, an increase in the pn junction area increases the EMI. There is a problem that the capacity of the entire filter increases. Therefore, in order to maintain the resistance value and total capacity of the resistor R required as filter characteristics and extend the resistor R, the width of the resistor R is widened, and the pn junction (diode D51) below the external electrode 521 and the external It is necessary to reduce the capacitance component of the pn junction (diode D52) below the electrode 522 (see FIG. 5C). However, since the capacitance component of the pn junctions (diodes D51 and D52) below the external electrodes 521 and 522 is reduced, there is a problem that the withstand capacity from electrostatic discharge (ESD) deteriorates.

  The present invention has been made in view of the above problems, and has a one-conductivity-type semiconductor substrate, a first reverse-conductivity-type impurity region provided on the one-conductivity-type semiconductor substrate, and the first reverse-conductivity-type impurity region apart from the one-conductivity-type impurity region. A second reverse conductivity type impurity region provided in the conductive type semiconductor layer, and the first reverse conductivity type impurity region and the first reverse conductivity type impurity region spaced apart from each other and provided in the one conductive type semiconductor layer. A third opposite conductivity type impurity region having a first end portion and a second end portion, and a resistance portion connecting the first end portion and the second end portion, and provided on the one conductivity type semiconductor layer An insulating film; a first opening provided in the insulating film and exposing a part of the first reverse conductivity type impurity region; and a second opening exposing a part of the second reverse conductivity type impurity region; , A third opening and a second opening in which a part of the first end and a part of the second end are respectively exposed. An opening, a first metal layer covering and contacting the first reverse conductivity type impurity region and the first end, and covering the second reverse conductivity type impurity region and the second end. This is solved by providing a second metal layer in contact with these.

  According to the embodiment of the present invention, the following numerous effects can be obtained.

  First, EMI filter characteristics and electrostatic breakdown resistance (ESD resistance) can be maintained as before. In the structure in which the resistor is formed by the n-type impurity region, the area (length × width) of the resistor that is not in contact with the metal layer hardly contributes to ESD protection, and the total area of the n-type impurity region in contact with the metal layer is Contributes to the improvement of ESD tolerance.

  Therefore, by separating the n-type impurity region serving as the resistance of the semiconductor protection device from the n-type impurity region serving as the diode, the area of the n-type impurity region serving as the resistor is set to the minimum area necessary for the EMI filter characteristics. Since the total area of the n-type impurity region serving as a diode can be ensured to the maximum, the pad portions can be separated while maintaining the ESD resistance as before. Furthermore, the ESD tolerance can be improved by optimizing the area of the n-type impurity region. Specifically, by making the areas of both ends of the n-type impurity region serving as a resistance equal to the area of the n-type impurity region serving as a diode, a portion that is weak in the ESD tolerance can be eliminated locally, so that the ESD tolerance can be improved.

  As described above, the pad portion can be arranged at a desired position without changing the resistance pattern (that is, maintaining the conventional filter characteristics). For example, in flip chip mounting, the pad portion is provided at the chip end portion. However, it is possible to prevent deterioration of the ESD tolerance.

  Second, since the resistor can be formed in the same process as the n-type impurity region of the diode, an increase in the number of manufacturing steps can be suppressed as compared with the case where the resistor is formed of polysilicon.

It is (A) top view, (B) top view, and (C) sectional view for explaining an embodiment of the present invention. It is a circuit diagram for demonstrating embodiment of this invention. It is (A) top view, (B) top view, and (C) sectional view for explaining an embodiment of the present invention. It is (A) circuit diagram and (B) sectional drawing for demonstrating a conventional structure. It is (A) sectional drawing, (B) top view, and (C) top view for demonstrating a conventional structure.

  The semiconductor protective device of the present invention will be described below with reference to FIGS. 1 and 3 are diagrams for explaining the semiconductor protection devices 100 and 150 of the present embodiment, respectively. FIG. 2 is a circuit diagram of the semiconductor protection devices 100 and 150 of this embodiment.

  Semiconductor protection devices 100 and 150 are semiconductor protection devices having a protection circuit that protects electronic equipment from electrostatic discharge and a low-pass filter (LPF) type EMI (Electro-magnetic interference) filter for preventing electromagnetic interference, for example. It is.

  The semiconductor protection devices 100 and 150 of the present embodiment include a one-conductivity type semiconductor substrate, a first reverse-conductivity type impurity region, a second reverse-conductivity type impurity region, a third reverse-conductivity type impurity region, an insulating film, It has a 1st metal layer and a 2nd metal layer.

  FIG. 1 is a diagram illustrating a semiconductor protection device 100 according to a first embodiment of the present embodiment, FIG. 1A is a plan view in which a metal layer is omitted, and FIG. 1B is a pattern of a metal layer. 1C is a cross-sectional view taken along the line aa of FIG. 1B. FIG. 2 is a circuit diagram of the semiconductor protection device of this embodiment.

The p-type semiconductor substrate 10 has an impurity concentration of, for example, about 8E18 cm ⁻³ , and a first n-type impurity region 11, a second n-type impurity region 12, and a third n-type impurity region 13 are provided on the surface thereof. Each of these impurity concentrations is, for example, about 8E19 cm ⁻³ , and the first n-type impurity region 11 and the second n-type impurity region 12 are provided on both outer sides of the third n-type impurity region 13 so as to be spaced apart from each other.

  An insulating film 30 is provided on the p-type semiconductor substrate 10, and a first opening OP1, a second opening OP2, a third opening OP3, and a fourth opening OP4 are provided in the insulating film 30 (FIG. 1 ( C)).

  Here, the first n-type impurity region 11 has a substantially circular shape with a diameter of about 70 μm, for example, and has a first contact portion 111 (broken line) exposed from the first opening OP1. That is, the first contact portion 111 is a region inside the first n-type impurity region 11, and is a substantially circular region having a diameter of about 68 μm, for example. Here, “substantially circular” refers to a circular shape or a polygonal corner portion chamfered into an arc shape or curved shape with a small curvature.

  The second n-type impurity region 12 is the same as the first n-type impurity region 11. That is, for example, the second contact portion 121 (broken line) having a substantially circular shape with a diameter of about 70 μm and a substantially circular shape (for example, with a diameter of about 68 μm) exposed from the second opening OP2.

  The third n-type impurity region 13 is provided in the p-type semiconductor substrate 10 apart from the first n-type impurity region 11 and the second n-type impurity region 12. The third n-type impurity region 13 includes a first end portion 134 and a second end portion 135, and a resistance portion 133 that connects the first end portion 134 and the second end portion 135. Each of the first end portion 134 and the second end portion 135 has a substantially circular shape with a diameter of, for example, about 15 μm, and a third contact portion 131 (broken line) with a substantially circular shape (for example, with a diameter of about 13 μm) exposed from the third opening OP3. And a fourth contact portion 132 (broken line) having a substantially circular shape (for example, a diameter of about 13 μm) exposed from the fourth opening OP4.

  The resistance portion 133 has a width W of, for example, 10 μm, a length L of, for example, about 100 μm, and a resistance value of, for example, about 100Ω. Further, the width W of the resistance portion 133 is smaller than the width (here, the diameter) of the first end portion 134 and the second end portion 135. The entire third n-type impurity region 13 functions as a resistance component of the semiconductor protection device 100. In the present embodiment, for convenience of explanation, the third n-type impurity region 13 is provided between the first end portion 134 and the second end portion 135. A region connecting the two is referred to as a resistance portion 133.

  The first metal layer 41 is, for example, aluminum (Al), and covers and contacts the first contact portion 111 and the third contact portion 131. The first metal layer 41 includes a first pad portion 41p and a first electrode portion 41e connected to the first pad portion 41p. The first pad portion 41 p overlaps with the first contact portion 111 and the first electrode portion 41 e overlaps with the third contact portion 131.

  The second metal layer 42 covers and contacts the second contact portion 121 and the fourth contact portion 132. The second metal layer 42 includes a second pad portion 42p and a second electrode portion 42e connected to the second pad portion 42p. The second pad portion 42p overlaps with this just above the second contact portion 121, and the second electrode portion 42e overlaps with this just above the fourth contact portion 132.

  The first electrode part 41e and the second electrode part 42e have smaller areas than the first pad part 41p and the second pad part 42p, respectively.

  The resistance portion 133 of the third impurity region 13 is covered with the insulating film 30, and the resistance portion 133 is not in direct contact with the first metal layer 41 or the second metal layer 42 (FIG. 1C).

  Diodes D1, D2, and D3 are formed by the first n-type impurity region 11, the second n-type impurity region 12, the third n-type impurity region 13, and the p-type semiconductor substrate 10, respectively. The pn junction capacitors C1, C2, and C3 and the resistance unit 133 constitute the semiconductor protection device 100 (FIG. 1C and FIG. 2).

  That is, as shown in FIG. 2, the semiconductor protection devices 100 and 150 are formed by connecting the low-voltage side of the diodes D1, D2, and D3, and connecting a resistor R in series between one ends of the diodes D1, D2, and D3 on the high-voltage side. is there. The input terminal Vi of the semiconductor protection device 100 is connected to an input signal terminal, and the output terminal Vo is connected to an integrated circuit element (not shown).

  Here, the total capacitance C includes the pn junction capacitance C1 of the first n-type impurity region 11 and the p-type semiconductor substrate 10, the pn junction capacitance C2 of the second n-type impurity region 12 and the p-type semiconductor substrate 10, and the third n-type impurity. This is the total of the pn junction capacitance C3 of the region 13 and the p-type semiconductor substrate 10.

  When the resistor part 133 of the semiconductor protection device is formed by the third n-type impurity region 13, the pn junction capacitance formed by this and the p-type semiconductor substrate 10 is also a capacitance component of the semiconductor protection device.

  In this embodiment, as described above, the first n-type impurity region 11 and the second n-type impurity region 12 that are located immediately below the first pad portion 41p and the second pad portion 42p and constitute the diode D1 and the diode D2 are replaced with the resistor portion. 133 and arranged separately.

  When the semiconductor protection device 100 is flip-chip mounted, bump electrodes are provided on the first pad portion 41p and the second pad portion 42p. Especially in the case of such flip chip mounting, the position of the bump electrode is limited by the wiring of the mounting substrate. For example, the first pad portion 41p and the second pad portion 42p are arranged most distant (for example, about 500 μm) in the chip.

  In such a case, the conventional structure employs a configuration in which the resistor R is extended and a metal layer is brought into contact with both ends of the resistor R and connected to the pad portion (see FIG. 5).

  However, in order to maintain the resistance value of the resistor R and the pn junction capacitance while extending the resistor R in order to connect to the separated pad portions, the width W of the resistor R is increased and the pn junction capacitance below the pad portion is reduced. There is a need to. In this case, there has been a problem that the ESD tolerance is deteriorated due to a decrease in the pn junction capacitance below the pad portion.

  Therefore, in the present embodiment, the n-type impurity region serving as the resistance of the semiconductor protection device 100 is separated from the n-type impurity regions serving as the diodes D1 and D2 immediately below the first pad portion 41p and the second pad portion 42p. .

  Specifically, the third n-type impurity region 13 is separated from the first n-type impurity region 11 and the second n-type impurity region 12, and is provided in the p-type semiconductor substrate 10 between them, whereby an n-type impurity serving as a resistance is provided. The area of the region can be set to the minimum area necessary for the EMI filter characteristics, and the total area of the n-type impurity regions that become the diodes D1 and D2 immediately below the first pad portion 41p and the second pad portion 42p is maximized. Since it can be ensured, the pad portions can be separated while improving the ESD resistance from FIG.

  3A and 3B are diagrams showing the semiconductor protection device 150 according to the second embodiment, in which FIG. 3A is a plan view in which the metal layer is omitted, and FIG. 3B is a plan view in which the pattern of the metal layer is also shown. FIG. 3C is a cross-sectional view taken along the line bb of FIG. Moreover, the same component as 1st Embodiment is shown with the same code | symbol.

  The semiconductor protection device 150 of the second embodiment is also located immediately below the first pad portion 51p and the second pad portion 52p, and the first n-type impurity region 21 and the second n-type impurity region 22 constituting the diode D1 and the diode D2. Are arranged separately from the resistance portion 233, but the pn junction area formed by the first n-type impurity region 21 and the p-type semiconductor substrate 10, and the first end portion 234 of the third n-type impurity region 23 and the p The pn junction area formed by the type semiconductor substrate 10 is equivalent.

  Actually, the first end portion 234 is continuous with the resistance portion 233, and a pn junction in the depth direction of the p-type semiconductor substrate 10 is not formed at a connection portion with the resistance portion 233 (FIG. 1C). ). However, the width W of the resistance portion 233 is about 10 μm, and the area (width 10 μm × depth 1.5 μm) is very small. Specifically, the pn junction area (including the bottom portion) when the first end portion 234 is formed in a substantially circular shape separated from the resistance portion 233 (when formed in the same area as the first n-type impurity region 21), The difference (area of the missing part) of the pn junction area (including the bottom part) when the junction part with the resistance part 233 is missing (C-shaped) is approximately 10 μm wide × 1.5 μm deep. In the present embodiment, the ratio of the area of the pn junction area (including the bottom part) to the missing part when formed in a substantially circular shape (when formed in the same area as the first n-type impurity region 21) is about 1/10 or less. Are equivalent areas.

  As an example, the first n-type impurity region 21 and the first end 234 are substantially circular with a diameter of about 50 μm, and the first opening OP1 and the third opening OP3 are substantially circular with a diameter of about 48 μm.

  Further, the first metal layer 51 covers and contacts the first contact portion 211 of the first n-type impurity region 21 and the third contact portion 231 of the first end portion 234. The areas of the first pad portion 51p and the first electrode portion 51e of the first metal layer 51 are equal.

  Thereby, the pn junction capacitance C1 formed by the first n-type impurity region 21 and the p-type semiconductor substrate 10 and the pn junction capacitance C31 formed by the first end 234 and the p-type semiconductor substrate 10 are made equal. (FIG. 3C).

  The ESD tolerance increases as the total capacity C increases. That is, in order to improve the ESD tolerance, the total capacity C may be increased. However, as described above, the total capacity C that maintains the predetermined filter characteristics is limited to a predetermined range. It cannot be made larger.

  Therefore, in the present embodiment, the n-type impurity region (the first n-type impurity region 21 and the first end portion 234) immediately below the metal layer (the first pad portion 51p and the first electrode portion 51e) that contributes to ESD tolerance is substantially circular. By setting the same area, it is possible to alleviate electric field concentration and uniformize the ESD tolerance in the chip, and this can also improve the ESD tolerance.

  This configuration is the same for the second n-type impurity region 22 and the second end portion 235. That is, the pn junction area formed by the second n-type impurity region 22 and the p-type semiconductor substrate 10 and the pn junction area formed by the second end 235 and the p-type semiconductor substrate 10 are equivalent. Specifically, the second n-type impurity region 22 and the second end 235 are substantially circular with a diameter of about 50 μm, and the second opening OP2 and the fourth opening OP4 are substantially circular with a diameter of about 48 μm.

  The second metal layer 52 covers and contacts the second contact portion 221 of the second n-type impurity region 22 and the fourth contact portion 232 of the second end portion 235. The areas of the second pad portion 52p and the second electrode portion 52e of the second metal layer 52 are equal.

  Thereby, the pn junction capacitance C2 formed by the second n-type impurity region 22 and the p-type semiconductor substrate 10 and the pn junction capacitance C32 formed by the second end portion 235 and the p-type semiconductor substrate 10 can be made equal. It is possible to make the ESD tolerance in the chip uniform.

  Here, although the pn junction areas of the first n-type impurity region 21 and the second n-type impurity region 22 are equal, they may be different pn junction areas.

  Since the configuration other than this is the same as that of the first embodiment, the description thereof is omitted.

  Furthermore, in this embodiment, the resistance portions 133 and 233 and the n-type impurity regions serving as the contact portions (diodes) have the same impurity concentration. Therefore, they can be formed in the same process and have a structure in which a resistor made of polysilicon is provided. In comparison, the number of manufacturing steps can be reduced.

10 p-type semiconductor substrate 11, 21 first n-type impurity region 12, 22 second n-type impurity region 13, 23 third n-type impurity region 30 insulating film 41, 51 first metal layer 41p, 51p first pad portion 41e, 51e first 1 electrode part 42,52 2nd metal layer 42p, 52p 2nd pad part 42e, 51p 2nd electrode part 100,150 Semiconductor protection device 111,211 1st contact part 121,221 2nd contact part 131,231 3rd contact Portion 132, 232 Fourth contact portion 133, 233 Resistance portion 501, 502 Aluminum wiring 503 Polysilicon 504 Insulating layer 505, 506 n-type layer 507 p-type semiconductor substrate 510, 520 Semiconductor protection device 521, 522 External electrode 524 n-type layer

Claims (6)

One conductivity type semiconductor substrate;
A first reverse conductivity type impurity region provided in the one conductivity type semiconductor substrate;
A second reverse conductivity type impurity region provided in the one conductivity type semiconductor layer apart from the first reverse conductivity type impurity region;
The first and second opposite conductivity type impurity regions and the second opposite conductivity type impurity region are spaced apart from each other, and are provided in the one conductivity type semiconductor layer between the first and second opposite conductivity type impurity regions. A third reverse conductivity type impurity region having a portion and a resistance portion connecting the second end portion;
An insulating film provided on the one conductivity type semiconductor substrate;
A first opening provided in the insulating film and exposing a part of the first reverse conductivity type impurity region; a second opening exposing a part of the second reverse conductivity type impurity region; A third opening and a fourth opening in which a part of the end and a part of the second end are respectively exposed;
A first metal layer covering and contacting the first opposite conductivity type impurity region and the first end;
A semiconductor protective device comprising: the second reverse conductivity type impurity region and the second metal layer covering and contacting the second end portion.   The semiconductor protection device according to claim 1, wherein a width of the resistance portion is smaller than a width of the first end portion and the second end portion.   3. The semiconductor protection device according to claim 2, wherein the first reverse conductivity type impurity region, the second reverse conductivity type impurity region, the first end portion, and the second end portion are substantially circular.   The pn junction area formed by the first opposite conductivity type impurity region and the one conductivity type semiconductor substrate is equal to the pn junction area formed by the first end portion and the one conductivity type semiconductor substrate. The semiconductor protection device according to claim 3.   The pn junction area formed by the second opposite conductivity type impurity region and the one conductivity type semiconductor substrate is equal to the pn junction area formed by the second end portion and the one conductivity type semiconductor substrate. The semiconductor protection device according to claim 4.   The semiconductor protection device according to claim 5, wherein the first end portion and the second end portion have the same area.

Images