JP2010278184A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which improves the quality of the semiconductor device and improves an yield by preventing a fault caused by the swelling of a film. <P>SOLUTION: A second inter-layer insulating film is formed in the upper part of a silicon substrate (step S100). First heat treatment is performed (step S110), and then, the substrate is cleaned (step S120). When a lower electrode adhesion film and a first conductive film are formed, the surface of the first conductive film is treated so as to remove impurities (step S170). Then, a first dielectric film is formed without exposing the first conductive film to the atmosphere (step S180). Besides, the surface of the first dielectric film is treated so as to remove impurities (step S200). Then, a second dielectric film is formed without exposing the first dielectric film to the atmosphere (step S210). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a dielectric capacitor.

  In recent years, with the development of digital technology, there is an increasing demand for processing or storing a large amount of data at high speed. For this reason, high integration and high performance are required for semiconductor devices used in electronic devices.

  With respect to semiconductor devices, for example, in order to realize high integration of DRAMs, a ferroelectric material or a high-intensity film can be used as a capacitive insulating film of a capacitive element constituting a DRAM, instead of a conventional silicon oxide or silicon nitride. Research and development has been conducted on technologies using dielectric constant materials. In addition, in order to realize a nonvolatile RAM that can perform a write operation and a read operation at a lower voltage and a higher speed, a technique using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been developed. Such a semiconductor device is called a ferroelectric memory (FeRAM).

  A ferroelectric memory stores information using the hysteresis characteristics of a ferroelectric, has features such as high-speed operation, low power consumption, and excellent write / read durability. Yes. A ferroelectric memory has a ferroelectric capacitor in which a ferroelectric film is arranged between a pair of electrodes. The ferroelectric capacitor generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed, so that information can be read out by detecting this spontaneous polarization.

  In order to improve the low-voltage operation and the degree of integration of a ferroelectric capacitor, it is necessary to reduce the capacitor area and reduce the dielectric inversion voltage of the ferroelectric capacitor by reducing the thickness of the dielectric film. Furthermore, it is necessary to make the residual polarization characteristics of the dielectric film uniform over the entire surface and to prevent cracks generated in the dielectric film. Further, when the dielectric film of the ferroelectric capacitor is thinned, the electric field applied to the dielectric film may be increased and a leak current may be generated, which needs to be prevented.

Here, an example of a conventional method for manufacturing a ferroelectric capacitor will be described below.
First, after an insulating film is formed over a semiconductor substrate, the insulating film is dehydrated by heat treatment. As this heat treatment, for example, the semiconductor substrate is heat-treated at a temperature of 200 ° C. to 300 ° C. or higher while flowing Ar gas. If moisture and the like are removed by this heat treatment, an increase in leakage current can be prevented.

  Next, brush scrubber cleaning is performed on the semiconductor substrate, and an adhesion layer and a lower electrode film are formed thereon. On the lower electrode film, after forming the first dielectric film, crystallization annealing is performed to reduce the voids present at the crystal grain boundaries in the dielectric film. As a result, a decrease in the effective film thickness of the first dielectric film is prevented, and an increase in leakage current is suppressed.

  Further, an amorphous second dielectric film is formed thereon at a low temperature (100 ° C. or lower). Then, a first upper electrode is formed on the second dielectric film, and after the crystallization process is performed on the first upper electrode, the second upper electrode film is formed, and then the back surface is cleaned and attached to the back surface of the substrate. The ferroelectric film is removed.

Cleaning with a brush scrubber after the heat treatment is performed in order to remove a film or the like attached to the substrate surface during the heat treatment. This is because the insulating film is thin in the periphery (bevel) of the semiconductor substrate, so that the film may be peeled off from the back surface of the semiconductor substrate and attached to the substrate surface when the semiconductor substrate is heat-treated. At this time, the cleaning is performed, for example, by dropping the cleaning liquid onto the center of the surface of the semiconductor substrate while moving the semiconductor substrate by vacuum suction on the back surface of the semiconductor substrate, and moving the cleaning liquid from the center of the semiconductor substrate to the outer periphery Clean the substrate surface with. Thereafter, rinsing is performed by spraying pure water onto the substrate surface. After cleaning the semiconductor substrate, heat is dehydrated by radiating heat to the surface of the rotating semiconductor substrate.

  In order to reduce protrusions (hillocks) generated on the film surface, a silicon nitride film is deposited on the surface layer, and then the semiconductor substrate is annealed at 450 ° C. and washed with a brush scrubber to mechanically remove hillocks. Things are also done.

JP-A-11-168174 JP-A-10-199854 Japanese Patent Laid-Open No. 04-214627 Japanese Patent Laid-Open No. 02-001927

  Here, the inventor of the present application conducted a defect inspection on the substrate surface after cleaning the back surface of the semiconductor substrate, and a defect was confirmed on the substrate surface. Accordingly, among the discovered defects, a cross-sectional TEM image was acquired for the defects whose surface was swollen, and the results shown in FIG. 8 were obtained. From this cross-sectional TEM image, the upper electrode 104 of the ferroelectric capacitor is deformed so as to swell with respect to the dielectric film 103, and a gap 110 is generated between the upper electrode 104 and the dielectric film 103. I understood.

  There are two possible causes for the generation of the air gap 110 at the interface between the upper electrode 104 and the dielectric film 103. The first cause is that a conductive film to be the upper electrode 104 is formed on the dielectric film 103 at a low temperature. In this case, when heat treatment is performed after the conductive film is formed, moisture adsorbed on the dielectric film 103 accumulates at the interface between the dielectric film 103 and the upper electrode 104 to generate a void 110. The size of the gap formed in this way is considered to be large and 1 μm or more.

  The second cause is that the dielectric film 103 is formed in a two-layer structure, and each dielectric film is formed at a low temperature. In this case, the second dielectric film and the upper electrode 104 are sequentially formed in a state where moisture and organic substances are adsorbed on the surface of the first dielectric film, which is the first dielectric film, and then heat treatment is performed. When this is done, moisture and organic matter adsorbed on the surface of the first dielectric film move to the surface of the second dielectric film and accumulate at the interface between the second dielectric film and the upper electrode 104, and the upper electrode 104. Inflate. The size of this defect is slightly small and is considered to be 0.5 μm to 2 μm.

Next, another defect observation result is shown in FIG. FIG. 9 is a cross-sectional TEM image of the defect. From the cross-sectional TEM image, it can be seen that swelling occurs at the interface between the lower electrode 102 and the dielectric film 103. There are two possible causes for this. The first cause is that the cleaning liquid, water, and organic matter remaining on the insulating film 101 under the lower electrode 102 and the semiconductor substrate are heated between the lower electrode 102 and the dielectric film 103 after the upper electrode 104 is formed. It accumulates at the interface and creates a gap 111.
The second cause is that the dielectric film 103 is formed on the surface of the lower electrode 102 in a state where organic substances and moisture in the atmosphere are adsorbed, and then the dielectric film 103 is annealed for crystallization, or the upper electrode By the heat treatment after forming 104, organic substances and moisture adsorbed on the lower electrode 102 move to the interface between the lower electrode 102 and the dielectric film 103, and a void 111 is generated at the interface.

  FIG. 10 shows a cross-sectional TEM image of another defect example. From the cross-sectional TEM image, it was found that voids 110 and 111 were generated at the interface between the dielectric film 103 and the lower electrode 104 and at the interface between the dielectric film 103 and the upper electrode 102, respectively.

Defects due to these swellings cause defects in the shape of the ferroelectric capacitor and defects such as pattern skipping, and cause a decrease in the yield of the semiconductor device.
The present invention has been made in view of such circumstances, and has as its main object to improve the quality and yield of semiconductor devices by preventing the occurrence of defects due to film swelling.

  According to one aspect of the present application, a step of forming an insulating film over a semiconductor substrate, a step of performing a first heat treatment on the semiconductor substrate after forming the insulating film, and after the first heat treatment Cleaning the semiconductor substrate; performing a second heat treatment on the insulating film after cleaning the semiconductor substrate; forming an adhesion film on the insulating film after the second heat treatment; Forming a first conductive film on the adhesion film as a lower electrode of a capacitor; forming a dielectric film on the first conductive film; and an upper portion of the capacitor on the dielectric film. Forming a second conductive film to be an electrode. A method for manufacturing a semiconductor device is provided.

  According to the present invention, since the first conductive film serving as the lower electrode is formed on the insulating film after performing the second heat treatment after cleaning the substrate, impurities in the insulating film and the surface of the insulating film are removed. In this state, the first conductive film can be formed. For this reason, even if heat treatment is performed in a later step, it is possible to prevent impurities from accumulating at the interface between the insulating film and the first conductive film and forming voids. As a result, the quality of the semiconductor device and the yield can be improved.

FIG. 1A is a cross-sectional view (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a sectional view (No. 2) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1C is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a cross-sectional view (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1E is a cross-sectional view (part 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1F is a cross-sectional view (part 6) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1G is a cross-sectional view (part 7) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1H is a sectional view (No. 8) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1I is a sectional view (No. 9) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1J is a cross-sectional view (part 10) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1K is a sectional view (No. 11) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the second embodiment of the present invention. FIG. 4 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the third embodiment of the present invention. FIG. 5 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. FIG. 6 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention. FIG. 7 is a flowchart showing a part of the manufacturing method of the semiconductor device according to the sixth embodiment of the present invention. FIG. 8 is a cross-sectional TEM image showing that a void is formed at the interface between the lower electrode and the dielectric film. FIG. 9 is a cross-sectional TEM image showing that a gap is formed at the interface between the dielectric film and the upper electrode. FIG. 10 is a cross-sectional TEM image showing that voids are formed at the interface between the lower electrode and the dielectric film and at the interface between the dielectric film and the upper electrode.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
1A to 1K are cross-sectional views of a manufacturing process of a semiconductor device according to the first embodiment of the present invention.
This semiconductor device is a planar-type FeRAM and is manufactured as follows.

First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.
First, an element isolation insulating film 2 is formed by thermally oxidizing the surface of an n-type or p-type silicon (semiconductor) substrate 1, and an active region of the transistor is defined by the element isolation insulating film 2. Such an element isolation structure is called LOCOS (Local Oxidation of Silicon). Note that STI (Shallow Trench Isolation) may be used for the element isolation region.

Next, a p-type impurity such as boron is introduced into the active region of the silicon substrate 1 to form the p-well 3, and then the surface of the active region is thermally oxidized to form a thermal oxide film of about 6 nm as the gate insulating film 5. Form a thickness of ˜7 nm.
Subsequently, an amorphous silicon film having a thickness of about 50 nm, a tungsten silicide film having a thickness of about 150 nm, and a silicon oxide film are sequentially formed on the entire upper surface of the silicon substrate 1. Note that a polycrystalline silicon film may be formed instead of the amorphous silicon film. Thereafter, these films are patterned using a photolithography technique and an etching technique to form gate electrodes 6A and 6B on the silicon substrate 1. Two gate insulating films 5 are formed in parallel with each other on the p-well 3, each of which constitutes a part of a word line.

  Further, ion implantation is performed using the gate electrodes 6A and 6B as a mask, phosphorus is introduced as an n-type impurity into the p-well 3 beside the gate electrodes 6A and 6B, and the first and second source / drain extensions 8A and 8B are introduced. Form. Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to leave the insulating electrodes 10 on the sides of the gate electrodes 6A and 6B. As the insulating film used for the insulating sidewall 10, for example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method is used.

Subsequently, an n-type impurity such as arsenic is ion-implanted again into the silicon substrate 1 while using the insulating sidewall 10 and the gate electrodes 6A and 6B as a mask, and the first p-well 3 on the side of the gate electrodes 6A and 6B is first implanted. Second source / drain regions 11A and 11B are formed.
Further, a refractory metal film such as a cobalt film is formed on the entire upper surface of the silicon substrate 1 by sputtering. Thereafter, the refractory metal film is heated and reacted with silicon, whereby the refractory metal silicide layers 12A and 12B such as a cobalt silicide layer are formed on the silicon substrate 1 in the first and second source / drain regions 11A and 11B. Then, the resistance of the source / drain regions 11A and 11B is reduced. Thereafter, the unreacted refractory metal film on the element isolation insulating film 2 and the like is removed by wet etching.

  Through the steps so far, in the active region of the silicon substrate 1, the MOS transistors T1 and T2 constituted by the gate insulating film 5, the gate electrodes 6A and 6B, the first and second source / drain regions 11A and 11B, and the like are provided. It is formed.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 1 by plasma CVD, and this is used as an antioxidant insulating film 13.
Further, a silicon oxide (SiO ₂ ) film is formed on the antioxidant insulating film 13 as a first interlayer insulating film 14 to a thickness of about 1000 nm by plasma CVD using TEOS (tetraethoxysilane) gas. Thereafter, the first interlayer insulating film 14 is polished by a CMP (Chemical Mechanical Polishing) method, and the upper surface thereof is flattened. By this polishing, the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 14 becomes about 785 nm.

  Further, the anti-oxidation insulating film 13 and the first interlayer insulating film 14 are patterned by photolithography technique and etching technique to form contact holes 15A and 15B. The depth of the contact holes 15A and 15B is set to reach the refractory metal silicide layers 12A and 12B of the source / drain regions 11A and 11B, respectively, and the diameter thereof is set to, for example, 0.25 μm.

  Then, conductive plugs 16A and 16B electrically connected to the source / drain regions 11A and 11B are formed using the contact holes 15A to 15C. Specifically, a titanium (Ti) film having a thickness of 30 nm and a titanium nitride (TiN) film having a thickness of 20 nm are sequentially formed on the inner surfaces of the contact holes 15A and 15B by sputtering or the like. An adhesion film (glue film) having a laminated structure is produced. Further, a tungsten (W) film is grown on the adhesion film by the CVD method. This film thickness is set to, for example, 300 nm on the first interlayer insulating film 14, and the voids of the contact holes 15A to 15C are filled with the W film. The excess W film and the adhesion film grown on the upper surface of the first interlayer insulating film 14 are removed by the CMP method. Thereby, conductive plugs 16A and 16B are formed in the contact holes 15A to 15C, respectively.

Here, FIG. 2 shows a main part of the steps that are carried out until the film constituting the ferroelectric capacitor is formed thereafter. That is, a second interlayer insulating film is first formed (step S100), and a first heat treatment is performed on the second interlayer insulating film (step S110). Thereafter, the semiconductor substrate 1 is cleaned (step S120), and a second heat treatment is performed on the second interlayer insulating film (step S130). Next, a lower electrode adhesion film is formed (step S140), and a heat treatment of the lower electrode adhesion film is performed (step S150).

Further, a first conductive film is formed (step S160), and the surface treatment of the first conductive film (step S170) and the formation of the first dielectric film (step S180) are performed as a continuous process. Here, the continuous processing refers to performing processing without exposing the silicon substrate 1 to the atmosphere.
Thereafter, the first dielectric film is crystallized (step S190), and then the surface treatment of the first dielectric film (step S200) and the formation of the second dielectric film (step S210) are performed as a continuous process. Then, after forming a second conductive film (step S220) and performing crystallization annealing (step S220), a third conductive film is formed (step S230).

Next, details of each step of FIG. 2 will be described.
First, details of the processing from step S100 to step S130 will be described with reference to FIG. 1B. 1B to 1K, a part of the transistor T1 shown in FIG. 1A is omitted.

First, a second interlayer insulating film is formed on the entire surface of the first interlayer insulating film 14 (step S100). The second interlayer insulating film 19 is formed in order to prevent the conductive plugs 16A and 16B from being oxidized when annealing is performed in an oxygen atmosphere in the process of forming the ferroelectric capacitor. In this embodiment, as the second interlayer insulating film 19, a 100 nm thick SiON film and a 100 nm thick SiO ₂ film using plasma TEOS gas are formed.

Thereafter, a first heat treatment is performed to remove moisture and hydrogen in the interlayer insulating film (step S110). As conditions for the first heat treatment, for example, the substrate temperature is set to 600 ° C. or higher, for example, 650 ° C. in a nitrogen atmosphere, and the heat treatment time is set to 10 minutes. The first heat treatment may be an inert atmosphere using Ar gas or the like.
Here, since the film thickness of the second interlayer insulating film 19 is thin at the peripheral portion of the silicon substrate 1, the Ti film or TiN film formed thereunder is peeled off and adheres to the second interlayer insulating film 19. There is. For this reason, after annealing, the silicon substrate 1 is cleaned using, for example, a brush scrubber (step S120). In this cleaning, for example, the substrate surface is jet-cleaned, the substrate back surface is brush-cleaned, and the spinner that holds the silicon substrate 1 is rotated to remove the cleaning liquid and water attached to the substrate surface and back surface.

However, it is difficult to completely remove the cleaning liquid and water from the surface of the silicon substrate 1. Therefore, the second heat treatment is performed (step S130). Specifically, the silicon substrate 1 is introduced into a rapid thermal processing (RTA) apparatus, and thermal processing is performed in an oxygen-containing atmosphere at a temperature of 600 ° C. or higher, for example, 650 ° C. for 60 seconds. Here, examples of the atmosphere containing oxygen include a mixed atmosphere of Ar = 2Slm and O ₂ = 100 Sccm, or an atmosphere of O ₂ = 2Slm. By this second heat treatment, the cleaning liquid and water remaining on the surface of the silicon substrate 1 are removed.

Next, details of the processing from step S140 to step S160 will be described with reference to FIG. 1C.
First, an alumina (Al ₂ O ₃ ) film is formed as a lower electrode adhesion film 23 on the second interlayer insulating film 19 to a thickness of about 20 nm by sputtering (step S140). The lower electrode adhesion film 23 is formed in order to improve adhesion between a lower electrode described later and the second interlayer insulating film 19. The lower electrode adhesion film 23 is formed at a temperature lower than the second heat treatment, such as room temperature. For this reason, when the lower electrode adhesion film 23 is formed, impurities adsorbed on the lower layer cannot be removed. However, since the impurities are removed by performing the second heat treatment in the process of step S130, the lower electrode adhesion film 23 is not formed with the impurities remaining on the surface of the second interlayer insulating film 19, and FIG. Thus, the swelling phenomenon at the interface between the lower electrode and the dielectric is less likely to occur. In order to prevent impurities from adsorbing to the second interlayer insulating film 19 after the second heat treatment, the lower electrode adhesion film 23 is formed without exposing the silicon substrate 1 to the atmosphere after the second heat treatment.

Thereafter, in order to improve the surface of the alumina film as the lower electrode adhesion film 23 and to improve the film density, the alumina film is oxidized by performing a rapid heat treatment in an oxygen atmosphere at 600 ° C. or higher, for example, 650 ° C. for 60 seconds. (Step S150).
Further, a platinum film is formed as a first conductive film 25 on the lower electrode adhesion film 23 to a thickness of about 150 nm by sputtering (step S160). Instead of the platinum film, the first conductive film 25 is one film selected from the group consisting of an iridium film, a ruthenium film, an osmium film, a rhodium film, a palladium film, and an oxide thereof, such as ruthenium oxide ( A single layer film of RuO ₂ ) film and SrRuO ₃ film, or a laminated film of these films may be used. Since the lower electrode adhesion film 23 is formed before the first conductive film 25 is formed, high adhesion to the second interlayer insulating film 19 can be obtained.

Next, details of the processing from step S170 to step S190 will be described with reference to FIG. 1D.
First, surface treatment is performed on the first conductive film 25 to remove impurities on the surface of the first conductive film 25 (step S170). Specifically, the silicon substrate 1 is introduced into a chamber for surface treatment, and the substrate temperature is 100 ° C. to 300 ° C., for example 150, in a reduced pressure atmosphere (for example, about 5.0 × 10 ⁻⁶ Pa) of 100 Pa or less. A non-plasma heat treatment is performed at 120 ° C. for 120 seconds.

Thereafter, the silicon substrate 1 is introduced into another chamber so as not to be exposed to the atmosphere, and an amorphous first dielectric film 27 is formed at 100 ° C. or lower (step S180). Specifically, PZT (Pb (Zrx, Ti1-x) O ₃ (0 ≦ 0) is formed on the first conductive film 25 as the first dielectric film 27 by RF (Radio Frequency) sputtering using a PZT target. x ≦ 1)) A film is formed to a thickness of about 90 nm to 130 nm (for example, 130 nm).

Here, the surface treatment of the first conductive film 25 and the formation of the first dielectric film 27 are performed as a continuous treatment without being exposed to the atmosphere.
The heat treatment before the formation of the first dielectric film 27 is preferably performed in a reduced pressure atmosphere of 100 Pa. When the pressure of the reduced pressure is 100 Pa or more, impurities are likely to remain in the heat treatment chamber, and the impurities on the surface of the first conductive film 25 cannot be efficiently removed.

  Further, the substrate temperature at the time of forming the first dielectric film 27 is set to 0 ° C. to 100 ° C., for example, 50 ° C., which is lower than the heating temperature at the surface treatment in step S170. When the deposition temperature of the first dielectric film 27 is 100 ° C. or higher, the (101) plane orientation and (100) plane orientation of the PZT film are increased and the (111) plane orientation is weakened. The characteristics deteriorate. If the film formation temperature of the first dielectric film 27 is too low, it is difficult to control the substrate temperature during film formation, which is disadvantageous for mass production.

  Since it is preferable to set the substrate temperature at the time of forming the first dielectric film 27 to 100 ° C. or less, it is difficult to remove impurities such as moisture and organic substances adsorbed on the surface of the first conductive film 25 by sublimation. For this reason, the first dielectric film 27 is formed in an RF sputtering chamber for PZT after heat treatment is performed in another chamber to remove impurities on the silicon substrate 1. As a result, no impurities remain at the interface between the first dielectric film 27 and the first conductive film 25, and the swelling phenomenon at the interface between the lower electrode and the dielectric as shown in FIG. 9 is less likely to occur.

The first dielectric film 27 is not limited to PZT. The first dielectric film 27 may be made of a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT. Further, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), and Bi layered compounds such as SrBi ₄ Ti ₄ O ₁₅ The first dielectric film 27 may be configured.
Further, the film formation method of the first dielectric film 27 is not limited to the sputtering method. The first dielectric film 27 may be formed by a sol-gel method or a MOCVD (Metal Organic CVD) method.

Here, it is known that the crystallinity of the ferroelectric film depends on the crystallization method of the ferroelectric film, but also strongly depends on the crystallinity and surface state of the first conductive film 25 below the ferroelectric film. To do.
Since the crystal of the first dielectric film 27 which is a ferroelectric film grows from between the crystal grains of the first conductive film 25, the uniformity of the crystallinity of the first conductive film 25 is determined by the ferroelectric material. It affects the crystallinity of the film. Further, if the composition of the first dielectric film 27 is shifted at the interface between the first conductive film 25 and the first dielectric film 27, the crystallinity of the first dielectric film 27 is also deteriorated. When a compound such as a strontium ruthenium oxide film (SRO), a lanthanum strontium cobalt oxide (LSCO), or a lanthanum nickel oxide (LNO) having a perovskite structure is formed on the surface of the first conductive film 25, a ferroelectric thereon The film grows with the same crystal as the underlayer.

In general, when a ferroelectric film is formed by sputtering or a sol-gel method, a Pt film is used as a base film. When a ferroelectric film is formed by the MOCVD method, an Ir film is used for the underlayer.
Further, when the first conductive film 25 is formed of an oxide, the ferroelectric film is formed while the oxide is reduced to a noble metal when the ferroelectric film is formed thereon. For example, when an IrO _x film is used as the first conductive film 25, the IrO _x is reduced to Ir immediately before the ferroelectric film is formed, and the PZT film grows on the Ir crystal grains. When an oxide is used for the first conductive film 25, it is possible to reduce oxygen deficiency at the ferroelectric-electrode interface of the ferroelectric capacitor and improve fatigue characteristics.

The first dielectric film 27 thus formed by sputtering is not crystallized immediately after the film formation and is in an amorphous state. For this reason, the dielectric characteristics of the first dielectric film 27 are not good at this stage. Therefore, in order to crystallize the first dielectric film 27, crystallization annealing is performed on the first dielectric film 27 (step S190). The crystallization annealing is performed by RTA (Rapid Thermal Anneal) in an oxygen-containing atmosphere, for example, an atmosphere composed of O ₂ and Ar adjusted so that the oxygen concentration is 2.0%, the substrate temperature is 610 ° C., and the processing is performed. The time is 90 seconds. Thereby, the first dielectric film 27 is crystallized, and a large number of PZT crystal grains are formed.

  When the first dielectric film 27 is formed by the MOCVD method, the first dielectric film 27 is crystallized at the time of film formation, so that crystallization annealing is not necessary.

  Next, details of the processing from step S200 to step S240 will be described with reference to FIG. 1E.

  By the way, if crystallization annealing is performed after the first dielectric film 27 is formed, the silicon substrate 1 is once exposed to the atmosphere. However, when the silicon substrate 1 is exposed to the atmosphere, impurities such as organic substances in the atmosphere are adsorbed on the first dielectric film 27 and the first dielectric film 27 and the second dielectric film 28 to be formed next Impurities may accumulate at the interface.

Therefore, as the surface treatment of the first dielectric film 200, the first dielectric film 27 is heat-treated in a non-plasma atmosphere to remove impurities on the film surface (step S200). Specifically, the heat treatment is performed for 60 seconds at a substrate temperature of 100 ° C. to 300 ° C., for example 150 ° C., in a reduced pressure atmosphere having a pressure of 100 Pa or less, for example, about 5.0 × 10 ⁻⁶ Pa.

The pressure during the heat treatment may be atmospheric pressure, but it is easier to remove impurities such as organic substances adhering to the first dielectric film 27 when the heat treatment is performed under reduced pressure.
Further, when the substrate temperature during the heat treatment is set to be equal to or higher than the crystallization temperature of PZT, when the dielectric film is formed at a low temperature in the next process, the waiting time until the substrate temperature is lowered can be shortened, so that the production efficiency is improved. Therefore, the substrate temperature when the first dielectric film 27 is heat-treated is desirably 350 ° C. or lower.

Furthermore, the atmosphere during the heat treatment is not particularly limited. However, if a reducing substance such as hydrogen is present in the atmosphere, the first dielectric film 27 is reduced by these substances and the dielectric characteristics are deteriorated. Therefore, heat treatment is performed in an atmosphere from which hydrogen is excluded. Is preferred. As such an atmosphere, for example, there is any atmosphere of Ar, N ₂ , and O ₂ . If annealing is performed in an O ₂ atmosphere, there is an advantage that oxygen vacancies in the first dielectric film 27 are compensated.
Note that the heat treatment method is not particularly limited. For example, heat treatment may be performed using a stage of a heating chamber or a sputtering chamber, or annealing may be performed using an RTA chamber or a furnace.

After performing the heat treatment, the silicon substrate 1 is transferred to a chamber where the second dielectric film 28 is formed so that the silicon substrate 1 is not exposed to the atmosphere, and an amorphous PZT film is thickened by RF sputtering as the second dielectric film 28. The film is formed to a thickness of 10 nm to 30 nm (step S210). Examples of film forming conditions include a substrate temperature of 100 ° C. to 350 ° C., for example, 150 ° C. in a reduced pressure atmosphere having a pressure of about 5.0 × 10 ⁻⁶ Pa, and 60 seconds.

The substrate temperature at the time of forming the second dielectric film 28 is desirably 0 ° C. to 100 ° C., which is lower than the heating temperature at the time of the surface treatment in step S200, for example, 50 ° C. The second dielectric film 28 is not limited to a PZT film, and may be a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT. _{Furthermore, (Bi 1-x R x} ) Ti 3 O 12 (R is 0 in the rare earth element _{<x <1), SrBi 2} Ta 2 O 9 (SBT), and in SrBi ₄ Ti ₄ O Bi layered compound such as ₁₅ The first dielectric film 28 may be configured. The first dielectric film 28 may be formed of a crystal having an ABO ₃ type perovskite structure. In this case, one or more elements selected from Sr, Ca, Ba, Na, K, Nb, Ta, W, Ir, Ru, and rare earth elements are added to the A site or B site of the crystal. The second dielectric film 28 is preferably formed of the same material as the first dielectric film 27.

  As described above, the second dielectric film 28 is formed at a low temperature such as room temperature. For this reason, when the second dielectric film 28 is formed, impurities adsorbed on the first dielectric film 27 cannot be removed. However, since the impurities are removed by performing the heat treatment in the previous process (step S200), the second dielectric film 28 is formed with the impurities remaining on the surface of the first dielectric film 27. And the swelling phenomenon at the interface between the dielectric and the upper electrode as shown in FIG. 8 is difficult to occur.

Next, an iridium oxide (IrO _x ) film is formed as a second conductive film 29 on the second dielectric film 28 to a thickness of about 50 nm by sputtering (step S220).

This method is used when the second dielectric film 28 and the second conductive film 29 cannot be continuously formed. There are two other methods for forming the second conductive film 29, but these methods may not be employed in this embodiment.
The first method is a method of forming the second conductive film 29 at a low temperature of 100 ° C. or lower. In this case, the second dielectric film 28 and the second conductive film 29 are continuously formed. That is, after the second dielectric film 28 is formed, the second dielectric film 28 is directly transferred to a chamber where the second conductive film 29 is formed so as not to be exposed to the atmosphere, and the second conductive film 29 is formed.
The second method is a method of forming the second conductive film 29 at a high temperature of 100 ° C. or higher. In this case, impurities can be removed when the second conductive film 29 is formed. Therefore, after forming the second dielectric film 28, the silicon substrate 1 may be exposed to the atmosphere once, or the second conductive film 29 may be formed without exposing the silicon substrate 1 to the atmosphere.

  By the way, the step of forming the second conductive film 29 includes the step of forming the first conductive noble metal oxide film and the step of flattening the interface between the first conductive noble metal film and the second dielectric film 28 by rapid heat treatment. And forming a second conductive noble metal oxide film having an oxidation degree higher than that of the first conductive noble metal film on the first conductive noble metal film. Examples of the first conductive noble metal film and the second conductive noble metal oxide film in this case include an iridium oxide film.

  In addition, before the step of forming the first conductive noble metal oxide film, a heat treatment at 100 ° C. or more and 300 ° C. or less is performed in a vacuum of 100 Pa or less, and the atmosphere is adsorbed on the surface of the second dielectric film 28. The step of removing impurities and the first conductive noble metal oxide film may be formed so as not to expose the silicon substrate 1 to the atmosphere. In this case, the deposition temperature of the first conductive noble metal oxide film is preferably 0 ° C. to 100 ° C.

Here, the first conductive noble metal oxide film is preferably formed as an amorphous film, but the first conductive noble metal oxide film may be formed as a crystal film. The film forming temperature of the first conductive noble metal oxide film in the case of the crystal film is preferably 150 ° C. to 350 ° C.
In this case, the thickness of the second dielectric film 28 is preferably 40% or less of the thickness of the first dielectric film 27.

  After forming the second conductive film 29, crystallization annealing is performed on the second dielectric film 28 in an oxygen-containing atmosphere (step S230). Thereby, the amorphous second dielectric film 28 is crystallized, and the crystallinity of the first dielectric film 27 under the second dielectric film 28 is further enhanced. In this embodiment, since atmospheric impurities absorbed in the first and second dielectric films 27 and 28 are previously removed by heat treatment, the second dielectric film 28 and the second conductive film 29 are removed by the impurities. It is possible to prevent the adhesion of the resin from being lowered.

  The crystallization annealing may be performed before the second conductive film 29 is formed. In this case, for example, the substrate temperature is set to 550 ° C. or higher, and rapid heat treatment is performed in an atmosphere containing oxygen.

The conditions for the crystallization annealing are not particularly limited, but in this embodiment, the substrate temperature is 710 ° C. and the processing time is 120 seconds. Further, as the oxygen-containing atmosphere in which the crystallization annealing is performed, a mixed atmosphere of O ₂ gas and Ar gas whose oxygen concentration is adjusted to 1% was used.

  In this way, by crystallization of the second dielectric film 28 in a state where the second conductive film 29 is formed, iridium oxide constituting the second conductive film 29 becomes crystal grains of the second dielectric film 28. It is possible to prevent entry into the field, and it is possible to suppress the formation of a leak path in the second dielectric film 28 due to iridium oxide.

  Also, by this crystallization annealing, oxygen is supplied to the second dielectric film 28 through the second conductive film 28, and oxygen vacancies in the second dielectric film 28 are compensated. In order to obtain such an effect, the thickness of the second conductive film 29 is preferably thin so that oxygen can easily pass through, for example, 10 nm to 100 nm. However, if the thin second conductive film 29 is formed on the second dielectric film 28 in this manner, damage in the subsequent etching process or the like cannot be absorbed by the second conductive film 28 alone. The two dielectric films 27 and 28 may be deteriorated.

Therefore, in the next step, the third conductive film 30 is formed on the second conductive film 29 as a conductive protective film for protecting the first and second dielectric films 27 and 28 (step S240). . The third conductive film 30 is, for example, an iridium oxide film, and is formed to a thickness of about 200 nm by sputtering.

Since the formation of the film constituting the ferroelectric capacitor has been completed by the steps so far, each film is patterned into a desired shape in the subsequent steps.
First, processing until obtaining the cross-sectional structure shown in FIG. 1F will be described.

After cleaning the back surface of the silicon substrate 1, a hydrogen barrier film 31 that suppresses permeation of the reducing substance is formed on the third conductive film 30. The hydrogen barrier film 31 is made of, for example, a TiN film, and is formed to a thickness of 34 nm by sputtering using a Ti target. The substrate temperature at that time is 200 ° C., and the atmosphere is a mixed gas atmosphere of Ar = 50 Sccm and N ₂ = 90 Sccm. The hydrogen barrier film 31 can also be used as a hard mask when the second conductive film 29 is etched to form the upper electrode. The hydrogen barrier film 31 is not limited to a TiN film. TaN, TiON, TiO _x , TaO _x , TaON, TiAlO _x , TaAlO _x , TiAlON, TaAlON, TiSiON, TaSiON, TiSiO _x , TaSiO _x , AlO _x , ZrO _x You can choose from materials such as

  Further, a resist film is applied to the surface of the hydrogen barrier film 31, and further a mask 32 for patterning the hydrogen barrier film 31 and the second and third conductive films 29 and 30 is formed by exposure and development.

Next, processing until obtaining the cross-sectional structure shown in FIG. 1G will be described.
Using the mask 32, the hydrogen barrier film 31 and the second and third conductive films 29 and 30 are processed by dry etching to form the upper electrode 35. As described above, since the hydrogen barrier film 31 can be used as a hard mask, the second and third conductive films 29 and 30 can be etched cleanly. Thereafter, the resist is removed by ashing or the like. Further, the hydrogen barrier film 31 used as the hard mask is removed by dry etching.

  Thereafter, the silicon substrate 1 is heat-treated in an atmosphere containing oxygen. The temperature of the heat treatment is 600 ° C to 700 ° C. In this embodiment, heat treatment is performed at 650 ° C. for 40 minutes. This heat treatment recovers the damage received by the first and second dielectric films 27 and 28 in the steps so far, and such annealing is also called recovery annealing.

Next, steps required until a sectional structure shown in FIG.
First, a photoresist film is formed on the second dielectric film 28, the second and third conductive films 29 and 30, and the hydrogen barrier film 31, for example, by spin coating. Further, the photoresist film is patterned into a planar shape of the dielectric film by exposure, development, or the like. Subsequently, the first and second dielectric films 27 and 28 are etched using the patterned photoresist film as a mask to form a dielectric film 36. When the patterning is completed, the photoresist film is removed by ashing or the like.

  Thereafter, the silicon substrate 1 is heat-treated in an oxygen atmosphere, for example, at 300 ° C. to 400 ° C. for 30 minutes to 120 minutes.

  Furthermore, the first protective film 41 is formed by, for example, sputtering or CVD. As the first protective film 41, for example, an aluminum oxide film having a thickness of 20 nm to 50 nm is used. Next, the silicon substrate 1 is heat-treated in an oxygen atmosphere, for example, at 400 ° C. to 600 ° C. for 30 minutes to 120 minutes.

Next, steps required until a sectional structure shown in FIG.
Thereafter, a photoresist film is formed on the entire surface of the silicon substrate 1 by, eg, spin coating, and the photoresist film is patterned into a planar shape of the lower electrode of the dielectric capacitor by exposure, development, or the like. Subsequently, the lower electrode 37 is formed by etching the first protective film 41 and the first conductive film 25. As a result, a dielectric capacitor 38 including the patterned upper electrode 35, dielectric film 36, and lower electrode film 37 is formed.

  The first protective film 41 remains so as to cover the upper electrode 35 and the dielectric film 36. Thereafter, the photoresist film is removed. Next, the silicon substrate 1 is heat-treated in an oxygen atmosphere, for example, at 300 ° C. to 400 ° C. for 30 minutes to 120 minutes.

Further, the second protective film 42 is formed on the entire surface of the silicon substrate 1 by, for example, sputtering or CVD. In this embodiment, an aluminum oxide film having a thickness of 20 nm is formed as the second protective film 42. The aluminum oxide film constituting the second protective film 42 is excellent in the function of preventing a reducing substance such as hydrogen and moisture from permeating. This prevents the ferroelectric characteristics of the dielectric film 36 from being deteriorated by the reducing substance.
After the second protective film 42 is formed, heat treatment is performed in an oxygen atmosphere, for example, at 500 ° C. to 700 ° C. for 30 minutes to 120 minutes. As a result, oxygen is supplied to the dielectric film 36, and the electrical characteristics of the dielectric capacitor 38 are restored.

Next, steps required until a sectional structure shown in FIG.
On the entire surface of the second protective film 42, silicon oxide is formed as a third interlayer insulating film 43 with a film thickness of 1400 nm by, for example, plasma CVD. When a silicon oxide film is formed as the third interlayer insulating film 43, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas. Thereafter, the surface of the third interlayer insulating film 43 is planarized by, eg, CMP.

Then, in a plasma atmosphere generated by using N _{2 O} gas or N ₂ gas, 2 minutes silicon substrate 1, for example at 350 ° C., a heat treatment. As a result of the heat treatment, moisture in the third interlayer insulating film 43 is removed, and the film quality of the third interlayer insulating film 43 changes, making it difficult for moisture to enter the film. Further, by this heat treatment, the surface of the third interlayer insulating film 43 is nitrided, and a SiON film is formed on the surface of the third interlayer insulating film 43.

Furthermore, a third protective film 44 is formed as a barrier film on the entire surface of the third interlayer insulating film 43 by, for example, sputtering or CVD. As the third protective film 44, for example, an Al ₂ O ₃ film having a film thickness of 20 nm to 50 nm is used. Since the third protective film 44 is formed on the planarized third interlayer insulating film 43, the surface of the third protective film 44 becomes flat.

Subsequently, a photoresist film (not shown) is formed on the upper surface of the third protective film 44, etching is performed using the photoresist film as a mask, and the ferroelectric film passes through the third protective film 44 and the third interlayer insulating film 43. A first via hole 51 reaching the upper electrode 28 of the capacitor 31 is formed.
Similarly, etching is performed using a photoresist film formed on the third protective film 44 to form a second via hole 52 that reaches the lower electrode 29 of the ferroelectric capacitor 31.

  Next, for example, heat treatment is performed for 30 minutes to 120 minutes in an oxygen atmosphere of 400 ° C. to 600 ° C. As a result, oxygen is supplied to the ferroelectric films 23 and 24, and the electrical characteristics of the ferroelectric capacitor 31 are restored. Note that this heat treatment may be performed not in an oxygen atmosphere but in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, the electric characteristics of the ferroelectric capacitor 31 are restored by supplying oxygen to the ferroelectric films 23 and 24.

Further, the conductive plugs 18A-1 pass through the third interlayer insulating film 43 and the protective films 44, 42.
Contact holes 53A and 53B reaching 8E are formed by photolithography and etching.
After the formation of the via holes 51 and 52 and the contact holes 53A and 53B, an annealing process is performed to degas the interlayer insulating film. The step of performing the annealing treatment is desirably performed in an inert gas atmosphere or in a vacuum. In addition, after forming the via holes 51 and 52 and the contact holes 53A and 53B, after the annealing process, surface treatment, for example, RF etching is performed on the inner wall surfaces of the via holes 51 and 52 and the contact holes 53A and 53B.

Next, steps required until a sectional structure shown in FIG.
First, a TiN film as a first conductive barrier film is formed on the entire surface of the third protective film 44 to a film thickness of 50 nm to 150 nm, for example, by sputtering. The TiN film is formed using, for example, a Ti target. The atmosphere during film formation is a mixed atmosphere of Ar gas = 50 Sccm and N ₂ gas = 90 Sccm, and the film formation temperature is 200 ° C.

The first conductive barrier film 51 is not limited to TiN. TiN, TaN, CrN, HfN, ZrN, TiAlN, TaAlN, TiSiN, TaSiN, CrAlN, HfAlN, ZrAlN, TiON, TaON, CrON, HfON, ZrON, TiAlON, TaAlON, CrAlON, HfArON, ZrAlON, TiSiON, TaSiON, Ir Selected from the group consisting of Ru, IrO _x , RuO _x , TiN laminated Ti film, TaN Ti laminated film, TiN Ta laminated film, TaN Ta laminated film It can be one kind.

  Subsequently, a plug tungsten film is formed on the entire surface of the first conductive barrier film to a thickness of 300 nm by, for example, a CVD method. Note that the material of the plug film is not limited to tungsten, but may be copper. Alternatively, a copper film may be further formed by partially burying tungsten or polysilicon on the first conductive barrier film.

  Thereafter, the tungsten film and the first conductive barrier film are polished by, for example, a CMP method until the surface of the third interlayer insulating film 43 is exposed. As a result, conductive plugs 54, 55, 56A, and 56B containing tungsten are buried in the via holes 51 and 52 and the contact holes 53A and 53B, respectively. Next, the natural oxide film or the like on the surfaces of the conductive plugs 54, 55, 56A, and 56B is removed by, for example, plasma cleaning using Ar gas.

  Thereafter, a TiN film having a thickness of 50 nm, a copper aluminum alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 50 nm are formed on the third interlayer insulating film 43, for example. In order, they are formed by PVD, for example, sputtering. As a result, a conductor film composed of a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed.

  Then, using a photoresist (not shown), the first-layer metal wiring film is patterned. As a result, a first metal wiring layer is formed. That is, the wiring 65A connected to the upper electrode 35 is connected to one source / drain region 11B of the side MOS transistor T2 (T1) via the conductive plugs 16B and 56B. Further, the wiring 65B connected to the lower electrode 37 through the conductive plug 55 is connected to the plate line of the memory cell.

Furthermore, the pattern of the metal wiring film that remains isolated on the conductive plugs 16B and 56A connected to the shared source / drain region 11A among the two MOS transistors T1 and T2 in the same p-well 3 is a bit It becomes the conductive pad 66 for lines.
Thereafter, although not particularly shown, an interlayer insulating film, a conductive plug, a wiring, and the like are sequentially formed on the wirings 65A and 65B, the conductive pad 66, and the third interlayer insulating film 43 to complete the ferroelectric memory cell. Let

  As described above, in this embodiment, after the second insulating interlayer film 19 is formed, the heat treatment is performed to clean both surfaces of the silicon substrate 1 and then the rapid heat treatment (second heat treatment) is performed. Even if the lower electrode adhesion film 23 is formed at a low temperature, impurities such as moisture and organic matter remaining on the surface of the second interlayer insulating film 19 can be removed. For this reason, even if heat treatment is performed in a later step, impurities may enter the surface of the first conductive film 25 from the lower layer of the first conductive film 25 or from the interface between the first conductive film 25 and the second interlayer insulating film 19. It is prevented from moving to form voids.

  Further, by performing a heat treatment before the first dielectric film 27 is formed, impurities adsorbed on the surface of the first conductive film 25 therebelow can be removed. Furthermore, since the first dielectric film 27 was formed so as not to be exposed to the atmosphere after the heat treatment, hydrogen or the like adhered to the surface of the first conductive film 25 even when the first dielectric film 27 was formed at a low temperature. In this state, the first dielectric film 27 can be prevented from being formed. Thereby, when the crystallization annealing is performed on the second dielectric film 27, it is possible to prevent a void from being generated at the interface between the first conductive film 25 and the first dielectric film 27.

  Further, since the impurities adsorbed on the surface of the crystallized first dielectric film 27 and the surface of the second dielectric film 28 are also removed by the heat treatment, the second dielectric film 28 is continuously formed after that. By forming at a low temperature, the swelling of the interface between the second dielectric film 28 and the second conductive film 29 is improved. As a result, the adhesion between the first conductive film 25 and the first dielectric film 27 and the adhesion between the second conductive film 29 and the second dielectric film 28 are improved, and the upper electrode 35 is peeled off. The occurrence of defects such as floating and swelling is prevented.

  The ferroelectric capacitor 38 manufactured in this way is prevented from generating air gaps at the interface between the lower electrode 37 and the dielectric 36 and at the interface between the dielectric 36 and the upper electrode 35. Therefore, the performance deterioration of the ferroelectric capacitor 38 is prevented, and the yield of the semiconductor device can be improved.

(Second Embodiment)
FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment.
In this embodiment, the process up to forming the first conductive film 25 in step S160 is the same as that of the first embodiment. After forming the first conductive film 25, a rapid heat treatment is performed (step S161).

The rapid thermal treatment is performed in an atmosphere of an inert gas, for example, Ar or N ₂ , using an RTA apparatus with a substrate temperature of 500 ° C. to 750 ° C., for example, 650 ° C. By this rapid heat treatment, the crystal grain size of the first conductive film 25 is increased. Thereby, the adhesion between the first conductive film 25 and the first dielectric film 27 is improved. Subsequent processes (steps S170 to S240) and other effects are the same as those in the first embodiment.

(Third embodiment)
FIG. 4 shows a flowchart of the semiconductor device manufacturing method according to this embodiment.
In this embodiment, in order to further improve the crystallinity of the dielectric film, a conductive oxide film is formed on the surface of the first conductive film after the first conductive film is formed.

That is, after forming the first conductive film 25 (step S160), the silicon substrate 1 is introduced into a low temperature furnace, and Pt of the first conductive film 25 is oxidized in an oxygen atmosphere to form a conductive oxide film. (Step S162). Specifically, the silicon substrate 1 is introduced into an RTA apparatus or a furnace core, and oxygen is allowed to flow without heating to form an amorphous PtO film having a thickness of 0.1 nm to 3 nm on the surface of the first conductive film 25. . The treatment temperature is 100 ° C. or less, more preferably 50 ° C. or less, and the most preferred treatment temperature is room temperature. An Os, Rh, or Pb film may be formed instead of the Pt film.

The formation time of the conductive oxide film varies depending on the flow rate of the oxygen gas. For example, in the case where O ₂ gas is flowed at 2 l / min, it is desirable that the time is 2 minutes or longer. If the treatment time is too short, a PtO film cannot be formed sufficiently. The treatment time is preferably 3 hours or longer, for example, 6 hours. This oxide film improves oxygen deficiency at the interface between the first dielectric film 27 and the first conductive film 25 and improves the crystallinity of the first dielectric film 27. Subsequent processes (steps S170 to S240) and other effects are the same as those in the first embodiment.

Note that the first dielectric film 27 performed thereafter is preferably formed by a sputtering method or a sol-gel method.
In the case where the first conductive film 25 is an Ir film or Ru film, an oxide of the same noble metal having a film thickness of 15 nm to 30 nm is formed on the surface thereof, and the first dielectric film 27 is formed by organometallic chemistry. You may form by a vapor phase growth method.

(Fourth embodiment)
FIG. 5 shows a flowchart of the manufacturing method of the semiconductor device according to this embodiment.
In this embodiment, the second embodiment and the third embodiment are combined. That is, when forming the ferroelectric capacitor 38, the first conductive film 25 is formed (step S160), followed by RTA heat treatment (step S161), and then the surface of the first conductive film 25 is electrically conductive. A conductive oxide film is formed (step S162). Thereby, the crystallinity of the ferroelectric capacitor 38 is improved, and the fatigue resistance can be improved. Subsequent processes (steps S170 to S240) and other effects are the same as those in the first embodiment.

(Fifth embodiment)
FIG. 6 shows a flowchart of a method for manufacturing a semiconductor device according to this embodiment.
This embodiment corresponds to the processing in the case where the temperature for forming the second conductive film 29 is 100 ° C. or lower in the fourth embodiment. Alternatively, it is performed when the second dielectric film 28 and the second conductive film 29 are not deposited by continuous film formation.
That is, after the second dielectric film 28 is formed as in the first embodiment, surface treatment is performed to remove moisture and impurities adsorbed on the surface of the second dielectric film 28 (step S211). More specifically, after the second dielectric film 28 is formed, the substrate temperature is set to 100 ° C. to 350 ° C., for example, 150 ° C. in a reduced pressure atmosphere having a pressure of about 5.0 × 10 ⁻⁶ Pa. Heat treatment is performed for 60 seconds. Thereafter, the silicon substrate 1 is transferred to a sputtering chamber so as not to be exposed to the atmosphere. Subsequently, the second conductive film 29 is formed in the chamber (step S220).

  Here, the second conductive film 29 is formed at a temperature lower than the heat treatment temperature in the surface treatment of step S211. For this reason, when the second conductive film 29 is formed, impurities adsorbed on the second dielectric film 28 cannot be removed. However, since the impurities are removed by performing the heat treatment in the previous step (step S211), the second conductive film 29 is formed with the impurities remaining on the surface of the second dielectric film 28. And the swelling phenomenon at the interface between the dielectric and the upper electrode as shown in FIG. 8 is difficult to occur.

Here, when the defect inspection of the semiconductor device manufactured by the manufacturing method according to this embodiment was performed, the number of defects after cleaning the back surface of the substrate could be greatly reduced. In particular, large defects, that is, defects that appear as gaps between the upper electrode 35 and the dielectric film 36 are almost eliminated.
In order to detect defects between the dielectric film 36 and the lower electrode 37 more precisely, the following processes are performed on the three samples to form the ferroelectric capacitors 38, and defect inspection is performed on each of them. did.

  First, the first heat treatment is performed on the silicon substrate 1 (step S110), the substrate is cleaned with a brush scrubber (step S120), and then the lower electrode adhesion film 23 is formed (step S140).

  Here, the first and second samples were subjected to a rapid heat treatment for 60 seconds at a substrate temperature of 650 ° C. in an oxygen atmosphere as a second heat treatment (step S130). In contrast, the third sample proceeded to the next step without performing step S130.

  Next, the lower electrode adhesion film 23 is formed (step S140), and then a rapid heat treatment is performed as a heat treatment at 650 ° C. for 60 seconds in an oxygen atmosphere (step S150). Further, 150 nm of Pt is formed as the first conductive film 25 (step S160), and rapid heat treatment is performed in an Ar atmosphere at 642 ° C. for 60 seconds (step S161), and 0.3 nm is formed on the surface of the first conductive film 25. About PtO is formed at a low temperature (step S162).

Here, the first sample is introduced into a reduced pressure chamber of 2 × 10 ⁻⁵ Pa, heat-treated at 150 ° C. for 200 seconds (Step S170), and transferred to the sputtering chamber for PZT film formation without being exposed to the atmosphere. Then, the first dielectric film 27 is formed to 130 nm at 50 ° C. (step S180). On the other hand, for the second and third samples, the first dielectric film 27 was formed without performing the surface treatment of step S170 for comparison.

Next, crystallization annealing is performed on each sample (step S190), and then heat treatment is performed at 150 ° C. for 60 seconds in a reduced-pressure atmosphere (step S200), and the second dielectric film 28 is formed to 10 nm without being exposed to the atmosphere. Form (step S210). Further, heat treatment is performed in a reduced pressure atmosphere at 150 ° C. for 60 seconds (step S211), and the second conductive film 29 is formed at 20 ° C. without exposure to the atmosphere (step S220). Thereafter, a heat treatment for 120 seconds was performed in a mixed atmosphere plus about 1% _{O 2} gas to the Ar gas at 717 ° C. (step S230). Then, the third conductive film 30 was formed (Step S240), and the silicon substrate 1 was cleaned on the back surface. In the back surface cleaning, for example, the surface of the wafer is protected with a resist, and the PZT film on the back surface of the silicon substrate 1 is removed with HF. Thereafter, the resist on the surface of the silicon substrate 1 was removed.

  When the defect inspection was performed on the sample thus manufactured, 131 bulges on the film surface due to the voids as shown in FIGS. 8 to 9 were confirmed in the third sample corresponding to the conventional manufacturing method. It was done. On the other hand, there were 41 bulges on the film surface due to voids in the second sample. And the swelling of the film | membrane surface resulting from the space | gap in the 1st sample manufactured according to the flowchart of FIG. 6 was 29 pieces.

  In the first sample, RTA heat treatment was performed before the lower electrode adhesion film 23 was formed, and the number of defects due to voids was small compared to the other two samples. This indicates that defects due to voids can be reduced by performing RTA heat treatment before forming the lower electrode adhesion film 23. Further, from the comparison of the results of the first sample and the second sample, the surface treatment (step S211) and the low-temperature film formation of the second conductive film 29 (step S220) are performed as a continuous treatment after the formation of the second dielectric film 28. It was found that the defect caused by the voids can be reduced by performing the above.

  The same inspection was performed when the thicknesses of the first dielectric film 27 and the second dielectric film 28 were changed. Specifically, the thickness of the first dielectric film 27 here is 90 nm, and the thickness of the second dielectric film 28 is 30 nm. The film thickness of these dielectric films 27 and 28 is greater than the above conditions (first dielectric film 27: 130 nm, second dielectric film 28: 10 nm) than the second dielectric film 28 and the second conductive film 29. It has been empirically changed that it is a condition in which voids are likely to occur at the interface.

  When the RTA heat treatment is performed before forming the lower electrode adhesion film 23 (step S130) and the heat treatment before forming the first dielectric film 25 is not performed (step S150), 74 defects due to voids are confirmed. It was. On the other hand, when the RTA heat treatment is performed before the lower electrode adhesion film 23 is formed (step S130) and the heat treatment before the first dielectric film 25 is formed (step S150), defects due to voids are caused. There were 36 confirmed. For this reason, even under conditions where voids are likely to occur, the manufacturing method according to this embodiment can reduce defects due to the voids.

  In the flowchart of FIG. 6, it is also possible to manufacture a semiconductor device without performing Step S161 and Step S161. That is, in the first embodiment, step S211 may be performed, and the surface treatment in step S211 and the low-temperature formation of the second conductive film 29 in step S220 may be performed as a continuous process.

(Sixth embodiment)
FIG. 7 shows a flowchart of a method for manufacturing a semiconductor device according to this embodiment.
In this embodiment, the dielectric film 36 of the ferroelectric capacitor 38 is formed as a single layer. That is, the first dielectric film 27 is formed to a thickness required for the ferroelectric capacitor 38 (step S180), and crystallization annealing is performed (step S190). Surface treatment of the first dielectric film 27 is performed to remove moisture and the like (step S200). Thereafter, the second conductive film 29 is formed (step S220). In this way, even in the case of the dielectric film 36 having a single layer structure, the generation of voids can be prevented in the same manner as described above.
Note that the rapid thermal processing (step S161) of the first conductive film 25 and the process of forming an oxide film on the surface of the first conductive film 25 (step S162) may not be performed.

In each embodiment, the apparatus and method for washing the silicon substrate 1 with water are not limited to brush scrubbers, but adopting a method for removing impurities in the air adsorbed on the substrate surface by washing the surface of the substrate with water. Also good. For example, you may use the batch-type washing | cleaning apparatus which immerses a some board | substrate in the liquid tank in which the pure water was stored collectively. Alternatively, a single wafer cleaning apparatus that drops and cleans pure water on the silicon substrate 1 rotating on the spinner may be used.
Further, after the silicon substrate 1 is washed with water, for example, IPA drying for drying the silicon substrate 1 in an atmosphere containing IPA (isopropyl alcohol) may be performed. Examples of the method for drying the silicon substrate 1 after cleaning include natural drying in the air and heat drying in which the silicon substrate 1 is heated to about 150 ° C. in the air, in addition to IPA drying. However, since these processes may adsorb impurities in the atmosphere, it is desirable to perform heat treatment before forming the next film.

The heat treatment may be performed by removing the impurities adsorbed on the substrate surface by heat-treating the silicon substrate 1 in a plasma atmosphere. Examples of such a plasma atmosphere include an O ₂ plasma atmosphere or an N ₂ O plasma atmosphere.
Here, the heat treatment in the O ₂ plasma atmosphere can be performed using, for example, an ashing chamber for ashing and removing the resist. The heat treatment conditions at this time include, for example, a substrate temperature of 150 ° C., a pressure of 133 Pa, and a treatment time of 30 seconds.
In order to prevent the reduction of the first and second dielectric films 27 and 28 by hydrogen, the heat treatment is preferably performed in a plasma atmosphere excluding hydrogen.
Furthermore, although the example which heat-processes in the atmosphere of pressure reduction was given as the heat processing, it can be used also by another method.

As a method of forming the dielectric films 27 and 28, in addition to the sputtering method and the MOCVD method, a sol-gel method, an organometallic decomposition (MOD) method, a CSD (Chemical Solution Deposition) method, and a chemical vapor deposition (CVD) method are used. And an epitaxial growth method. Further, the dielectric film 27,
As 28, for example, a film whose crystal structure becomes a Bi layered structure or a perovskite structure can be formed by heat treatment. Examples of such a film include a film represented by the general formula ABO3 such as PZT, SBT, BLT, and Bi-based layered compound doped with a trace amount of La, Ca, Sr, and / or Si, in addition to the PZT film.

  In forming the second conductive film 29, for example, sputtering using a target containing platinum, iridium, ruthenium, rhodium, rhenium, osmium, and / or palladium is performed under conditions in which oxidation of these noble metal elements occurs. This can be done below. In particular, when an Ir oxide film is formed as the second conductive film 29, the film forming temperature is preferably set to 20 ° C. to 400 ° C., for example, 300 ° C. Further, the partial pressure of the oxygen gas relative to the pressure of the oxygen gas and the inert gas constituting the sputtering gas is preferably 10% to 60%, and the film thickness is preferably 10 nm to 75 nm.

The temperature of the heat treatment after forming the second conductive film 29 is preferably 650 ° C. to 750 ° C., for example 700 ° C., and the atmosphere during the heat treatment has an oxygen content of 1% to 50%. Is preferred.
Further, the third conductive film 30 is not limited to the IrO _x film, and may be a metal film containing a noble metal element such as Pt, Ir, Ru, Rh, Re, Os and / or Pd. Alternatively, an oxide film such as a SrRuO ₃ film may be formed. Further, a film having a two-layer structure or more may be formed as the conductive film.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of these embodiments are described below.
(Appendix 1) A step of forming an insulating film above a semiconductor substrate, a step of performing a first heat treatment on the semiconductor substrate after forming the insulating film, and a step of forming the semiconductor substrate after the first heat treatment. A step of cleaning, a step of performing a second heat treatment on the insulating film after cleaning the semiconductor substrate, a step of forming an adhesion film on the insulating film after the second heat treatment, and Forming a first conductive film on the first conductive film; forming a dielectric film on the first conductive film; and forming a first conductive film on the dielectric film. And a step of forming a two-conductive film.
(Additional remark 2) The manufacturing method of the semiconductor device of Additional remark 1 characterized by the film-forming temperature of the said adhesion film being lower than the temperature of said 2nd heat processing.
(Supplementary note 3) In the step of forming the dielectric film, the first conductive film is heat-treated to remove impurities adsorbed on the surface of the first conductive film, and then the first conductive film is put into the atmosphere. The manufacturing method of a semiconductor device according to appendix 1 or appendix 2, wherein the dielectric film is formed without being exposed.
(Additional remark 4) The manufacturing temperature of the said dielectric film is lower than the temperature of the heat processing at the time of removing the impurity adsorbed on the surface of the said 1st conductive film, The manufacturing of the semiconductor device of Additional remark 3 characterized by the above-mentioned Method. (Additional remark 5) The manufacturing temperature of the said dielectric film is 0 to 100 degreeC, The manufacturing method of the semiconductor device of Additional remark 3 or Additional remark 4 characterized by the above-mentioned.
(Supplementary Note 6) After the dielectric film is formed, the dielectric film is heat-treated to remove impurities adsorbed on the surface, and then the dielectric film is exposed to the atmosphere without exposing the dielectric film to the first film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a conductive film.
(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein a deposition temperature of the second conductive film is lower than a temperature of heat treatment for removing impurities adsorbed on the surface of the second dielectric film. Manufacturing method.
(Supplementary Note 8) The step of forming the dielectric film is a step of sequentially forming a first dielectric film and a second dielectric film, and after forming the first dielectric film, the first dielectric film Any one of appendix 1 to appendix 7, including the step of forming the second dielectric film without exposing the first dielectric film to the atmosphere after removing the impurities adsorbed on the surface by heat treatment A method for manufacturing a semiconductor device according to claim 1.
(Appendix 9) The semiconductor according to any one of appendices 1 to 8, wherein a conductive oxide film is formed on a surface of the first conductive film before forming the dielectric film. Device manufacturing method.

1 Silicon substrate (semiconductor substrate)
19 Second Interlayer Insulating Film 23 Lower Electrode Adhesive Layer 25 First Conductive Film 27 First Dielectric Film 28 Second Dielectric Film 29 Second Conductor Film 38 Ferroelectric Capacitor

Claims (5)

Forming an insulating film above the semiconductor substrate;
Performing a first heat treatment on the semiconductor substrate after forming the insulating film;
Cleaning the semiconductor substrate after the first heat treatment;
Performing a second heat treatment on the insulating film after cleaning the semiconductor substrate;
Forming an adhesion film on the insulating film after the second heat treatment;
Forming a first conductive film to be a lower electrode of a capacitor on the adhesion film;
Forming a dielectric film on the first conductive film;
Forming a second conductive film to be an upper electrode of the capacitor on the dielectric film;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein a film forming temperature of the adhesion film is lower than a temperature of the second heat treatment.   In the step of forming the dielectric film, after the first conductive film is heat-treated to remove impurities adsorbed on the surface of the first conductive film, the first conductive film is not exposed to the atmosphere, The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is formed.   After the dielectric film is formed, the dielectric film is heat-treated to remove impurities adsorbed on the surface, and then the second conductive film is formed on the dielectric film without exposing the dielectric film to the atmosphere. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming the semiconductor device.   The step of forming the dielectric film is a step of forming a first dielectric film and a second dielectric film in order, and after forming the first dielectric film, the first dielectric film is heat-treated. 5. The method according to claim 1, further comprising: forming the second dielectric film without exposing the first dielectric film to the atmosphere after removing impurities adsorbed on the surface. A method for manufacturing the semiconductor device according to the item.

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