JP2010278181A5

JP2010278181A5 -

Info

Publication number: JP2010278181A5
Application number: JP2009128531A
Authority: JP
Filing date: 2009-05-28
Publication date: 2012-03-29
Anticipated expiration: 2029-05-28

Description

また、シリコン基板１００の下面側の絶縁層１２０の上に、貫通電極２００に接続されると共に、コンタクトホールＣＨ２を通してツェナーダイオードＺＤのｐ型シリコン部１００ａの下面に接続される配線層３２０を形成する。 A wiring layer 320 is formed on the insulating layer 120 on the lower surface side of the silicon substrate 100 and connected to the through electrode 200 and connected to the lower surface of the p-type silicon portion 100a of the Zener diode ZD through the contact hole CH2. .

次いで、図５（ａ）に示すように、シリコン基板１０の両面側において、第１バリア金属層３０ａ上及びコンタクトホールＣＨ１，ＣＨ２内にスパッタ法によって第２バリア金属層４２ａをそれぞれ形成する。第２バリア金属層４２ａは、バリア層として機能すると共に、電解めっきのめっき給電経路となるシード層として機能する。 Next, as shown in FIG. 5A, on both sides of the silicon substrate 10, the second barrier metal layer 42a is formed on the first barrier metal layer 30a and in the contact holes CH1 and CH2 by sputtering. The second barrier metal layer 42a functions as a barrier layer and also functions as a seed layer serving as a plating power supply path for electrolytic plating.

例えば、第２バリア金属層４２ａは、下から順に、Ｔｉ層（膜厚：５０ｎｍ）／Ｃｕ層（膜厚：３００ｎｍ）から形成される。あるいは、第２バリア金属層４２ａは、下から順に、Ｔｉ層／ＴｉＮ層、又はＴｉ層／ＴｉＮ層／Ｃｕ層から形成されてもよい。 For example, the second barrier metal layer 42a is formed from a Ti layer (film thickness: 50 nm) / Cu layer (film thickness: 300 nm) in order from the bottom. Alternatively, the second barrier metal layer 42a may be formed from Ti layer / TiN layer or Ti layer / TiN layer / Cu layer in order from the bottom.

さらに、シリコン基板１０の両面側には、貫通電極２０の上下面に電気接続される第１配線層４０がそれぞれ形成されている。第１配線層４０は、下から順に、貫通電極２０に接触して接続される第１バリア金属パターン層３０、第２バリア金属パターン層４２及び導電パターン層４４によって構成される。 Further, first wiring layers 40 that are electrically connected to the upper and lower surfaces of the through electrode 20 are formed on both sides of the silicon substrate 10. The first wiring layer 40 includes, in order from the bottom, a first barrier metal pattern layer 30, a second barrier metal pattern layer 42, and a conductive pattern layer 44 that are in contact with and connected to the through electrode 20.

このとき、貫通電極２０は第１バリア金属層３０ａで保護されていることから、ウェット処理時に貫通電極２０の銅がエッチング液に拡散しないので、ツェナーダイオードＺＤが銅で汚染されるおそれがない。その後に、第１バリア金属層３０ａを利用して、貫通電極２０及びツェナーダイオードＺＤに接続される第１、第２配線層４０，４０ａが同時に形成される。 At this time, since the through electrode 20 is protected by the first barrier metal layer 30a, the copper of the through electrode 20 does not diffuse into the etching solution during the wet process, so that there is no possibility that the Zener diode ZD is contaminated with copper. Thereafter, the first and second wiring layers 40 and 40a connected to the through electrode 20 and the Zener diode ZD are simultaneously formed using the first barrier metal layer 30a.

そして、シリコン基板１０の上面側にＬＥＤなどの発光素子（不図示）が第１、第２配線層４０，４０ａに接続されて実装され、ツェナーダイオードＺＤは、電源ラインにおいて発光素子と電気的に並列になるように接続されて電源レギュレータとして機能する。そして、シリコン基板１０の下面側の第１、第２配線層４０，４０ａが配線基板（マザーボード）に接続される。 A light emitting element (not shown) such as an LED is mounted on the upper surface side of the silicon substrate 10 so as to be connected to the first and second wiring layers 40 and 40a, and the Zener diode ZD is electrically connected to the light emitting element in the power supply line. Connected in parallel and functions as a power regulator. Then, the first and second wiring layers 40 and 40a on the lower surface side of the silicon substrate 10 are connected to the wiring board (mother board).

なお、シリコン基板１０の下面側では、貫通電極２０の下面を被覆する第１バリア金属パターン層３０が少なくとも形成されていればよく、必ずしも第２バリア金属パターン層４２及び導電パターン層４４を形成する必要はない。この場合、第１バリア金属パターン層３０は第１バリア金属層３０ａ（図９（ｂ））が直接パターン化されて形成され、第１バリア金属パターン層３０に接続電極を設けてもよい。 It should be noted that at least the first barrier metal pattern layer 30 that covers the lower surface of the through electrode 20 need only be formed on the lower surface side of the silicon substrate 10, and the second barrier metal pattern layer 42 and the conductive pattern layer 44 are necessarily formed. There is no need. In this case, the first barrier metal pattern layer 30 may be formed by directly patterning the first barrier metal layer 30a (FIG. 9B), and a connection electrode may be provided on the first barrier metal pattern layer 30.

Claims

A semiconductor substrate;
An element formed on the semiconductor substrate;
A through hole formed through the semiconductor substrate;
Insulating layers formed on both sides of the semiconductor substrate and the inner surface of the through hole;
A through electrode formed in the through hole;
A contact hole formed in the insulating layer and reaching a connection portion of the element;
A first wiring layer including a first barrier metal pattern layer connected to the through electrode;
A second wiring layer formed from the same layer as the first wiring layer, including the first barrier metal pattern layer disposed in a portion excluding the contact hole, and connected to the connection portion of the element through the contact hole; A semiconductor device comprising:

The first wiring layer is formed from the first barrier metal pattern layer, the second barrier metal pattern layer, and the conductive pattern layer in order from the bottom,
The second wiring layer is formed on the first barrier metal pattern layer disposed in a portion excluding the contact hole, the second barrier metal pattern layer connected to a connection portion of the element, and the second barrier metal pattern layer. The semiconductor device according to claim 1, wherein the semiconductor device is formed of the conductive pattern layer.

The semiconductor device according to claim 1, wherein the element is a Zener diode, a transistor, or a capacitor.

The element is a Zener diode configured by forming an impurity diffusion region having a conductivity type opposite to that of the semiconductor substrate in a surface layer portion of the semiconductor substrate, and the impurity diffusion region and a lower surface of the semiconductor substrate serve as the connection portion. And
The semiconductor device according to claim 3, wherein the contact hole is formed in the insulating layer on both sides of the semiconductor substrate.

The through electrode is formed of copper;
The said 1st barrier metal pattern layer consists of any one of a titanium layer, a titanium layer / titanium nitride layer, an aluminum layer, and an aluminum alloy layer in order from the bottom. The semiconductor device described.

A semiconductor substrate; an element formed on the semiconductor substrate; a through hole penetrating the semiconductor substrate; and an insulating layer formed on both sides of the semiconductor substrate and on the inner surface of the through hole to cover the element. Preparing a prepared structure;
Forming a through electrode in the through hole;
Forming a first barrier metal layer covering the insulating layer and the through electrode on both sides of the semiconductor substrate;
Forming a contact hole reaching the connection portion of the element by processing the first barrier metal layer and the insulating layer;
Removing a natural oxide film at a connection portion of the element in the contact hole;
Forming a first wiring layer connected to the through electrode and a second wiring layer connected to the connection portion of the element through the contact hole using the first barrier metal layer. A method of manufacturing a semiconductor device.

Forming the first wiring layer and the second wiring layer;
Forming a second barrier metal layer on the first barrier metal layer and in the contact hole;
Forming a plating resist on the second barrier metal layer in which an opening is provided in a portion where the first and second wiring layers are disposed;
Forming a conductive pattern layer in the opening of the plating resist by electrolytic plating using the second barrier metal layer as a plating power feeding path;
Removing the plating resist;
The method of manufacturing a semiconductor device according to claim 6, further comprising: etching the second barrier metal layer and the first barrier metal layer using the conductive pattern layer as a mask.

The method for manufacturing a semiconductor device according to claim 6, wherein the element is a Zener diode, a transistor, or a capacitor.

The element is a Zener diode configured by forming an impurity diffusion region having a conductivity type opposite to that of the semiconductor substrate in a surface layer portion of the semiconductor substrate, wherein the impurity diffusion region and the lower surface of the semiconductor substrate are connected to the connection portion. And
In the step of forming the contact hole,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the contact hole is formed in the insulating layer on both sides of the semiconductor substrate.

The through electrode is formed of copper;
The said 1st barrier metal pattern layer consists of any one of a titanium layer, a titanium layer / titanium nitride layer, an aluminum layer, and an aluminum alloy layer in order from the bottom. The manufacturing method of the semiconductor device of description.