JP2010273446A - Power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply device which can convert a voltage, even when the voltage is in a low-load state with high power efficiency. <P>SOLUTION: In the power supply device which converts an input voltage into an output voltage, the power supply device includes a first switch M1 and a second switch M2 connected in series between an input voltage terminal and a reference power supply; an inductor Lout arranged between a connecting node LX of the first and second switches and an output terminal Out; a control unit 1 which alternately on/off-controls the first and second switches according to an output voltage of the output terminal; and a comparator unit 15, which detects a first state that a voltage of the connecting node becomes equal to or higher than a voltage of a reference power supply and a second state that the voltage of the connecting node becomes equal to or higher than a comparison voltage lower than the voltage of the reference power supply. Then, the control unit makes the resistance of the second switch increase, in response to the detection of the second state by the comparator unit and turns off the second switch in response to the detection of the first state by the comparator unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power supply device that generates an output voltage from an input voltage.

  The power supply device generates an output voltage having a different voltage from the input voltage. A power supply device that performs such power supply voltage conversion is also called a DCDC converter, and is widely used in mobile phones and portable information terminals having low power supply LSIs.

  The DCDC converter has, for example, a first switch and a second switch connected in series between an input voltage and a ground voltage, and further includes a connection point between the first and second switches and an output terminal. A smoothing circuit including an inductor such as a coil and a capacitor such as a capacitor is provided between them. The first switch and the second switch are turned on and off alternately, current is supplied from the input voltage via the coil, and output voltage is generated at the output terminal by the current smoothed by the smoothing circuit. To do.

  The above-mentioned DCDC converter is described in Patent Documents 1 and 2, for example.

JP 2007-20316 A JP 2006-262646 A

  The DCDC converter is required to increase the power efficiency that is output power versus input power. In general, in a light load state in which the load current decreases, the efficiency of the DCDC converter decreases. One of the causes is that when the first switch is turned off and the second switch is turned on, a backflow current is generated in the coil of the smoothing circuit and the charge stored in the capacitor is thrown away to the ground side. There is movement. That is, in a normal load state, the energy stored in the coil is sufficiently large, so that when the second switch is turned on, a regenerative current flows in the direction of the second switch, coil, and output terminal. However, when the load is lightened, the energy stored in the coil is not sufficient, and a reverse current is generated in the coil when the second switch is turned on.

  In order to avoid or suppress the generation of the reverse current, the timing at which the reverse current is generated is detected and control for turning off the second switch is performed.

  However, it is not always easy to detect the timing at which the reverse current is generated with high accuracy, and a wasteful reverse current cannot be eliminated due to a timing shift. Alternatively, energy cannot be supplied to the coil with high efficiency due to timing shift.

  Accordingly, an object of the present invention is to provide a power supply device capable of performing voltage conversion with high power efficiency even in a low load state.

The first aspect of the power supply device is a power supply device that converts an input voltage into a predetermined output voltage.
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit for detecting a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply and a second state in which the voltage of the connection node is equal to or higher than a comparison voltage lower than the voltage of the reference power supply; Have
The control unit increases the resistance of the second switch in response to the detection of the second state by the comparator unit, and responds to the detection of the first state by the comparator unit. 2 switch off.

The second aspect of the power supply apparatus is a power supply apparatus that converts an input voltage into a predetermined output voltage.
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit that detects a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply;
The control unit increases the ON resistance of the second switch after the comparator unit detects the first state after the first switch is turned OFF and the second switch is turned ON. In response to the comparator unit detecting the first state, the second switch is turned off.

  According to the first or second aspect, the power efficiency of the power supply device can be increased.

It is a whole lineblock diagram of a power supply device in this embodiment. It is an operation | movement waveform diagram of the power supply device of FIG. It is a figure explaining the reverse direction current of the inductor current ILX. It is a figure which shows the operation | movement by discontinuous current mode. FIG. 6 is an operation waveform diagram when the second comparator 15 includes a positive offset voltage. FIG. 6 is an operation waveform diagram when the second comparator 15 includes a negative offset voltage. 1 is a circuit diagram of a power supply device according to a first embodiment. It is an operation | movement waveform diagram when the 2nd comparator 15 in 1st Embodiment has a negative offset voltage. It is an operation | movement waveform diagram when the 2nd comparator 15 in 1st Embodiment has a positive offset voltage. It is a circuit diagram of the power supply device in 2nd Embodiment. It is a circuit diagram of the power supply device in 3rd Embodiment. It is an operation | movement waveform diagram in 3rd Embodiment.

  FIG. 1 is an overall configuration diagram of a power supply device according to the present embodiment. The power supply apparatus 10 of FIG. 1 includes a first switch M1 and a second switch connected in series between an input voltage terminal In to which an input voltage Vin is applied and a reference power supply voltage (for example, ground) Vss lower than the input voltage. Two switches M2, an inductor Lout such as a coil provided between a connection node (or connection point) LX of the first and second switches and an output terminal Out from which an output voltage Vout is output, and an output voltage Vout And a control unit 1 that performs switching control of the first and second switches M1 and M2 alternately in a predetermined switching cycle in accordance with an error with respect to the target voltage.

  The first switch M1 is a high-side transistor composed of a P-channel MOS transistor, and is controlled to be conductive or nonconductive by a gate drive signal Vgh generated by the control unit 1. The second switch M2 is a low-side transistor composed of an N-channel MOS transistor, and is controlled to be conductive or nonconductive by a gate drive signal Vgl generated by the control unit 1. Further, the first and second switches M1, M2 are alternately controlled to be on, off or off, on.

  A capacitor Cout is provided between the output terminal Out and the reference power supply voltage Vss, and a smoothing circuit is configured by the inductor Lout and the capacitor Cout. The output terminal Out is connected to the power supply terminal of the load circuit 20 and supplies a load current Iload to the load circuit.

  The input voltage Vin is a DC voltage having a predetermined potential, and the output voltage Vout is a DC voltage lower than the input voltage Vin. The reference power supply voltage Vss is, for example, a ground voltage.

  The control unit 1 includes an error amplifier 11 that amplifies an error between the feedback voltage Vfb obtained by dividing the output voltage Vout by the feedback resistors R1 and R2 and the target reference voltage Vref, an error Verror generated by the error amplifier 11, and a comparison voltage Vslope. A first comparator (PWM (Pulse Width Modulation) comparator) 12 and a drive control circuit 14 for driving the first and second switches M1, M2 according to the result Vo of the first comparator 12. Have. Then, the first comparator 12 detects that the output voltage Vout has dropped below the target voltage and sets the output signal Vo to the H level, and the drive control circuit 14 sets the gate drive signals Vgh and Vgl to the L level in response thereto. Thus, the first switch M1 is turned on and the second switch M2 is turned off.

  The first comparator 12 compares the error Verror with the slope voltage Vslope that rises and falls in the first period, and the drive control circuit 14 controls the first switch M1 to be in a conductive state according to the input / output voltage ratio. Perform pulse width modulation control. For example, when the error Verror is large (when the output voltage Vout is significantly lower than the target voltage), the drive control circuit 14 controls the first switch M1 to be in a conductive state for a longer time than when the error is small. Width modulation control is performed. The comparison voltage generation circuit 13 generates a slope voltage Vslope that rises and falls in the first cycle.

  The control unit 1 performs conduction / non-conduction control alternately between the first switch M1 and the second switch M2. For this purpose, the first comparator 12 compares the slope voltage Vslope having a certain period with the error voltage Verror, and performs PWM modulation for modulating the error magnitude of the error voltage Verror to the pulse width of the output signal Vo. The drive control circuit 14 generates gate drive signals Vgh and Vgl according to the output signal Vo of the first comparator 12, and controls conduction and non-conduction of the first and second switches M1 and M2.

  FIG. 2 is an operation waveform diagram of the power supply device of FIG. In FIG. 2, in the first half period ton of the cycle T1, the gate drive signal Vgh becomes L level, the first switch M1 is turned on, and the high-side output current IoutH flows. At that time, the gate drive signal Vgl is at L level, and the second switch M2 is turned off. In the first half period ton, when the first switch M1 is turned on, the node voltage VLX rises to near the input voltage Vin, and the high-side output current IoutH gradually increases according to the inductor value of the inductor Lout. The voltage VLX gradually decreases. The high-side output current IoutH is the same as the inductor current ILX, increases during the first half period, and the inductor Lout stores electromagnetic energy. In response to this, the feedback voltage Vfb also rises.

  In FIG. 2, in the second half period toff of the cycle T1, the gate drive signal Vgh becomes H level and the first switch M1 becomes non-conductive, and the gate drive signal Vgl also becomes H level and the second switch M2 becomes conductive. When the second switch M2 is turned on, the inductor Lout keeps flowing the inductor current ILX due to the regenerative operation by the accumulated electromagnetic energy. Therefore, the second switch M2 has a low-side output current from the reference power supply voltage Vss toward the connection point LX. IoutL flows. Therefore, the connection point voltage VLX once becomes a negative potential as shown in the figure. Then, electromagnetic energy is released by the regenerative operation of the inductor LOUT, the inductor current ILX gradually decreases, and accordingly, the connection point voltage VLX increases from a negative voltage toward 0V. As the inductor current ILX decreases, the feedback voltage Vfb also decreases.

  As described above, in the first half period ton of the cycle T1, the first switch M1 is turned on to supply charge from the input voltage VIN to the output terminal Out, the output voltage Vout rises, and the feedback voltage Vfb also rises. On the other hand, in the second half period toff, the second switch M2 conducts and charges are supplied to the output terminal Out by the regenerative operation of the inductor LOUT, so that the output voltage Vout decreases and the feedback voltage Vfb also decreases.

  As shown in FIG. 2, the first comparator 12 in the control unit 1 sets the output signal Vo to the H level while the error Verror is lower than the slope voltage Vslope, and sets the output signal Vo to the L level while it is high. When the load decreases, the output voltage Vout increases and the feedback voltage Vfb also increases, so the H level period of the output signal Vo of the first comparator 12 is shortened. When the H level period of the output signal Vo is shortened, the conduction period ton of the first switch M1 is shortened, so that the output voltage Vout is lowered.

  In FIG. 2, the solid line of the inductor current ILX indicates a normal load, and the broken line of the inductor current ILX indicates a light load. The solid line of the node voltage VLX indicates the normal load, and the broken line indicates the light load. During the normal load, the conduction period ton of the first switch M1 is long, so that the inductor LOUT accumulates sufficient energy and the inductor current ILX does not fall below 0A. That is, the inductor current ILX always flows in the forward direction from the connection point LX toward the output terminal Out.

  On the other hand, when the load is light, the conduction period ton of the first switch M1 is shortened, the stored energy of the inductor LOUT is reduced, and when the second switch M2 is conducting, the inductor current ILX becomes lower than 0 A and a negative current (reverse direction) Current). Along with this, the connection point voltage VLX goes from 0 V (= Vss) from the negative potential to the positive potential. That is, at a light load, the low-side current IoutL flowing through the second switch M2 flows from the connection point LX toward the reference power supply voltage Vss.

  Since the inductor current LOUT in the reverse direction draws out the electric charge accumulated in the load capacitor Cout to the ground side, the power efficiency, which is the ratio of input power to output power, is reduced.

  1 has a second comparator 15 that compares the connection point LX with the reference power supply voltage Vss. The second comparator 15 sets the detection output Vc to L level when the voltage VLX at the connection point LX is lower than the reference power supply voltage Vss, and sets the detection output Vc to H when the voltage VLX at the connection point LX is equal to or higher than the reference power supply voltage Vss. To level. Therefore, when the connection point voltage VLX shown by the broken line reaches a positive potential from a negative potential at a light load shown in FIG. 2, the second comparator 15 changes the detection output Vc from the L level to the H level.

  In response to this, while the detection output Vc is at the H level, the drive control circuit 14 sets the gate drive signal Vgl to the L level to turn off the second switch M2. As a result, the inductor current ILX can be prevented from flowing in the reverse direction. Hereinafter, the discontinuous current mode will be further described with reference to FIGS.

  FIG. 3 is a diagram for explaining the reverse current of the inductor current ILX. As described above, when the first switch M1 is turned on, the high-side current IoutH flows through the inductor Lout as the inductor current ILX. This high side current IoutH is an increasing current. On the other hand, when the second switch M2 is turned on, the low-side current IoutL flows through the inductor Lout as the inductor current ILX. This low-side current IoutL is a decreasing current. That is, the inductor current ILX includes a ripple (pulsating current).

  As shown on the right side of FIG. 3, in the normal load state, the inductor current ILX has a relatively high average value Iave1, and even if a ripple is included in the inductor current ILX, it does not become a negative current. However, in the light load state, the average value Iave2 of the inductor current ILX is low, and in the regenerative operation in which the second switch M2 is turned on, the forward inductor current ILX decreases and eventually becomes a reverse current. In the figure, it is as indicated by a broken line.

  FIG. 4 is a diagram illustrating an operation in the discontinuous current mode. The same circuit as FIG. 1 is shown on the upper side of FIG. A second comparator 15 is provided to detect the timing at which the inductor current ILX changes from the positive direction to the reverse direction. The second comparator 15 compares the drain and source of the second switch M2. That is, the reference power supply voltage Vss is input to the minus input of the second comparator 15, and the voltage VLX at the connection point LX is input to the plus input.

  4 shows an inductor current ILX, a connection point voltage VLX, and a detection signal Vc in the discontinuous current mode operation. When the switch M1 is turned on and the M2 is turned off, the node voltage VLX becomes a positive potential and the inductor current ILX increases. When the switch M2 is turned on and the M1 is turned off, the node voltage VLX becomes a negative potential and the inductor current ILX decreases. To do. As the inductor current ILX decreases, the node voltage VLX increases from a negative potential toward the ground (0 V).

  While the node voltage VLX is negative, the detection signal Vc of the comparator 15 is at L level. However, when the node voltage VLX reaches the ground (0 V), the comparator 15 inverts the detection output Vc to the H level. In response to this, the drive control circuit 14 switches the gate drive signal Vgl to L level and turns off the second switch M2. At the same time, both ends of the inductor Lout are short-circuited by a short circuit (not shown). As a result, the reverse inductor current ILX flowing through the second switch M2 is cut off. At this time, since the first switch M1 is also in the OFF state, the connection point LX becomes the high impedance state HiZ. This is the operation in the discontinuous current mode.

  In the operation in the discontinuous current mode, it is ideal to turn off the second switch M2 at an accurate timing when the connection point voltage VLX becomes 0V. However, since the comparator 15 includes an offset voltage due to manufacturing variations of circuit elements, it is difficult to accurately detect the timing of VLX = 0V.

  When the timing of turning off the second switch M2 is delayed, the connection point voltage VLX exceeds 0V and becomes a positive potential, the backflow current ILX is generated, and the charge of the output capacitor Cout is wasted. Conversely, if the timing of turning off the second switch M2 is advanced, the second switch M2 is turned off before the node voltage VLX reaches 0V, and the energy that can be supplied to the inductor by the forward current is reduced. Supply energy is reduced with respect to switching loss due to operation. In either case, the ratio of output power to input power decreases and power efficiency decreases.

  FIG. 5 is an operation waveform diagram when the second comparator 15 includes a positive offset voltage. If the comparator 15 includes the positive offset voltage Voffset (+), the detection signal Vc switches to the H level when the connection point voltage VLX exceeds 0V and reaches the offset voltage Voffset (+). Therefore, as indicated by 30 in the figure, the inductor current ILX becomes a negative current, that is, a reverse current. This reverse current means that energy is wasted, leading to a reduction in power efficiency.

  FIG. 6 is an operation waveform diagram when the second comparator 15 includes a negative offset voltage. In the case of the negative offset voltage Vofset (−), contrary to FIG. 5, before the connection point voltage VLX reaches 0V, the offset voltage Voffset (−) is reached and the detection signal Vc is switched to the H level. Therefore, as indicated by 32 in the figure, the second switch M2 is turned off before the inductor current ILX reaches zero. This means that the energy supply to the output capacitor Cout is interrupted by the forward current ILX when the second switch M2 is in the ON state, which also causes a reduction in power efficiency.

  The maximum reverse current ILX1 in FIG. 5 is equal to the current obtained by dividing the offset voltage Voffset (+) by the on-resistance of the second switch M2. Further, the maximum loss current ILX2 in FIG. 6 is equal to a current obtained by dividing the offset voltage Vouset (−) by the on-resistance of the second switch M2. Therefore, if the on-resistance of the second switch M2 is increased, the maximum reverse current ILX1 and the maximum loss current ILX2 can be reduced even if the comparator 15 includes an offset voltage, thereby suppressing a decrease in power efficiency. be able to.

  However, if the on-resistance of the second switch M2 is increased, the power consumption in the second switch M2 due to the low-side current IoutL flowing through the second switch M2 increases, and the power consumed in the second switch M2 increases. It causes a decrease in power efficiency.

  FIG. 7 is a circuit diagram of the power supply device according to the first embodiment. In FIG. 7, the configurations of the feedback resistors R1, R2, the error amplifier 11, and the first comparator 12 in the previous stage of the drive control unit 14 of the power supply device of FIG. 1 are omitted. In FIG. 7, the second and third comparators 15 and 21 constitute a comparator unit, and the latch circuit 22, inverter 23, and AND gate 24 for processing the output Vd of the third comparator 21 are the same as those in the control unit 1 of FIG. It is the structure in.

  In the power supply device of the first embodiment, the connection node voltage VLX is equal to or higher than the reference power supply voltage Vss, and the connection node voltage VLX is equal to or higher than the reference power supply voltage Vss. Comparator units 15 and 21 for detecting the second state, and the drive control unit 14, the latch circuit 22, the inverter 23, and the AND gate 24 in the control unit are connected to the second comparator 21 by the third comparator 21. In response to the detection of the state (Vd = H), the resistance of the second switch M2 is increased, and in response to the detection of the first state (Vc = H) by the second comparator 15, the second switch Turn off M2.

  The second switch M2 includes a plurality of transistors M2-1 and M2-2 connected in parallel between the connection point LX and the reference power supply voltage Vss. Then, when the drive control unit 14 turns on the second switch M2 in the latter half of the PWM cycle, the drive control unit 14 sets the gate drive signal Vgl to the H level so that the transistors M2-1 and M2- constituting the second switch M2 are turned on. Turn on both of the two. As a result, the on-resistance of the second switch is lowered. Thereby, power consumption in the second switch M2 due to the low-side current IoutL is reduced. The latch circuit 22 is in the L level state by the gate drive signal Vgl = H, and the output of the inverter 23 is in the H level.

  As described above, the comparator unit includes the second comparator 15 and the third comparator 21, and the third comparator 21 compares the comparison voltage Vref1 lower than the reference power supply voltage Vss with the voltage VLX of the connection node LX. When the connection point voltage VLX becomes equal to or higher than the comparison voltage Vref1, the detection signal Vd is set to H level. The latch circuit 22 latches it. As a result, the output of the inverter 23 becomes L level, the output of the AND gate 24 also becomes L level, and the transistor M2-2 is turned off.

  The transistor sizes of the transistors M2-1 and M2-2 are, for example, that the transistor M2-1 is smaller than the M2-2, and thus the on-resistance is higher. Alternatively, the second switch M2 may include a plurality of N-channel transistors connected in parallel, and the transistors M2-1 and M2-2 may be configured by, for example, a 1:10 number of N-channel transistors. . That is, when the gate size of the transistor is 1:10, the on-resistance of the transistor M2-1 is high and the on-resistance of the transistor M2-2 is low.

  Since the transistor M2-2 is turned off, only the transistor M2-1 is turned on, and the on-resistance of the second switch M2 becomes higher. As a result, a larger voltage is generated in the transistor M2-1 even with a smaller current, and the second comparator 15 sets the detection signal Vc to the H level until the low side current IoutL, that is, the inductor current ILX becomes a small current closer to 0A. Do not flip. In response to the detection signal Vc = H, the drive control circuit 14 sets the gate drive signal Vgl to L level, the transistor M2-1 is also turned off, and the inductor current ILX is cut off.

  FIG. 8 is an operation waveform diagram when the second comparator 15 in the first embodiment has a negative offset voltage. At time t1, the gate drive signals Vgh and Vgl become L level, the first switch M1 is turned on, the second switch M2 (transistors M2-1 and M2-2) is turned off, and the high side current IoutH is increased. . As a result, the inductor L stores energy.

  At time t2, the gate drive signals Vgh and Vgl are once set to the H and L levels, and then both the gate drive signals Vgh and Vgl are set to the H level, the first switch M1 is turned off, and the second switch M2 (transistor M2 -1, M2-2) is turned on. Since the inductor Lout stores energy, the low-side current IoutL is generated from the reference power supply Vss toward the connection point LX in the second switch M2, and the forward current ILX flows in the inductor Lout. This inductor current ILX gradually decreases.

  On the other hand, when the gate drive signals Vgh and Vgl are once set to the H and L levels at time t2, both the first and second switches M1 and M2 are turned off, but the transistor M2- constituting the second switch M2 Since a parasitic diode is formed in the direction from the source to the drain of M1-2, the inductor current ILX flows through this parasitic diode. Therefore, the connection point voltage VLX once becomes a deep negative potential 81 immediately after time t2.

  Thereafter, both the gate drive signals Vgh and Vgl become H level, the first switch M1 is turned off, the second switch M2 (transistors M2-1 and M2-2) is turned on, and the inductor current ILX decreases. Thus, the absolute value of the connection point voltage VLX decreases along the slope 82. The slope 82 of the node voltage is relatively gentle based on the low resistance due to the transistors M2-1 and M2-2 constituting the second switch M2.

  When the node voltage VLX becomes equal to or higher than the comparison voltage Vref1 of the third comparator 21 at time t3, the output Vd of the third comparator 21 is inverted to H level. In response to this, the latch circuit 22 latches H level, the output of the inverter 23 becomes L level, and the output of the AND gate 24 becomes L level. As a result, of the second switch M2, the transistor M2-2 having a relatively small on-resistance is turned off, and only the transistor M2-1 having a relatively large on-resistance is maintained in the on state. As a result, the slope 83 of the connection point voltage VLX switches to a steeper slope than the slope 82.

  Then, the connection point voltage VLX decreases with a slope 83 due to the decrease of the inductor current ILX, and when the connection point voltage VLX becomes equal to or higher than the offset voltage Voffset (−) of the second comparator 15 at time t5, the second comparator 15 detects. Set the output Vc to H level. In response to this, the driver control circuit 14 sets the gate driver signal Vgl to the L level, and the transistor M2-1 of the second switch M2 is turned off. As described above, the inductor current ILX2 at time t5 has a value obtained by dividing the offset voltage Voffset (−) by the on-resistance of the second switch M2, that is, the on-resistance of the transistor M2-1. Therefore, it becomes smaller than the inductor current ILX2 shown in FIG. 6 (inductor current at time t4 in FIG. 8). Therefore, the low-side current IoutL generated by turning on the switch M2 can be supplied to the inductor Lout longer until the time t5 later than the time t4, and the power efficiency can be improved.

  As described above, before the connection point voltage VLX reaches the offset voltage Voffset (−) of the second comparator 15, it is necessary for the third comparator 21 to detect that the connection point voltage VLX has reached the comparison voltage Vref1. Therefore, the comparison voltage Vref1 of the third comparator 21 is required to be lower than the offset voltage of the second comparator 15 in consideration of the offset voltage of the third comparator. Since any comparator has an offset voltage due to manufacturing variations, the comparison voltage is determined in consideration of them.

  After the high impedance state HiZ due to the OFF state of the first and second switches M1 and M2, the drive control circuit 14 sets the gate drive signals Vgh and Vgl to the L level again to turn on the first switch M1 and the second The switch M2 is turned off to generate the high side current IoutH. The subsequent operation is the same as described above.

  FIG. 9 is an operation waveform diagram when the second comparator 15 in the first embodiment has a positive offset voltage. At time t11, the gate drive signals Vgh and Vgl become L level, the first switch M1 is turned on, the second switch M2 (transistors M2-1 and M2-2) is turned off, and the high side current IoutH is increased. .

  At time t12, after the gate drive signals Vgh and Vgl are once set to the H and L levels, the gate drive signals Vgh and Vgl are both set to the H level, the first switch M1 is turned off, and the second switch M2 (transistor M2 -1, M2-2) is turned on. A low-side current IoutL is generated in the second switch M2 from the reference power supply Vss toward the connection point LX, and a forward current ILX flows in the inductor Lout.

  On the other hand, when the gate drive signals Vgh and Vgl are once set to the H and L levels at time t12, the first and second switches M1 and M2 are both turned off, but the transistor M2- constituting the second switch M2 is turned off. Since a parasitic diode is formed in the direction from the source to the drain of M1 and M2-2, the inductor current ILX flows through this parasitic diode, and the node voltage VLX once becomes a deep negative potential 81 immediately after time t12.

  Thereafter, both the gate drive signals Vgh and Vgl become H level, the first switch M1 is turned off, the second switch M2 (transistors M2-1 and M2-2) is turned on, and the inductor current ILX decreases. Thus, the absolute value of the connection point voltage VLX decreases along the slope 82.

  When the connection point voltage VLX becomes equal to or higher than the comparison voltage Vref1 of the third comparator 21 at time t13, the output Vd of the third comparator 21 is inverted to H level. In response to this, the latch circuit 22 latches H level, the output of the inverter 23 becomes L level, and the output of the AND gate 24 becomes L level. As a result, of the second switch M2, the transistor M2-2 having a relatively small on-resistance is turned off, and only the transistor M2-1 having a relatively large on-resistance is maintained in the on state. As a result, the slope 83 of the connection point voltage VLX switches to a steeper slope than the slope 82. Up to this point, the process is the same as in FIG.

  Since the second comparator 15 has a positive offset voltage Voffset (+), the inductor current ILX turns to a reverse flow at time t14, and at time t15, the second comparator 15 changes the connection voltage VLX to the offset voltage Voffset. (+) Or more is detected and detection signal Vs is set to H level. In response to this, the drive control circuit 14 sets the gate drive signal Vgl to the L level, and turns off the transistor M2-1 of the second switch M2. As a result, the inductor current ILX in the reverse direction is cut off.

  At time t15, the inductor current ILX is a value obtained by dividing the offset voltage Voffset (+) by the on-resistance of the transistor M2-1, and the on-resistance of the second switch M2 is larger than the case of the slope 82 as shown by the slope 83. Therefore, the inductor current ILX1 when the inductor current is cut off becomes smaller than the current at time t16 (current ILX1 in FIG. 5) reaching the offset voltage with the slope 82. That is, the time during which the reverse inductance current ILX flows wastefully can be shortened, and the power efficiency can be improved.

  FIG. 10 is a circuit diagram of the power supply device according to the second embodiment. The power supply device according to the second embodiment shown in FIG. 10 is different from the first embodiment shown in FIG. 7 in the configuration of the second switch M2. The other configuration is the same as in FIG. In the second embodiment shown in FIG. 10, the second switch M2 has a configuration in which a transistor M2-2 having a relatively low on-resistance, a resistor R3 and a switching transistor M2-3 are connected in series. Are provided in parallel between the connection point LX and the reference power supply voltage Vss.

  The operation waveforms of this power supply device are the same as those in FIGS. That is, when the drive control circuit 14 sets the gate drive signal Vgl to H level to turn on the second switch M2, both the transistors M2-2 and M2-3 are turned on. At this time, the low-side current IoutL, that is, the inductor current ILX flows to the transistor M2-2 side having a low on-resistance. First, the third comparator 21 detects that the connection point voltage VLX is equal to or higher than the comparison voltage Vref1, and sets the output Vd to H level. In response to this, the transistor M2-2 is turned off. Thereafter, the low-side current IoutL, that is, the inductor current ILX flows through the resistor R3 and the transistor M2-3, and the second comparator 15 detects that the connection point voltage VLX is equal to or higher than the offset voltage Voffset, and outputs the detection output Vc. Set to H level. In response to this, the drive control circuit 14 sets the gate drive signal Vgl to L level, turns off the transistor M2-3, and cuts off the inductor current ILX.

  By providing the resistor element R3, the transistor M2-3 only needs to have a function as a switch, and does not have to be a transistor having a large on-resistance.

  FIG. 11 is a circuit diagram of a power supply device according to the third embodiment. In the configuration of FIG. 7, the power supply device includes a comparator 25, a flip-flop 26, an inverter 27, a delay circuit 28, an inverter 29, and an AND gate 30 instead of the comparator units 15 and 21. The configuration of the second switch M2 includes transistors M2-1 and M2-2. However, the configuration of the second switch M2 in FIG. 10 may be used.

  In the power supply device of FIG. 11, one comparator 25 can take two threshold values according to the threshold control signal S25. The comparator 25 inputs the connection point voltage VLX to the plus input terminal and the comparison voltage Vref2 having a predetermined voltage to the minus input terminal. The comparator 25 has a threshold Vth2 when the threshold control signal S25 is L, and takes a threshold Vth1> Vth2 when the threshold control signal S25 is H level. The threshold value Vth1 is, for example, the reference power supply voltage Vss, and the threshold value Vth2 is the above-described comparison voltage Vref1.

  11, the flip-flop 26, the inverter 27, the delay circuit 28, the inverter 29, and the AND gate 30 detect that the comparator 25 has switched its output N1 to H level twice, and the detection signal Set Vc to H level.

  FIG. 12 is an operation waveform diagram according to the third embodiment. FIG. 12 shows the node voltage VLX after time t2 in FIG. 8, the signals of the nodes N1 to N4, the detection signal Vc, and the gate drive signal Vgl. First, when both the gate drive signals Vgh and Vgl are at the H level, the flip-flop 26 is reset, the node N1 as the output terminal Q is set to the L level, and the comparator 25 is reset to the threshold value Vth2.

  Then, the transistors M2-1 and M2-2 constituting the second switch M2 are turned on, the node voltage VLX becomes a negative potential, and the node voltage VLX becomes the reference power supply voltage Vss as the inductor current ILX decreases. Ascend toward. At time t3, the comparator 25 detects that the connection point voltage VLX is equal to or higher than the threshold voltage Vth2, and sets the output N1 to the H level. In response to this, the output N4 of the AND gate 24 becomes L level, and the transistor M2-2 is turned off. Further, the node N2, which is the output of the flip-flop 26, also becomes H level, and the comparator 25 is switched to the threshold value Vth1 by the threshold control signal S25 = H. In response to this switching, the output N1 of the comparator 25 returns to the L level at time t3a. Further, when the node N2 becomes the H level, the connection point voltage VLX greatly decreases primarily due to the large ON resistance of only the transistor M2-1.

  The H level of the node N2 goes through the inverter 27, the delay circuit 28, and the inverter 29, and the node N3 also becomes the H level after a predetermined delay time Del. However, when the node N3 becomes H level, the output N1 of the comparator 25 is already at L level, and the detection signal Vc that is the output of the AND gate 30 remains at L level.

  After time t3a, the node voltage VLX increases with the on-resistance slope of only the transistor M2-1. At time t5, when the connection point voltage VLX reaches the first threshold value Vth1, the comparator 25 sets its output N1 to the H level. In response to this, the output Vc of the AND gate 30 becomes H level, the drive control unit 14 sets the gate drive signal Vgl to L level, and the transistor M2-1 is also turned off. That is, the supply of forward inductor current ILX continues until time t5, which is later than time t4, and the power efficiency increases.

  In FIG. 12, when the threshold value Vth1 is on the plus side, the inductor current ILX in the reverse direction is quickly cut off as in FIG.

  In the power device in the third embodiment, the comparator 25 is configured to be able to take two threshold values, and has both functions of the second and third comparators 15 and 21 in FIG. The power consumption can be reduced.

  As described above, according to the power devices in the first, second, and third embodiments, the on-resistance of the second switch M2 is lowered to reduce the power consumption at the switch with respect to the low-side current IoutL. Since the timing at which the inductor current ILX changes from the forward direction to the reverse direction can be detected with high accuracy, the power efficiency can be improved.

  In the power supply device 10 shown in FIG. 1, the control unit 1 may be configured by an LSI, and the first and second switches M1 and M2, the inductor Lout, and the capacitor Cout may be externally configured. In that case, the second switch M2 is composed of two or more transistors as in the above embodiment, and all of the second switches M2 are externally attached or part of them are built in the LSI, and the comparator unit. Etc. are provided in the control unit 1.

  The above embodiment is summarized as follows.

(Appendix 1)
In a power supply device that converts an input voltage into a predetermined output voltage,
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit for detecting a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply and a second state in which the voltage of the connection node is equal to or higher than a comparison voltage lower than the voltage of the reference power supply; Have
The control unit increases the resistance of the second switch in response to the detection of the second state by the comparator unit, and responds to the detection of the first state by the comparator unit. A power supply device that turns off the switch 2.

(Appendix 2)
In Appendix 1,
The second switch has a plurality of transistors connected in parallel,
The control unit increases the resistance of the second switch by reducing the number of ON states of the plurality of transistors.

(Appendix 3)
In Appendix 1,
The second switch includes a first transistor provided between the connection node and the reference power supply, and a resistance element and a second transistor provided in series between the connection node and the reference power supply. And
The control unit increases the resistance of the second switch by changing both the first and second transistors from the on state to the first transistor.

(Appendix 4)
In Supplementary Note 1, the comparator unit inputs a voltage of the connection node and a voltage of the reference power supply to detect the first state, and inputs a voltage of the connection node and the comparison voltage. And a second comparator for detecting the second state.

(Appendix 5)
In Supplementary Note 1, the comparator unit is set to a second threshold value to detect the second state, and after detecting the second state, the comparator unit is set to the first threshold value to detect the first state Power supply.

(Appendix 6)
In a power supply device that converts an input voltage into a predetermined output voltage,
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit that detects a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply;
The control unit increases the ON resistance of the second switch after the comparator unit detects the first state after the first switch is turned OFF and the second switch is turned ON. A power supply device that turns off the second switch in response to the comparator unit detecting the first state.

(Appendix 7)
In Appendix 6,
The comparator unit detects a second state in which the voltage of the connection node is equal to or higher than a comparison voltage lower than the voltage of the reference power supply;
The control unit increases the on-resistance of the second switch in response to detection of the second state by the comparator unit.

(Appendix 8)
In Appendix 6,
The second switch has a plurality of transistors connected in parallel,
The control unit increases the resistance of the second switch by reducing the number of ON states of the plurality of transistors.

(Appendix 9)
In any one of appendices 1 to 8,
The power supply device, wherein the first switch is a P-channel transistor and the second switch is an N-channel transistor.

(Appendix 10)
A power supply control device for controlling a first switch and a second switch connected in series between an input voltage terminal and a reference power supply,
According to an output voltage generated through an inductor provided at a connection node of the first and second switches, the first and second switches are alternately turned on and off,
A comparator unit for detecting a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply and a second state in which the voltage of the connection node is equal to or higher than a comparison voltage lower than the voltage of the reference power supply; And
In response to the detection of the second state by the comparator unit, the resistance of the second switch is increased, and in response to the detection of the first state by the comparator unit, the second switch is turned off. Power control device to make.

(Appendix 11)
A power supply control device for controlling a first switch and a second switch connected in series between an input voltage terminal and a reference power supply,
According to an output voltage generated through an inductor provided at a connection node of the first and second switches, the first and second switches are alternately turned on and off,
A comparator for detecting a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply;
The control unit increases the ON resistance of the second switch after the first switch is turned OFF and the second switch is turned ON before the comparator detects the first state, A power supply control device that turns off the second switch in response to the comparator detecting the first state.

10: Power supply device 1: Control unit Vin: Input voltage In: Input voltage terminal Vout: Output voltage Out: Output terminal M1: First switch M2: Second switch Lout: Inductor LX: Connection node, connection point ILX: Inductor Current 14: Drive control circuit Vgh, Vgl: Gate drive signal 15: Comparator

Claims (5)

In a power supply device that converts an input voltage into a predetermined output voltage,
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit for detecting a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply and a second state in which the voltage of the connection node is equal to or higher than a comparison voltage lower than the voltage of the reference power supply; Have
The control unit increases the resistance of the second switch in response to the detection of the second state by the comparator unit, and responds to the detection of the first state by the comparator unit. A power supply device that turns off the switch 2. In Appendix 1,
The second switch has a plurality of transistors connected in parallel,
The control unit increases the resistance of the second switch by reducing the number of ON states of the plurality of transistors. In Supplementary Note 1, the comparator unit inputs a voltage of the connection node and a voltage of the reference power supply to detect the first state, and inputs a voltage of the connection node and the comparison voltage. And a second comparator for detecting the second state. In Supplementary Note 1, the comparator unit is set to a second threshold value to detect the second state, and after detecting the second state, the comparator unit is set to the first threshold value to detect the first state Power supply. In a power supply device that converts an input voltage into a predetermined output voltage,
A first switch and a second switch connected in series between an input voltage terminal and a reference power supply;
An inductor provided between a connection node and an output terminal of the first and second switches;
A control unit for alternately turning on and off the first and second switches according to the output voltage of the output terminal;
A comparator unit that detects a first state in which the voltage of the connection node is equal to or higher than the voltage of the reference power supply;
The control unit increases the ON resistance of the second switch after the comparator unit detects the first state after the first switch is turned OFF and the second switch is turned ON. A power supply device that turns off the second switch in response to the comparator unit detecting the first state.

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