JP2010269547A - Image forming apparatus and main scanning magnification correcting method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image forming apparatus capable of properly correcting the main scanning magnification without degrading the quality of print image, and a main scanning magnification correcting method therefor. <P>SOLUTION: The image forming apparatus carries out a pixel dividing modulation of input image signal into two or more bit data which show the emission or extinction of laser beam in a pixel corresponding to density by pixel unit. When correcting the gap of the scanning direction on one line scanned by the laser beam in a latent image carrier, the pixel data of new image of the one line is formed by inserting the bit data in the bit position, based on the attribute information showing the deviation of the bit data which shows the emission or extinction of the laser beam in the pixel corresponding to density, or by extracting the bit data from the bit position. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image forming apparatus and a main scanning magnification correction method thereof. That is, an input image signal is subjected to pixel division modulation, a laser light source is modulated and driven based on the pixel division modulated image signal, and the latent image carrier is scanned with laser light emitted from the laser light source. Thus, the present invention relates to an image forming apparatus that forms a latent image on a latent image carrier and a main scanning magnification correction method thereof.

  In general, in an image forming apparatus such as a laser beam printer or a digital copying machine, a semiconductor laser is driven by a laser beam driving circuit, and a laser beam emitted from the semiconductor laser is modulated by an image signal. The modulated laser beam is raster-scanned on the photosensitive drum by a rotating polygon mirror (polygon mirror) to form a latent image.

  Here, in an apparatus having a plurality of semiconductor lasers, the magnification of the latent image varies depending on each position on the photosensitive drum irradiated with the laser beam from each semiconductor laser. Further, since the surface accuracy of the polygon mirror is different, the writing position of the latent image is different for each surface. Further, in an image forming apparatus capable of double-sided printing, due to shrinkage of the paper size after fixing, the image size after printing differs even if the ratio of the latent image on both sides is the same.

  On the other hand, there has been proposed a method of correcting the image size to be printed by controlling the length between image data by adding an image clock for transferring image data at an arbitrary point (see Patent Document 1). ).

  However, in the above-described conventional example, the image data to be interpolated to correct the image clock is fixed, and a space is generated at a place where the image clock is slightly lengthened, which may impair the quality of the print image.

  In order to solve the above-described problem, for each correction point, the final bit of the pixel division modulated pixel data of the pixel located before the correction point is used as the pixel division modulated pixel of the pixel located at the correction point. A method of adding data as the first bit of data has been proposed (see Patent Document 2). For each pixel located after the correction point, the pixel data of the pixel that has been subjected to pixel division modulation is sequentially transferred to the next pixel in units of bits, thereby generating pixel data of a new pixel to be added on one line. To do. The generated pixel data of the new pixel is output in synchronization with an image clock having a fixed frequency.

JP 2000-238342 A JP 2004-351908 A

  However, in the method proposed in Patent Document 2, whether the bit data to be inserted is “0” or “1” depends on the last bit of the pixel data before the correction point. It may impair quality.

  An object of the present invention is to provide an image forming apparatus capable of appropriately correcting a main scanning magnification without degrading the quality of a print image, and a main scanning magnification correcting method thereof. It is another object of the present invention to provide an image forming apparatus capable of appropriately correcting a main scanning magnification by delaying a writing start position by a preset time and a main scanning magnification correcting method thereof.

  In view of the above problems, the image forming apparatus of the present invention performs pixel division modulation on an input image signal into a plurality of bit data indicating emission or extinction of laser light in a pixel corresponding to density in units of pixels, and A pixel division modulation means for outputting the image signal modulated by pixel division in synchronization with an image clock having a fixed frequency, a drive means for driving a laser light source based on the image signal outputted from the pixel division modulation means, and a latent image A scanning unit that scans the latent image carrier with laser light emitted from the laser light source so as to form a latent image on the carrier, wherein the pixel division modulation unit includes: Bit data indicating light emission or extinction of laser light in pixels corresponding to the density when correcting a shift in the scanning direction on one line scanned with the laser light on the latent image carrier Correction means for generating pixel data of a new pixel of the one line by inserting bit data into or extracting bit data from the bit position based on attribute information indicating bias; The pixel data of a new pixel is output in synchronization with the fixed frequency image clock.

  According to the present invention, pixel data of a new pixel to be added on one line is generated by inserting or extracting a bit at a position corresponding to the correction point attribute information, so that the quality of the print image is not degraded. The main scanning magnification can be corrected appropriately.

  Also, the print start ratio is corrected without degrading the print image quality by delaying the line start position with respect to the image start position signal for a preset time and adjusting the line to the same magnification within each line. There is an effect that can be done.

It is a correspondence diagram in the case where the density and the pulse position of a pulse in a data string subjected to 8-bit pixel division modulation are left-justified. FIG. 10 is a correspondence diagram in the case where the density and the pulse position of a pulse in a data string subjected to 8-bit pixel division modulation are in the center. It is a conceptual diagram which shows the structural example of the image signal in case the pulse position processed by the main scanning magnification correction process which concerns on this embodiment is left alignment or a center. It is a correspondence diagram in the case where the density and the pulse position of a pulse in a data string subjected to 8-bit pixel division modulation are right-justified. It is a conceptual diagram which shows the structural example of the image signal in case the pulse position processed by the main scanning magnification correction process which concerns on this embodiment is right alignment. FIG. 10 is a correspondence diagram when the density and the pulse position of a pulse in a data string subjected to 8-bit pixel division modulation are split. It is a conceptual diagram which shows the structural example of the image signal in case the pulse position processed by the main scanning magnification correction process which concerns on this embodiment is a split. 1 is a longitudinal sectional view schematically showing a configuration example of an image forming apparatus according to an embodiment. It is a block diagram which shows typically the structural example of the exposure control part which controls the exposure part 51 of FIG. FIG. 10 is a block diagram illustrating a configuration example of an image processing circuit 907 in FIG. 9 according to the first embodiment. 6 is a diagram illustrating a format example of pulse data LUT1007 according to Embodiment 1. FIG. 11 is a timing chart of main blocks when bit data is inserted in the image processing circuit of FIG. 10. 11 is a timing chart of main blocks when bit data is extracted in the image processing circuit of FIG. 10. FIG. 10 is a block diagram illustrating another configuration example of the image processing circuit in FIG. 9 according to the second embodiment. FIG. 10 is a block diagram illustrating another configuration of the image processing circuit in FIG. 9 according to the third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Principle of Main Scanning Magnification Correction Process in Present Invention>
First, the principle of main scanning magnification correction processing in the present invention will be described with reference to FIGS.

  In the main scanning magnification correction processing according to the present invention, for each of one or more correction points on one line scanned with a laser beam on the photosensitive drum, pixel division modulated pixel data of the pixel at the correction point is Insert or remove a bit at a position. In this way, pixel data of a new pixel added on the one line is generated. The position of the bit to be inserted or extracted (first bit, intermediate bit, final bit, etc.) is determined according to the attribute information of the correction point included in the image signal. The generated pixel data of the new pixel is output in synchronization with a fixed-frequency image clock. Here, the main scanning magnification means the width when scanning in the main scanning direction by the laser light on the photosensitive drum.

  1, 2, 4, and 6 show four different attributes of the correction point attribute information included in the image signal. The attribute information is a pulse position (in the exposure position). 3, 5, and 7 are conceptual diagrams illustrating a configuration example of an image signal processed by the main scanning magnification correction processing according to the present invention in correspondence with the attribute information. It should be noted that the pixel data constituting the image signal is composed of an 8-bit pixel-division modulated data sequence as shown in FIGS. 1 to 7, for example, and the pre-correction image data is 4 pixels per line. Suppose there is. Here, the first pixel and the third pixel on the same line are assumed as correction points in the main scanning magnification correction process.

<When the pulse position of attribute information is left justified or centered>
FIG. 1 shows an 8-bit pixel-division-modulated data string when the pulse position is left-justified. FIG. 2 shows an 8-bit pixel-division modulated data string when the pulse position is in the center. Here, “1” in the data string indicates emission of laser light from the laser light source, and “0” indicates extinction.

(Example of correction bit position in case of left alignment or center)
FIG. 3 is a diagram illustrating an example of bit insertion (upper figure), bit extraction (middle figure), bit insertion and extraction (lower figure) when the pulse position of the attribute information is left-justified or centered.

  The upper diagram of FIG. 3 shows how insertion correction is performed at the correction points. The last bit (index 8) of the pixel data subjected to the pixel division modulation of the first pixel and the third pixel is copied and inserted immediately after copying. As a result, valid bit data is shifted to the fifth pixel, and the invalid portion of the fifth pixel is filled with bit data “0”.

  The central view of FIG. 3 shows how the sampling correction is performed at the correction points. The last bit (index 8) of the pixel data subjected to the pixel division modulation of the first pixel and the third pixel is extracted. As a result, valid bit data ends in the middle of the fourth pixel, and the invalid portion of the fourth pixel is filled with bit data “0”.

  The lower diagram of FIG. 3 shows a state in which insertion correction is performed at the first pixel and sampling correction is performed at the third pixel among the correction points. The last bit (index 8) of the pixel data subjected to the pixel division modulation of the first pixel is copied and inserted immediately thereafter, and the last bit (index 8) of the pixel data subjected to the pixel division modulation of the third pixel is extracted. ing. As a result, it becomes plus or minus zero, and the number of valid bit data before and after correction does not change. Therefore, when viewed in the whole line, the main scanning width is the same before and after correction. However, if the first and second pixels are segment 0 and the third and fourth pixels are segment 1, the main scan width of segment 0 is enlarged after correction, and the main scan width of segment 1 is corrected after correction. Has been reduced.

  As described above, when the pulse position is left-justified or centered, the last bit (index 8) of pixel data subjected to pixel division modulation is operated. As a result, as can be seen from FIGS. 1 and 2, bit data “0” can always be inserted / extracted except in the case of 100% lighting (the lowest stage in FIGS. 1 and 2). Therefore, it is possible to appropriately correct the main operation magnification without degrading the quality of the print image.

<When the pulse position of attribute information is right-justified>
FIG. 4 shows an 8-bit pixel-division modulated data string when the pulse position is right-justified.

(Example of correction bit position for right alignment)
FIG. 5 is a diagram illustrating an example of bit insertion (upper figure), bit extraction (center figure), bit insertion and extraction (lower figure) when the pulse position of the attribute information is right-justified.

  The upper diagram of FIG. 5 shows how insertion correction is performed at the correction points. The first bit (index 1) of the pixel data subjected to the pixel division modulation of the first pixel and the third pixel is copied and inserted immediately after copying. As a result, valid bit data is shifted to the fifth pixel, and the invalid portion of the fifth pixel is filled with bit data “0”.

  The central view of FIG. 5 shows how the sampling correction is performed at the correction points. The first bit (index 1) of the pixel data subjected to the pixel division modulation of the first pixel and the third pixel is extracted. As a result, valid bit data ends in the middle of the fourth pixel, and the invalid portion of the fourth pixel is filled with bit data “0”.

  The lower diagram of FIG. 5 shows a state in which insertion correction is performed at the first pixel and sampling correction is performed at the third pixel among the correction points. The first bit (index 1) of the pixel data subjected to the pixel division modulation of the first pixel is copied and inserted immediately thereafter, and the first bit (index 1) of the pixel data subjected to the pixel division modulation of the third pixel is extracted. (The lowermost stage in FIGS. 1 and 2). As a result, it becomes plus or minus zero, and the number of valid bit data before and after correction is not changed. Therefore, when viewed in the whole line, the main scanning width is the same before and after correction. However, if the first and second pixels are segment 0 and the third and fourth pixels are segment 1, the main scan width of segment 0 is enlarged after correction, and the main scan width of segment 1 is corrected after correction. Has been reduced.

  As described above, when the pulse position is right-justified, the first bit (index 1) of pixel data subjected to pixel division modulation is manipulated. Accordingly, as can be seen from FIG. 4, the bit data “0” can always be inserted / extracted except in the case of 100% lighting (the lowermost stage in FIG. 4). Therefore, it is possible to appropriately correct the main operation magnification without degrading the quality of the print image.

<When the attribute information pulse position is split>
FIG. 6 shows an 8-bit pixel-division modulated data sequence when the pulse position is split.

(Example of correction bit position for split)
FIG. 7 is a diagram illustrating an example of bit insertion (upper figure), bit extraction (center figure), bit insertion and extraction (lower figure) in the case of a split in which the pulse position of the attribute information is biased toward both ends of the pixel.

  The upper diagram of FIG. 7 shows how insertion correction is performed at the correction points. An intermediate bit (index 4) of pixel data subjected to pixel division modulation of the first pixel and the third pixel is copied and inserted immediately after copying. As a result, valid bit data is shifted to the fifth pixel, and the invalid portion of the fifth pixel is filled with bit data “0”.

  The center diagram of FIG. 7 shows how the sampling correction is performed at the correction points. An intermediate bit (index 4) of the pixel data subjected to the pixel division modulation of the first pixel and the third pixel is extracted. As a result, valid bit data ends in the middle of the fourth pixel, and the invalid portion of the fourth pixel is filled with bit data “0”.

  The lower diagram of FIG. 7 shows a state in which insertion correction is performed at the first pixel and sampling correction is performed at the third pixel among the correction points. The intermediate bit (index 4) of the pixel data subjected to the pixel division modulation of the first pixel is copied and inserted immediately thereafter, and the intermediate bit (index 4) of the pixel data subjected to the pixel division modulation of the third pixel is extracted. ing. As a result, it becomes plus or minus zero, and the number of valid bit data before and after correction is not changed. Therefore, when viewed in the whole line, the main scanning width is the same before and after correction. However, if the first and second pixels are segment 0 and the third and fourth pixels are segment 1, the main scan width of segment 0 is enlarged after correction, and the main scan width of segment 1 is corrected after correction. Has been reduced.

  As described above, in the case of split, an intermediate bit (index 4) of pixel data subjected to pixel division modulation is manipulated. Accordingly, as can be seen from FIG. 6, the bit data “0” can always be inserted / extracted except in the case of 100% lighting (the lowest stage in FIG. 6). Therefore, it is possible to appropriately correct the main operation magnification without degrading the quality of the print image.

  Although not shown in FIGS. 3, 5, and 7, the pulse position that is the attribute information may be switched for each pixel in the middle of the page or line.

  As described above, in this example, the number of effective bit data in one line can be increased or decreased by the main scanning magnification correction process, and the main scanning magnification can be corrected.

[Embodiment 1]
<Example of Configuration of Image Forming Apparatus of Present Embodiment>
Next, a specific configuration of the image forming apparatus of the present embodiment capable of executing the main scanning magnification correction process will be described with reference to FIGS.

(Configuration example of image forming apparatus of this embodiment)
FIG. 8 is a longitudinal sectional view schematically showing the configuration of the image forming apparatus according to the present embodiment.

  As shown in FIG. 8, the image forming apparatus according to the present embodiment corresponds to, for example, a four-drum type color laser beam printer. In this color image forming apparatus, a transfer material cassette 53 is mounted on the lower part of the right side surface of the main body apparatus. The transfer material set in the transfer material cassette 53 is taken out one by one by the paper feed roller 54 and fed to the image forming unit by the pair of transport rollers 55-a and 55-b. In the image forming unit, a transfer conveyance belt 10 that conveys a transfer material is flattened in a transfer material conveyance direction (from right to left in FIG. 8) by a plurality of rotating rollers. Is electrostatically attracted to the transfer conveyance belt 10. Further, four photosensitive drums 14-C, 14-Y, 14-M, and 14-K as the latent image bearing members in the form of drums are arranged in a straight line so as to face the belt conveying surface, and the image. The forming part is configured.

  The developing units 52-C, 52-Y, 52-M, and 52-K, which are image forming units, include the photosensitive drum, C (CYAN), Y (YELLOW), M (MAGENTA), and K (BLACK). Each color toner, a charger, and a developer. A predetermined gap is provided between the charger and the developer in the housing of each of the developing units 52-C, 52-Y, 52-M, and 52-K. Through this gap, the peripheral surface of the photosensitive drum 14 is uniformly charged with a predetermined charge from the exposure units 51-C, 51-Y, 51-M, 51-K made of a laser scanner. The exposure sections 51-C, 51-Y, 51-M, 51-K expose the peripheral surfaces of the charged photosensitive drums 14-C, 14-Y, 14-M, 14-K according to image information. Thus, an electrostatic latent image is formed on the latent image carrier. Then, the developing device transfers the toner to the blackout portion of the electrostatic latent image and develops a toner image (development).

  Transfer members 57-C, 57-Y, 57-M, and 57-K are arranged across the conveyance surface of the transfer conveyance belt 10. A transfer electric field is formed by the transfer members 57-C, 57-Y, 57-M, and 57-K corresponding to the photosensitive drums 14-C, 14-Y, 14-M, and 14-K. Due to this transfer electric field, the toner images formed (developed) on the peripheral surfaces of the photosensitive drums 14-C, 14-Y, 14-M, and 14-K are charged with the charges generated on the transferred transfer material. It is absorbed and transferred to the transfer material surface. The transfer material onto which the toner image has been transferred is fixed on the transfer material by the fixing device 58, and is then discharged out of the apparatus by a pair of discharge rollers 59-a and 59-b. The transfer / conveying belt 10 may be an intermediate transfer belt configured to temporarily transfer each color toner of C (CYAN), Y (YELLOW), M (MAGENTA), and K (BLACK) to a transfer material. Absent.

(Configuration example of exposure control unit)
FIG. 9 is a block diagram schematically showing a configuration of an exposure control unit that controls the exposure unit 51 of FIG. In the following description, one color among C (CYAN), Y (YELLOW), M (MAGENTA), and K (BLACK) will be representatively described. Therefore, the reference numbers are numbers other than -C, -Y, -M, and -K.

  Laser light generated by the path shown in FIG. 9 is incident on the exposure unit 51.

  The image processing circuit 907 performs pixel division modulation on the image signal 1057 input from the outside into a plurality of bit data indicating light emission or extinction of laser light in the pixel corresponding to the density in units of pixels. Then, the pixel division modulated image signal 1073 is output in synchronization with the image clock. The laser drive unit 906 drives the semiconductor laser 901 based on the pixel division modulated image signal 1073 output from the image processing circuit 907.

  Inside the semiconductor laser 901, a photodiode sensor (PD sensor; not shown) for detecting a part of the laser beam is provided. The laser driving unit 906 performs APC (Auto Power Control) control of the semiconductor laser 901 using the detection signal of the PD sensor. Laser light emitted from the semiconductor laser 901 becomes substantially parallel light via an optical system having a collimator lens 902 and a diaphragm, and enters a polygon mirror (rotating polygon mirror) 903 with a predetermined beam diameter.

  The polygon mirror 903 rotates at a constant angular velocity in a predetermined direction, and the laser light incident on the polygon mirror 903 along with this rotation is reflected as a deflected beam that continuously changes its angle. The laser beam reflected as a deflected beam is focused by the f-θ lens 904. At the same time, the f-θ lens 904 corrects distortion so as to guarantee the temporal linearity of scanning, so that the laser light that has passed through the f-θ lens 904 is directed onto the photosensitive drum 14 in a predetermined direction. Combined scanning is performed at a constant speed. A beam detect sensor 905 that detects the laser beam reflected from the polygon mirror 903 is provided in the vicinity of one end of the photosensitive drum 14. The detection signal of this sensor is used as a synchronization signal for synchronizing the rotation of the polygon mirror 903 and the data writing.

  In such a laser driving unit 906, in order to keep the amount of laser light during one scanning constant, the output of the laser light is detected in the light detection section during one scanning, and the driving current of the semiconductor laser 901 is set to 1. A drive system is used in which the image is held during scanning.

  In this embodiment, the main scanning magnification correction control unit 908 detects a variation in magnification in the main scanning direction based on the rotation signal of the polygon mirror 903, the detection signal of the beam detect sensor 905, and the like. Then, the main scanning magnification correction in the image processing circuit 907 is executed by the correction control signal 909 for the correction. The present invention relates to how pixels are inserted / extracted in the image processing circuit 907. Means for detecting variation in magnification in the main scanning direction and generation of the correction control signal 909 in the main scanning magnification correction control unit 908 are means. Because it is not, detailed explanation is omitted.

(Configuration Example of Image Processing Circuit of Embodiment 1)
FIG. 10 is a block diagram showing a configuration of the image processing circuit 907 of FIG.

  The image processing circuit 907 includes a control signal generation circuit 1001 that receives a correction control signal 909 from the main scanning magnification correction control unit 908 as shown in FIG. The control signal generation circuit 1001 generates a bit data insertion / extraction position signal (FIFO control signal) 1052 from the correction amount of the correction control signal 909 and the like. The bit data insertion / extraction position signal 1052 is input to a FIFO (First In-First Out Memory) clock generation circuit 1003 and a parallel-serial (hereinafter abbreviated as PS) conversion / bit data insertion / extraction circuit 1008. . The control signal generation circuit 1001 generates an insertion / extraction selection signal 1050 for the conversion / bit data insertion / extraction circuit 1008. The control signal generation circuit 1001 generates an SP conversion control signal 1053 for a serial-parallel (hereinafter abbreviated as “SP”) clock generation circuit 1004.

  The FIFO clock generation circuit 1003 generates a read clock 1054 based on the reference clock (refclk) 1051 and the bit data insertion / extraction position signal (FIFO control signal) 1052. The read clock 1054 is input to the FIFO 1002, the delay time generation circuit 1005, the pulse data LUT (Look Up Table) 1007, and the LUT address generation circuit 1006. The SP clock generation circuit 1004 generates an SP conversion clock 1055 for the SP conversion circuit 1009 based on the reference clock 1051 and the SP conversion control signal 1053. The SP conversion clock 1055 is output from the image processing circuit 907 as an image clock.

  The FIFO 1002 is supplied with a reset 1058, a FIFO write signal 1056, and a write clock 1059 from a main body control unit (not shown). At the same time, in this example, a 6-bit image signal (data) 1057 is input from an external image generation unit (not shown) in units of pixels. The upper 2 bits of the image signal 1057 are attribute values representing pulse positions, and the lower 4 bits are pixel values that have undergone halftone processing. That is, 6-bit write pixel data 1057 is input to the FIFO 1002. From the FIFO 1002, 6-bit read pixel data (data) 1061 is output by the read clock 1054 from the FIFO clock generation circuit 1003 and the FIFO read signal 1060 from the delay time generation circuit 1005.

  In this example, there are four types of pulse positions, which are attribute information, center, right justification, left justification, and split, so they can be represented by 2 bits. Further, since the pulse data of one pixel is 16 bits, the pixel value can be represented by 4 bits. However, if the type of attribute or the number of bits of pulse data for one pixel changes, the number of bits of the attribute value or pixel value also changes.

  The read pixel data (data) 1061 output from the FIFO 1002 is input to the delay time generation circuit 1005. The delay time generation circuit 1005 adjusts the FIFO read signal 1060 according to the delay time 1063 designated by the main body control unit (not shown) with reference to the BD signal 1062 output from the BD sensor 905 (not shown). . Then, after a delay time 1063 designated by the main body control unit with the BD signal 1062 as a reference, pixel data (pixel value 1065 and pulse position 1066) and a pixel data valid signal 1064 are input to the LUT address generation circuit 1006. .

  The LUT address generation circuit 1006 sends the pixel value 1065 and the pulse position 1066 as the address (addr) 1067 to the pulse data LUT 1007 based on the pixel data valid signal 1064 input from the delay time generation circuit 1005. Then, 16-bit pulse data 1068 is read from the pulse data LUT1007.

(Configuration example of pulse data LUT1007)
FIG. 11 is a diagram showing a configuration example of the pulse data LUT 1007 in FIG.

  As shown in FIG. 11, the pulse data LUT 1007 stores 16-bit pulse data 1102 for a 4-bit pixel value for each of four types of pulse positions 1101a. The pulse position 1066 indicates the center at 2'b00 (binary), right justified at 2'b01, left justified at 2'b10, and split at 2'b11. Then, the pulse data LUT address 1067 may be a 6-bit signal in which the pulse position 1066 is the upper 2 bits and the 16-level pixel value 1065 is the lower 4 bits.

  The pulse data LUT 1007 may be implemented by a ROM (Read Only Memory). Further, it may be implemented by a RAM (Random Access Memory) and write pulse data from a main body control unit (not shown).

  The 16-bit LUT output pulse data 1068 from the pulse data LUT 1007 is input to the PS conversion / bit data insertion / extraction circuit 1008 as pulse data (pix) 1070 in synchronization with the pulse data valid signal (valid) 1069. At the same time, the pulse position 1071 (atr) is also input to the PS conversion / bit data insertion / extraction circuit 1008.

  The PS conversion / bit data insertion / removal circuit 1008 converts the 16-bit pulse data 1070 input from the LUT address generation circuit 1006 into a serial pixel signal using a PS conversion clock (reference clock) 1051. At the same time, the correction point is determined based on the bit data insertion / extraction position signal 1052 input from the control signal generation circuit 1001, and bit data is inserted or extracted based on the insertion / extraction selection signal 1050. At this time, referring to the pulse position 1071 of the pixel data as described above, the position where the bit data of the pixel data subjected to the pixel division modulation of the pixel at the correction point is inserted / extracted is determined.

  The serial pixel signal 1072 into which the bit data has been inserted or extracted is input to the SP conversion circuit 1009. The SP conversion circuit 1009 converts the input serial pixel signal 1072 into a 16-bit parallel pixel signal 1073 using the SP conversion clock 1055 and outputs the converted signal.

<Operation Example of Image Processing Circuit of Present Embodiment>
Next, an operation example of the image processing circuit 907 will be described with reference to FIGS. In FIGS. 12 and 13, in order to illustrate the insertion of bit data having different pulse positions, a special example in which insertion or extraction is continuously performed with three pixels will be described. However, in actuality, the number of pixels inserted or extracted by the control signal generation circuit 1001 or the number of inserted or extracted pixels based on the magnification correction amount in the main scanning direction included in the correction control signal 909 from the main scanning magnification correction control unit 908. A pixel position is determined. The determination of the number of pixels and the pixel position may also be configured by an LUT having the magnification correction amount as an address. Further, in order to control a device having a plurality of main scanning pixels, the number of main scanning pixels or the upper bits thereof may be included in the address. Note that the number of pixels and the pixel position may be determined by the main scanning magnification correction control unit 908.

<Operation example of bit data insertion>
FIG. 12 is a timing chart of main blocks when bit data is inserted in the image processing circuit of FIG.

  A reference clock (PS conversion clock) 1051 (shown in FIG. 12A) is a signal serving as a reference for the next clock. That is, it becomes a reference for a read clock (FIFO Read clock / RAM Read clock) 1054 (shown in FIG. 12B) and an image clock (SP conversion clock) 1055 (shown in FIG. 12F). The reference clock 1051 has a frequency proportional to the resolution of the pixel division modulation (the number of divisions = the number of bits) in which the density of one pixel is expressed by bits of a plurality of division regions with respect to the frequency of the SP conversion clock 1055 serving as an image clock. . In this embodiment, the resolution of pixel division modulation is 16 bits, and the frequency of the reference clock 1051 is set to 16 times the SP conversion clock 1055.

  A bit data insertion / extraction position signal 1052 (shown in FIG. 12 (d)) designates a pixel position for insertion or extraction of a bit, and an insertion / extraction selection signal 1050 (not shown in FIG. 12) is inserted or extracted. Specifies insertion at the specified pixel location.

  A read clock (FIFO Read clock / RAM Read clock) 1054 is a clock for instructing the timing of reading pixel data from the FIFO 1002 and the pulse data LUT 1007 in units of one pixel. The FIFO clock generation circuit 1003 counts the reference clock 1051 for 16 pixels that are not inserted or removed, and generates one read clock 1054. The read clock 1054 has a timing for one bit so that the last bit of the previous pixel arrives at the first bit of the next output pixel when reading the next pixel of the pixel in which the data is inserted at the time of data insertion. Delay. As shown in FIG. 12B, normally, a broken-line clock is a solid-line clock. Thereafter, the same period of 16 bits (16 counts) is used until the bit insertion is performed again within the pixel. However, in the example of FIG. 12, in order to explain the insertion process with different attributes, a special example in which different attribute information is inserted continuously for three pixels as described above is shown.

  By delaying the readout clock 1054 by one bit as described above, PS output data (serial pixel signal) 1072 (shown in FIG. 12E) is the first bit of the pixel next to the pixel where bibit insertion is performed. Is controlled not to be updated.

  The PS conversion / bit data insertion / extraction circuit 1008 inserts a bit at the bit position corresponding to the pulse position of the designated pixel when the pulse data 1070 (shown in FIG. 12C) is parallel / serial converted. To implement. This bit insertion is controlled by a 2-bit pulse position 1071, a bit data insertion / extraction position signal 1052, and an insertion / extraction selection signal 1050.

  The SP conversion clock 1055 (shown in (f) of FIG. 12) is output as an image clock defining one pixel section at a frequency 1/16 of the reference clock 1051. With this SP conversion clock 1055, PS output data (serial pixel signal) 1072 into which bit data has been inserted is converted into 16-bit SP output data (parallel pixel signal) 1073 (shown in FIG. 12G) and output. Is done. Accordingly, in the SP output data (parallel pixel signal) 1073, the bit pattern of the pixel data is shifted to the subsequent pixel by the number of inserted bits.

(Insertion process when the pulse position is in the center)
When the pulse position is in the center, PS output data (serial pixel signal) 1072 is output by copying the rightmost bit of the pixel into which bit insertion is performed. Since the last bit of the pixel to which bit insertion is performed is output without being updated even when it is the first bit of the next output pixel, the last bit is shifted to the first bit of the next output pixel. As shown in FIG. 12C, the 16-bit pixel data at the bit insertion position output from the pulse data LUT1007 is “0000001111000000”, and the next pixel data is “1111000000001111”. In this case, as shown in FIG. 12G, the pixel data output from the SP conversion circuit 1009 does not change the pixel data at the bit insertion position, but the next pixel data begins with “01111000... 0 ”is inserted.

(Insertion process when the pulse position is split)
When the pulse position is split, PS output data (serial pixel signal) 1072 is output by copying the center bit of the pixel into which bit insertion is performed. Also in this case, since the pulse data 1070 is output without being updated at the first bit of the next output pixel, the last bit is shifted to the first bit of the next output pixel. As shown in FIG. 12C, the 16-bit pixel data at the bit insertion position output from the pulse data LUT1007 is “1111000000001111”, and the next pixel data is “0000000000001111”. In this case, the pixel data output from the SP conversion circuit 1009 is also inserted at the previous pixel as shown in FIG. Therefore, the pixel data “0111100000000011” at the insertion position and “0” are shifted from the previous pixel at the beginning and “0” is inserted at the center, and the next pixel data is “11000000…” and the previous pixel at the beginning. "11" is shifted from.

(Insertion process when the pulse position is right-justified)
When the pulse position is right-justified, PS output data (serial pixel signal) 1072 is output by copying the leftmost bit of the pixel into which bit insertion is performed. Also in this case, since the pulse data 1070 is output without being updated at the first bit of the next output pixel, the last bit is shifted to the first bit of the next output pixel. As shown in FIG. 12C, the 16-bit pixel data at the bit insertion position output from the pulse data LUT 1007 is set to “0000000000001111”. In this case, the pixel data output from the SP conversion circuit 1009 is also inserted with the previous two pixels as shown in FIG. Therefore, the pixel data “1100000000000001” at the insertion position and “11” from the previous pixel are shifted to the top, “0” is inserted at the left end, and “111” at the right end is shifted to the next pixel data. .

  As described above, since the insertion bit is always “0”, magnification correction in the main scanning direction can be performed without degrading the quality of the output image.

<Operation example of bit data extraction>
FIG. 13 is a timing chart of main blocks when bit data is extracted in the image processing circuit of FIG.

  A reference clock (PS conversion clock) 1051 (shown in FIG. 13A) is a signal serving as a reference for the next clock. That is, it becomes a reference for a read clock (FIFO Read clock / RAM Read clock) 1054 (shown in FIG. 13B) and an image clock (SP conversion clock) 1055 (shown in FIG. 13F). The reference clock 1051 has a frequency proportional to the resolution of the pixel division modulation (the number of divisions = the number of bits) in which the density of one pixel is expressed by bits of a plurality of division regions with respect to the frequency of the SP conversion clock 1055 serving as an image clock. . In this embodiment, the resolution of pixel division modulation is 16 bits, and the frequency of the reference clock 1051 is set to 16 times the SP conversion clock 1055.

  A bit data insertion / extraction position signal 1052 (shown in FIG. 13 (d)) designates a pixel position for insertion or extraction of a bit, and an insertion / extraction selection signal 1050 (not shown in FIG. 13) is inserted or extracted. Specifies sampling at a specified pixel position.

  A read clock (FIFO Read clock / RAM Read clock) 1054 is a clock for instructing the timing of reading pixel data from the FIFO 1002 and the pulse data LUT 1007 in units of one pixel. The FIFO clock generation circuit 1003 counts the reference clock 1051 for 16 pixels that are not inserted or removed, and generates one read clock 1054. The readout clock 1054 has a timing for one bit so that the first bit of the next output pixel reaches the last bit of the previous pixel when reading the next pixel of the pixel from which data has been extracted at the time of data extraction. Make it fast. As shown in FIG. 13B, normally, a broken-line clock is a solid-line clock. Thereafter, the same period of 16 bits (16 counts) is used until the bit extraction is performed again within the pixel. However, in the example of FIG. 13, in order to explain the insertion process with different attributes, a special example in which different attribute information is extracted continuously for three pixels as described above is shown.

  As described above, the PS output data (serial pixel signal) 1072 (shown in (e) of FIG. 13) is updated with the last bit of the pixel from which bibit extraction is performed by increasing the read clock 1054 by one bit. To control.

  The PS conversion / bit data insertion / extraction circuit 1008 extracts the bit at the bit position corresponding to the pulse position of the designated pixel when the pulse data 1070 (shown in FIG. 13C) is parallel / serial converted. To implement. This bit extraction is controlled by a 2-bit pulse position 1071, a bit data insertion / extraction position signal 1052, and an insertion / extraction selection signal 1050.

  The SP conversion clock 1055 (shown in (f) of FIG. 13) is output as an image clock defining one pixel section at a frequency 1/16 of the reference clock 1051. By this SP conversion clock 1055, the PS output data (serial pixel signal) 1072 from which bit data has been extracted is converted into 16-bit SP output data (parallel pixel signal) 1073 (shown in FIG. 13G) and output. Is done. Accordingly, in the SP output data (parallel pixel signal) 1073, the bit pattern of the pixel data is shifted to the previous pixel by the number of extracted bits.

(Sampling process when the pulse position is in the center)
When the pulse position is in the center, PS output data (serial pixel signal) 1072 is extracted from the rightmost bit of the pixel from which bit extraction is performed. Since the pulse data 1070 is updated at the last bit of the pixel from which bit extraction is performed, the first bit of the next output pixel is shifted to the last bit of the pixel from which bit extraction has been performed. As shown in FIG. 13C, the 16-bit pixel data of the bit extraction position output from the pulse data LUT1007 is “0000001111000000”, and the next pixel data is “1111000000001111”. In this case, as shown in (g) of FIG. 13, the pixel data output from the SP conversion circuit 1009 is shifted from the next pixel data to “0000001111000001” and “1” in the pixel data at the bit sampling position. The pixel data is “11100000...”.

(Sampling process when the pulse position is split)
When the pulse position is split, PS output data (serial pixel signal) 1072 is output with the bit extracted at the center bit of the pixel where the bit is inserted. Also in this case, since the pulse data 1070 is updated at the last bit of the pixel from which bit extraction is performed, the first bit of the next output pixel is shifted to the last bit of the pixel from which bit extraction has been performed. As shown in FIG. 13C, the 16-bit pixel data at the bit sampling position output from the pulse data LUT 1007 is “1111000000001111”, and the next pixel data is “0000000000001111”. In this case, the pixel data output from the SP conversion circuit 1009 is affected by sampling at the previous pixel as shown in FIG. Therefore, the pixel data “1110000000111100” and the first bit “1” at the sampling position are shifted out to the previous pixel, the center “0” is extracted, and “00” is shifted in from the next pixel to the right end. The

(Sampling process when the pulse position is right-justified)
When the pulse position is right-justified, PS output data (serial pixel signal) 1072 is extracted from the leftmost bit of the pixel from which bit extraction is performed. Also in this case, since the pulse data 1070 is updated at the last bit of the pixel from which bit extraction is performed, the first bit of the next output pixel is shifted to the last bit of the pixel from which bit extraction has been performed. As shown in FIG. 13C, the 16-bit pixel data at the bit sampling position output from the pulse data LUT 1007 is set to “0000000000001111”. In this case, the pixel data output from the SP conversion circuit 1009 is also considered for sampling at the previous two pixels as shown in FIG. Therefore, the pixel data “0000000001111xxx” at the sampling position and the leading “00” are shifted to the previous pixel and “0” is extracted from the left end portion, and the next pixel data “xxx” is shifted into the right end portion. The

  As described above, since the sampling bit is always “0”, magnification correction in the main scanning direction can be performed without degrading the quality of the output image.

  Although the example of the combination is not shown in the above example of insertion / extraction, those skilled in the art will understand from the above example of insertion / extraction.

<Specific example of main scanning magnification correction processing of this embodiment>
Next, a specific example by the main scanning magnification correction process in the present embodiment will be described.

  In this embodiment, one pixel is 16-bit data, and the number of pixels in one line is 4960 dots (corresponding to a printing resolution of 600 dpi and an effective printing area of 210 mm).

(When expanding the overall magnification)
For example, when it is necessary to extend about 0.2 inches in the main scanning direction, it is assumed that 1 bit is inserted in pixels for 124 dots. Since one pixel is 16-bit data, it is necessary to insert bit data 1984 times (= 124 × 16). That is, bit data may be inserted into 1984 dots out of 4960 dots.

  Here, consider a case where 4960 dots in the main scanning direction are divided into 16 segments and each segment is processed. In this case, the width of one segment is 310 dots (= 4960/16), and the number of dots into which bit data is inserted in one segment is 1984/16 = 124 dots. That is, bit data is inserted into 124 dots out of 310 dots of one segment width. As for specific insertion positions, when bit data is inserted into 310 dots on an average basis, 310/124 = 2.5, so that insertion is performed once every two dots and once every three dots. Will be repeated alternately.

  In addition, a configuration in which bit data insertion positions are randomly scattered for each line without changing the number of insertions and insertion frequency of bit data in the line is also conceivable (also shown in the fifth embodiment below). By doing so, the bit data is uniformly inserted over the entire row of 4960 dots, and furthermore, the arrangement of the inserted bit data becomes random, so that it is possible to prevent deterioration in image quality due to regular changes. . If it makes a table, it becomes like Table 1.

  This indicates how many bits out of 310 dots of one segment width are to be inserted with bit data. + Indicates bit data insertion. Further, seg0 (segment 0) is the left end of the paper, and seg15 (segment 15) is the right end of the paper.

(When reducing the overall magnification)
For example, when it is necessary to shorten about 0.2 inches in the main scanning direction, it is assumed that one bit is extracted from pixels for 124 dots. This is essentially the same as the case of enlarging the overall magnification, and bit data is extracted from 124 dots out of 310 dots in one segment width.

  The correction amount is shown in Table 2.

  This indicates how many bits out of 310 dots of one segment width are to be extracted. -Indicates extraction of bit data. Further, seg0 (segment 0) is the left end of the paper, and seg15 (segment 15) is the right end of the paper.

(When performing partial magnification correction)
For example, from a rotation of the polygon mirror 903 or an image formed on the photosensitive drum 14, a correction amount calculation unit (not shown) is obtained from information stored in a deviation amount storage unit (not shown) of the main scanning magnification correction control unit 908. ) Calculates the partial magnification correction amount. In the present embodiment, the actual main scanning line measured at a plurality of points and the deviation amount of the ideal main scanning line in the main scanning direction are stored in the deviation amount storage unit as information indicating the distortion of the main scanning line. The information stored in the deviation amount storage unit may be configured to measure the deviation amount and store it as information unique to the apparatus in the manufacturing process of the apparatus. Alternatively, a detection mechanism for detecting the shift amount is prepared in the apparatus itself, a predetermined pattern for measuring the shift is formed for each color image carrier, and the shift amount detected by the detection mechanism is stored. Such a configuration may be used.

  When dividing 4960 dots in the main scanning direction into 16 segments, the correction amount calculation unit calculates, for example, correction amount information as shown in Table 3 below as the partial magnification correction amount.

  This indicates how many dots out of 310 dots of one segment width are to be inserted or extracted. + Indicates insertion of bit data, and-indicates extraction of bit data. Further, seg0 (segment 0) is the left end of the paper, and seg15 (segment 15) is the right end of the paper. In this example, as shown in Table 3, when the number of bit data insertions and the number of bit data extractions are equal, the overall magnification correction is not performed.

(When performing overall magnification enlargement and partial magnification correction)
When enlarging the overall magnification by inserting bit data, it was necessary to insert bit data into 124 dots out of 310 dots per segment width. The sum obtained by adding the correction amount in the case of performing the partial magnification correction shown in Table 3 is the correction amount of this example, as shown in Table 4.

  This indicates how many dots out of 310 dots of one segment width are to be inserted or extracted. + Indicates insertion of bit data, and-indicates extraction of bit data. Further, seg0 (segment 0) is the left end of the paper, and seg15 (segment 15) is the right end of the paper. As in this example, a more precise magnification correction can be performed by distinguishing and superimposing a plurality of tendencies.

(When performing overall magnification reduction and partial magnification correction)
This is essentially the same as when full magnification enlargement and partial magnification correction are performed. The sum of the correction amount for the overall magnification reduction and the correction amount for the partial magnification correction is the correction amount of this example, and is shown in Table 5.

  This indicates how many dots out of 310 dots of one segment width are to be inserted or extracted. + Indicates insertion of bit data, and-indicates extraction of bit data. Further, seg0 (segment 0) is the left end of the paper, and seg15 (segment 15) is the right end of the paper. As in this example, a more precise magnification correction can be performed by distinguishing and superimposing a plurality of tendencies.

  The above five examples show typical examples of magnification correction in the main scanning direction, but are not limited thereto. It is also conceivable to add three or more correction amounts corresponding to the tendency of a plurality of deviation amounts.

[Embodiment 2]
(Configuration Example of Image Processing Circuit of Embodiment 2)
The image processing circuit 907 can also be configured as shown in FIG.

  In the figure, the description of the same reference numerals as those in FIG. 10 is omitted.

  In FIG. 14, when 16-bit pulse data is generated from a 4-bit pixel value, the pulse data generation circuit 1010 is used instead of referring to the pulse data LUT 1007 as shown in the first embodiment. Yes.

  The pulse data generation circuit 1010 generates pulse data 1070 from the pixel value 1065 and the pulse position 1066. The generated pulse data 1070 is input to the PS conversion / bit data insertion / extraction circuit 1008 together with the pulse position 1071 in synchronization with the pulse data valid signal 1069.

[Embodiment 3]
(Configuration Example of Image Processing Circuit of Embodiment 3)
The image processing circuit 907 can be further configured as shown in FIG.

  In the figure, the description of the same reference numerals as those in FIG. 10 is omitted.

  In the configuration of FIG. 15, the data bit width of the FIFO 1002 is 18 bits. Write pixel data 1057 input from the external image generation unit (not shown) to the FIFO 1002 is 6-bit pixel data as shown in the first and second embodiments (2 bits are pulse positions, 4 bits are pixel values). )is not. In this embodiment, it is 18-bit pixel data (2 bits are pulse positions and 16 bits are pulse data).

  Therefore, hardware (LUT address generation circuit 1006, pulse data LUT 1007, pulse data generation circuit 1010) for generating pulse data from pixel values is not necessary.

[Other Embodiments]
The FIFO clock generation circuit 1003 can delay the read clock 1054 for a predetermined time with respect to the reference signal when it is initially generated in units of the reference clock 1051 period. As a result, a delay time can be generated in units of the reference clock 1051 period, so that it can be used in combination with the delay time generation circuit 1005 that generates a delay time in units of the period of the read clock 1054, so that finer line start position adjustment is possible. Can be done.

  Further, the timing at which the control signal generating device 1001 validates the bit data insertion / extraction position signal can be randomly changed for each line. As a result, the correction pixel position can be randomly changed for each line without changing the number of corrections and the correction frequency in the line. Therefore, it is possible to prevent occurrence of vertical stripes that may occur when the arrangement of correction pixels is random and the correction pixel position is not changed for each line.

  In the present embodiment, each circuit is described as being configured by a hardware circuit. However, all or part of the circuit can be realized by software by a computer that executes a program. Such a computer includes at least a CPU for arithmetic control, a nonvolatile memory such as a ROM for storing a program executed by the CPU, and a RAM used as a primary storage unit of data while the CPU executes the program.

  In addition, the present invention may be applied to a system or an integrated device composed of a plurality of devices (for example, a host computer, an interface device, a printer, etc.) or an apparatus composed of a single device.

  Another object of the present invention is to supply a storage medium (or recording medium) in which a program code of software that realizes the functions of the above-described embodiments is recorded to a system or apparatus. Needless to say, this can also be achieved by the computer (or u CPU or MPU) of the system or apparatus reading and executing the program code stored in the storage medium.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  The functions of the above-described embodiments are not only realized by executing the program code read by the computer. This includes the case where the operating system (OS) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing. Needless to say.

  Further, the program code read from the storage medium is written in a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer. Thereafter, based on the instruction of the program code, the CPU provided in the function expansion card or function expansion unit performs part or all of the actual processing. It goes without saying that the case where the functions of the above-described embodiments are realized by such processing is also included.

  When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the flowcharts described above.

901 Semiconductor laser
902 Collimator lens
903 polygon mirror
904 f-θ lens
905 Beam Detect Sensor
906 Laser drive unit
907 Image processing circuit
908 Main scanning magnification correction controller
909 Correction control signal

Claims (13)

The input image signal is pixel-divided into a plurality of bit data indicating the emission or extinction of laser light in the pixel corresponding to the density in units of pixels, and the image signals that have been subjected to pixel division modulation in units of pixels are fixed-frequency images. A pixel division modulation unit that outputs in synchronization with a clock; a drive unit that drives a laser light source based on an image signal output from the pixel division modulation unit; and a latent image formed on the latent image carrier. An image forming apparatus comprising: a scanning unit that scans the latent image carrier with laser light emitted from a laser light source;
The pixel division modulation means includes
Attribute indicating bias of bit data indicating light emission or extinction of laser light in a pixel corresponding to density when correcting a shift in the scanning direction on one line scanned with the laser light on the latent image carrier Correction means for generating pixel data of the new pixels of the one line by inserting bit data in the bit position based on the information or extracting the bit data from the bit position;
An image forming apparatus, wherein the generated pixel data of a new pixel is output in synchronization with the fixed-frequency image clock.   The correction means inserts bit data indicating extinction at a bit position where the bit data indicating the extinction of laser light is biased or extracts bit data indicating extinction from the bit position where the bit data indicating the extinction of laser light is biased. The image forming apparatus according to claim 1, wherein:   The image forming apparatus according to claim 1, wherein the attribute information is a pulse position represented by a bias of bit data indicating emission of laser light corresponding to density.   The pulse position includes left alignment in which bit data indicating emission of laser light corresponding to density is biased to the left end in the pixel, right alignment biased to the right end, a center biased to the center, and a split biased to both ends. The image forming apparatus according to claim 3.   The image forming apparatus according to claim 4, wherein the correction unit inserts bit data at the right end of the pixel or extracts bit data at the right end when the pulse position is left-justified or centered.   The image forming apparatus according to claim 4, wherein the correction unit inserts bit data at the left end of the pixel or extracts bit data at the left end when the pulse position is right-justified.   The image forming apparatus according to claim 4, wherein the correction unit inserts bit data at the center of a pixel or extracts bit data at the center when the pulse position is split.   8. The correction by the correction means, wherein insertion or extraction of the bit data is switched in the middle of a line for each segment having a preset width in the scanning direction. The image forming apparatus described.   9. The image according to claim 1, wherein the position of the pixel to be corrected by the correction unit is determined in advance in accordance with the number of pixels scanned in one line and the correction amount. Forming equipment.   The image forming apparatus according to claim 1, wherein the position of the pixel to be corrected by the correcting unit can be randomly selected for each line.   When inserting bit data into a pixel, the timing of the clock for reading out the next pixel data is delayed by the inserted bit, and when extracting bit data into the pixel, the timing of the clock at which the next pixel data is read out is extracted. The image forming apparatus according to claim 1, further comprising a clock generation unit that speeds up by a predetermined number of bits. Means for outputting an image writing reference signal;
12. The image forming apparatus according to claim 1, wherein a timing at which the output of the pixel data is started is delayed by a predetermined time with respect to the image writing reference signal. The input image signal is pixel-divided into a plurality of bit data indicating the emission or extinction of laser light in the pixel corresponding to the density in units of pixels, and the image signals that have been subjected to pixel division modulation in units of pixels are fixed-frequency images. A pixel division modulation unit that outputs in synchronization with a clock; a drive unit that drives a laser light source based on an image signal output from the pixel division modulation unit; and a latent image formed on the latent image carrier. A main scanning magnification correction method for an image forming apparatus, comprising: a scanning unit that scans the latent image carrier with laser light emitted from a laser light source;
When correcting a shift in the scanning direction on one line scanned with the laser beam on the latent image carrier,
By inserting bit data into the bit position based on the attribute information indicating the deviation of the bit data indicating the emission or extinction of the laser beam in the pixel corresponding to the density, or extracting the bit data from the bit position, a new one line is obtained. A step of generating pixel data of a correct pixel;
And a step of outputting the generated pixel data of the new pixel in synchronization with the image clock having the fixed frequency.

Images