JP2010268179A - Ldpc decoding circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of having to hold a large amount of memories for storing estimated posteriori probability data in parallel in order to increase a transfer speed in an LDPC (low density parity check code) decoding circuit. <P>SOLUTION: A memory A and a memory B are memories that correspond to a column 901 in which 1 continuously exists in code parts of an inspection matrix, and are composed of high-speed memories or flip-flops to always receive access. A memory C is a memory corresponding to a column 902 in which 1 exists at random in code parts, and a memory D is a memory corresponding to a parity part 1003 in which 1 exists step-wise, each of them being configured by a normal memory. Thus, the number of used memories is reduced by taking into consideration the characteristic of the inspection matrix to devise a method for storing the estimated posteriori probability data. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an LDPC decoding circuit.

  LDPC (Low Density Parity Check Code) is a redundant code that is added to information for the purpose of correcting the error when the information is erroneous due to noise in communications, etc. It is. An apparatus for adding redundant codes is called an encoding apparatus, and an apparatus for correcting errors is called a decoding apparatus.

  LDPC was proposed in the 1960s, but at that time, it had to have a large amount of storage space in order to realize its algorithm, and was considered not very practical. However, due to the recent demand for high integration and powerful error correction, it has begun to attract attention.

  First, LDPC encoding will be described. A set of n-bit information codes is C, and a set of m-bit check codes is M. If the information to be sent to the communication channel is defined as X = (C, M) and the check matrix having m rows and (m + n) columns is H, a set M such that X · H = 0 is found. be able to. The calculation of X is called encoding.

  Next, LDPC decoding will be described. In the communication channel, when the set that modulates X is F, if the data is corrupted due to noise, etc., and the result of demodulating F becomes Y, after estimating the error from that value and correcting it If y is set to y, H · y = 0, and finding such y is called decoding. At this time, Y and y are soft-decision codes because they are demodulated data. However, when calculating H · y = 0, y is performed with the information after the hard decision.

  LDPC decoding is performed by sequentially updating the estimated posterior probability data ZR from the initial value (demodulation result Y) according to the check matrix H (m, m + n). In this updating process, a matrix L (m, m + n) having the same size as the check matrix H (m, m + n) that is updated with the values of all elements as the initial value 0 is used. When all the processes are completed for the elements whose elements of the parity check matrix H (m, m + n) are 1, the check of H · y = 0 is performed, and in the case of NG, the process is repeated. When such LDPC code decoding is circuitized, a circuit configuration as shown in FIG. 16 is generally employed.

  The estimated posterior probability data ZR is very large data and is continuous data, and therefore can be stored in a memory. A memory that stores the estimated posterior probability data ZR is called a ZR memory, and generally stores one data at one address. If the bit width of the memory is one data per address according to the number of quantization bits of the estimated posterior probability data ZR, the memory bit width and the data quantization bit width are equivalent. It is theoretically possible to read the estimated posterior probability data ZR serially one by one, but since the calculation speed is greatly reduced, it is generally necessary to read several data at a time. The value of L is the same, and the value is stored in the L memory. However, since the L memory is not directly related to the present invention, a detailed description is omitted.

  The ZR memory stores the estimated posterior probability data ZR for each column of the check matrix H (m, m + n), and the L memory stores the value of each element of the matrix L (m, m + n). In the course of the above process, the ZR memory and L memory are read and calculated, and the result is stored again in the ZR memory and L memory. At this time, in the estimated posterior probability data ZR, it is necessary to extract the element of the column in which 1 exists among the elements of the check matrix.

  By the way, when the check matrix H (m, m + n) is enormous, the storage capacity of the ZR memory and the L memory also becomes enormous, and when all information is stored in one memory, reading and writing processing of the information is serialized. Since this is done, processing performance falls. With respect to this type of problem, there is known a conventional technique in which estimated posterior probability data is divided and stored in a plurality of memories.

  However, since this technique simply divides the memory into a plurality of memories, in the check matrix H (m, m + n) that is blocked as will be described later, “1” randomly exists and is not accessed. In any case, since there is a continuous “1” and the memory that is always accessed is read / written at a low speed, there is a problem that the processing performance is inevitably deteriorated. On the other hand, in order to increase the read / write speed, if all the memories are simply configured with high-speed memories or flip-flops, or the number of memories that can be read / written in parallel increases, the cost will increase.

JP2008-278184

  The problem to be solved is that the read / write speed of the memory storing the estimated posterior probability data that is always accessed is slow.

  The main feature of the present invention is that the storage method is devised in accordance with the characteristics of the check code in order to improve the speed of the memory for storing the estimated posterior probability data.

  The LDPC decoding circuit of the present invention has the advantage that the circuitization of the LDPC decoding algorithm can be realized with a small number of memories in order to provide high transfer performance. This is because the estimated posterior probability data is stored in the memory according to the characteristics of the check matrix. That is, when processing is performed in units of rows of the check matrix, the data required at that time is easily read from the memory.

Flow chart showing general decoding algorithm (main part) of LDPC Flow chart showing general LDPC decoding algorithm (Z calculator) Flow chart showing the general decoding algorithm flow (L calculation part) of LDPC Diagram illustrating a general check matrix Diagram illustrating block formation of check code (Quasi-Cyclic LDPC code) Diagram illustrating display of block check code Diagram illustrating a general check code displayed in block form The figure which shows the LDPC decoding circuit of this invention The figure which shows the correspondence of a check matrix and the memory which comprises ZR memory Diagram showing the correspondence between memory A, estimated posterior probability data ZR, and matrix Diagram showing the correspondence between memory C, estimated posterior probability data ZR, and matrix A more specific view of FIG. Timing chart showing an operation example of the LDPC decoding circuit of the present invention The figure which shows the correspondence of the other check matrix and the memory which comprises ZR memory Timing chart showing an operation example of the LDPC decoding circuit corresponding to FIG. Circuit diagram of a general decoder

  The purpose of improving the read / write speed of the memory that stores the estimated posterior probability data was realized while suppressing the cost.

  First, a general algorithm for LDPC decoding will be briefly described with reference to FIGS. The circuit configuration for realizing this algorithm is basically as shown in FIG. The parity check matrix H has m rows, (m + n) columns, and Z (i) = Y (i) and L (j, i) = 0 as initial values. However, j = 0 to (m-1) and i = 0 to (m + n-1) (step S1 in FIG. 1). Note that t represents the number of tries.

  The first row of the check matrix H is designated as j = 0 (step S2), make Z (step S3), and then make L (step S4) is activated. This is repeated until j = (m−1) (step S5), and H · y = 0 is confirmed (step S6). The final ZR is y. If H · y = 0 is not satisfied, and t is counted up (step S7) and the number of tries has not reached the maximum number (step S8), the process returns to step S2.

  FIG. 2 shows the details of make Z. Designate the first column of the parity check matrix H as i = 0 (step S3-1), and if the parity check matrix H (j, i) = 1 (step S3-2), Z (i) = ZR (i) -L (ji) (step S3-3), if the check matrix H (j, i) = 1 is not true (step S3-2), the process Z (i) = 0 (step S3-4) is i = (m + n -1) is repeated (steps S3-5 and S3-6).

  FIG. 3 shows the details of make L. The first column of the parity check matrix H is designated as i = 0 (step S4-1). If the parity check matrix H (j, i) = 1 (step S4-2), L (j, i) = f (Z, i) and ZR (i) = Z (i) + L (j, i) (step S4-3), if parity check matrix H (j, i) = 1 is not satisfied (step S4-2), L = 0 (step The process of S4-4) is repeated until i = (m + n-1) (steps S4-5 and S4-6).

  Here, the minimum value among the absolute values of Z (0) to Z (i-1) and Z (i + 1) to Z (m + n-1) is a, Z (0) to Z (i- When the multiplication result of the sign of 1) and Z (i + 1) to Z (m + n-1) is b, f (Z, i) = a · b.

  Now, an example of the parity check matrix H used at the time of encoding and decoding is shown in FIG. Although FIG. 4 is made small for simplicity of explanation, the rows and columns of the check matrix H may be very large, and it is very difficult to express only 0 and 1 as shown in FIG. Become. Therefore, there are cases where a block is formed as shown in FIG. 5 and a number indicating the position where the 1 exists is assigned to the block as shown in FIG. The ZR memory stores the estimated posterior probability data basically in units of columns of the check matrix H, but stores them in units of blocks when the blocks are formed as shown in FIG.

  In FIG. 6, 0 is assigned to blocks in which 1 is regularly arranged diagonally from the upper left corner to the lower right corner, −1 is assigned to all 0 blocks, and 1 is assigned to other blocks. The 1 in the block needs to be circulated regularly. A code that can be expressed in this way is called a Quasi-Cyclic code. Also, as shown in FIG. 4, the right half of the parity check matrix is called “Repeat Accumulate code”, which is a code in which 1's are regularly arranged diagonally, and is advantageous in encoding.

  LDPC decoding is considered to be very difficult to implement in circuits due to the large amount of computation. The biggest problem is that it is necessary to store all the ZR and L information in step S4-3 in FIG. 3, and a lot of memory must be used for this storage. This much memory means that a large number of memories are used. The reason is that ZR and L are large. For example, 8 bits for one numeric element, LDPC (2000, 1000), if there are 10 1 per line, L must memorize 1000 x 10 x 8 = 80000 bits of data, When designing with flip-flops, the circuit scale becomes enormous.

  Next, even if all the data is stored in one memory, the memory can exchange only data corresponding to the data width in one access. However, since the LDPC of the serial algorithm described in FIGS. 1 to 3 requires 10 data almost simultaneously in step S4-3, it is necessary to divide the memory so that it can be read in parallel.

  When a block is formed by the Quasi-Cyclic code, memory is required for at least that block when viewed in a row. Even if the code of LDPC (2000, 1000) given as an example is blocked in units of 20 bits, the required memory will be 100 with 2000/20 = 100, which will hinder implementation on ASIC etc. Become. Accordingly, if all the information is stored in one memory without dividing the memory, the processing performance deteriorates because the information is read and written serially.

  As shown in FIG. 16, the LDPC decoding circuit according to the present invention does not use a large amount of memory for the ZR memory, but integrates columns having areas that are not continuously accessed from the characteristics of the parity check matrix. As shown in FIG. 8, the number of memories constituting the ZR memory 1-1 is reduced. Specifically, in the case of a parity check matrix of block display as shown in FIG. 7, since the code portion column 701 always has 1 and the parity portion 702 has 1 in a staircase pattern, Is assigned to a memory or flip-flop, one memory is assigned to the parity portion 702, and the other columns in the code portion are all assigned another one memory. Note that the numbers such as “12” in FIG. 8 replace the numbers such as “−1” in FIG. 6 corresponding to the large parity check matrix, and uniquely indicate the pattern of the 20 × 20 matrix. Yes.

  According to the present invention, in the parity check matrix as shown in FIG. 7, the number of places where at least 12 memories are required for 12 columns is reduced to 2 (when column 701 is assigned to a flip-flop) or 4 It can be reduced and performance is not degraded.

  Referring to FIG. 9, the correspondence relationship between the parity check matrix and the memories A to D constituting the ZR memory 1-1 is shown. In FIG. 9, a memory A and a memory B are memories corresponding to a column 901 in which 1s continuously exist in the code part, and are constituted by high-speed memories or flip-flops because they are always accessed. The memory C is a memory corresponding to the column 902 in which 1s are randomly present in the code part, and the memory D is a memory corresponding to the parity part 1003 in which 1s are present in steps, both of which are normal memories. Consists of.

  10 and 11 detail FIG. 9 and show the correspondence between the memory A, the memory C, the estimated posterior probability data ZR, and the matrix. The unit matrix 1001 in FIG. 10 is an enlargement of the column 901 in FIG. The estimated posterior probability data ZR corresponding to the unit matrix 1001 is stored in the memory A as in the image shown in FIG. Similarly, the unit matrices 1101 and 1102 in FIG. 11 are enlarged views of the column 902 in FIG. The estimated posterior probabilities ZR corresponding to the unit matrices 1101 and 1102 are stored in the memory C as in the image shown in FIG. Thus, the memory C stores the estimated posterior probability data ZR of a plurality of columns. Therefore, it is important that the unit matrix 1101 and the unit matrix 1102 are configured to be read exclusively.

  FIG. 12 shows FIG. 9 in a form corresponding to FIG. The memory C and the memory D do not always execute the same column, but execute the column specified by the control circuit 5. The memory D is a part to which the data of the staircase-like matrix part is allocated. However, as can be seen from FIG. 9, the estimated posterior probability data ZR read once is always used in the next process (for the row). By buffering, memory access can be reduced. The L memory 2 stores L information corresponding to the memories A to D. The control circuit 5 controls all the blocks 1-1, 2-4. The calculation circuit 3 executes the processing shown in FIGS.

  The operation will be described with reference to FIG. In the memories A to D, the value of Y is stored as the initial value of the estimated posterior probability data ZR. The control circuit 5 reads the first row from the memory A to the memory D and the L memory 2. As described above, the estimated posterior probability data ZR arranged in these memories can read one row by one access. In addition, regarding the L memory 2, it is assumed that data is arranged so that information for one row can be read by one access.

  The buffer 4 holds the estimated posterior probability data ZR from the memory D read out last time, and the presence thereof makes it possible to reduce access to the memory D. After the horizontal row is read, new estimated posterior probability data ZR and L information are created by the calculation circuit 3 and stored again in each memory. By repeating this, the rows of the matrix are executed to the end, and correction is made once when execution of all the rows is completed. By repeating this correction several times, an error can be corrected. FIG. 13 is a timing chart showing a case where one correction is repeated twice by executing four rows.

  Although the basic configuration is as described above, as shown in FIG. 14, a timing chart corresponding to a check matrix different from FIG. 9 is shown in FIG. In FIG. 14, in the column 1402 where 1 is randomly present in the code portion, the memory C needs to be accessed with the estimated posterior probability data ZR of two columns at a time. For this reason, in FIG. 15, the reading of the other memory is waited until the two readings of the memory C are completed.

1 ZR memory 2 L memory 3 Calculation circuit 4 Buffer 5 Control circuit
2-1 ZR memory
701 Code sequence
702 Parity part
901 Code part sequence
902 Code part sequence
903 Parity part
1001 identity matrix
1101 identity matrix
1102 identity matrix
1401 Code sequence
1402 Code sequence
1403 identity matrix

Claims (3)

In an LDPC decoding circuit that serially processes and decodes low density parity code (LDPC) information according to a check matrix,
The memory for storing the estimated posterior probability data is a high-speed memory or a high-speed memory for a portion where a number of blocks having “1” exist in a column in the code portion of the check matrix that is blocked based on the pattern of the check matrix It is composed of a flip-flop memory, is composed of at least one random memory for other portions of the code part of the parity check matrix, and is composed of another random memory for the parity code part of the parity check matrix LDPC decoding circuit characterized by the above.   2. The LDPC decoding circuit according to claim 1, wherein the blocking is performed by a Quasi-Cyclic code and a Repeat Accumulate code of the parity check matrix.   When the data of the parity code part is such that the data once read from the random memory is always used in the processing for the next row, the previously read data is retained. The LDPC decoding circuit according to claim 1 or 2.

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