JP2010267363A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of controlling a current flowing through a magnetic tunnel junction device according to temperature during data reading operation. <P>SOLUTION: The semiconductor memory device includes: a plurality of memory cells for storing data on logic states corresponding to the directions of a current flowing through a first drive line and a second drive line; a current production means that produces a reading current of predetermined magnitude, supplies the current to the plurality of memory cells and produces a variation of the reading current according to the data as a data current; and a current control means that is connected on a current path of the reading current and controls a current amount of the reading current according to temperature information. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor design technique, and more particularly to a semiconductor memory device using a magnetic tunnel junction device (MTJ).

  Generally, DRAM (Dynamic Random Access Memory) devices and SRAM (Static Random Access Memory) devices are volatile memory devices, and have a drawback in that data stored in memory cells is lost when power is not applied. Therefore, research on nonvolatile memory devices has been actively conducted recently. Among non-volatile memory devices, there is an MRAM (Magnetic Random Access Memory) device, which is a kind of magnetic memory device. In particular, the MRAM device has not only non-volatile characteristics but also high integration, and Since it has high-speed operation and low power consumption characteristics, it is attracting attention as a next-generation semiconductor memory device.

  A memory cell of the MRAM device includes one transistor that performs a switching operation in response to an externally applied address signal, and a magnetic tunnel junction element (MTJ) that stores information. A magnetic tunnel junction element (MTJ), which is a kind of magnetic memory element, has different magnetoresistance ratios (MRs) depending on the magnetization directions of two ferromagnetic materials. By sensing the current corresponding to the change, it is determined whether the logical state of the data stored in the magnetic tunnel junction element is “1” or “0”.

  FIG. 1 is a diagram for explaining a memory cell structure of a conventional semiconductor memory device.

  As shown in FIG. 1, the memory cell includes one NMOS transistor 110 and one magnetic tunnel junction element (MTJ) 130.

  In the NMOS transistor 110, a source / drain path is formed between the source line SL and the magnetic tunnel junction element 130, a gate is connected to the word line WL, and the NMOS transistor 110 is turned on / off depending on whether the word line WL is activated. At this time, the word line WL is selected by a row address.

  The magnetic tunnel junction element 130 includes a free layer 132, a tunnel insulating film 134, and a pinned layer 136. Here, the free film 132 is made of a ferromagnetic material, and the magnetization direction is changed by an external stimulus (for example, a current passing through the magnetic tunnel junction element 130). However, the pinned film 136 is magnetized even when an external stimulus is applied. The direction does not change. The pinned film 136 has a magnetization direction fixed by a pinning film (not shown) made of an antiferromagnetic material, and the tunnel insulating film 134 can be formed of, for example, a magnesium oxide film (MgO).

  A tunneling current flows through the magnetic tunnel junction element 130 according to the voltage applied to both ends. The magnetization direction of the free film 132 is determined by the direction of the current. When the magnetization direction of the free film 132 coincides with the magnetization direction of the pinned film 136, the resistance value of the magnetic tunnel junction element 130 decreases, and when the magnetization direction of the free film 132 does not coincide with the magnetization direction of the pinned film 136. The resistance value of the magnetic tunnel junction element 130 increases. Generally, the state in which the magnetization direction of the free film 132 and the magnetization direction of the pinned film 136 coincide with each other corresponds to data “0”, and vice versa.

  That is, when a positive voltage of a predetermined magnitude or more is applied to the free film 132 paired with the pinned film 136 and a positive current greater than the critical current flows in the free film 132, the magnetization direction of the free film 132 And the magnetization direction of the pinned film 136 coincide with each other. That is, the write operation of data “0” is performed, and the resistance value of the magnetic tunnel junction element 130 becomes small. On the contrary, when a negative voltage greater than a predetermined magnitude is applied to the free film 132 paired with the pinned film 136 and a negative current greater than the critical current flows in the free film 132. The magnetization direction of the free film 132 and the magnetization direction of the pinned film 136 are opposite to each other. That is, the write operation of data “1” is performed, and the resistance value of the magnetic tunnel junction element 130 increases.

  FIG. 2 is a diagram showing the temperature dependence of the tunnel magnetoresistance (TMR) characteristics of the magnetic tunnel junction element shown in FIG.

  As shown in FIG. 2, the magnetic tunnel junction element 130 has hysteresis, and has a low resistance value and a high resistance value due to a positive or negative current larger than the critical current. Has two stable states. These stable states are maintained even when no voltage is applied.

  On the other hand, the resistance value of the magnetic tunnel junction element 130 changes according to the temperature. In particular, it can be seen that the resistance value decreases as the temperature rises in the state where the magnetization directions are opposite to each other. That is, the tunnel magnetoresistive characteristics change according to the temperature. The change of the tunnel magnetoresistive characteristic that changes according to the temperature gradually reduces the difference between the resistance values of the data “1” and “0”, so that the magnetic tunnel junction element 130 maintains a large resistance value or a small resistance value. It causes the problem of making it difficult to decide whether to maintain. This leads to a malfunction in which stored data cannot be read accurately during a read operation of the semiconductor memory device.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of controlling the current flowing through the magnetic tunnel junction element according to the temperature during a data read operation. Is to provide.

  In order to achieve the above object, a semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cells that store data in a logic state corresponding to directions of currents flowing through a first drive line and a second drive line; A current generation unit configured to generate a read current of a predetermined magnitude and supply the read current to the plurality of memory cells, and to generate a change amount of the read current according to the data as a data current; and on a current path of the read current Current control means connected to control the amount of the read current according to temperature information.

  In order to achieve the above object, a semiconductor memory device according to another embodiment of the present invention includes a plurality of memory cells that store data in a logic state corresponding to the direction of current flowing in a source line and a bit line, and a predetermined size. A read current is generated and supplied to the plurality of memory cells, and a change amount of the read current according to the data is generated as a data current; and connected to a current path of the read current. Current control means for controlling a current amount of the read current according to temperature information, and a plurality of reference memory cell groups for storing reference data of logic states corresponding to directions of currents flowing in the reference source line and the reference bit line, Generating a reference current corresponding to the reference data by generating a current having a predetermined magnitude and supplying the current to the plurality of reference memory cells. And a reference current control means for controlling the current supplied from the reference current generating means to the plurality of reference memory cells according to the temperature information, and detecting and amplifying the data current and the reference current. Sense amplification means.

  The present invention can improve the tunnel magnetoresistance characteristics of the magnetic junction element provided in the semiconductor memory device by controlling the read current flowing through the magnetic tunnel junction element according to the temperature during the data read operation.

  According to the present invention, it is possible to improve the reliability of the semiconductor memory device by improving the temperature dependency of the tunnel magnetoresistive characteristic of the magnetic junction element and performing a stable data reading operation even when the temperature changes. it can.

It is a figure explaining the memory cell structure of the conventional semiconductor memory device. It is a figure which shows the temperature dependence of the tunnel magnetoresistive (TMR) characteristic of the magnetic tunnel junction element shown in FIG. 1 is a block diagram of a semiconductor memory device according to the present invention. FIG. 4 is a block diagram of a control signal generation unit shown in FIG. 3. FIG. 4 is a circuit diagram of a semiconductor memory device according to the present invention, corresponding to a circuit of a portion excluding a control signal generation unit shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings to such an extent that those skilled in the art to which the present invention pertains can practice the present invention.

  FIG. 3 is a block diagram of a semiconductor memory device according to the present invention.

  As shown in FIG. 3, the semiconductor memory device includes a current generation unit 310, a current control unit 330, and a memory cell array 350.

  The current generator 310 generates a read current I_RD having a predetermined magnitude for the read operation and supplies the read current I_RD to the memory cell array 350. In addition, the current generator 310 generates a data current I_DAT that represents the amount of change in the read current I_RD. Here, the current amount of the read current I_RD changes according to data stored in the memory cell array 350, and the current amount of the data current I_DAT is determined according to data stored in the memory cell array 350. As will be described later, the semiconductor memory device according to the present invention compares the data current I_DAT thus generated with the reference current I_REF (see the figure) to determine the data stored in the memory cell array 350. .

  The current control unit 330 is connected on the current path of the read current I_RD, and controls the amount of read current I_RD supplied to the memory cell array 350 according to the temperature information INF_TMP. The current control unit 330 includes a control signal generation unit 332 that generates a current control signal CTR_I corresponding to the temperature information INF_TMP, and a current adjustment unit 334 that adjusts the amount of read current I_RD in response to the current control signal CTR_I. . Here, the temperature information INF_TMP is a signal generated outside or inside the semiconductor memory device.

  The memory cell array 350 includes a magnetic tunnel junction element, and stores data in a logic state corresponding to the direction of current flowing through the source line SL and the bit line BL in the magnetic tunnel junction element. Data write and read operations related to the memory cell array 350 will be described in detail with reference to FIG.

  FIG. 4 is a block diagram of the control signal generator 332 shown in FIG.

  4, the control signal generation unit 332 includes a voltage generation unit 410 that generates a plurality of bias voltages V_BIAS0, V_BIAS1,... V_BIASn, and a selection signal SEL <0: N> corresponding to the temperature information INF_TMP (here, , N is a natural number, for example, N = n) and a selection signal generation unit 430 generates a current from any one of a plurality of bias voltages V_BIAS0, V_BIAS1,. And a multiplexing unit 450 that outputs the control signal CTR_I.

  Here, the plurality of bias voltages V_BIAS0, V_BIAS1,... V_BIASn have different voltage levels, and the selection signals SEL <0: N> have different values according to the temperature information INF_TMP. Therefore, it is possible to select any of a plurality of bias voltages V_BIAS0, V_BIAS1,... V_BIASn as the selection signal SEL <0: N>. Thereby, the control signal generation unit 332 can output the bias voltage corresponding to the temperature information INF_TMP as the current control signal CTR_I.

  FIG. 5 is a circuit diagram of a semiconductor memory device according to the present invention. FIG. 5 shows a circuit diagram corresponding to a portion excluding the control signal generation unit 332 shown in FIG.

  As shown in FIG. 5, the semiconductor memory device includes a plurality of memory cells 510A, a plurality of reference memory cells 510B, a first write driver 530A and a second write driver 530B, a cell current generator 550A, The current generation unit 550B includes a first current adjustment unit 570A and a second current adjustment unit 570B, and a sense amplification unit 590.

  As described with reference to FIG. 3, the semiconductor memory device according to the present invention controls the amount of read current I_RD supplied to the memory cell array 350 according to the temperature information INF_TMP. In the semiconductor memory device shown in FIG. 5, such a feature is applied not only to the plurality of memory cells 510A but also to the plurality of reference memory cells 510B. 3 corresponds to the cell current generation unit 550A and the reference current generation unit 550B in FIG. 5, and the current adjustment unit 334 in FIG. 3 includes the first current adjustment unit 570A and the second current adjustment unit 570A in FIG. Corresponding to the current adjustment unit 570B, the memory cell array 350 corresponds to a plurality of memory cells 510A and a plurality of reference memory cells 510B.

  Hereinafter, each component in FIG. 5 will be described.

  The plurality of memory cells 510A are for storing data. As shown in FIG. 1, an NMOS transistor NM that performs a switching operation in response to each address signal, and a magnetic tunnel junction element MTJ that stores data are used. Are provided. Each of the plurality of memory cells 510A corresponds to the plurality of word lines WL0, WL1,... WLn, and is connected between the source line SL and the bit line BL. Data write and read operations related to the plurality of memory cells 510A will be described later.

  The first write driver 530A includes a source line driver 530A_1 and a bit line driver 530A_2, and drives the source line SL and the bit line BL according to data.

  Here, the source line driver 530A_1 drives the source line SL with the core voltage VCORE or the ground voltage VSS in response to data, and the bit line driver 530A_2 sends the bit line BL with the core voltage VCORE in response to data. It is driven by the ground voltage VSS.

  Hereinafter, a data write operation related to the plurality of memory cells 510A will be described. For convenience of explanation, a case will be described in which any one of the plurality of word lines WL0, WL1,... WLn corresponding to the memory cell performing the write operation is activated. Since the bit line selection signal BS is activated during the write operation, the bit line BL can be driven by the bit line driver 530A_2.

  First, at the time of writing data “1”, the source line driver 530A_1 drives the source line SL with the core voltage VCORE, and the bit line driver 530A_2 drives the bit line BL with the ground voltage VSS. Therefore, a current flows from the source line SL to the bit line BL through the magnetic tunnel junction element MTJ, and data “1” is stored in the memory cell as described with reference to FIG.

  Next, at the time of writing data “0”, the source line driver 530A_1 drives the source line SL with the ground voltage VSS, and the bit line driver 530A_2 drives the bit line BL with the core voltage VCORE. Therefore, current flows from the bit line BL to the source line SL through the magnetic tunnel junction element MTJ, and data “0” is stored in the memory cell.

  On the other hand, the plurality of reference memory cells 510B are for generating the reference current I_REF, have a configuration similar to that of the plurality of memory cells 510A, and two reference memory cells correspond to one word line. Arranged in groups. For convenience of explanation, of the plurality of reference memory cells 510B, two reference memory cells corresponding to one word line are referred to as “reference memory cell group”.

  In general, before commercializing a semiconductor memory device, data “1” and data “0” must be stored in two reference memory cells provided in all reference memory cell groups. That is, of the two reference memory cells included in each reference memory cell group, one reference memory cell should be a magnetic tunnel junction element RH having a large resistance value, and the other reference memory cell should have a small resistance. It should be a magnetic tunnel junction element RL having a value. The reason why data “0” and “1” having different logic states must be stored in all the reference memory cell groups is that the magnetic tunnel junction element has the resistance value variation characteristic shown in FIG. The plurality of reference memory cells 510B store data “0” and data “1” so that the reference current I_REF corresponding to the change state can be generated based on the change state of the resistance value of the selected memory cell. Must. Data write and read operations related to the plurality of reference memory cells 510B will be described later.

  The second write driver 530B includes a first line driver 530B_1 and a second line driver 530B_2, and stores data “1” and data “0” in the plurality of reference memory cells 510B.

  Here, the first line driver 530B_1 drives the reference source line REF_SL with the core voltage VCORE or the ground voltage VSS according to the stored data, and the second line driver 530B_2 receives the first reference according to the stored data. The bit line REF_BL1 and the second reference bit line REF_BL2 are driven by the core voltage VCORE or the ground voltage VSS.

  Hereinafter, a data write operation related to the reference memory cell 510B will be described. For convenience of explanation, a case will be described in which any one of the plurality of word lines WL0, WL1,... WLn is activated.

  First, during the data “1” write operation, the first drive control signal REF_H becomes logic high, and the first NMOS transistor NM1 is turned on. In this state, the first line driver 530B_1 drives the reference source line REF_SL with the core voltage VCORE, and the second line driver 530B_2 drives the first reference bit line REF_BL1 with the ground voltage VSS. Accordingly, the current flows from the reference source line REF_SL through the magnetic tunnel junction element RH to the first reference bit line REF_BL1, and data “1” is stored in the magnetic tunnel junction element RH. That is, the magnetic tunnel junction element RH has a large resistance value.

  Next, during the write operation of data “0”, the second drive control signal REF_L becomes logic high, and the second NMOS transistor NM2 is turned on. In this state, the first line driver 530B_1 drives the reference source line REF_SL with the ground voltage VSS, and the second line driver 530B_2 drives the second reference bit line REF_BL2 with the core voltage VCORE. Accordingly, the current flows from the second reference bit line REF_BL2 to the reference source line REF_SL through the magnetic tunnel junction element RL, and data “0” is stored in the magnetic tunnel junction element RL. That is, the magnetic tunnel junction element RL has a small resistance value.

  By this operation, the plurality of reference memory cells 510B have the magnetic tunnel junction element RH having a large resistance value and the magnetic tunnel junction element RL having a small resistance value. That is, in order to store data “1” and “0” in the reference memory cell group corresponding to one word line, one word line is activated and the first drive control signal REF_H and the second drive control are activated. The first line driver 530B_1 and the second line driver 530B_2 must operate after selecting the reference memory cell to be stored by the signal REF_L. Thereafter, in order to store data “1” and “0” in another reference memory cell group, the above operation is repeated for each word line corresponding to the reference memory cell of the storage destination.

  The cell current generator 550A includes a current mirror circuit, and generates a data current I_DAT corresponding to a memory cell selected by a plurality of word lines WL0, WL1,... WLn among the plurality of memory cells 510A. To do. Here, the cell current generation unit 550A generates not only the data current I_DAT but also the read current I_RD, but due to the current mirror structure, the amount of change in the read current I_RD during the read operation is reflected in the data current I_DAT.

  The reference current generator 550B generates a reference current I_REF corresponding to the reference memory cell group selected by the plurality of word lines WL0, WL1,. Here, the current amount of the reference current I_REF is about half of the amount of current flowing through the selected reference memory cell group. That is, the reference current I_REF has a current amount that is half of the sum of the amount of current flowing through the magnetic tunnel junction element RH having a large resistance value and the amount of current flowing through the magnetic tunnel junction element RL having a small resistance value.

  Note that the cell current generator 550A and the reference current generator 550B are enabled in response to a current supply control signal CSE that is activated during a read operation.

  The first current adjustment unit 570A includes a third NMOS transistor NM3 that receives the current control signal CTR_I as a gate input, and adjusts the amount of read current I_RD generated by the cell current generation unit 550A in response to the current control signal CTR_I. This is transmitted to the plurality of memory cells 510A. Here, the first current adjustment unit 570A forms source / drain paths between the cell current generation unit 550A and the plurality of memory cells 510A. In the semiconductor memory device according to the present invention, the voltage level of the current control signal CTR_I is determined according to the temperature information INF_TMP. This means that the read current I_RD can be controlled according to the temperature.

  The second current adjustment unit 570B includes a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5 connected between the reference current generation unit 550B and the plurality of reference memory cells 510B. The second current adjustment unit 570B adjusts the current generated by the reference current generation unit 550B in response to the current control signal CTR_I and transmits this to the plurality of reference memory cells 510B. Here, the fourth NMOS transistor NM4 forms a source / drain path between the reference current generator 550B and the first reference bit line REF_BL1, receives the current control signal CTR_I as a gate input, and the fifth NMOS transistor NM5 A source / drain path is formed between the generator 550B and the second reference bit line REF_BL2, and the current control signal CTR_I is used as a gate input. Similar to the first current adjustment unit 570A, the second current adjustment unit 570B can control the amount of current flowing through the plurality of reference memory cells 510B according to the temperature.

  The sense amplifier 590 senses and amplifies the data current I_DAT and the reference current I_REF. That is, the sense amplifier 590 receives the reference current I_REF of the reference memory cell group corresponding to the selected word line and the data current I_DAT that changes according to the data of the memory cell corresponding to the selected word line. The reference current I_REF and the data current I_DAT are compared, and the comparison result is output. Thereby, the semiconductor memory device can determine the logical state of the data stored in the memory cell.

  Hereinafter, a data read operation related to the plurality of memory cells 510A will be described. For convenience of explanation, a case where the first word line WL1 is activated will be described. During the read operation, the read activation signal RD is also activated.

  First, when the first word line WL1 is activated, the corresponding NMOS transistor NM in the memory cell 510A is turned on, and according to the data stored in the corresponding magnetic tunnel junction element MTJ in the memory cell 510A, The amount of read current I_RD generated in cell current generation unit 550A is determined. Here, if the data stored in the magnetic tunnel junction element is “1”, it means that the resistance value of the magnetic tunnel junction element is large, and the read current I_RD becomes small. If the data stored in the magnetic tunnel junction element is “0”, it means that the resistance value of the magnetic tunnel junction element is small, and the read current I_RD becomes large. In the present invention, the read current I_RD is readjusted according to the voltage of the current control signal CTR_I corresponding to the temperature information INF_TMP. Next, the current amount of the read current I_RD is reflected in the data current I_DAT, and the data current I_DAT is transmitted to the sense amplifier 590. The cell selection signal YI is activated corresponding to the column address.

  On the other hand, when the first word line WL1 is activated, two corresponding NMOS transistors in the reference memory cell group are turned on, and a magnetic tunnel junction element RH having a large resistance value and a magnetic tunnel junction having a small resistance value. A current flows through the reference source line REF_SL through the element RL. As a result, a current flows through the magnetic tunnel junction element RH having a large resistance value and the magnetic tunnel junction element RL having a small resistance value, which are arranged corresponding to the first word line WL1, and the reference current generator 550B A reference current I_REF having a current amount that is approximately half of the sum of the current amount flowing through the magnetic tunnel junction element RH having a large resistance value and the current amount flowing through the magnetic tunnel junction element RL having a small resistance value is generated. In the present invention, the amount of current supplied to the plurality of reference memory cells 510B can be controlled according to the voltage of the current control signal CTR_I. The reference cell activation signal YREF is activated during a read operation, and transmits the reference current I_REF to the sense amplifier 590.

  Next, the sense amplifying unit 590 includes a data tunneling element having a large resistance value selected corresponding to the data current I_DAT of the memory cell 510A selected corresponding to the first word line WL1 and the first word line WL1. RH and the reference current I_REF of the magnetic tunnel junction element RL having a small resistance value are sensed, and the difference between them is amplified. The semiconductor memory device performs a read operation through the above-described operation process.

  As described above, the semiconductor memory device according to the present invention can control the amount of the read current I_RD applied to the plurality of memory cells 510A according to the temperature. Therefore, even if the magnetic tunnel junction elements provided in the plurality of memory cells 510A have the resistance change characteristics due to temperature as shown in FIG. 2, the read current I_RD is controlled by controlling the amount of the read current I_RD. The temperature compensation operation is reflected, so that the data can be determined more clearly.

  Further, the semiconductor memory device according to the present invention can also control the amount of current applied to the plurality of reference memory cells 510B according to the temperature. Therefore, the temperature compensation operation can be reflected in the corresponding reference current I_REF.

  The technical idea of the present invention has been specifically described by the above embodiment, but the above embodiment is for explaining the present invention and not for limiting the present invention. You must keep in mind. In addition, a general expert in the technical field of the present invention can understand that various embodiments can be implemented by various substitutions, modifications, and changes within the scope of the technical idea of the present invention. .

  In addition, the logic gates and transistors exemplified in the above embodiments may be implemented such that their positions and types differ depending on the logic state of the input signal.

310 current generation unit 330 current control unit 332 control signal generation unit 334 current adjustment unit 350 memory cell array

Claims (15)

A plurality of memory cells storing logic state data corresponding to directions of currents flowing through the first drive line and the second drive line;
Current generation means for generating a read current of a predetermined magnitude and supplying the read current to the plurality of memory cells, and generating a change amount of the read current according to the data as a data current;
Current control means connected on the current path of the read current and controlling the amount of the read current according to temperature information;
A semiconductor memory device comprising:   2. The semiconductor memory device according to claim 1, further comprising write driving means for driving the first drive line and the second drive line with a voltage corresponding to the data. The current control means is
A control signal generator for generating a current control signal corresponding to the temperature information;
A current adjustment unit that adjusts the amount of the read current in response to the current control signal;
The semiconductor memory device according to claim 1, comprising:   4. The semiconductor memory device according to claim 3, wherein the current control signal has a voltage level corresponding to the temperature information. The control signal generator is
A selection signal generator for generating a selection signal corresponding to the temperature information;
A voltage generator for generating a plurality of bias voltages;
A multiplexing unit that outputs any one of the plurality of bias voltages as the current control signal in response to the selection signal;
The semiconductor memory device according to claim 3, further comprising: Each of the plurality of memory cells is
A switching unit that performs a switching operation in response to an address signal;
A magnetic tunnel junction element connected to the switching unit;
The semiconductor memory device according to claim 1, comprising: A plurality of memory cells storing logic state data corresponding to the direction of current flowing in the source line and the bit line;
Cell current generating means for generating a read current of a predetermined magnitude and supplying the read current to the plurality of memory cells, and generating a change amount of the read current according to the data as a data current;
Current control means connected on the current path of the read current and controlling the amount of the read current according to temperature information;
A plurality of reference memory cell groups storing reference data of a logic state corresponding to the direction of current flowing in the reference source line and the reference bit line;
A reference current generating means for generating a current of a predetermined magnitude and supplying the current to the plurality of reference memory cells, and generating a reference current corresponding to the reference data;
Reference current control means for controlling the current supplied from the reference current generating means to the plurality of reference memory cells according to the temperature information;
Sensing amplification means for sensing and amplifying the data current and the reference current;
A semiconductor memory device comprising: First write driving means for driving the source line and the bit line with a voltage corresponding to the data;
Second write driving means for driving the reference source line and the reference bit line with a voltage corresponding to the reference data;
The semiconductor memory device according to claim 7, further comprising: Each of the current control means and the reference current control means is
The semiconductor device according to claim 7, further comprising: a current adjusting unit that adjusts a current amount of the read current or a current amount supplied to the plurality of reference memory cells according to the temperature information. Memory device.   The semiconductor memory device of claim 9, further comprising a control signal generation unit that generates a current control signal corresponding to the temperature information and controls the current adjustment unit.   11. The semiconductor memory device according to claim 10, wherein the current control signal has a voltage level corresponding to the temperature information. The control signal generator is
A selection signal generator for generating a selection signal corresponding to the temperature information;
A voltage generator for generating a plurality of bias voltages;
A multiplexing unit that outputs any one of the plurality of bias voltages as the current control signal in response to the selection signal;
The semiconductor memory device according to claim 10, comprising: Each of the plurality of memory cells is
A switching unit that performs a switching operation in response to an address signal;
A magnetic tunnel junction element connected to the switching unit;
The semiconductor memory device according to claim 7, comprising: Each of the plurality of reference memory cell groups is
A first switching unit and a second switching unit that perform a switching operation in response to an address signal;
A first magnetic tunnel junction element connected to the first switching unit;
A second magnetic tunnel junction element connected to the second switching unit;
The semiconductor memory device according to claim 7, comprising:   The semiconductor memory device of claim 14, wherein the first magnetic tunnel junction element and the second magnetic tunnel junction element store data of different logic states.

Images