JP2010258521A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit which can achieve low power consumption, and which is superior in reliability. <P>SOLUTION: The level shift circuit shifts voltage levels of signals VIN and VINB input to a first input terminal IN and a second input terminal INB to a high-potential power supply voltage or low-potential power supply voltage, and outputs them from an output terminal OUT. The level shift circuit includes: first to sixth transistors Tr1 to Tr6; and a capacity portion. All of the first to sixth transistors Tr1 to Tr6 are an N-channel type or P-channel type. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a level shift circuit.

  In general, an electronic device including a level shift circuit is known. When the electronic device is a liquid crystal display device, the liquid crystal display device includes a plurality of pixels, a plurality of scanning lines connected to the plurality of pixels, a plurality of signal lines, a signal line driving circuit connected to the signal lines, and the like. . The signal line driving circuit is formed by an IC (integrated circuit) chip. A control signal for operating the signal line driving circuit is a low voltage. For this reason, the drive voltage output from the signal line driver circuit may not be able to obtain the level of the drive voltage applied to the signal line.

  Therefore, a level shift circuit is connected between the signal line driving circuit and the signal line (see, for example, Patent Document 1). Thereby, the drive voltage applied to the signal line can be shifted from a low voltage to a high voltage, and the level of the drive voltage applied to the signal line can be obtained.

JP 2007-11278 A

By the way, when the level shift circuit is operated, it is necessary to use two input signals and a bootstrap control signal for each level shift circuit, which causes a problem of high power consumption.
One level shift circuit is composed of seven transistors and four capacitors. Since the number of elements is large, a large number of capacitors are particularly necessary, so that a short circuit due to the breakdown of the insulating film may occur, and the product yield may be reduced. As a result, there is a problem that a level shift circuit having excellent reliability cannot be obtained stably.
The present invention has been made in view of the above points, and an object of the present invention is to provide a level shift circuit that can reduce power consumption and has excellent reliability.

In order to solve the above problem, a level shift circuit according to an aspect of the present invention includes:
In a level shift circuit that shifts the level of a voltage of a signal input to the first input terminal and the second input terminal to a high potential power supply voltage or a low potential power supply voltage and outputs it from the output terminal,
A first transistor including a source electrode connected to a high potential power source, a drain electrode connected to the output terminal, and a gate electrode;
A second transistor including a source electrode connected to a low potential power source, a drain electrode connected to the output terminal, and a gate electrode;
A third transistor including a source electrode connected to the first input terminal, a drain electrode connected to the gate electrode of the first transistor, and a gate electrode, the source electrode and the gate electrode being connected and diode-connected;
A fourth transistor including a source electrode connected to the second input terminal, a drain electrode connected to the gate electrode of the second transistor, and a gate electrode, and the diode connected to the source electrode and the gate electrode;
A fifth transistor including a source electrode connected to the low potential power source, a drain electrode connected to the drain electrode of the fourth transistor, and a gate electrode connected to the drain electrode of the third transistor;
A sixth transistor including a source electrode connected to the low potential power source, a drain electrode connected to the drain electrode of the third transistor, and a gate electrode connected to the drain electrode of the fourth transistor;
A capacitor connected between the drain electrode and the gate electrode of the first transistor,
The first to sixth transistors are all N-channel type or P-channel type.

  According to the present invention, it is possible to reduce the power consumption and provide a level shift circuit having excellent reliability.

It is a block diagram which shows the level shift circuit which concerns on embodiment of this invention. In the level shift circuit driving method, the pulse widths and amplitudes of the signals VIN, VINB, and VOUT when the signal VOUT shifted to the low potential power supply voltage (−5 V) is output when the voltage of the signal VIN is 0 V are shown. FIG. FIG. 3 is a diagram illustrating a state in which the signals VIN and VINB are input in the level shift circuit driving method as in FIG. 2. FIG. 5 is a diagram illustrating a state in which the node n1 is pulled down toward −5V following FIG. 3. FIG. 5 is a diagram illustrating a state in which the voltage of the output terminal VOUT is lowered to −5V and a signal VOUT of −5V is output following FIG. 4. FIG. 11 is a diagram showing pulse widths and amplitudes of signals VIN, VINB, and VOUT when a signal VOUT shifted to a high potential power supply voltage (+10 V) is output when the voltage of the signal VIN is +5 V in the level shift circuit driving method. It is. FIG. 7 is a diagram showing a state in which the signals VIN and VINB shown in FIG. 6 are being input in the level shift circuit driving method as in FIG. 6. FIG. 8 is a diagram illustrating a state in which the node n <b> 2 is pulled down to −5V following FIG. 7. FIG. 9 is a diagram illustrating a state in which the voltage of the output terminal VOUT is increased to +10 V and a signal VOUT of +10 V is output following FIG. 8. It is a figure which shows the modification of the said level shift circuit, and is a block diagram which shows the level shift circuit further provided with the 7th transistor especially.

Hereinafter, a level shift circuit and a method for driving the level shift circuit according to embodiments of the present invention will be described in detail with reference to the drawings. First, the configuration of the level shift circuit will be described.
As shown in FIG. 1, the level shift circuit includes first to sixth transistors Tr1-6, a capacitor C as a capacitor, a first input terminal IN, a second input terminal INB, and an output terminal OUT.

  The level shift circuit shifts the voltage levels of the signals VIN and VINB input to the first input terminal IN and the second input terminal INB to a high potential power supply voltage or a low potential power supply voltage, and outputs them from the output terminal OUT. is there. Here, the high potential power supply voltage is + 10V and the low potential power supply voltage is −5V.

The first transistor Tr1 includes a source electrode connected to the high potential power supply VDD, a drain electrode connected to the output terminal OUT, and a gate electrode.
The second transistor Tr2 includes a source electrode connected to the low potential power supply VSS, a drain electrode connected to the output terminal OUT, and a gate electrode.

  The third transistor Tr3 includes a source electrode connected to the first input terminal IN, a drain electrode connected to the gate electrode of the first transistor Tr1, and a gate electrode. The third transistor Tr3 is diode-connected with the source electrode and the gate electrode connected.

The fourth transistor Tr4 includes a source electrode connected to the second input terminal INB, a drain electrode connected to the gate electrode of the second transistor Tr2, and a gate electrode. The fourth transistor Tr4 is diode-connected with the source electrode and the gate electrode connected.
Note that the third transistor Tr3 and the fourth transistor Tr4 serve as load resistors.

  The fifth transistor Tr5 includes a source electrode connected to the low potential power supply VSS, a drain electrode connected to the drain electrode of the fourth transistor Tr4, and a gate electrode connected to the drain electrode of the third transistor Tr3.

The sixth transistor Tr6 includes a source electrode connected to the low potential power supply VSS, a drain electrode connected to the drain electrode of the third transistor Tr3, and a gate electrode connected to the drain electrode of the fourth transistor Tr4.
In this embodiment, the first to sixth transistors Tr1-6 are each N-channel type. The threshold voltage Vth of the first to sixth transistors Tr1-6 is about 1 to 3V.

  The third transistor Tr3 and the fourth transistor Tr4 are designed to have a sufficiently high resistance. For this reason, the third transistor Tr3 and the fourth transistor Tr4 adopt at least one of the following (1) to (3).

(1) Reduce the gate width.

(2) Increase the gate length.

(3) A double gate configuration is adopted.

The capacitor C is connected between the drain electrode and the gate electrode of the first transistor Tr1. The capacitor C has a first electrode C1 connected to the drain electrode of the first transistor Tr1, and a second electrode C2 connected to the gate electrode of the first transistor Tr1.
The level shift circuit is configured as described above.

  Here, the gate electrode of the first transistor Tr1, the second electrode C2, the drain electrode of the third transistor Tr3, the gate electrode of the fifth transistor Tr5, and the drain electrode of the sixth transistor Tr6 are at the same potential. The potential is described as the potential of the node n1.

  The gate electrode of the second transistor Tr2, the drain electrode of the fourth transistor Tr4, the drain electrode of the fifth transistor Tr5, and the gate electrode of the sixth transistor Tr6 are at the same potential, and these potentials are hereinafter referred to as the potential of the node n2. Will be described.

  Next, the levels of voltages (0 to +5 V amplitude) of the signals VIN and VINB input to the first input terminal IN and the second input terminal INB are set to a high potential power supply voltage and a low potential power supply voltage (−5 to +10 V amplitude). A driving method of the level shift circuit that shifts and outputs the signal VOUT from the output terminal OUT will be described.

  First, the operation of the level shift circuit that outputs the signal VOUT shifted to the low potential power supply voltage (−5 V) when the voltage of the signal VIN input to the first input terminal IN is 0 V from the output terminal OUT will be described.

  As shown in FIGS. 2 and 3, the signal VIN input to the first input terminal IN is a pulse signal, and a voltage of 0 V is input to the first input terminal IN. The signal VINB input to the second input terminal INB is an inverted signal (inverted pulse) of the signal VIN, and a voltage of +5 V is input to the second input terminal INB. Here, the signal VIN is at a low level “L”, and the signal VINB is at a high level “H”.

  As a result, the fourth transistor Tr4 is turned on, and current is supplied from the second input terminal INB to the node n2 via the fourth transistor Tr4. The voltage at the node n2 decreases by the threshold voltage Vth of the fourth transistor Tr4. Therefore, the node n2 is charged with a voltage of 5V-Vth.

Subsequently, when focusing on the second transistor Tr2 and the sixth transistor Tr6, the voltage Vgs between the gate electrode and the source electrode can be expressed by the following equation.
Vgs = (5V−Vth) − (− 5V) >> Vth
For this reason, the second transistor Tr2 and the sixth transistor Tr6 are strongly turned on.

  Next, focusing on the third transistor Tr3 and the sixth transistor Tr6, as shown in FIG. 4, the third transistor Tr3 and the sixth transistor Tr6 constitute an inverter circuit having the third transistor Tr3 as a load resistance. For this reason, the potential of the node n1 is lowered toward the potential of the low potential power supply (−5V). As a result, the first transistor Tr1 and the fifth transistor Tr5 are turned off.

  As described above, the third transistor Tr3 is designed to have a sufficiently high resistance in order to keep the through current flowing from the first input terminal IN toward the low potential power supply VSS low.

  As shown in FIG. 5, next, when focusing on the second transistor Tr2, the second transistor Tr2 lowers the output terminal OUT to the low potential power supply voltage (−5 V). In addition, since the voltage at the node n1 goes to the low potential power supply voltage as described above, the first transistor Tr1 and the fifth transistor Tr5 are turned off. As a result, as shown in FIGS. 2 and 5, a signal VOUT having a low potential power supply voltage (−5 V) is output from the output terminal OUT.

  Next, the operation of the level shift circuit that outputs the signal VOUT shifted to the high potential power supply voltage (+10 V) from the output terminal OUT when the voltage of the signal VIN input to the first input terminal IN is +5 V will be described.

  As shown in FIGS. 6 and 7, the signal VIN input to the first input terminal IN is a pulse signal, and a voltage of +5 V is input to the first input terminal IN. The signal VINB input to the second input terminal INB is an inverted signal (inverted pulse) of the signal VIN, and a voltage of 0 V is input to the second input terminal INB. Here, the signal VIN is at a high level “H”, and the signal VINB is at a low level “L”.

  As a result, the third transistor Tr3 is turned on, and current is supplied from the first input terminal IN to the node n1 via the third transistor Tr3. The voltage at the node n1 decreases by the threshold voltage Vth of the third transistor Tr3. Therefore, the node n1 is charged with a voltage of 5V-Vth.

Subsequently, focusing on the fifth transistor Tr5, the voltage Vgs between the gate electrode and the source electrode can be expressed by the following equation.
Vgs = (5V−Vth) − (− 5V) >> Vth
For this reason, the fifth transistor Tr5 is strongly turned on.

  Next, focusing on the fourth transistor Tr4 and the fifth transistor Tr5, as shown in FIG. 8, the fourth transistor Tr4 and the fifth transistor Tr5 constitute an inverter circuit having the fourth transistor Tr4 as a load resistance. Therefore, the potential of the node n2 is lowered toward the potential of the low potential power supply (−5V). As a result, the second transistor Tr2 and the sixth transistor Tr6 are turned off.

  As described above, the fourth transistor Tr4 is designed to have a sufficiently high resistance in order to keep the through current flowing from the second input terminal INB toward the low potential power supply VSS low.

  As shown in FIG. 9, next, when focusing attention on the first transistor Tr1, the first transistor Tr1 raises the output terminal OUT toward the high potential power supply voltage (+10 V). The increase in potential of the output terminal OUT (+ 10V − (− 5V) = + 15V) pushes up the potential of the node n1 due to the bootstrap effect by the coupling of the capacitor C.

  Then, since the third transistor Tr3 is cut off, the node n1 enters a floating state, and the potential continues to rise. The potential of the node n1 finally rises to (5V−Vth) + 15V, and turns on the first transistor Tr1. As a result, as shown in FIGS. 6 and 9, a signal VOUT having a high potential power supply voltage (+10 V) is output from the output terminal OUT.

According to the level shift circuit and the level shift circuit driving method configured as described above, the level shift circuit is formed of six transistors and one capacitor. Since the level shift circuit can be formed with a smaller number of elements than in the prior art, the number of capacitors is particularly small, so that the occurrence of a short circuit due to the breakdown of the insulating film can be suppressed, and a level shift circuit with a high product yield is obtained. As a result, a level shift circuit having excellent reliability can be stably obtained.
Further, since the number of elements is small, a sufficiently large capacitance can be obtained so that the parasitic capacitance generated between the wirings can be ignored without increasing the size of the capacitor C.

  Only two signals VIN and VINB need be input to the level shift circuit, and it is not necessary to use a bootstrap control signal or the like or a power supply of an intermediate potential, so that power consumption can be kept low.

  The first to sixth transistors Tr1-6 are all N-channel type. A level shift circuit can be formed without a P-channel transistor. Therefore, the manufacturing process of the level shift circuit can be greatly simplified and the manufacturing cost can be reduced as compared with the case where the level shift circuit is formed using N-channel and P-channel transistors.

  Since the level shift circuit can be built on the substrate, the component cost can be reduced by the amount of the IC chip of the level shift function that was conventionally externally attached, and the conventional mounting cost can also be reduced. it can. For example, when a level shift circuit is built in a liquid crystal display panel, the level shift circuit can be built in the same manufacturing process as a pixel thin film transistor formed on a glass substrate.

  Furthermore, since the interface signal amplitude between the glass substrate and the PCB can be lowered, unnecessary radiation noise can be reduced.

Since the level shift circuit has a wide operation margin, it can be applied not only to a low-temperature polysilicon process but also to an IGZO process and an a-Si process.
From the above, it is possible to achieve low power consumption and to obtain a level shift circuit and a driving method of the level shift circuit which are excellent in reliability.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiments. For example, some components may be deleted from all the components shown in the embodiment.

  For example, as shown in FIG. 10, the level shift circuit may further include a seventh transistor Tr7. The seventh transistor Tr7 includes a source electrode connected to the gate electrode of the first transistor Tr1, a drain electrode of the third transistor Tr3, a gate electrode of the fifth transistor Tr5, and a drain electrode connected to the drain electrode of the sixth transistor Tr6, And a gate electrode connected to the high-potential power supply VDD. The seventh transistor Tr7 is an N-channel type. The level shift circuit is configured as described above.

  Here, the gate electrode of the first transistor Tr1, the second electrode C2, and the source electrode of the seventh transistor Tr7 have the same potential, and these potentials will be described below as the potential of the node n3.

  The drain electrode of the third transistor Tr3, the gate electrode of the fifth transistor Tr5, the drain electrode of the sixth transistor Tr6, and the drain electrode of the seventh transistor Tr7 are at the same potential, and these potentials are hereinafter referred to as the potential of the node n4. Will be described.

  As described above, when the signal VOUT of the high potential power supply voltage (+ 10V) is output from the output terminal OUT, the potential of the node n3 finally rises to (5V−Vth) + 15V. Here, by newly providing the seventh transistor Tr7, the potential of the node n4 can be controlled to +10 V or less.

  A voltage exceeding +10 V at the maximum is not applied to the gate electrode of the fifth transistor Tr5 and the drain electrode of the sixth transistor Tr6. For this reason, in terms of voltage durability, the reliability of the fifth transistor Tr5 and the sixth transistor Tr6 can be improved.

  The levels (amplitudes) of the signals VIN and VINB can be variously modified. For example, the signal amplitude may be 0 to +3 V amplitude. In this case, the threshold voltage Vth of the first to sixth transistors Tr1-6 may be adjusted.

The high potential power supply voltage and the low potential power supply voltage are not limited to +10 V and −5 V, respectively, and may be set to voltages desired to be output from the output terminal OUT.
The first to sixth transistors Tr1-6 are not limited to the N-channel type, but may be all P-channel type. In this case, by inverting the polarities of the signals VIN and VINB, the same signal VOUT as that of the level shift circuit adopting the N channel type can be obtained.

  Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7 ... Transistor, C ... Capacitor, IN, INB ... Input terminal, OUT ... Output terminal, VDD ... High potential power supply, VSS ... Low potential power supply, n1, n2, n3 n4 ... node, VIN, VINB ... signal.

Claims (4)

In a level shift circuit that shifts the level of a voltage of a signal input to the first input terminal and the second input terminal to a high potential power supply voltage or a low potential power supply voltage and outputs it from the output terminal,
A first transistor including a source electrode connected to a high potential power source, a drain electrode connected to the output terminal, and a gate electrode;
A second transistor including a source electrode connected to a low potential power source, a drain electrode connected to the output terminal, and a gate electrode;
A third transistor including a source electrode connected to the first input terminal, a drain electrode connected to the gate electrode of the first transistor, and a gate electrode, the source electrode and the gate electrode being connected and diode-connected;
A fourth transistor including a source electrode connected to the second input terminal, a drain electrode connected to the gate electrode of the second transistor, and a gate electrode, and the diode connected to the source electrode and the gate electrode;
A fifth transistor including a source electrode connected to the low potential power source, a drain electrode connected to the drain electrode of the fourth transistor, and a gate electrode connected to the drain electrode of the third transistor;
A sixth transistor including a source electrode connected to the low potential power source, a drain electrode connected to the drain electrode of the third transistor, and a gate electrode connected to the drain electrode of the fourth transistor;
A capacitor connected between the drain electrode and the gate electrode of the first transistor,
The first to sixth transistors are all N-channel type or P-channel type level shift circuits. Each of the first to sixth transistors is an N-channel type,
When a low level signal is input to the first input terminal and a high level signal is input to the second input terminal, the low potential power supply voltage is output from the output terminal,
2. The level shift circuit according to claim 1, wherein when a high level signal is input to the first input terminal and a low level signal is input to the second input terminal, the high potential power supply voltage is output from the output terminal. Each of the first to sixth transistors is a P-channel type,
When a low level signal is input to the first input terminal and a high level signal is input to the second input terminal, the high potential power supply voltage is output from the output terminal,
2. The level shift circuit according to claim 1, wherein when the high-level signal is input to the first input terminal and the low-level signal is input to the second input terminal, the low-potential power supply voltage is output from the output terminal.   A source electrode connected to the gate electrode of the first transistor, a drain electrode of the third transistor, a drain electrode connected to the gate electrode of the fifth transistor and the drain electrode of the sixth transistor, and the high potential power source The level shift circuit according to any one of claims 1 to 3, further comprising an N-channel seventh transistor including a connected gate electrode.

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