JP2010258305A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that suppresses damage to a substrate itself during very-short-time annealing. <P>SOLUTION: The method of manufacturing the semiconductor device includes the steps of: forming a gate electrode on the semiconductor substrate; introducing a conductive impurity into the semiconductor substrate; forming a protective film on the semiconductor substrate and gate electrode; polishing the entire reverse surface of the semiconductor substrate after forming the protective film; and activating the impurity through a heat treatment in which the top surface of the semiconductor substrate is held at a temperature of ≥1,000°C for ≤0.1 s after polishing the entire reverse surface of the semiconductor substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using an extremely short time annealing technique.

  With the progress of miniaturization of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) elements, there is an increasing demand for thinning of the impurity active layer formed as a part of the MOSFET elements. In order to realize the thinning of the impurity active layer, it has been required to simultaneously increase the temperature and shorten the time for the heat treatment at the time of impurity activation.

In recent years, an extremely short time annealing (MSA) using a flash lamp or an infrared laser has been used. (For example, refer to Patent Document 1.)
However, in the case of using such an extremely short time annealing process, the heat applied to the semiconductor substrate is applied in an extremely non-equilibrium state, so that the stress applied to the substrate is increased. Specifically, since the mechanism is such that the time is very short and only the front surface side of the semiconductor substrate is heated, the temperature of the semiconductor substrate during the heat treatment generates a temperature gradient in the thickness direction of the substrate, and the back surface of the substrate is large. Tensile stress is applied.

  By the way, in the manufacturing process of a semiconductor device, various processes are performed before the MSA process is performed. Various processes are performed on the back surface of the semiconductor substrate by mechanical transport of the semiconductor substrate or holding the substrate in the process chamber in these processes. There is an opportunity to get scratched.

  Such scratches on the back surface of the semiconductor substrate may be able to be reduced by adjustment of the apparatus depending on the semiconductor manufacturing apparatus. However, even if adjustments are made even if the damage is caused by the mechanism of the manufacturing apparatus. There are also wounds that are accidentally attached, and it is virtually impossible to completely eliminate the chance of such wounds.

  In the manufacturing process of a semiconductor device before applying the MSA process, the scratches on the back surface have been regarded as a problem only as a source of particles that mainly increase the defective rate of the product. However, the application of MSA technology causes this flaw to function as a concentration point of the back surface stress generated during the MSA process, and it becomes a problem that the substrate is cracked starting from the back surface flaw. ing.

JP2008-108891

  It is an object of the present invention to provide a method for manufacturing a semiconductor device that suppresses damage to the substrate itself when performing an extremely short time annealing treatment.

  A method for manufacturing a semiconductor device according to an aspect of the present invention includes a step of forming a gate electrode over a semiconductor substrate, a step of introducing a conductive impurity into the semiconductor substrate, and a protective film over the semiconductor substrate and the gate electrode. Forming the protective film, polishing the entire back surface of the semiconductor substrate after forming the protective film, and holding the surface of the semiconductor substrate at a temperature of 1000 ° C. or higher after polishing the entire back surface of the semiconductor substrate. And a step of activating the impurities by heat treatment for 1 second or less.

  According to the present invention, it is possible to provide a method of manufacturing a semiconductor device that suppresses damage to the substrate itself when performing an extremely short time annealing treatment.

It is sectional drawing which represented typically the mechanism of the stress generation | occurrence | production by the back surface damage which concerns on the 1st Embodiment of this invention. It is the graph which showed how much the stress concentrated on the maximum stress point was amplified from the original stress by the change of the value of d / r concerning a 1st embodiment of the present invention. It is a process flow figure showing a manufacturing method of a semiconductor device concerning Example 1 of the present invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is a process flow figure showing a manufacturing method of a semiconductor device concerning Example 2 of the present invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is a process flow figure showing a manufacturing method of a semiconductor device concerning Example 3 of the present invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is process sectional drawing which represented typically the manufacturing method of the semiconductor device which concerns on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

First, a mechanism in which tensile stress is concentrated due to scratches on the back surface of the semiconductor substrate in the MSA process will be described with reference to FIG. The stress applied to the back surface of the substrate and sigma _0, the depth of the substrate back surface scratches that occur in the process d, the curvature radius of the wound of the tip assuming r, the maximum stress point near the tip of the substrate back surface flaws (back surface flaws Specifically, the maximum stress σ _max concentrated in the region of about 2 / r in the depth direction from the tip of the tip can be expressed by the following equation.

σ _max to (1 + 2 (d / r) ^1/2 ) σ ₀
As can be seen from the above equation, the greater the value of d and the smaller the value of r, the greater the stress concentrated at the maximum stress point. In other words, a scratch having a narrow opening width is more problematic than a scratch having a wide opening width and a shallow opening. FIG. 2 is a graph showing how much the stress concentrated at the maximum stress point is amplified from the original stress by changing the value of d / r.

As shown in FIG. 2, to reach even several tens of times from several times the original stress sigma _0, the resulting tensile stress at the time of MSA treatment, concentrated stress value is silicon brittle fracture stress (about 1～2GPa) This causes a problem that the silicon substrate is damaged. In order to solve this problem, it is required to perform the MSA process in a state where there is no flaw that causes stress concentration on the back surface of the semiconductor substrate.

  As a result of observing backside scratches in the semiconductor manufacturing process so far, it has been found that there are various depths of backside scratches d ranging from shallow depths of less than 1 μm to very deep depths of about 10 to 20 μm. Therefore, if the back surface of the semiconductor substrate is polished at least 20 μm or more, most of the scratches will be eliminated, or even if some scratches remain, the depth of the scratches will be greatly reduced. It can be considered to be smaller.

  FIG. 3 is a process flow diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. 4 to 6 are process sectional views schematically showing the process flow shown in FIG. A first embodiment of the present invention will be described with reference to FIGS. It should be noted that each configuration shown in FIGS. 4 to 6 is different from the actual dimensional ratio.

  First, as shown in FIG. 4A, a trench is formed in the main surface of the semiconductor substrate 1 by using, for example, RIE (Reactive Ion Etching) method, and an insulating film is embedded in the trench, thereby isolating elements. The insulating region 2 is formed (S101). Subsequently, the well diffusion layer region 3 is formed on the main surface of the semiconductor substrate 1 by ion implantation (S102). The well diffusion layer region may be appropriately formed into a p-type well and an n-type well for each region surrounded by each element isolation region 2.

Next, as shown in FIG. 4B, a gate insulating film 4 and a gate electrode 5 such as polycrystalline silicon are formed on the well diffusion layer region 3 by a well-known transistor formation technique (S103). The gate electrode insulating film 4 is, for example, a silicon oxide film (SiO ₂ ) formed by thermally oxidizing the surface of the well diffusion layer, and the gate electrode is a polycrystalline silicon film formed on the gate insulating film 4 or It is formed by processing a gate electrode material made of a metal film or the like.

  Next, as shown in FIG. 4C, ion implantation is performed by a known ion implantation technique using the gate electrode 4 as a mask, thereby forming an ion implantation region 6 to be a source / drain region of the transistor (S104).

  Subsequently, as shown in FIG. 5A, a gate electrode sidewall material (for example, silicon nitride film) 7 is deposited so as to cover the semiconductor substrate 1 and the gate electrode 5, and a substrate surface protective film (for example, silicon oxide film) is deposited. A film) 8 is formed (S105). This protective film 8 is formed to protect the surface of the semiconductor substrate 1 in the subsequent back surface polishing process of the semiconductor substrate 1. The material of the protective film 8 may be, for example, a silicon oxide film or a silicon nitride film using a CVD (Chemical Vapor Deposition) method.

  After forming the protective film 8, as shown in FIG. 5B, the entire back surface of the semiconductor substrate 1 is polished using, for example, a CMP (Chemical Mechanical Polishing) method or the like (S106). Here, the back surface of the semiconductor substrate 1 refers to a surface opposite to the surface on which the gate electrode 5 is formed. The amount of polishing the back surface of the semiconductor substrate 1 can be adjusted as appropriate, but is preferably 20 μm or more. By polishing at least 20 μm or more, most of the scratches that have occurred on the entire back surface of the semiconductor substrate 1 until this step are eliminated or significantly shallow, so that damage to the semiconductor substrate 1 can be effectively suppressed. .

  After the back surface of the semiconductor substrate 1 is polished, as shown in FIG. 5C, the protective film 8 is removed by using, for example, a dilute acid etching process. (S107). Further, the gate electrode sidewall 7 is formed by processing the exposed gate electrode sidewall material 7 using a RIE (Reactive Ion Etching) method or the like. Then, as shown in FIG. Light is applied to the entire surface of the semiconductor substrate 1 using a xenon (Xe) flash lamp (S108).

  The flash lamp irradiation time is 10 ms or less, and the irradiation energy density is 20 to 35 J / cm 2. By this light irradiation (flash lamp annealing), the crystal elements formed in the ion implantation region 6 are recovered, and at the same time, the introduced impurity element is activated, and the source / drain diffusion layer region 9 is obtained. When irradiating with flash lamp light, it is desirable to heat the substrate to a temperature of about 400 ° C. in advance before the light irradiation.

In addition to annealing using flash lamp light, MSA processing uses annealing processing using laser light from infrared to visible light, such as gas lasers such as CO ₂ lasers and semiconductor lasers such as YAG lasers. It doesn't matter. In this embodiment, the MSA treatment refers to a heat treatment in which the surface of the semiconductor substrate 1 is heated to 1000 ° C. or higher and the holding time of the surface of the semiconductor substrate 1 at 1000 ° C. or higher is 0.1 second or less.

  In this embodiment, the surface protective film 8 is removed and the gate sidewall material 7 is processed before the MSA process such as flash lamp annealing. However, the protective film 8 and the gate sidewall material 7 are formed on the substrate surface. You may perform MSA process in the state which remained in the whole.

  Subsequently, as shown in FIG. 6B, a metal such as nickel (Ni) is deposited on the surface of the semiconductor substrate 1 by a sputtering method or the like, and heat treatment is performed to thereby form the gate electrode 5 and the source / drain diffusion layers. The surface of the region 9 is silicided to form a nickel silicide film 10. After the heat treatment, unreacted metal remaining on the element isolation region 2 and the like is removed by wet etching or the like.

  Next, as illustrated in FIG. 6C, an interlayer insulating film 11 such as a silicon oxide film is deposited on the surface of the semiconductor substrate 1. Then, contact holes are opened in the interlayer insulating film 11 on the gate electrode 5 and the source / drain diffusion layer 9, respectively. A contact plug 12 is formed by burying a conductive material such as metal in each contact hole, and a metal wiring 13 is connected to the contact plug 12 to manufacture a semiconductor device.

  As described above, by using the method for manufacturing a semiconductor device according to the first embodiment of the present invention, it is possible to remove or shallow a scratch generated on the back surface of the semiconductor substrate 1 before the MSA process. By doing so, the thermal stress to the semiconductor substrate 1 at the time of MSA processing can be relieved, and damage to the semiconductor substrate 1 can be suppressed.

  The process position for polishing the back surface of the semiconductor substrate 1 is most preferably immediately before the MSA process, but if it is difficult to perform the process immediately before the MSA process due to a combination of processes, at least the pattern of the gate electrode 4 is formed. If polishing of the back surface of the semiconductor substrate is performed at any timing after the completion, the effect of suppressing damage to the semiconductor substrate 1 can be obtained.

  Then, the manufacturing method of the semiconductor device which concerns on Example 2 of this invention is demonstrated. FIG. 7 is a process flow diagram illustrating the method of manufacturing a semiconductor device according to the second embodiment of the present invention. 8 to 10 are process sectional views schematically showing the process flow shown in FIG. A second embodiment of the present invention will be described with reference to FIGS. The method for manufacturing a semiconductor device according to the second embodiment of the present invention is characterized in that it includes a process in which MSA processing and conventional RTA (Rapid Thermal Annealing) processing are combined.

  Examples thereof will be described below. First, as shown in FIG. 8A, a trench is formed on the main surface of the semiconductor substrate 21 using, for example, RIE, and an element isolation region 22 is formed by embedding an insulating film inside the trench. (S201). Subsequently, the well diffusion layer region 23 is formed on the main surface of the semiconductor substrate 21 by ion implantation (S202). The well diffusion layer region may be appropriately formed into a p-type well and an n-type well for each region surrounded by each element isolation region 22.

  Next, as shown in FIG. 8B, a gate insulating film 24 and a gate electrode 25 such as polycrystalline silicon are formed on the well diffusion layer region 23 by a well-known transistor formation technique (S203). The material of the gate insulating film 24 is, for example, a silicon oxide film formed by thermally oxidizing the surface of the well diffusion layer 23, and the gate electrode 25 is a polycrystalline silicon film or metal film formed on the gate insulating film 24. It is formed by processing a gate electrode material made of or the like.

  Next, as shown in FIG. 8C, a relatively shallow ion implantation region 26 to be a source / drain / extension region of the transistor is formed by a well-known ion implantation technique (S204). Further, as shown in FIG. 9A, a gate oxide film 27 is formed by depositing a silicon oxide film or the like on the entire surface of the substrate and processing it using the RIE method or the like (S205). By using the sidewall insulating film 27 as a mask, a relatively deep ion implantation region 28 to be a source / drain / contact region of the transistor is formed by a well-known ion implantation technique (S206).

  Subsequently, as shown in FIG. 9B, a surface protective film 29 such as a silicon nitride film is deposited on the entire surface of the substrate (S207). As the RTA treatment, for example, Spike RTA of about 1000 to 1070 ° C., 1000 By performing a Soak RTA process or the like at about 10 ° C. or below for about 10 ° C. or less, a relatively shallow ion implantation region 26 serving as a source / drain / extension region or a relatively deep ion implantation region 28 serving as a source / drain / contact region. At the same time, the introduced impurity elements are activated, and the source / drain / extension diffusion layer region 30 and the source / drain / contact diffusion layer region 31 are obtained. In this embodiment, the RTA process refers to a heat treatment in which the time during which the temperature of the semiconductor substrate 21 is maintained in the range of 900 ° C. to 1100 ° C. is 1 second to 120 seconds.

  Here, by using a high-stress silicon nitride film or the like as the surface protection film 29 material such as a silicon nitride film, stress is accumulated in the polycrystalline silicon gate electrode during the recrystallization process by the RTA process, and the transistor channel It can also be used in combination with so-called SMT (Stress Memorization Technology) technology that improves carrier mobility in a region.

  Thereafter, as shown in FIG. 9C, the back surface of the semiconductor substrate 21 is polished using, for example, a CMP method (S209). The amount of polishing the back surface of the semiconductor substrate 21 can be adjusted as appropriate, but is preferably 20 μm or more. By polishing at least 20 μm or more, most of the scratches that have occurred on the entire back surface of the semiconductor substrate 21 until this step are eliminated or significantly shallow, so that damage to the semiconductor substrate 21 can be effectively suppressed. .

  After the back surface of the semiconductor substrate 21 is polished, the protective film 29 is removed. Note that when the subsequent MSA process is performed via the protective film 29, the order of the MSA process and this process may be interchanged (S210). In this embodiment, since the RTA treatment is performed before the protective film 16 is formed, it is possible to suppress etching of the impurity diffusion layer that is not crystallized when the protective film is removed.

After removing the protective film 29, as shown in FIG. 10, the entire surface of the semiconductor substrate 21 is irradiated with an MSA treatment using, for example, a xenon (Xe) flash lamp (S209). Irradiation time of the flash lamp is less 10 ms, the irradiation energy density and 20~35J / cm ^2. By this light irradiation (flash lamp annealing), the activation rate of impurities introduced into the source / drain / extension diffusion layer region 30, the source / drain / contact diffusion layer region 31, and the polycrystalline silicon gate electrode 25 is increased. Improved performance. When irradiating the flash lamp light, it is desirable to heat the semiconductor substrate 21 to a temperature of about 400 ° C. in advance before the light irradiation.

In addition to annealing using flash lamp light, MSA treatment uses annealing treatment using laser light from infrared to visible light such as gas laser such as CO ₂ laser and semiconductor laser such as YAG laser. It doesn't matter. In this embodiment, the MSA treatment refers to a heat treatment in which the surface of the semiconductor substrate 11 is heated to 1000 ° C. or more and the holding time of the surface of the semiconductor substrate 11 at 1000 ° C. or more is 0.1 second or less.

  Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted here.

  As described above, by using the semiconductor device manufacturing method according to the second embodiment of the present invention, it is possible to remove or shallow the scratches generated on the back surface of the semiconductor substrate 21 before the MSA process. By doing so, the thermal stress to the semiconductor substrate 21 at the time of MSA processing can be relieved, and damage to the semiconductor substrate 21 can be suppressed. Further, since the RTA treatment is performed before the formation of the protective film 29, the crystal defects remaining in the impurity layer can be further suppressed, and the surface of the impurity diffusion layer when the protective film 29 is removed can be suppressed.

  The process position for polishing the back surface of the semiconductor substrate 21 is most preferably immediately before the MSA process, but if it is difficult to perform the process immediately before the MSA process due to a combination of processes, at least the pattern of the gate electrode 25 is formed. If polishing of the back surface of the semiconductor substrate is performed at any timing after the completion, the effect of suppressing damage to the semiconductor substrate 21 can be obtained.

  Then, the manufacturing method of the semiconductor device which concerns on Example 3 of this invention is demonstrated. FIG. 11 is a process flow diagram illustrating the method of manufacturing a semiconductor device according to the third embodiment of the present invention. 12 to 14 are process sectional views schematically showing the process flow shown in FIG. A third embodiment of the present invention will be described with reference to FIGS. The semiconductor device manufacturing method according to Embodiment 3 of the present invention includes a step of forming at least one of a boron-doped polycrystalline silicon film and a silicon nitride film on the back surface of the semiconductor substrate in addition to the steps of Embodiment 1. It is characterized by being.

  In the manufacturing process of a semiconductor device, a polycrystalline silicon doped with high-concentration boron (Boron) is attached to the back surface of the semiconductor substrate, or a silicon nitride film is left on the back surface of the semiconductor substrate. Techniques may be used to reduce the impact on unpredictable metal contamination in the process. Here, the boron-doped polycrystalline silicon film mainly serves as a gettering layer for the metal element, and the silicon nitride film mainly serves as a protective layer for protecting the back surface of the semiconductor substrate from contamination of the metal element. When polishing the back surface of the substrate in the manufacturing process of the semiconductor device, the problem that the polycrystalline silicon or silicon nitride film doped with high-concentration boron previously formed is lost is as follows. Can be avoided.

  First, as shown in FIG. 12A, a trench is formed in the main surface of the semiconductor substrate 41 by using, for example, the RIE method, and an element isolation insulating region 42 is formed by embedding an insulating film in the trench. Form (S301). Subsequently, a well diffusion layer region 43 is formed on the main surface of the semiconductor substrate 41 by ion implantation (S302). The well diffusion layer region may be appropriately formed into a p-type well and an n-type well for each region surrounded by each element isolation region 42.

Next, as shown in FIG. 12B, a gate insulating film 44 and a gate electrode 45 such as polycrystalline silicon are formed on the well diffusion layer region 43 by a well-known transistor formation technique (S303). The material of the gate insulating film 44 is, for example, a silicon oxide film (SiO ₂ ) formed by thermally oxidizing the surface of the well diffusion layer, and the gate electrode 45 is a polycrystalline silicon film formed on the gate insulating film 44, Alternatively, it is formed by processing a gate electrode material made of a metal film or the like.

  Next, as shown in FIG. 12C, ion implantation regions 46 to be the source / drain regions of the transistor are formed by performing ion implantation using the gate electrode 45 as a mask by a known ion implantation technique (S304).

  Subsequently, as shown in FIG. 13A, a gate electrode sidewall material (for example, silicon nitride film) 47 is deposited so as to cover the semiconductor substrate 41 and the gate electrode 45, and a substrate surface protective film (for example, silicon oxide film) is further deposited. 48 is formed (S305). The protective film 48 is formed to protect the surface of the semiconductor substrate 41 in the subsequent back surface polishing process of the semiconductor substrate 41. As a material of the protective film 48, for example, a silicon oxide film or a silicon nitride film using a CVD method can be considered.

  After forming the protective film 48, the entire back surface of the semiconductor substrate 41 is polished by using, for example, a CMP method (S306). Here, the back surface of the semiconductor substrate 41 refers to a surface opposite to the surface on which the gate electrode 45 is formed. The amount of polishing the back surface of the semiconductor substrate 41 can be adjusted as appropriate, but is preferably 20 μm or more. By polishing at least 20 μm or more, most of the scratches that have occurred on the entire back surface of the semiconductor substrate 41 until this step are eliminated or significantly shallow, so that damage to the semiconductor substrate 41 can be effectively suppressed. .

  After the back surface of the semiconductor substrate 41 is polished, as shown in FIG. 13B, the semiconductor can be formed by a method capable of forming a film at a relatively low temperature such as sputtering or plasma CVD and selectively depositing on the back surface of the substrate. A boron-doped polycrystalline silicon film 49 is formed on the back surface of the substrate 41 (S307). Here, following the formation of the boron-doped polycrystalline silicon film 49, the silicon nitride film 50 may be formed on the boron-doped polycrystalline silicon film 49. Further, a silicon nitride film may be formed directly on the back surface of the semiconductor substrate 41 without forming the boron-doped polycrystalline silicon film 49. By using a process capable of forming a film at a low temperature, diffusion of impurities in the ion implantation region 25 before the heat treatment for activation can be suppressed.

  Furthermore, a deposition method such as an LP-CVD method in which the boron-doped polycrystalline silicon film 49 and the silicon nitride film 50 are formed simultaneously on the front and back surfaces of the semiconductor substrate 41 may be used. It is also possible to form the back surface protective film by simultaneously forming films on the front and back surfaces of the semiconductor substrate 41 and removing only the film deposited on the front surface side of the semiconductor substrate 41. As a method for removing the film deposited on the surface side of the semiconductor substrate 41, etching by the RIE method using the surface protective film 48 as an etching stopper can be cited.

  Subsequently, as shown in FIG. 13C, the surface protective film 48 is removed by using, for example, dilute boiling acid etching (S308). Further, the gate electrode sidewall 47 is formed by processing the exposed gate electrode sidewall material (for example, silicon nitride film) 47 by the RIE method or the like. After the gate electrode sidewall 47 is formed, light is irradiated on the entire surface of the semiconductor substrate 41 using, for example, a xenon (Xe) flash lamp as an MSA process (S309).

  The flash lamp irradiation time is 10 ms or less, and the irradiation energy density is 20 to 35 J / cm 2. By this light irradiation (flash lamp annealing), the crystal defects formed in the ion implantation region 46 are recovered, and at the same time, the introduced impurity element is activated, and the source / drain diffusion layer region 51 is obtained. When irradiating the flash lamp light, it is desirable to heat the semiconductor substrate 41 to a temperature of about 400 ° C. in advance before the light irradiation.

In addition to annealing using flash lamp light, MSA treatment uses annealing treatment using laser light from infrared to visible light such as gas laser such as CO ₂ laser and semiconductor laser such as YAG laser. It doesn't matter. In this embodiment, the MSA treatment refers to a heat treatment in which the surface of the semiconductor substrate 41 is heated to 1000 ° C. or more and the holding time of the surface of the semiconductor substrate 41 at 1000 ° C. or more is 0.1 second or less. In this embodiment, the surface protective film 48 is removed and the gate sidewall material 47 is processed before performing the MSA process such as flash lamp annealing. However, the protective film 48 and the gate sidewall material 47 are formed on the substrate surface. You may perform MSA process in the state which remained in the whole.

  Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted here.

  As described above, by using the semiconductor device manufacturing method according to the third embodiment of the present invention, it is possible to remove or shallow the scratches generated on the back surface of the semiconductor substrate 41 before the MSA process. By doing so, thermal stress to the semiconductor substrate 41 during the MSA process can be relaxed, and damage to the semiconductor substrate 41 can be suppressed.

  The process position for polishing the back surface of the semiconductor substrate 41 is most preferably immediately before the MSA process. However, if it is difficult to perform the process immediately before the MSA process by a combination of processes, at least a pattern of the gate electrode 45 is formed. If polishing of the back surface of the semiconductor substrate is performed at any timing after completion of the process, an effect of suppressing damage to the semiconductor substrate 41 can be obtained.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in addition to the steps of Example 2, the boron-doped polycrystalline silicon film and silicon nitride film described in Example 3 may be formed on the back surface of the semiconductor substrate.

1, 21, 41 Semiconductor substrate 2, 22, 42 Element isolation region 3, 23, 43 Well diffusion layer region 4, 24, 44 Gate insulating film 5, 25, 45 Gate electrode 6, 46 Ion implantation region 7, 27, 47 Gate sidewall material 8, 29, 48 Protective film 9, 51 Source / drain diffusion layer region 10 Nickel silicide film 11 Interlayer insulating film 12 Contact plug 13 Metal wiring 26 Shallow ion implantation region 28 Deep ion implantation region 30 Source / drain extension diffusion Layer region 31 Source / drain / contact diffusion layer region 49 Boron doped polycrystalline silicon film 50 Silicon nitride film

Claims (7)

Forming a gate electrode on the semiconductor substrate;
Introducing a conductive impurity into the semiconductor substrate;
Forming a protective film on the semiconductor substrate and the gate electrode;
Polishing the entire back surface of the semiconductor substrate after forming the protective film;
And a step of activating the impurities by a heat treatment such that after the entire back surface of the semiconductor substrate is polished, the surface of the semiconductor substrate has a retention time at 1000 ° C. or higher of 0.1 seconds or less. A method for manufacturing a semiconductor device.   2. The semiconductor according to claim 1, wherein the step of introducing conductive impurities into the semiconductor substrate is a step of introducing impurities of the same conductivity type having at least two types of depth distribution into the semiconductor substrate. Device manufacturing method.   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a heat treatment step of maintaining the temperature of the semiconductor substrate in a range of 900 ° C. to 1100 ° C. for 1 second to 120 seconds.   4. The method of manufacturing a semiconductor device according to claim 1, wherein film formation is selectively performed on the back surface of the semiconductor substrate after the step of polishing the entire back surface of the semiconductor substrate. 5.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the protective film before the step of activating the impurities.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the entire back surface of the semiconductor substrate is polished by 20 [mu] m or more.   The semiconductor manufacturing apparatus according to claim 1, wherein the impurity activation step is performed using flash lamp annealing or laser annealing.

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