JP2010253698A - Drive signal generating circuit, and fluid jetting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase an electric charge that is recovered when the charge when discharging a capacitive load is recovered. <P>SOLUTION: One end of a charge pump capacitor is connected to a high-voltage side power supply voltage terminal of a current amplification circuit which charges and discharges the capacitive load according to a voltage change of an original drive signal, and the other end of the charge pump capacitor is connected to a low-voltage side power supply voltage terminal of the current amplification circuit. When the charge pump capacitor is charged with a predetermined voltage, a first storage capacitor and a second storage capacitor are connected in series, and the predetermined voltage is impressed to the series-connected first storage capacitor and second storage capacitor. when discharging the capacitive load, the first storage capacitor and the second storage capacitor are electrically cut from each other, and the charge from the low-voltage side power supply voltage terminal of the current amplification circuit is accumulated in at least one of the first storage capacitor and the second storage capacitor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a drive signal generation circuit and a fluid ejection device.

  2. Related Art Ink jet printers that eject ink and print an image are known that eject ink using a piezoelectric element (for example, a piezo element). The piezoelectric element is electrically a capacitive load such as a capacitor. A piezoelectric element is provided for each nozzle, and it is necessary to supply a sufficient current to operate the piezoelectric element of each nozzle. For this reason, the original drive signal is amplified by a current amplifier circuit, and the amplified drive signal is supplied to the head (see, for example, Patent Document 1).

JP 2006-272907 A

In the current amplification circuit of Patent Document 1, the high-voltage power supply voltage terminal of the current amplification circuit is connected to the power supply, and the low-voltage power supply voltage terminal is grounded. When the current drive circuit amplifies the current of the original drive signal, the power consumption in the charging transistor is the amount obtained by multiplying the voltage difference between the high-voltage power supply voltage and the drive signal by the current, and the power consumption in the discharge transistor. Since the power is an amount obtained by multiplying the voltage difference between the low-voltage power supply voltage and the drive signal by the current, the power consumption in each transistor increases.
Therefore, an object of the present invention is to provide a configuration that reduces power consumption. In addition, an object of the present invention is to increase the amount of charge that can be regenerated when regenerating the charge during discharge in a configuration that employs a charge pump circuit to reduce power consumption.

  A main invention for achieving the above object is to provide a current amplification circuit that receives an original drive signal and charges and discharges a capacitive load according to a voltage change of the original drive signal, and a high-voltage side power supply voltage terminal of the current amplification circuit. A charge pump capacitor having one end connected to the low voltage side power supply voltage terminal of the current amplifier circuit and the other end connected to the capacitor, the charge pump capacitor being charged at the predetermined voltage when the capacitive load is charged A charge pump capacitor for raising the voltage of the high-voltage side power supply voltage terminal of the current amplification circuit to a voltage higher than the predetermined voltage by increasing the voltage on the other end side of the current amplification circuit, and discharging the capacitive load A drive signal generation circuit comprising a first power storage capacitor and a second power storage capacitor for storing charge, wherein the charge pump capacitor The first power storage capacitor and the second power storage capacitor by electrically connecting one end of the first power storage capacitor and one end of the second power storage capacitor when charging the battery at the predetermined voltage. Are connected in series, and the predetermined voltage is applied to the first power storage capacitor and the second power storage capacitor connected in series, and when discharging the capacitive load, the one end of the first power storage capacitor and the first 2 electrically disconnecting the one end of the storage capacitor, and charge from at least one of the first storage capacitor and the second storage capacitor to the low-voltage power supply voltage terminal of the current amplification circuit. It is a drive signal generation circuit characterized by being accumulated.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

1 is a block diagram of the overall configuration of a printer. FIG. 2A is a schematic diagram of the overall configuration of the printer 1. FIG. 2B is a cross-sectional view of the overall configuration of the printer 1. It is explanatory drawing of the drive signal COM. It is explanatory drawing of a structure of the drive signal generation circuit 65 of the 1st reference example. It is explanatory drawing of operation | movement of the drive signal generation circuit 65 of the 1st reference example. It is explanatory drawing of a structure of the drive signal generation circuit 65 of the 2nd reference example. It is explanatory drawing of the time change of the voltage at the original drive signal OCOM of 2nd reference example, a control signal, and each point. It is explanatory drawing of the drive signal generation circuit 65 of 1st Embodiment. It is explanatory drawing of the time change of a drive signal and the electric potential in each point. It is explanatory drawing of on / off control of each switch. It is explanatory drawing of the drive signal generation circuit of 2nd Embodiment. FIG. 12A is an explanatory diagram of changes over time in the original drive signal OCOM, the control signal, and the voltage at the point E in the second embodiment. FIG. 12B is an explanatory diagram of changes over time in the original drive signal OCOM and the voltages at points A and B. FIG. 13A is an explanatory diagram of current at time T0. FIG. 13B is an explanatory diagram of current at times Tb to T2. FIG. 13C is an explanatory diagram of current at times T4 to T5. It is explanatory drawing of the drive signal generation circuit of 3rd Embodiment. FIG. 15A is an explanatory diagram of changes over time in the original drive signal OCOM, the control signal, and the voltage at the point E in the third embodiment. FIG. 15B is an explanatory diagram of changes over time in the voltages of the original drive signal OCOM, point A, and point B.

  At least the following matters will become clear from the description of the present specification and the accompanying drawings.

An original drive signal is input, one end of the current amplification circuit that charges and discharges the capacitive load according to a voltage change of the original drive signal, and one end of the current amplification circuit that is connected to the high-voltage side power supply voltage terminal. A charge pump capacitor having the other end connected to the low-voltage side power supply voltage terminal, by increasing the voltage at the other end of the charge pump capacitor charged at the predetermined voltage when charging the capacitive load; A charge pump capacitor for causing the voltage of the high-voltage side power supply voltage terminal of the current amplifier circuit to be higher than the predetermined voltage, a first storage capacitor for accumulating charges during discharging of the capacitive load, and a first capacitor A storage signal capacitor, and when charging the charge pump capacitor at the predetermined voltage, The first power storage capacitor and the second power storage capacitor are connected in series by electrically connecting one end of one power storage capacitor and one end of the second power storage capacitor, and the first power storage connected in series The predetermined voltage is applied to the capacitor for storage and the capacitor for second storage, and when the capacitive load is discharged, the one end of the first storage capacitor and the one end of the second storage capacitor are electrically disconnected. And a drive signal generation circuit characterized in that at least one of the first power storage capacitor and the second power storage capacitor stores charge from the low-voltage power supply voltage terminal of the current amplifier circuit. It becomes.
According to such a drive signal generation circuit, more electric charge can be regenerated during discharge of the capacitive load.

In this drive signal generation circuit, a first switch provided between the one end of the first power storage capacitor and the one end of the second power storage capacitor, and the one end of the first power storage capacitor and the ground And a third switch provided between the one end of the second power storage capacitor and the other end of the first power storage capacitor, and the first power storage When the capacitor for storage and the capacitor for second storage are connected in series, the first switch is turned on, the second switch and the third switch are turned off, and the first storage capacitor and the second storage capacitor When the capacitors are connected in parallel, it is desirable to turn off the first switch and turn on the second switch and the third switch.
According to such a drive signal generation circuit, the connection state of the first power storage capacitor and the second power storage capacitor can be easily changed to the series connection and the parallel connection by controlling on / off of the first switch to the third switch. It can be switched easily.

The drive signal generation circuit includes a power source having the predetermined voltage, and a fourth switch provided between the power source and the other end of the first storage capacitor, and the first switch is turned off. The fourth switch is preferably turned off when the second switch and the third switch are turned on.
According to such a drive signal generation circuit, it is possible to avoid the first power storage capacitor and the second power storage capacitor from being charged from the power source during charge regeneration.

In this drive signal generation circuit, a first state in which the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off, and the first switch and the fourth switch are turned on. It is desirable to turn off all the switches between the second state where the second switch and the third switch are turned on.
According to such a drive signal generation circuit, it can be avoided that the first switch and the fourth switch, and the second switch and the third switch are simultaneously turned on.

In this drive signal generation circuit, it is desirable to have a third power storage capacitor having one end connected to the other end of the first power storage capacitor and the other end grounded.
According to such a drive signal generation circuit, it is possible to prevent the voltage from becoming unstable when the switches are simultaneously turned off.

  A piezoelectric element that is displaced in response to a voltage change in order to eject a fluid from the nozzle; a current amplification circuit that receives an original drive signal and charges and discharges the piezoelectric element in accordance with a voltage change in the original drive signal; A charge pump capacitor having one end connected to the high-voltage side power supply voltage terminal of the current amplification circuit and the other end connected to the low-voltage side power supply voltage terminal of the current amplification circuit, wherein the predetermined voltage is applied when the piezoelectric element is charged. A charge pump capacitor for increasing the voltage at the other end of the charged charge pump capacitor to make the voltage of the high-voltage power supply voltage terminal of the current amplifier circuit higher than the predetermined voltage; A drive signal generation circuit comprising a first power storage capacitor and a second power storage capacitor for storing charge during discharge of the piezoelectric element. When the charge pump capacitor is charged at the predetermined voltage, the first power storage capacitor and the second power storage capacitor are electrically connected to each other by electrically connecting one end of the first power storage capacitor and the second power storage capacitor. A second power storage capacitor is connected in series, the first power storage capacitor and the second power storage capacitor are charged with the predetermined voltage, and when the piezoelectric element is discharged, the one end of the first power storage capacitor The one end of the second power storage capacitor is electrically disconnected, and at least one of the first power storage capacitor and the second power storage capacitor is connected to the low voltage side power supply voltage terminal of the current amplification circuit. A fluid ejecting apparatus characterized by accumulating electric charge becomes clear.

  In the following embodiments, an ink jet printer (hereinafter also referred to as printer 1) will be described as an example.

=== Printer configuration ===
<Inkjet printer configuration>
FIG. 1 is a block diagram of the overall configuration of the printer 1. FIG. 2A is a schematic diagram of the overall configuration of the printer 1. FIG. 2B is a cross-sectional view of the overall configuration of the printer 1. Hereinafter, a basic configuration of the printer will be described.

  The printer 1 includes a transport unit 20, a carriage unit 30, a head unit 40, a detector group 50, and a controller 60. The printer 1 that has received print data from the computer 110 that is an external device controls each unit (the conveyance unit 20, the carriage unit 30, and the head unit 40) by the controller 60. The controller 60 controls each unit based on the print data received from the computer 110 and prints an image on paper. The situation in the printer 1 is monitored by the detector group 50, and the detector group 50 outputs the detection result to the controller 60. The controller 60 controls each unit based on the detection result output from the detector group 50.

  The transport unit 20 is for transporting a medium (for example, paper S) in a predetermined direction (hereinafter referred to as a transport direction). The transport unit 20 includes a paper feed roller 21, a transport motor 22 (also referred to as a PF motor), a transport roller 23, a platen 24, and a paper discharge roller 25. The paper feed roller 21 is a roller for feeding the paper inserted into the paper insertion slot into the printer. The transport roller 23 is a roller that transports the paper S fed by the paper feed roller 21 to a printable region, and is driven by the transport motor 22. The platen 24 supports the paper S being printed. The paper discharge roller 25 is a roller for discharging the paper S to the outside of the printer, and is provided on the downstream side in the transport direction with respect to the printable area.

  The carriage unit 30 is for moving (also referred to as “scanning”) the head in a predetermined direction (hereinafter referred to as a moving direction). The carriage unit 30 includes a carriage 31 and a carriage motor 32 (also referred to as a CR motor). The carriage 31 can reciprocate in the moving direction and is driven by a carriage motor 32. Further, the carriage 31 detachably holds an ink cartridge that stores ink.

  The head unit 40 is for ejecting ink onto paper. The head unit 40 includes a head 41 having a plurality of nozzles. Since the head 41 is provided on the carriage 31, when the carriage 31 moves in the movement direction, the head 41 also moves in the movement direction. Then, by intermittently ejecting ink while the head 41 is moving in the moving direction, dot lines (raster lines) along the moving direction are formed on the paper. Each nozzle of the head 41 is provided with a piezo element, and ink is ejected from the nozzle by driving the piezo element with a drive signal COM (described later).

  The detector group 50 includes a linear encoder 51, a rotary encoder 52, a paper detection sensor 53, an optical sensor 54, and the like. The linear encoder 51 detects the position of the carriage 31 in the moving direction. The rotary encoder 52 detects the rotation amount of the transport roller 23. The paper detection sensor 53 detects the position of the leading edge of the paper being fed. The optical sensor 54 detects the presence or absence of paper by a light emitting unit and a light receiving unit attached to the carriage 31. The optical sensor 54 can detect the position of the edge of the paper while being moved by the carriage 31, and can detect the width of the paper. The optical sensor 54 also detects the leading end (the end on the downstream side in the transport direction, also referred to as the upper end) and the rear end (the end on the upstream side in the transport direction, also referred to as the lower end) depending on the situation. it can.

  The controller 60 is a control unit for controlling the printer. The controller 60 includes an interface unit 61, a CPU 62, a memory 63, a unit control circuit 64, and a drive signal generation circuit 65. The interface unit 61 transmits and receives data between the computer 110 that is an external device and the printer 1. The CPU 62 is an arithmetic processing unit for controlling the entire printer. The memory 63 is for securing an area for storing a program of the CPU 62, a work area, and the like, and includes storage elements such as a RAM and an EEPROM. The CPU 62 controls each unit via the unit control circuit 64 in accordance with a program stored in the memory 63.

The drive signal generation circuit 65 generates a drive signal COM for driving the piezo elements of the head unit 40. The drive signal COM generated by the drive signal generation circuit 65 is transmitted to the head 41 of the head unit 40 via the flexible cable 71.
The details of the drive signal generation circuit 65 will be described later.

  FIG. 3 is an explanatory diagram of the drive signal COM. The drive signal COM generated by the drive signal generation circuit 65 is applied to the piezo element. The piezoelectric element is charged while the voltage of the drive signal COM is increasing. Further, the piezo element is discharged during the period when the voltage of the drive signal COM is decreasing. The figure shows the drive signal COM during a period in which dots are formed in one pixel on the medium. When printing on the medium, the driving signal COM shown in the figure is repeatedly generated every time a dot is formed in each pixel. Then, the piezoelectric element is charged and discharged in accordance with the change of the drive signal COM. In this way, the piezo element is charged and discharged by the drive signal COM, and the piezo element is displaced according to the voltage change of the drive signal COM, whereby the ink chamber expands and contracts, and ink is ejected from the corresponding nozzle.

<Printing procedure>
When receiving a print command and print data from the computer 110, the controller 60 analyzes the contents of various commands included in the print data, and performs the following processing using each unit.

  First, the controller 60 rotates the paper feed roller 21 to send the paper S to be printed to the conveyance roller 23. Next, the controller 60 rotates the transport roller 23 by driving the transport motor 22. When the transport roller 23 rotates with a predetermined rotation amount, the paper S is transported with a predetermined transport amount.

  When the paper S is conveyed to the lower part of the head unit 40, the controller 60 rotates the carriage motor 32 based on the print command. In response to the rotation of the carriage motor 32, the carriage 31 moves in the movement direction. Further, as the carriage 31 moves, the head unit 40 provided on the carriage 31 also moves in the moving direction at the same time. Then, the controller 60 intermittently ejects ink droplets from the head 41 while the head unit 40 is moving in the movement direction. When the ink droplets land on the paper S, a dot row in which a plurality of dots are arranged in the moving direction is formed. A dot forming operation by ejecting ink from the moving head 41 is called a pass.

Further, the controller 60 drives the transport motor 22 while the head unit 40 reciprocates. The transport motor 22 generates a driving force in the rotation direction according to the commanded driving amount from the controller 60. And the conveyance motor 22 rotates the conveyance roller 23 using this driving force. When the transport roller 23 rotates with a predetermined rotation amount, the paper S is transported with a predetermined transport amount. That is, the transport amount of the paper S is determined according to the rotation amount of the transport roller 23. In this way, the pass and the transport operation are alternately repeated to form dots on each pixel of the paper S. Thus, an image is printed on the paper S.
Finally, the controller 60 discharges the paper S on which printing has been completed by the paper discharge roller 25 that rotates in synchronization with the transport roller 23.

=== Drive Signal Generation Circuit of First Embodiment ===
<First Reference Example>
FIG. 4 is an explanatory diagram of the configuration of the drive signal generation circuit 65 of the first reference example. Since the piezo element functions as a capacitive load, the piezo element is described as a capacitor (C1) in the figure. Further, the printer 1 is provided with a piezo element for each nozzle, but in the drawing, one capacitor indicating the piezo element is omitted.
The drive signal generation circuit 65 of the first reference example includes a D / A converter (hereinafter also referred to as DAC) 651 and a current amplification circuit 652.

  Drive signal data (digital data) is input to the DAC 651 from the CPU 62. The DAC 651 converts this digital data into an analog signal and outputs an original drive signal OCOM corresponding to the drive signal data. Note that the voltage change of the original drive signal OCOM is almost the same as the drive signal COM of FIG.

  The current amplifying circuit 652 is a circuit for supplying a sufficient current so that a large number of piezoelectric elements can operate without any trouble. The current amplifier circuit 652 outputs a drive signal COM for charging / discharging the piezo element C1 in accordance with a voltage change of the input original drive signal OCOM. The current amplifier circuit 652 includes a charge side transistor Q1 and a discharge side transistor Q2. The charge side transistor Q1 is an NPN type transistor, and the discharge side transistor Q2 is a PNP type transistor. That is, the current amplifier circuit 652 is a push-pull amplifier circuit in which two transistors are complementarily connected.

  The original drive signal OCOM from the DAC 651 is input to the base of the charge side transistor Q1 (NPN type transistor). The collector of the charge side transistor Q1 is connected to the 42V power source, the emitter of the charge side transistor Q1 is connected to the emitter of the discharge side transistor Q2, and the output signal line of the drive signal COM to the piezo element C1. It is connected. The drive signal COM is applied to the piezo element C1 through the switch SW1.

  The original drive signal OCOM from the DAC 651 is input to the base of the discharge side transistor Q2 (PNP transistor). The collector of the discharge side transistor Q2 is connected to the ground (GND), and the emitter of the discharge side transistor Q2 is connected to the emitter of the charge side transistor Q1.

  Next, the operation of the drive signal generation circuit 65 of the first reference example will be described. FIG. 5 is an explanatory diagram of the operation of the drive signal generation circuit 65 of the first reference example.

(When charging)
When the piezo element C1 is charged, the voltage of the original drive signal OCOM from the DAC 651 gradually increases. As a result, the charge-side transistor Q1 is turned on, and a current I1 flows as shown in the figure to charge the piezo element C1. The amount of heat generated (power consumption) of the charging side transistor Q1 at this time is represented by the product of the voltage between the collector and the emitter of the charging side transistor Q1 and the current I1. That is, the product is the product of the current I1 and the hatched portion on the left side of FIG.

(Hold)
At the time of holding, the voltage of the original drive signal OCOM does not change. As a result, both the charge side transistor Q1 and the discharge side transistor Q2 are turned off. Therefore, no current flows and the drive signal COM maintains the same voltage.

(During discharge)
When the piezo element C1 is discharged, the voltage of the original drive signal OCOM from the DAC 651 gradually decreases. As a result, the discharge-side transistor Q2 is turned on, and a current I2 flows as shown in the figure to discharge the piezo element. The amount of heat generated by the discharge-side transistor Q2 at this time is represented by the product of the voltage between the collector and emitter of the discharge-side transistor Q2 and the current I2. That is, the product is the product of the current I2 and the hatched portion on the right side of FIG.

<Second Reference Example>
In the first reference example, the area of the hatched portion (voltage difference between the collector and the emitter) is large and the amount of heat generation is large. On the other hand, in the second reference example, the voltage difference between the collector and the emitter is reduced to reduce the heat generation amount.
In the first reference example, all the charges charged in the piezo element are discharged to the ground. On the other hand, in the second reference example, part of the electric charge charged in the piezo element is regenerated during discharging.

  FIG. 6 is an explanatory diagram of the configuration of the drive signal generation circuit 65 of the second reference example. The drive signal generation circuit 65 of the second reference example includes a DAC 651, a current amplification circuit 652, a charge pump circuit 66, a regeneration capacitor C3, and a 21V power supply V1. The high-voltage side power supply voltage terminal of the current amplifier circuit 652 is connected to the high-voltage side output terminal of the charge pump circuit 66 (point A). The low-voltage power supply voltage terminal of the current amplifier circuit 652 is connected to the low-voltage output terminal of the charge pump circuit 66 (point B). A charging terminal of the charge pump circuit 66 is connected to a 21V power source V1 and a capacitor C3 (point C). The discharge terminal of the charge pump circuit 66 is connected to GND (D point).

  The DAC 651 has the same configuration as that of the first reference example. However, the DAC 651 of the second reference example outputs not only the original drive signal OCOM but also a control signal. The control signal will be described later.

  The current amplifier circuit 652 has the same configuration as that of the first reference example. However, in the second reference example, the connection destination of the collector of the charging side transistor Q1 is not the 42V power source but the high voltage side terminal of the capacitor C2 of the charge pump circuit 66 described later. The connection destination of the discharge side transistor Q2 is not the ground (GND) but the low voltage side terminal of the capacitor C2 of the charge pump circuit 66.

  The charge pump circuit 66 includes a capacitor C2, a voltage adjustment unit 661, a diode D1, and a diode D2. The charge pump circuit 66 applies a voltage higher than the original drive signal OCOM to the high-voltage power supply voltage terminal of the current amplifier circuit 652 (point A), and receives the voltage from the original drive signal OCOM to the low-voltage power supply voltage terminal of the current amplifier circuit 652. A low voltage is applied (point B).

  The capacitor C2 is a charge pump capacitor, and has a capacity larger than that of the capacitor C1 (the sum of the capacities of all piezo elements). The high voltage side terminal of the capacitor C2 is connected to the collector of the charge side transistor Q1, and the low voltage side terminal of the capacitor C2 is connected to the collector of the discharge side transistor Q2.

  The voltage adjustment unit 661 adjusts the voltage at point B (the low-voltage side terminal of the capacitor C2, that is, the collector of the discharge-side transistor Q2) in the figure. The operation of the voltage adjustment unit 661 is controlled by a control signal from the DAC 651.

  The voltage adjustment unit 661 of the second reference example has a source follower configuration including an N-channel FET (Q3) and a P-channel FET (Q4) that are complementarily connected. With this configuration, the output voltage (point B voltage) of the voltage adjustment unit 661 is controlled to be the same as the input voltage (control signal voltage).

  A control signal from the DAC 651 is applied to the gate of an N-channel FET (hereinafter also referred to as N-type FET) Q3. The drain of the N-type FET Q3 is connected to the power source V1 (21V), and the source of the N-type FET Q3 is connected to the source of the P-channel FET (Q4).

  A control signal from the DAC 651 is applied to the gate of a P-channel FET (hereinafter also referred to as P-type FET) Q4. The drain of the P-type FET Q4 is connected to the ground (GND), and the source of the P-type FET Q4 is connected to the source of the N-type FET Q3. The source of the N-type FET Q3 and the source of the P-type FET Q4 are connected to the collector of the discharge side transistor Q2 of the current amplification circuit 652 and the low voltage side terminal of the capacitor C2.

  When the voltage at point B is lower than the voltage of the control signal, the N-type FET Q3 is turned on. When the voltage at point B is higher than the voltage of the control signal, the P-type FET Q4 is turned on. Thus, the voltage adjustment unit 661 adjusts the voltage at the point B so as to be the same voltage as the control signal.

  The diode D1 is a diode for preventing backflow, the cathode side of the diode D1 is connected to the collector of the charging side transistor Q1 of the current amplification circuit 652 and the high voltage side terminal of the capacitor C2, and the anode side is connected to the power source V1 and the N-type FET Q3. Connected to the drain.

  The diode D2 is a regenerative diode and is for allowing a current to flow from the discharge-side transistor Q2 to the capacitor C3. The cathode side of the diode D1 is connected to the high voltage side terminal of the capacitor C3, and the anode side is connected to the collector of the discharge side transistor Q2.

  The capacitor C3 is for accumulating the regenerated charge. Charges discharged from the discharge-side transistor Q2 when the piezo element C1 is discharged are regenerated to the capacitor C3 via the diode D2. The capacity of the capacitor C3 is larger than the capacity of the capacitor C1 (the total capacity of all the piezoelectric elements) and the capacitor C2. The low-voltage side terminal of the capacitor C3 is connected to the ground, and the high-voltage side terminal is connected to the power source V1, the anode side of the diode D1, and the cathode side of the diode D2.

  The power source V1 is a 21V power source. That is, the power supply voltage in the second reference example is lower than the power supply voltage (42 V) in the first reference example.

Next, the operation of the drive signal generation circuit 65 of the second reference example will be described.
FIG. 7 is an explanatory diagram of the time variation of the original drive signal OCOM (drive signal COM), the control signal, and the voltage at each point in the second reference example.
First, at time T0, there is no change in the original drive signal OCOM, and both the charge side transistor Q1 and the discharge side transistor Q2 are off. The voltage at point A (the high-voltage side terminal of the capacitor C2 and the collector of the charge-side transistor Q1 of the current amplification circuit 652) is 21V by the power source V1. Further, at this time, the control signal is the GND voltage, whereby the point B voltage (the low-voltage side terminal of the capacitor C2) becomes the GND voltage. Therefore, the capacitor C2 is charged with 21V.

  At times T1 to T2 (when the piezo element C1 is charged when the original drive signal OCOM is 21 V or less), the potential of the original drive signal OCOM from the DAC 651 gradually increases. When the original drive signal becomes high, the charging side transistor Q1 of the current amplifier circuit 652 is turned on, and the piezo element C1 is charged. Since the collector voltage of the charging side transistor Q1 at this time is 21V, the voltage difference between the collector and the emitter of the charging side transistor Q1 is 21V−the voltage of the drive signal COM (the hatched portion of T1 to T2 in the figure). This is smaller than in the case of the first reference example. That is, the heat generation of the charge side transistor Q1 is smaller than that in the first reference example.

  At this time, the control signal is a GND voltage. That is, the voltage at point B in the figure is the GND voltage.

  At time T2, the original drive signal OCOM (drive signal COM) becomes 21V. At this time, the DAC 651 changes the control signal from the GND voltage to 21V. As a result, the N-type FET Q3 is turned on, and a current flows from the power source V1 (21V) to the point B. As a result, the voltage at the point B becomes 21 V from the GND voltage. Further, since the capacitor C2 is charged at 21V immediately before the time T2, the voltage on the low voltage side (point B voltage) becomes 21V from the GND voltage at the time T2, so that the voltage on the high voltage side (point A voltage) ) Becomes 42V (21V + 21V).

  At times T2 to T3 (when the piezo element C1 is charged when the original drive signal OCOM is 21 V or higher), the charge side transistor Q1 is on and the piezo element C1 is charged. Note that the voltage difference between the collector and the emitter of the charging side transistor Q1 during this period is the voltage of the 42V-driving signal COM (hatched portion of T2 to T3 in the figure) because the voltage at the point A is 42V.

  From time T3 to T4 (during hold), the original drive signal OCOM becomes constant. As a result, the charge-side transistor Q1 (and the discharge-side transistor Q2) is turned off, no current flows through the piezo element C1, and the drive signal COM maintains the same voltage.

  At times T4 to T5 (when the piezo element C1 is discharged when the original drive signal OCOM is 21 V or higher), the voltage of the original drive signal OCOM from the DAC 651 gradually decreases. As a result, the discharge-side transistor Q2 of the current amplification circuit 652 is turned on, and the piezo element C1 is discharged. The control signal remains at 21V. Further, when the discharge side transistor Q2 is turned on, the P-type FET Q4 is turned on, and the charge from the discharge side transistor Q2 is discharged to the GND. Thus, the voltage at point B is adjusted to 21 V (the same voltage as the control signal). When the discharge side transistor Q2 is turned on, a part of the electric charge from the discharge side transistor Q2 is regenerated to the capacitor C3 via the diode D2. The charge regenerated in the capacitor C3 is used when the piezo element C1 is charged next time.

  Therefore, the voltage difference between the collector and the emitter of the discharge-side transistor Q2 during this period is the voltage -21V of the drive signal COM (hatched portion of T4 to T5 in FIG. 7). This is smaller than in the case of the first reference example. That is, the heat generation of the discharge-side transistor Q2 can be made smaller than in the case of the first reference example.

At time T5 (when the original drive signal OCOM becomes 21V), the DAC 651 changes the control signal from 21V to the GND voltage.
Again, the P-type FET Q4 is turned on, and a current flows to the ground (GND). However, since the control signal becomes the GND voltage, the voltage at the point B changes from 21 V to the GND voltage. Further, when the voltage at the point B is changed from 21V to the GND voltage, the voltage at the point A is changed from 42V to 21V.

Also at times T5 to T6 (when the piezo element C1 is discharged when the original drive signal is 21 V or less), the discharge-side transistor Q2 is turned on and the piezo element C1 is discharged. Since the voltage at point B is the GND voltage, the voltage difference between the collector and the emitter of the discharge-side transistor Q2 is the voltage -GND of the drive signal COM (hatched portion from T5 to T6 in FIG. 7).
Thereafter, the same operation is repeated.

<First Embodiment>
In the second reference example, charge regeneration to the capacitor C3 is performed only when the piezo element C1 is discharged until the drive signal COM becomes 21V. This is because the capacitor C3 is charged with 21V during charge regeneration.
On the other hand, in the present embodiment, charge regeneration can be performed even when the drive signal COM is lower than 21V.

FIG. 8 is an explanatory diagram of the drive signal generation circuit 65 of the first embodiment. Compared with the second reference example, the regenerative capacitor C3 is provided in the second reference example, whereas in this embodiment, the regenerative capacitor C3 (corresponding to the first power storage capacitor) is used as the regenerative capacitor. And a capacitor C4 (corresponding to a second power storage capacitor). Further, in this embodiment, a capacitor C5 (corresponding to a third power storage capacitor) and switches SW2 to SW5 are added.
Hereinafter, a configuration different from the second reference example will be described.

  The capacitor C3 and the capacitor C4 are regenerative capacitors, and accumulate electric charges when the piezo element C1 is discharged. The capacities of the capacitors C3 and C4 are larger (for example, 40 μF) than the capacitors C1 (the total capacity of all the piezoelectric elements, for example, 1 μF) and the capacitors C2 (for example, 20 μF). The connection relationship (series connection and parallel connection) of the capacitor C3 and the capacitor C4 of this embodiment is switched by switches SW2 to SW4 described later. The lower terminal of the capacitor C3 in the drawing is connected to the ground (GND), and the upper terminal of the capacitor C4 in the drawing is connected to the charging terminal of the charge pump circuit 66 (point C).

  The capacitor C5 is for preventing the potential from becoming indefinite when all the switches (switches SW2 to SW5) described later are turned off. The capacitor C5 has a small capacity (for example, 0.01 μF). The upper terminal in the figure of the capacitor C5 is connected to the upper terminal in the figure of the capacitor C4, and the lower terminal in the figure of the capacitor C5 is connected to the ground (GND).

The switches SW <b> 2 to SW <b> 5 are controlled on / off by the controller 60.
The switch SW2 is provided between the upper terminal of the capacitor C3 in the drawing and the lower terminal of the capacitor C4 in the drawing. Note that the switch SW2 corresponds to a first switch.
The switch SW3 is provided between the lower terminal of the capacitor C4 in the drawing and the ground (GND). Note that the switch SW3 corresponds to a second switch.
The switch SW4 is provided between the upper terminal of the capacitor C4 in the drawing and the upper terminal of the capacitor C3 in the drawing. Note that the switch SW4 corresponds to a third switch.
The switch SW5 is provided between the upper terminal of the capacitor C4 in the figure and the power source V1 (21V). The switch SW5 is provided between the upper terminal of the capacitor C3 in the figure and the power source V1 via the switch SW4. Note that the switch SW5 corresponds to a fourth switch.

FIG. 9 is an explanatory diagram of the time change of the drive signal and the potential at each point. FIG. 10 is an explanatory diagram of on / off control of each switch.
Until the first time T0 to immediately before time T5, the controller 60 turns on the switches SW2 and SW5 and turns off the switches SW3 and SW4. Thereby, the capacitor C3 and the capacitor C4 are connected in series. Thus, until the time T5, the state in which the switches SW2 and SW5 are on and the switches SW3 and SW4 are off is maintained, and the same operation as in the second reference example is performed.
When charging the capacitor C2 of the charge pump circuit 66, a power supply voltage of 21V of the power source V1 is applied to the capacitor C3 and the capacitor C4 connected in series, and the capacitor C3 and the capacitor C4 are charged to 10.5V, respectively.
At time T5, the controller 60 once turns off all the switches SW2 to SW5. This is to avoid the switches SW2 and SW5 and the switches SW3 and SW4 from being turned on simultaneously.

From time T5 to time Ta, the controller 60 turns off the switches SW2 and SW5 and turns on the switches SW3 and SW4. Thereby, the capacitor C3 and the capacitor C4 are connected in parallel. Therefore, the large capacity C (C3 + C4) can be charged. The voltage on the high potential side of each of the capacitors C3 and C4 is 10.5V.
As a result, part of the charge from the discharge-side transistor Q2 moves to the capacitors C3 and C4 via the diode D2 (regeneration) until the drive signal COM becomes 10.5V (regeneration). That is, in the present embodiment, the charge from the discharge-side transistor Q2 can be regenerated not only from time T4 to time T5 but also from time T5 to Ta.

On the other hand, in the second reference example, regeneration was possible only until the drive signal COM reached 21 V (time T4 to time T5). Therefore, this embodiment can regenerate more charges.
Since the switch SW5 is off during this period, it is possible to avoid the capacitors C3 and C4 from being charged from the 21V power source.
At time Ta, the controller 60 once turns off all the switches SW2 to SW5. This is to avoid the switches SW2 and SW5 and the switches SW3 and SW4 from being turned on simultaneously.

  From time Ta to time T6, the controller 60 turns on the switch SW2 and the switch SW5 and turns off the switch SW3 and the switch SW4. Thereby, the capacitor C3 and the capacitor C4 are connected in series. The operation at this time is the same as in the second reference example described above.

<Modification of First Embodiment>
In the above-described embodiment, at time T5 to Ta, the switch SW3 and the switch SW4 are simultaneously turned on and the capacitor C3 and the capacitor C4 are connected in parallel. However, only one of the switch SW3 and the switch SW4 is turned on. The charge from the discharge-side transistor Q2 may be regenerated in either the capacitor C3 or the capacitor C4.

  The drive signal generation circuit 65 of the present embodiment described above includes a current amplification circuit 652, a charge pump capacitor C2, and a capacitor C3 and a capacitor C4 that accumulate electric charges when the piezoelectric element C1 is discharged. The current amplifier circuit 652 receives the original drive signal OCOM and outputs the drive signal COM that follows the voltage change of the original drive signal OCOM, thereby charging and discharging the piezo element C1 that is a capacitive load. The capacitor C2 has a high voltage side terminal connected to the high voltage side power supply voltage terminal (collector of the charge side transistor Q1) of the current amplification circuit 652, and a low voltage connected to the low voltage side power supply voltage terminal (the collector of the discharge side transistor Q2) of the current amplification circuit 652. Side terminals are connected. The capacitor C2 raises the voltage of the high-voltage side terminal of the capacitor C2 to a voltage higher than 21V by increasing the voltage of the low-voltage side terminal of the capacitor C2 charged with 21V when the piezo element C1 is charged. Capacitor C3 and capacitor C4 accumulate the discharge charge of discharge transistor Q2.

  In the drive signal generating circuit 65 having such a configuration, in the present embodiment, when the capacitor C2 of the charge pump circuit 66 is charged, the upper terminal in the drawing of the capacitor C3 and the lower terminal in the drawing of the capacitor C4 are electrically connected. By doing so, the capacitor C3 and the capacitor C4 are connected in series. At this time, the power supply V1 to 21V is applied to the upper terminal of the capacitor C4 in the figure, and the capacitor C3 and the capacitor C4 are each charged to 10.5V. Further, when the piezo element C1 is discharged, the upper terminal in the drawing and the lower terminal in the drawing of the capacitor C4 are electrically disconnected. Then, the charge from the discharge-side transistor Q2 is accumulated in at least one of the capacitor C3 and the capacitor C4. At this time, since the capacitor C3 and the capacitor C4 are charged to 10.5V, the charge from the discharge-side transistor Q2 can be regenerated up to 10.5V. That is, more electric charges can be regenerated than in the second reference example that can regenerate only up to 21V.

=== Drive Signal Generation Circuit of Second Embodiment ===
In the first embodiment, during the regeneration from time T4 to T5, most of the electric charge discharged from the piezo element C1 flows to the GND via the P-type FET Q4, and is regenerated to the capacitor C3 and the capacitor C4 via the diode D2. Less charge is generated.
This is because the P-type FET Q4 is turned on when the source-side voltage (point B voltage) of the P-type FET Q4 becomes higher than the gate-side voltage. For this reason, in 1st Embodiment, the efficiency of regeneration is bad.
Therefore, in the second embodiment, the P-type FET Q4 of the voltage adjustment unit 661 is controlled so that the P-type FET Q4 is less likely to be turned on when the capacitor C1 is discharged.

  FIG. 11 is an explanatory diagram of a drive signal generation circuit according to the second embodiment. Compared with the first embodiment, a voltage control circuit 67 is added in the second embodiment. Here, the voltage control circuit 67 will be mainly described, and the description common to the first embodiment will be omitted.

  The voltage control circuit 67 controls the gate voltage (point E voltage in the figure) of the P-type FET Q4 based on the control signal output from the DAC 651 and the original drive signal OCOM as described below.

  The voltage control circuit 67 includes a transistor Q5, resistors R1 to R3, and a diode D3. The collector of the transistor Q5 is connected to a transmission line through which the DAC 651 outputs a control signal via the resistor R1. The emitter of the transistor Q5 is connected to a transmission line through which the DAC 651 outputs the original drive signal OCOM via the resistor R2. The base of the transistor Q5 is connected to the 21V power source V1 via the resistor R3 and the diode D3. The voltage control circuit 67 applies the control signal output from the DAC 651 to the gate of the N-type FET Q3. The voltage control circuit 67 applies the collector voltage of the transistor Q5 (the voltage at point E in the figure) to the P-type FET Q4.

  The base voltage of the transistor Q5 of the voltage control circuit 67 is approximately 21V. Therefore, if the original drive signal OCOM is 21 V or less, the base voltage is higher than the collector voltage of the transistor Q5, and the transistor Q5 is turned off. As a result, a signal having substantially the same voltage as the control signal output from the DAC 651 is applied to the gate of the P-type FET Q4. On the other hand, if the original drive signal OCOM is 21 V or higher, the transistor Q5 is turned on. As a result, a signal obtained by dividing the control signal output from the DAC 651 and the original drive signal OCOM by the resistors R1 and R2 is applied to the gate of the P-type FET Q4. In this embodiment, at this time, the resistance values of the resistors R1 and R2 are determined so that a signal having substantially the same voltage as the original drive signal OCOM is applied.

  FIG. 12A is an explanatory diagram of a time change of the original drive signal OCOM, the control signal, and the voltage at the point E (gate voltage of the P-type FET Q4) in the second embodiment.

  First, the time change of the original drive signal OCOM will be described. At time T0, the original drive signal OCOM is the lowest voltage of about 3V. From time T1 to T3, the potential of the original drive signal OCOM gradually increases. Note that the original drive signal OCOM reaches 21V at a time T2 on the way. At time T3, the original drive signal OCOM becomes the highest voltage. From time T3 to T5, the original drive signal OCOM is a constant voltage. This time is called hold time. From time T4 to T6, the potential of the original drive signal OCOM gradually decreases. Note that the original drive signal OCOM reaches 21V at time T5 in the middle. At time T6, the original drive signal OCOM becomes the minimum voltage of about 3V. The DAC 651 outputs such an original drive signal OCOM. Note that the drive signal COM output from the drive signal generation circuit 65 has substantially the same voltage change as the original drive signal OCOM.

  Next, the time change of the control signal will be described. In the first embodiment, the control signal has a rectangular shape, whereas in the second embodiment, the control signal has a trapezoidal shape. At time T0, the control signal is the GND voltage. From time Tb after time T1 when the voltage of the original drive signal OCOM gradually increases, the voltage of the control signal gradually increases with the same slope as the voltage change of the original drive signal OCOM. From time T3 to T4, the control signal is a constant voltage. From time T4 to Tc, the voltage of the control signal gradually decreases with the same slope as the voltage change of the original drive signal OCOM. At time Tc, the control signal becomes the GND voltage. The DAC 651 outputs such a control signal.

  Further, the time change of the point E voltage (gate voltage of the P-type FET Q4) will be described. When the original drive signal OCOM is lower than 21V, the transistor Q5 of the voltage control circuit 67 is turned off as described above. As a result, the voltage at point E becomes substantially the same as the control signal. On the other hand, when the original drive signal OCOM is higher than 21V, the transistor Q5 of the voltage control circuit 67 is turned on. As a result, the point E voltage becomes substantially the same as the original drive signal OCOM. Therefore, at time T0, the voltage at point E is the GND voltage. From time Tb after the voltage of the original drive signal OCOM gradually increases, the point E voltage gradually increases together with the control signal. When the original drive signal OCOM reaches 21V at time T2, the voltage at the point E becomes substantially the same voltage (21V) as the original drive signal OCOM. At times T2 to T5, the voltage at point E is substantially the same as the original drive signal OCOM. That is, the point E voltage gradually increases at times T2 to T3, becomes a constant voltage at times T3 to T4, and gradually decreases at times T4 to T5. When the original drive signal OCOM becomes 21 V at time T5, the point E voltage becomes the same as the control signal. The point E voltage gradually decreases at times T5 to Tc and becomes the GND voltage at time Tc.

Next, the operation of the circuit based on these signals (original drive signal OCOM, control signal) will be described.
FIG. 12B is an explanatory diagram of changes over time in the original drive signal OCOM and the voltages at points A and B. FIG. 13A is an explanatory diagram of current at time T0. FIG. 13B is an explanatory diagram of current at times Tb to T2. FIG. 13C is an explanatory diagram of current at times T4 to T5. Similar to the first embodiment, from time T0 to time T5, the switch SW2 and the switch SW5 are on, and the switch SW3 and the switch SW4 are off. Thereby, the capacitor C3 and the capacitor C4 are connected in series. In FIGS. 13A to 13C, the switches SW2 to SW5 and the capacitor C5 are not shown for the sake of simplicity.

  At time T0, the voltage at point A (the high-voltage side terminal of the capacitor C2 and the collector of the charge-side transistor Q1 of the current amplification circuit 652) becomes 21V by the power source V1. At this time, the control signal is the GND voltage, and the point E voltage is also the GND voltage. Thereby, the point B voltage (the low voltage side terminal of the capacitor C2) becomes the GND voltage. Therefore, the capacitor C2 is charged with 21V (see FIG. 13A).

  At times T1 to Tb (when the original drive signal OCOM is 21 V or less and the piezo element C1 is charged with the control signal being the GND voltage), the potential of the original drive signal OCOM from the DAC 651 gradually increases. When the original drive signal OCOM becomes high, the charging side transistor Q1 of the current amplification circuit 652 is turned on, and the piezo element C1 is charged. Since the collector voltage of the charging side transistor Q1 at this time is 21V, the voltage difference between the collector and the emitter of the charging side transistor Q1 is 21V−the voltage of the drive signal COM. This is smaller than in the case of the first reference example. That is, the heat generation of the charge side transistor Q1 is smaller than that in the first reference example.

  At this time, the control signal and the point E voltage are GND voltages. That is, the voltage at point B in the figure is the GND voltage.

  At times Tb to T2 (when the piezo element C1 is charged when the original drive signal OCOM is 21 V or less and the control signal is equal to or higher than the GND voltage), the voltage of the control signal gradually increases, so that the N-type FET Q3 of the voltage adjustment unit 661 Is turned on. When the N-type FET Q3 is turned on, a current flows from the 21V power source V1 to the point B, and the voltage at the point B becomes the same voltage as the control signal. Further, since the capacitor C2 is charged with 21V, the voltage at the point A becomes the control signal + 21V (see FIG. 13B). Further, when the original drive signal OCOM becomes high, the charging side transistor Q1 of the current amplifier circuit 652 is turned on, and the piezo element C1 is charged. Since the collector voltage of the charging side transistor Q1 at this time is “control signal + 21V”, the voltage difference between the collector and the emitter of the charging side transistor Q1 becomes “control signal + 21V−voltage of the driving signal COM”. This is smaller than in the second reference example. That is, the heat generation of the charge side transistor Q1 is smaller than that of the second reference example.

  At times T2 to T3 (when the piezo element C1 is charged when the original drive signal OCOM is 21 V or higher), the transistor Q5 of the voltage control circuit 67 is turned on, and the point E voltage is substantially the same as the original drive signal OCOM. Other than this, it is the same as that at the time Tb to T2. That is, the N-type FET Q3 of the voltage adjustment unit 661 is turned on by gradually increasing the voltage of the control signal. As a result, current flows from the 21V power source V1 to the point B, the point B voltage becomes the same voltage as the control signal, and the capacitor C2 is charged with 21V, so the point A voltage becomes the control signal + 21V (see FIG. 13B). ). Further, when the original drive signal OCOM becomes high, the charging side transistor Q1 of the current amplifier circuit 652 is turned on, and the piezo element C1 is charged. Since the collector voltage of the charging side transistor Q1 at this time is “control signal + 21V”, the voltage difference between the collector and the emitter of the charging side transistor Q1 becomes “control signal + 21V−voltage of the driving signal COM”. This is smaller than in the second reference example. That is, the heat generation of the charge side transistor Q1 is smaller than that of the second reference example.

  From time T3 to T4 (during hold), the original drive signal OCOM becomes constant. As a result, the charge-side transistor Q1 (and the discharge-side transistor Q2) is turned off, no current flows through the piezo element C1, and the drive signal COM maintains the same voltage.

  At times T4 to T5 (when the piezo element C1 is discharged when the original drive signal OCOM is 21 V or higher), the voltage of the original drive signal OCOM from the DAC 651 gradually decreases. As a result, the discharge-side transistor Q2 of the current amplification circuit 652 is turned on, and the piezo element C1 is discharged. At this time, the point B voltage rises to 21V and the point A voltage becomes 42V.

At this time, in this embodiment, the point E voltage is 21 V or more (see FIG. 12A). For this reason, in this embodiment, even if the discharge side transistor Q2 is turned on and the voltage at the point B rises, the P-type FET Q4 is not turned on. As a result, the charge released from the discharge-side transistor Q2 is not released to the GND via the P-type FET Q4, but is regenerated to the capacitor C3 and the capacitor C4 connected in series via the diode D2 (see FIG. 13C). For this reason, in this embodiment, the electric charge regenerated is larger than in the case of the second reference example.
Since the voltage at point B is 21V, the capacitors C3 and C4 connected in series are each charged to 10.5V.

At time T5, the controller 60 once turns off all the switches SW2 to SW5. This is to avoid the switches SW2 and SW5 and the switches SW3 and SW4 from being turned on simultaneously. Further, when the original drive signal OCOM becomes approximately 21 V at time T5, the transistor Q5 of the voltage control circuit 67 is turned off, and the point E voltage becomes substantially the same as the control voltage.
From time T5 to time Tc, the control signal gradually decreases and the P-type FET Q4 is turned on. For this reason, the electric charge discharged from the discharge side transistor Q2 is discharged to the ground (GND) through the P-type FET Q4.
From time Tc to Ta, the control voltage is almost the GND voltage.

  At time T5 to time Ta, the controller 60 turns off the switch SW2 and the switch SW5 and turns on the switch SW3 and the switch SW4. Thereby, the capacitor C3 and the capacitor C4 are connected in parallel. Therefore, a large capacity C (C3 + C4) can be charged. The voltage on the high potential side of the capacitors C3 and C4 is 10.5V.

Thereby, until the drive signal COM becomes 10.5 V (until time Ta), a part of the electric charge from the discharge side transistor Q2 moves to the capacitors C3 and C4 via the diode D2 (regeneration).
On the other hand, in the second reference example, regeneration was possible only until the drive signal COM became 21V. Therefore, this embodiment can perform regeneration more efficiently.
Since the switch SW5 is off during this period, it is possible to avoid the capacitors C3 and C4 from being charged from the 21V power source.

  At time Ta, the controller 60 once turns off all the switches SW2 to SW5. This is to avoid the switches SW2 and SW5 and the switches SW3 and SW4 from being turned on simultaneously.

  From time Ta to time T6, the controller 60 turns on the switch SW2 and the switch SW5 and turns off the switch SW3 and the switch SW4. Thereby, the capacitor C3 and the capacitor C4 are connected in series. The operation at this time is the same as that in the above-described embodiment.

  As described above, in the second embodiment, at the time T4 to T5 when the voltage of the original drive signal OCOM from the DAC 651 gradually decreases (when the piezo element C1 is discharged when the original drive signal OCOM is 21 V or more), the P-type FET Q4. Does not turn on.

  In the first embodiment (and the second reference example), the P-type FET Q4 is turned on from time T4 to T5 when the voltage of the original drive signal OCOM from the DAC 651 gradually decreases, and a large amount of charge is discharged from the discharge-side transistor Q2. A portion was discharged to GND through the P-type FET Q4. On the other hand, in the second embodiment, since the P-type FET Q4 does not turn on from time T4 to T5, the charge discharged from the discharge-side transistor Q2 is regenerated to the capacitor C3 and the capacitor C4 via the diode D2. . Therefore, charge regeneration can be performed more efficiently than in the first embodiment.

In the second embodiment, the DAC 651 generates the original drive signal OCOM and the control signal. However, the present invention is not limited to this, and the DAC 651 may generate only the original drive signal OCOM. A circuit that drops the original drive signal OCOM output from the DAC 651 by a predetermined voltage (for example, 14 V) may be provided, and a signal generated by this circuit may be applied to the gate of the N-type FET Q3. In this case, a signal generated by the voltage control circuit 67 of the second embodiment may be applied to the P-type FET Q4 based on the signal generated by this circuit and the original drive signal OCOM.
Further, the DAC 651 may separately generate a signal to be applied to the P-type FET Q4. In this case, the voltage control circuit 67 is not necessary.

=== Drive Signal Generation Circuit of Third Embodiment ===
In the above-described embodiment, the capacitor C3 and the capacitor C4 are connected in parallel only between the time T5 and the time Ta. In the third embodiment, the time for connecting the capacitor C3 and the capacitor C4 in parallel is increased.

FIG. 14 is an explanatory diagram of a drive signal generation circuit according to the third embodiment.
Compared with the second embodiment (FIG. 11), the position of the switch SW5 is different. A diode D4 is provided between the point A and the collector of the charging side transistor Q1.
In the third embodiment, the switch SW5 is provided between the power supply V1 and the cathode side of the diode D3.
The diode D4 is a diode for preventing backflow, the anode side is connected to the high voltage side terminal (point A) of the capacitor C2, and the cathode side is connected to the collector of the charging side transistor Q1.

  In the second embodiment, the base voltage of the transistor Q5 of the voltage control circuit 67 is 21V. In the third embodiment, the base voltage of the transistor Q5 is 21V when the switch SW5 is on, and the switch SW5 is When it is off, it becomes the voltage at point C (the voltage at the high-voltage side terminal of the capacitor C4). Note that if the base voltage is higher than the collector voltage of the transistor Q5, the transistor Q5 is turned off. As a result, a signal having substantially the same voltage as the control signal is applied to the gate of the P-type FET Q4. On the other hand, if the base voltage is lower than the collector voltage of the transistor Q5, the transistor Q5 is turned on. As a result, a signal having substantially the same voltage as the original drive signal OCOM is applied to the gate of the P-type FET Q4.

FIG. 15A is an explanatory diagram of changes over time of the original drive signal OCOM, the control signal, and the voltage at point E (the gate voltage of the P-type FET Q4) in the third embodiment. FIG. 15B is an explanatory diagram of changes over time in the original drive signal OCOM and the voltages at points A and B. In the third embodiment, the switches SW2 and SW5 are turned off and the switches SW3 and SW4 are turned on between time T3 and time T4 (for example, immediately before time T4). That is, the capacitor C3 and the capacitor C4 are connected in parallel. Further, when the switch SW5 is turned off, the base voltage of the transistor Q5 becomes the voltage at the point C (10.5 V).
In FIG. 15A, the change over time of the original drive signal OCOM and the control signal is the same as that in the second embodiment, and a description thereof will be omitted.

The point E voltage (gate voltage of the P-type FET Q4) changes in the same manner as in the second embodiment until time T5. However, in the third embodiment, the voltage at point E changes along the original drive signal OCOM from time T5 to time Ta, and becomes the same as the control signal at time Ta when the original drive signal OCOM becomes 10.5V. That is, until the time Ta, the point E voltage is 10.5 V or more.
In FIG. 15B, the time T0 to the time T4 are the same as those in the second embodiment.

In the third embodiment, immediately before time T4, the point B voltage becomes 10.5V, and 10.5V is maintained until time Ta. At this time, in this embodiment, the point E voltage is 10.5 V or more (see FIG. 15A). For this reason, the P-type FET Q4 is not turned on. As a result, the electric charge discharged from the discharge side transistor Q2 is not discharged to the GND via the P-type FET Q4, but is regenerated to the capacitor C3 and the capacitor C4 connected in parallel via the diode D2. At time Ta, the point E voltage becomes lower than 10.5 V (to the GND voltage), whereby the P-type FET Q4 is turned on, and the point B voltage becomes the GND voltage. In addition, A point voltage is B point voltage + 21V. In this case, there is a point where the base voltage (OCOM) of the charge side transistor Q1 becomes higher than the collector voltage (the voltage at the point A), but the reverse current is prevented by the diode D4.
After time ta, it is the same as in the second embodiment.

  As described above, in the third embodiment, during the period from time T4 to time Ta, the capacitor C3 and the capacitor C4 are connected in parallel to regenerate the charge discharged from the discharge-side transistor Q2. Further, since the P-type FET Q4 is not turned on during this period (time T4 to time Ta), regeneration can be performed efficiently.

  In the third embodiment, a sufficient margin can be taken for the switch switching timing. In the above-described embodiment, the switch is switched (the capacitor C3 and the capacitor C4 are switched from serial to parallel) at the time T5. For this reason, if a slight timing shift occurs, the waveform of the drive signal COM may be affected. On the other hand, in the third embodiment, since the switch is switched during the period from time T3 to time T4 (during hold), noise due to switch switching is not affected (the waveform of the drive signal COM is not affected). However, in the third embodiment, since the potential difference between the drive signal COM and the capacitor at the time of regeneration of the charge of the discharge-side transistor Q2 is large, heat is likely to be generated in the path therebetween.

=== Other Embodiments ===
Although a printer or the like as one embodiment has been described, the above embodiment is for facilitating the understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof. In particular, the embodiments described below are also included in the present invention.

<About the printer>
The printer of the above-described embodiment is a printer (so-called serial printer) that alternately repeats a dot forming operation (pass) in which the head moves in the movement direction and a conveyance operation in which the paper is conveyed in the conveyance direction. However, the type of printer is not limited to this. For example, a printer (so-called line printer) that performs printing by fixing the head and discharging the ink from the head while conveying the paper while facing the head may be used.

<About liquid ejecting device>
In the above-described embodiment, an ink jet printer is described as an example of the liquid ejecting apparatus. However, the liquid ejecting apparatus is not limited to the ink jet printer, and liquids other than ink (including liquids in which functional material particles are dispersed and liquids such as gels other than liquids) and liquids are also used. The present invention is also applicable to a fluid ejecting apparatus that ejects a fluid (a solid that can be ejected as a fluid, such as powder). For example, an injection device for injecting a liquid colorant or an electrode material used for manufacturing a liquid crystal display, an EL display and a surface emitting display, or an injection device for injecting a liquid bioorganic material used for biochip manufacturing The embodiment may be applied.

<About ink>
Since the above-described embodiment is an embodiment of the printer, the ink is ejected from the nozzle. However, the ink may be water-based or oil-based. Further, the fluid ejected from the nozzle is not limited to ink. For example, liquids (including water) including metal materials, organic materials (especially polymer materials), magnetic materials, conductive materials, wiring materials, film forming materials, electronic ink, processing liquids, gene solutions, etc. are ejected from nozzles. May be.

<About piezo elements>
In the above-described embodiment, ink is ejected using a piezo element. However, as long as the element to be driven has a function of a capacitive load, the piezoelectric element is not limited to the piezoelectric element, and another piezoelectric element may be used.

<About DAC>
In the above-described embodiment, the original drive signal OCOM and the control signal are generated using a DAC (D / A converter), but the present invention is not limited to this. The original drive signal OCOM and the control signal may be directly output as an analog signal without converting the digital data into an analog signal.

1 printer,
20 transport unit, 21 paper feed roller, 22 transport motor (PF motor),
23 transport roller, 24 platen, 25 discharge roller,
30 Carriage unit, 31 Carriage,
32 Carriage motor (CR motor),
40 head units, 41 heads, 42 data receivers, 43 drive signal generators,
50 sensor groups, 51 linear encoder, 52 rotary encoder,
53 Paper detection sensor, 54 Optical sensor,
60 controller, 61 interface, 62 CPU,
63 memory, 64 unit control circuit,
65 drive signal generation unit, 651 DAC, 652 current amplification circuit,
66 charge pump circuit, 661 voltage adjustment unit, 67 voltage control circuit,
Q1 charging transistor, Q2 discharging transistor,
Q3 N-type FET, Q4 P-type FET, Q5 transistor,
C1 piezo elements, C2 to C5 capacitors,
SW1-SW5 switch, V1 21V power supply

Claims (6)

A current amplification circuit that receives an original drive signal and charges and discharges a capacitive load in accordance with a voltage change of the original drive signal;
A charge pump capacitor having one end connected to the high-voltage side power supply voltage terminal of the current amplification circuit and the other end connected to the low-voltage side power supply voltage terminal of the current amplification circuit, wherein the predetermined capacitance is charged when the capacitive load is charged. A charge pump capacitor for increasing the voltage at the other end of the charge pump capacitor charged with a voltage to a voltage higher than the predetermined voltage at the high-voltage power supply voltage terminal of the current amplifier circuit When,
A first power storage capacitor and a second power storage capacitor for accumulating charge during discharging of the capacitive load;
A drive signal generation circuit comprising:
When charging the charge pump capacitor at the predetermined voltage, the first power storage capacitor and the second power storage capacitor are electrically connected to one end of the first power storage capacitor and the second power storage capacitor. Two storage capacitors are connected in series, and the predetermined voltage is applied to the first storage capacitor and the second storage capacitor connected in series;
At the time of discharging the capacitive load, the one end of the first power storage capacitor and the one end of the second power storage capacitor are electrically disconnected from the first power storage capacitor and the second power storage capacitor. And a charge signal from the low-voltage power supply voltage terminal of the current amplification circuit is accumulated in at least one of the drive signal generation circuits. The drive signal generation circuit according to claim 1,
A first switch provided between the one end of the first power storage capacitor and the one end of the second power storage capacitor;
A second switch provided between the one end of the first power storage capacitor and ground;
A third switch provided between the one end of the second power storage capacitor and the other end of the first power storage capacitor;
When the first power storage capacitor and the second power storage capacitor are connected in series, the first switch is turned on, the second switch and the third switch are turned off,
When the first power storage capacitor and the second power storage capacitor are connected in parallel, the first switch is turned off, and the second switch and the third switch are turned on.
A drive signal generation circuit characterized by the above. The drive signal generation circuit according to claim 2,
A power supply of the predetermined voltage;
A fourth switch provided between the power source and the other end of the first power storage capacitor;
Turning off the first switch and turning off the fourth switch when turning on the second switch and the third switch;
A drive signal generation circuit characterized by the above. The drive signal generation circuit according to claim 3,
A first state in which the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off; the first switch and the fourth switch are turned off; the second switch and the All switches are turned off during the second state in which the third switch is turned on.
A drive signal generation circuit characterized by the above. The drive signal generation circuit according to claim 4,
A third power storage capacitor having one end connected to the other end of the first power storage capacitor and the other end grounded;
A drive signal generation circuit characterized by the above. A piezoelectric element that is displaced in response to a voltage change in order to eject fluid from the nozzle;
A current amplification circuit that inputs an original drive signal and charges and discharges the piezoelectric element in accordance with a voltage change of the original drive signal;
A charge pump capacitor having one end connected to the high-voltage side power supply voltage terminal of the current amplification circuit and the other end connected to the low-voltage side power supply voltage terminal of the current amplification circuit, wherein the predetermined voltage is charged when the piezoelectric element is charged. A charge pump capacitor for causing the voltage of the high-voltage power supply voltage terminal of the current amplifier circuit to be higher than the predetermined voltage by increasing the voltage on the other end side of the charge pump capacitor charged in ,
A first power storage capacitor and a second power storage capacitor for accumulating charges during discharge of the piezoelectric element;
A drive signal generation circuit comprising:
When charging the charge pump capacitor at the predetermined voltage, the first power storage capacitor and the second power storage capacitor are electrically connected to one end of the first power storage capacitor and the second power storage capacitor. Two power storage capacitors are connected in series, and the first power storage capacitor and the second power storage capacitor are charged with the predetermined voltage;
During the discharging of the piezoelectric element, the one end of the first power storage capacitor and the one end of the second power storage capacitor are electrically disconnected, and one of the first power storage capacitor and the second power storage capacitor At least one of the electric charges from the low-voltage power supply voltage terminal of the current amplifier circuit is accumulated,
A fluid ejecting apparatus.

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