JP2010252332A - Self-timed delay element based on ring oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a two-terminal self-timed delay element without needing any external reset input by generating a self-timed reset signal while using a ring oscillator internally and using a flip-flop for delaying an input signal with a clock signal of the ring oscillator as a reference, with respect to a self-timed delay element based on the ring oscillator. <P>SOLUTION: The self-timed delay element includes: a ring oscillator that generates an internal clock signal; and a signal delay circuit section in which the clock signal generated by the ring oscillator is applied to a counter and an external input signal is delayed by a determined clock cycle. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a self-timing delay element based on a ring oscillator. More specifically, a self-timed ring oscillator is used internally, a flip-flop that delays the input signal with reference to the clock signal of the ring oscillator, a self-timed reset signal is generated, and an external reset input is It relates to a two-terminal delay element which is not necessary.

  Conventional two-terminal delay elements are disadvantageous in that it is difficult to design and implement a circuit because it is an analog circuit inside even if it is a delay element used in a digital circuit. . In general digital circuits, in order to overcome this problem, a circuit realization method that uses a plurality of inverters or delays an input signal by a fixed clock time using a clock and a counter is used.

  However, when using a plurality of inverters, a large number of delay elements must be used in order to ensure a sufficient delay time and ensure a minimum pulse width. In addition, in the case of a circuit using a clock and a counter, it must be composed of at least three input / output terminals such as an external clock and a reset input, so that it is difficult to realize in the form of a simple two-terminal delay element like an inverter. There is a problem.

  Examples of conventional techniques include Patent Document 1 and Non-Patent Document 1. In the case of Patent Document 1, an input signal is directly applied to two flip-flop clocks, respectively, and a rising edge and a falling edge are generated respectively. Delay. Thereafter, the delayed two rising and falling edges are transmitted to the final latch set or reset signal input to output a delayed signal.

  In Patent Document 1, two delay paths are configured by using two flip-flops at the first input end for time delay, and a signal that has passed through these two delay paths at the final end is converted into one output signal. It has a configuration to convert. Patent Document 1 is a three-terminal delay element that requires input of a reset signal to the entire circuit in addition to an input and an output signal, and includes two paths including an existing delay element therein. The use of the circuit complicates the circuit configuration, and there is a disadvantage that many delay elements must be used in order to secure a sufficient delay time.

  The configuration of Non-Patent Document 1 uses a self-timing oscillator that uses a single NAND circuit to generate an internal clock, and delays the input signal for a fixed time using a counter that counts a predetermined number of clock signals. It is a circuit to make.

  Since the self-timing oscillator using the NAND circuit used in the delay circuit according to Non-Patent Document 1 has a very high oscillation speed, one additional latch and a plurality of additional logic circuits are used to drive the flip-flop. Since the additional oscillation circuit (LSO: Latched synchronized oscillator) used is configured and used, the configuration is complicated.

  As in the case of Patent Document 1, the delay circuit according to Non-Patent Document 1 is a three-terminal delay element that requires an input of a reset signal, and is used for a reset signal in addition to two terminals of input and output. Since an additional terminal is required, there is a disadvantage that it cannot be used for a two-terminal input simple delay element circuit that is generally used.

  All the delay circuits according to Non-Patent Document 1 and Patent Document 1 described above require an external reset terminal, and at least one external reset signal must be applied in order to perform a normal operation. However, a general two-terminal delay element should not have such an additional external procedure.

US Pat. No. 6,255,878

Yosaf Zafar, M.M.Ahmed, ‘‘ A novel FPGA compliant micropipeline ’’, IEEE Trans. On Circuits & Systems II, Vol.52, No.9, Sep.2005, pp.611-615

  The present invention has been proposed in order to solve the above-described problems, and in the existing delay element, the circuit size is increased by using a plurality of inverters used for securing a sufficient delay time. By generating an internal clock signal using a ring oscillator based on self-timing, applying the generated internal clock signal to the internal counter, and delaying the input signal by a predetermined clock period Used for general circuits because a small number of circuit elements are used to secure a sufficient delay time, and a signal based on internal self-timing is generated so that an external clock signal and external reset signal are not required. An object of the present invention is to provide a delay element capable of operating like a two-terminal simple delay element.

  The self-timing delay element according to the present invention applies a ring oscillator that generates an internal clock signal and a clock signal generated by the ring oscillator to a counter, and delays an external input signal by a predetermined clock period. A signal delay circuit unit to be provided. In particular, the ring oscillator includes one oscillation combinational logic element and one latch.

  The oscillation combinational logic element may include one or more logic elements selected from an AND logic element, an OR logic element, an XOR logic element, a NAND logic element, a NOR logic element, and an XNOR logic element.

  The signal delay circuit unit controls the start and stop of the ring oscillator and the start and stop of the counter based on a counter that counts the output clock of the self-timing ring oscillator and an external input signal and an external output signal. A self-timed combinational logic element is provided.

  The self-timing generation combinational logic element detects the states of the external input signal and the external output signal and generates an internal reset signal for controlling the start and stop of the ring oscillator and the start and stop of the counter. It is characterized by that.

  The self-timing generation combinational logic element detects the activation state of the external input signal and the deactivation state of the external output signal, deactivates the internal reset signal, and activates the external input signal. The internal reset signal is activated by detecting the state and the activation state of the external output signal.

  The counter may count an output clock of the ring oscillator with reference to a state of the external input signal.

  The counter may count the output clock of the ring oscillator when the state of the external input signal is activated.

  The counter activates the external output signal when the count value of the output clock satisfies a preset count value.

  The counter may not count the clock of the ring oscillator any more by the self-timing generation combinational logic element when the external output signal is activated.

  The counter may inactivate the external output signal and initialize an internal counter value when the state of the external input signal is inactivated.

  The self-timing delay element uses only one input signal and one output signal.

  According to the present invention, the following effects can be expected. Like a general two-terminal delay element, it can be used like an existing two-terminal delay element using only two terminals, one input terminal and one output terminal, and a small number of circuit elements. A delay element capable of securing a desired delay time at the same time is realized.

  Moreover, not only is it necessary to input an external clock signal and external reset signal, but it also ensures stable operation by using a self-timing generation combinational logic element that guarantees safe operation of the internal ring oscillator and counter. There are advantages that can be guaranteed.

It is a figure for demonstrating one Embodiment of the delay element which concerns on this invention. It is a figure which shows the signal timing of the delay element which concerns on this invention. It is a figure for demonstrating other embodiment of the delay element based on this invention.

  The present invention will be described in detail with reference to the accompanying drawings. Here, repeated descriptions, well-known functions that may unnecessarily obscure the subject matter of the present invention, and detailed descriptions of configurations will be omitted. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for a clearer description.

  First, the present invention applies a ring oscillator that generates an internal clock signal based on self-timing inside, and a clock signal generated by the ring oscillator to an internal counter, and inputs an input signal for a predetermined clock period. Includes a signal delay circuit portion for delaying the delay time. The present invention does not require the input of an external clock signal and an external reset signal by generating a self-timed internal reset signal. Therefore, an operation like a two-terminal simple delay element used in a general circuit is enabled without using an additional reset input terminal.

  More specifically, the self-timing delay element based on the ring oscillator to be realized by the present invention includes a ring oscillator circuit composed of one combinational logic element and one latch, and an output clock of the ring oscillator circuit. A counter circuit that counts a signal a predetermined number of times and a self-timed combinational logic element that controls the start and stop of the internal ring oscillator and the start and stop of the counter based on the input signal and the output signal are provided It is characterized by that.

  FIG. 1 is a diagram for explaining an embodiment of a self-timing delay element based on a ring oscillator according to the present invention. Referring to FIG. 1, a delay element 100 according to the present invention includes a ring oscillator 120 that internally generates a clock signal, and a clock signal generated by the ring oscillator 120 applied to a counter, and is externally provided for a predetermined clock period. A signal delay circuit unit for delaying the input signal is provided. Here, the “signal delay circuit unit” refers to a circuit configuration excluding the ring oscillator 120 in FIG. The ring oscillator 120 includes an oscillation combinational logic element 122 for oscillation of a clock signal and one latch 124 inside.

  The ring oscillator 120 of FIG. 1 is an embodiment in which an oscillation combinational logic element 122 for oscillating a clock signal is configured inside using an XOR combinational logic element.

  The signal delay circuit unit receives an input signal (A) 112 and an output signal (Z) 114 as input, and a reset signal (for controlling start and stop of the internal ring oscillator 120 and start and stop of the counter 130). The self-timing generation combinational logic element 110 that generates (rst) 126 and the counter 130 circuit that receives the clock output signal (ck) 128 of the ring oscillator 120 as inputs.

  In the embodiment of the self-timing delay element 100 based on the ring oscillator according to the present invention of FIG. 1, the counter 130 counts the internal clock signal (ck) 128 once and transmits the external input signal (A) 112. It is an example designed to receive and output this.

  In the embodiment of FIG. 1, the external input signal (A) 112 and the output signal (Z) 114 are signals activated by a logic “0”. The input signal (A) 112 deactivated in the initial state has a logic “1” value, and the self-timing generation combinational logic element 110 sets the reset signal (rst) 126 to a logic “0” value accordingly. Output.

  A logic “0” reset signal (rst) 126 applied to the ring oscillator 120 fixes the output of the internal latch 124 of the ring oscillator 120 to a logic “1” value. Therefore, the ring oscillator 120 does not oscillate. Further, the input signal (A) 112 is applied to the set input of the counter 130 so that the output signal (Z) 114 of the counter 130 is output as a logic “1” in an inactive state.

  In this initial state, when the input signal A112 is activated and changes to the logic “0” state, the self-timing generation combinational logic element 110 inputs the logic “1” of the initial output signal (Z) 114 accordingly. A logic “1” value is output to the reset signal (rst) 126 by the logic “0” of the signal A 112.

  The logic “1” value of the reset signal (rst) 126 deactivates the set input of the internal latch 124 of the ring oscillator 120. At this time, the oscillation combinational logic element 122 for oscillation of the internal clock signal of the ring oscillator 120 transitions from the logic “1” state to the logic “0” state, and the transitioned state value passes through the latch 124 again. The oscillation of the clock output signal (ck) 128 is started through a process applied to the oscillation combinational logic element 122.

  The counter 130 circuit starts counting with the internal clock output signal (ck) 128 and, in the embodiment of FIG. 1, transmits the input signal (A) 112 to the output signal (Z) 114 using the flip-flop 132, The state of the output signal (Z) 114 is changed to a logic “0” value. The changed output signal (Z) 114 is applied again to the self-timing generation combinational logic element 110, and a logic “0” value is output to the reset signal (rst) 126 according to the logic “0” value of the output signal (Z) 114. Thus, the oscillation of the ring oscillator 120 is interrupted. Therefore, the input signal (A) 112 is delayed and transmitted to the output signal (Z) 114, and the state is maintained until the input signal (A) 112 returns to the logic “1” value which is in the inactive state.

  FIG. 1 shows an embodiment according to the present invention, and the types of logic elements (AND, OR) used for the self-timing combinational logic element 110 and the oscillation combinational logic element 122 for oscillation of the internal clock signal of the ring oscillator 120. , XOR, NAND, NOR, XNOR, etc.), and there is no restriction on the counter 130 circuit implementation method, the count value, and the like.

  FIG. 2 is a timing diagram showing waveforms of the input signal (A) 112, the output signal (Z) 114, the internal clock signal (ck) 128, and the reset signal (rst) 126 according to the above-described process.

  FIG. 3 is a view for explaining a delay element according to another embodiment of the present invention. More specifically, FIG. 3 shows that the input signal (A) 112 and the output signal (Z) 114 used in the self-timing delay element 100 based on the ring oscillator according to the present invention of FIG. This is an embodiment using a signal.

  The delay element 300 according to the embodiment of FIG. 3 is different from the delay element of FIG. 1 in that a reset signal is used for the combinational logic value of the self-timing generation combinational logic element 114 and the flip-flop 134 used in the counter 130. is there.

  The present invention is a two-terminal delay element in which the number of input / output signals of the delay element is two, and includes an oscillation combinational logic element 122 for oscillating a clock signal and one latch 124 inside the delay element. A ring oscillator 120, a counter 130 circuit for counting clocks, and a self-timing generation combinational logic element 110 for controlling the start and stop of the internal ring oscillator 120 and the start and stop of the counter 130 are provided. . Further, the function and type of the combinational logic element for the configuration method and configuration of the ring oscillator 120, the counter 130, and the self-timing generation combinational logic element 110 according to the present invention are not limited.

  On the other hand, the conventional two-terminal delay element has a disadvantage that a large number of delay elements must be used in order to obtain a sufficient delay time in the case of an analog circuit or a digital circuit. is there. In order to overcome this, when a delay circuit using a counter circuit using a clock is configured, an additional input signal such as a reset input is required, which causes a problem that the implementation of the circuit becomes complicated. In addition, if the reset signal is improperly applied in a state where the clock is applied, an incorrect clock count or timing standard is violated.

  However, the present invention internally generates an internal clock signal using a ring oscillator based on self-timing, applies the generated clock signal to an internal counter, and delays the input signal by a predetermined clock period. Not only is the input of an external clock signal and an external reset signal unnecessary, but it enables operation like a two-terminal simple delay element used in a general circuit. In addition, it is possible to realize a delay element that uses a small number of circuit elements and at the same time secures a sufficient delay time.

  In addition, there is an advantage that a stable operation can always be ensured by using a self-timing generation combinational logic element that ensures a safe operation of a ring oscillator and a counter used therein.

  Some steps of the present invention can be realized as a computer-readable code on a computer-readable recording medium. Computer-readable recording media include all types of recording devices that store data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, CD-RW, magnetic tape, floppy disk, HDD, optical disk, magneto-optical storage device, etc., and carrier wave (for example, the Internet). Including transmission). A computer-readable recording medium can be distributed in a computer system connected to a network, and stored and executed as a computer-readable code in a distributed manner.

  As described above, the optimum embodiment is disclosed in the drawings and specification. Although specific terms are used herein, they are used merely for the purpose of describing the present invention and limit the scope of the invention as defined in the meaning limitations and claims. It was not used for that purpose. Accordingly, those having ordinary skill in the art should understand that various modifications and other equivalent embodiments are possible. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

110, 114 Self-timing generation combinational logic element 112 Input signal 114 Output signal 120 Ring oscillator 122 Oscillation combinational logic element 124 Latch 126 Reset signal 128 Clock signal 130 Counter 132, 134 Flip-flop

Claims (12)

A ring oscillator that generates an internal clock signal, and a circuit unit that applies a clock signal generated by the ring oscillator to a counter and delays an external input signal by a predetermined clock period. Self-timing delay element.   The self-timing delay element according to claim 1, wherein the ring oscillator includes one oscillation combinational logic element and one latch.   The oscillation combination logic element comprises one or more logic elements selected from an AND logic element, an OR logic element, an XOR logic element, a NAND logic element, a NOR logic element, and an XNOR logic element. 3. The self-timing delay element according to 2. The circuit section is
A counter that counts the output clock of the ring oscillator, and a self-timed combinational logic element that controls start and stop of the ring oscillator and start and stop of the counter based on an external input signal and an external output signal The self-timing delay element according to claim 1, comprising:   The self-timing generation combinational logic element detects the states of the external input signal and the external output signal, and generates an internal reset signal for controlling the start and stop of the ring oscillator and the start and stop of the counter. The self-timing delay element according to claim 4, wherein The self-timing generation combinational logic element is:
Detecting the activation state of the external input signal and the deactivation state of the external output signal to deactivate the internal reset signal;
6. The self-timing delay element according to claim 5, wherein the internal reset signal is activated by detecting an activation state of the external input signal and an activation state of the external output signal.   The self-timing delay element according to claim 4, wherein the counter counts an output clock of the ring oscillator with reference to a state of the external input signal.   5. The self-timing delay element according to claim 4, wherein the counter counts an output clock of the ring oscillator when the state of the external input signal is activated.   The self-timing delay element according to claim 8, wherein the counter activates the external output signal when a count value of the output clock satisfies a preset count value.   The self-timing delay element according to claim 9, wherein the counter does not count the clock of the ring oscillator any more by the self-timing generation combinational logic element when the external output signal is activated. .   5. The self-timing delay element according to claim 4, wherein when the state of the external input signal is deactivated, the counter deactivates the external output signal and initializes an internal counter value. .   The self-timing delay element according to claim 1, wherein the self-timing delay element uses only one input signal and one output signal.

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