JP2010251640A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with high reliability, and to provide the semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming a first plug electrode in a first opening penetrating a first insulator layer provided on a semiconductor substrate; forming a first wiring layer to come in contact with the first plug electrode; forming an etching stop layer and a second insulator layer on the first insulator layer and first wiring layer in this order; exposing the first wiring layer by removing the etching stop layer and second insulator layer on the first wiring layer by using dry etching, and forming a sidewall including the etching stop layer and second insulator layer provided on a side face of the first wiring layer and part of the first insulator layer; forming a third insulator layer; forming a second opening penetrating the third insulator layer; and forming a second plug electrode to come in contact with the first wiring layer in the second opening. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having multilayer wiring and a semiconductor device.

  With the miniaturization of semiconductor processes, the gate length of MOS transistors formed in semiconductor devices, the line width of aluminum wiring connected to the source and drain of MOS transistors, and the lines of multilayer wiring stacked in the upper direction of the semiconductor substrate The width is also smaller. For this reason, various problems occur due to slight deviations in the formation position of the wiring.

  FIG. 5 is a schematic cross-sectional view showing a configuration of a semiconductor device having a conventional multilayer wiring. In this semiconductor device 115, an ILD (inter layer dielectric) layer 102 and an IMD (inter metal dielectric) layer 103 are stacked on a semiconductor substrate 101, and a first aluminum wiring 110 is provided between the ILD layer 102 and the IMD layer 103. A second aluminum wiring 111 is provided on the IMD layer 103. Also, a first plug electrode 106 that electrically connects the semiconductor substrate 101 and the first aluminum wiring 110 and a second plug electrode 107 that electrically connects the first aluminum wiring 110 and the second aluminum wiring 111 are provided. Yes. In the semiconductor device 115, the line widths of the first aluminum wiring 110 and the second aluminum wiring 111 and the diameter values of the cross sections of the first plug electrode 106 and the second plug electrode 107 are substantially reduced by miniaturization of the semiconductor process. It is the same.

  6A to 6I are schematic cross-sectional views showing a manufacturing process of a semiconductor device having a conventional multilayer wiring. First, an ILD layer 102 is formed on a semiconductor substrate 101 as shown in FIG. 6A, and then, as shown in FIG. 6B, an ILD layer on the source or drain of a transistor that is the semiconductor substrate 101. 102 is dry-etched to form an opening 122 (contact hole). Next, the semiconductor substrate in which the opening 122 is formed is cleaned with a predetermined cleaning liquid to remove a product such as a polymer attached to the inner wall of the opening 122. Next, the first plug electrode 106 is formed in the opening 122 as shown in FIG.

  Next, as shown in FIG. 6D, a first aluminum wiring 110 is formed on the first plug electrode 106. Next, as shown in FIG. 6E, the IMD layer 103 is formed on the ILD layer 102 on which the first aluminum wiring 110 is formed. Next, as shown in FIGS. 6F and 6G, the IMD layer 103 on the first aluminum wiring 110 is dry-etched to form an opening 126 (via hole). Then, the semiconductor substrate in which the opening 126 is formed is cleaned with a predetermined cleaning liquid, and a product such as a polymer attached to the inner wall of the opening 126 is removed. After removing the polymer and the like, the second plug electrode 107 is formed in the opening 126 as shown in FIG. Thereafter, a second aluminum wiring 111 is formed on the second plug electrode 107 as shown in FIG. In this way, the semiconductor device 115 having the multilayer wiring shown in FIG. 5 can be obtained.

  However, the line widths of the first aluminum wiring 110 and the second aluminum wiring 111 and the diameter values of the cross sections of the first plug electrode 106 and the second plug electrode 107 are substantially the same. A problem arises when a slight shift occurs in the position where the opening 126 is formed. 7A and 7B are schematic cross-sectional views showing a manufacturing process of a semiconductor device having a conventional multilayer wiring when a slight deviation occurs in the position where the opening 126 is formed.

  As shown in FIG. 7A, when a slight shift occurs in the position where the opening 126 is formed, the ILD layer 102 may be over-etched by dry etching when the opening 126 is formed. In this case, the first plug electrode 106 may be exposed due to over-etching of the ILD layer 102 as shown in FIG. If the semiconductor substrate in which the opening 126 is formed is cleaned with a predetermined cleaning liquid with the first plug electrode 3 exposed, the first plug electrode 106 is eroded by the cleaning liquid as shown in FIG. 7B. There is a case. When the first plug electrode 106 is eroded, the reliability of the semiconductor device is greatly impaired.

  Therefore, Patent Document 1 proposes a method of manufacturing an electronic device that can prevent over-etching of the ILD layer 102 even when the formation position of the first aluminum wiring 110 and the formation position of the opening 126 are slightly shifted. Yes.

  FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing process of the electronic device of Patent Document 1. In Patent Document 1, an ILD layer 102 in which a first plug electrode 106 is formed on a semiconductor substrate 101 is formed on a semiconductor substrate 101 by a process similar to a method for manufacturing a semiconductor device having a conventional multilayer wiring, and a first aluminum wiring 110 is formed. ing. Thereafter, as shown in FIG. 8A, an etching stop layer (silicon oxynitride layer) 128 is formed on the ILD layer 102 so as to cover the first aluminum wiring 110, and further, an IMD layer (oxidation layer) is formed on the etching stop layer 128. Silicon layer) 103 is formed.

Next, as shown in FIG. 8B, the IMD layer 103 on the first aluminum wiring 110 is etched under the first etching condition in which the etching rate for the IMD layer 103 is higher than the etching rate for the etching stop layer 128. The etching stop layer 128 is exposed by forming the opening 126.
Next, as shown in FIG. 8C, the etching stop layer 128 exposed through the opening 126 is removed by etching under a second etching condition in which the etching rate for the etching stop layer 128 is higher than the etching rate for the ILD layer 102. A via hole reaching the first aluminum wiring 110 is formed in the IMD layer 103. Thereafter, an electronic device having a multilayer wiring is manufactured by a process similar to that of a method for manufacturing a semiconductor device having a conventional multilayer wiring.

  In the method for manufacturing an electronic device proposed in Patent Document 1, even if the formation position of the first aluminum wiring 110 and the formation position of the opening 126 are slightly shifted from the first plug electrode 106, the ILD layer 102 is Since it is protected by the etching stop layer 128, over-etching of the ILD layer 102 can be prevented when the opening 126 is formed.

JP 2006-49409 A

  However, in the manufacturing method of Patent Document 1, when the formation position of the opening 126 is shifted from the position of the first aluminum wiring 110, the etching stop on the first aluminum wiring 110 is performed as shown in FIG. The etch stop layer 128 on the ILD layer 102 may be removed together with the layer 128. Further, when the formation position of the first aluminum wiring 110 is shifted with respect to the first plug electrode 106, the etching stop layer 128 on the ILD layer 102 is removed as shown in FIG. The plug electrode 106 may be exposed. In such a case, when the semiconductor substrate having the openings 126 is cleaned with a predetermined cleaning liquid to remove products such as polymers adhering to the inner walls of the openings 126, the cleaning liquid as shown in FIG. As a result, the first plug electrode 106 may be eroded. When the first plug electrode 106 is eroded, the reliability of the semiconductor device is greatly impaired.

Also, with the miniaturization of semiconductor processes, the diameter of openings such as via holes becomes smaller, the composition of products such as polymers that adhere to the inner wall changes to stabilize the etching shape of via holes, etc., and conventional cleaning liquids can handle this. It can be difficult. When it is necessary to use a cleaning liquid that reduces the etching selectivity of the plug electrode, the conventional technique may erode the plug electrode, which may greatly impair the reliability of the semiconductor device.
The present invention has been made in view of such circumstances, and provides a highly reliable manufacturing method of a semiconductor device and a semiconductor device.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first plug electrode in a first opening penetrating a first insulator layer provided on a semiconductor substrate; and a first plug electrode on the first insulator layer. A step of forming a first wiring layer in contact, a step of forming an etching stop layer and a second insulator layer in this order on the first insulator layer and the first wiring layer, and an etching on the first wiring layer The first wiring layer is exposed by removing the stop layer and the second insulator layer using dry etching, and an etching stop provided on the side surface of the first wiring layer and a part of the first insulator layer A step of forming a sidewall including a layer and a second insulator layer, a step of forming a third insulator layer on the first insulator layer, the first wiring layer, and the sidewall, and using dry etching Third on the first wiring layer Forming a second opening through the edge layer; forming a second plug electrode in contact with the first wiring layer in the second opening; and a second contact in contact with the second plug electrode on the third insulator layer. And a step of forming three wiring layers.

In the method of manufacturing a semiconductor device according to the present invention, the first wiring layer is exposed when the sidewall is formed. Therefore, it is not necessary to remove the etching stop layer when forming the second opening that penetrates the third insulator layer. For this reason, even if the formation position of the second opening penetrating the third insulator layer is shifted from the first wiring layer, the dry etching at the time of forming the second opening is performed on the first insulator layer included in the sidewall. It can be stopped by an etching stop layer. Thus, the first plug electrode can be prevented from being exposed by forming the second opening.
As a result, the first plug electrode can be prevented from being eroded by the cleaning process of the second opening, so that a highly reliable semiconductor can be obtained even if the first wiring layer or the second opening is slightly displaced. The device can be manufactured.
In addition, when the sidewall is a stacked film of the etching stop layer and the second insulator layer, stress generated in the transistor can be reduced as compared with the case where the sidewall is formed using only the etching stop layer.

It is a schematic sectional drawing which shows the structure of the semiconductor device of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device of one Embodiment of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device of one Embodiment of this invention. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device which has the conventional multilayer wiring. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device which has the conventional multilayer wiring. It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device which has the conventional multilayer wiring. It is a schematic sectional drawing which shows the manufacturing process of the electronic device of patent document 1. It is a schematic sectional drawing which shows the manufacturing process of the electronic device of patent document 1.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description.

1. Configuration of Semiconductor Device FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 15 according to the present embodiment includes a first insulator layer 2 provided on the semiconductor substrate 1, a first wiring layer 11 provided on the first insulator layer 2, and the first insulator layer 2. And a third insulator layer 4 provided on the first wiring layer 11, a first plug electrode 8 penetrating through the first insulator layer 2 and in contact with the first wiring layer 11, and a third insulator layer 4 A second plug electrode 9 that penetrates and contacts the first wiring layer 11 and is provided immediately above the first plug electrode 8; an etching stop layer 6 and a second insulator provided on the side surface of the first wiring layer 11; And a sidewall 10 including the layer 3, and the etching stop layer 6 covers a part on the first insulator layer 2.
FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the embodiment of the present invention.
In addition, the semiconductor device 15 of the present embodiment may include the second wiring layer 16 provided on the semiconductor substrate 1.
Further, the semiconductor device 15 of the present embodiment may include the third wiring layer 12 provided on the third insulator layer 4.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device of this embodiment.
The manufacturing method of the semiconductor device 15 of the present embodiment includes a step of forming the first plug electrode 8 in the first opening 17 penetrating the first insulator layer 2 provided on the semiconductor substrate 1, and the first insulator layer 2. A step of forming a first wiring layer 11 in contact with the first plug electrode 8; and an etching stop layer 6 and a second insulating layer 3 on the first insulating layer 2 and the first wiring layer 11 in this order. And the etching stop layer 6 and the second insulator layer 3 on the first wiring layer 11 are removed by dry etching to expose the first wiring layer 11, and the side surfaces of the first wiring layer 11 are exposed. A step of forming a sidewall 10 including an etching stop layer 6 and a second insulator layer 3 provided on the upper portion and a part of the first insulator layer 2, and a first wiring on the first insulator layer 2; Third layer on layer 11 and sidewall 10 A step of forming the body layer 4, a step of forming the second opening 20 penetrating the third insulator layer 4 on the first wiring layer 11 using dry etching, and the first wiring layer 11 in the second opening 20. A step of forming a second plug electrode 9 in contact with the second plug electrode 9 and a step of forming a third wiring layer 12 in contact with the second plug electrode 9 on the third insulator layer 4.

In addition, the method for manufacturing the semiconductor device 15 of the present embodiment includes the step of forming the second wiring layer 16 on the semiconductor substrate 1, the step of forming the first insulator layer 2 on the semiconductor substrate 1, and the first insulator layer. The process of forming the 1st opening 17 which penetrates 2 may be provided.
Hereinafter, the semiconductor device 15 of the present invention, its components, and its manufacturing method will be described.

1-1. Semiconductor Device The semiconductor device 15 is not particularly limited as long as it is a semiconductor device having a multi-layer wiring.

1-2. Semiconductor substrate The semiconductor substrate 1 is not particularly limited, but is, for example, a MOS type semiconductor substrate or a substrate for a CMOS type solid-state imaging device. For example, the semiconductor substrate 1 may be formed with a source, a drain, and a gate.

1-3. Second Wiring Layer The second wiring layer 16 may be provided on the semiconductor substrate 1. Further, the second wiring layer 16 may be in contact with the first plug electrode 8. The second wiring layer 16 may be electrically connected to the first wiring layer 11 via the first plug electrode 8. The second wiring layer 16 may be electrically connected to the source, gate, or drain included in the semiconductor substrate 1. The second wiring layer 16 may be provided immediately above the source, gate, or drain. Further, the line width of the second wiring layer 16 may be substantially the same as the diameter of the circular cross section of the first plug electrode 8.

In this specification, “substantially the same” means that when one length is 100, the other is between 80 and 120.
The material of the second wiring layer 16 is not particularly limited as long as it is a conductive material. For example, the second wiring layer 16 is made of a metal such as aluminum, titanium, or tungsten.
Although the thickness of the 2nd wiring layer 16 is not specifically limited, For example, they are 200 nm-500 nm.
Although the line width of the 2nd wiring layer 16 is not specifically limited, For example, they are 0.2 micrometer-0.5 micrometer.
Although the formation method of the 2nd wiring layer 16 is not specifically limited, For example, a metal layer is formed on the semiconductor substrate 1 by sputtering, and a resist pattern is formed on a metal layer. Then, after removing a part of the metal layer by dry etching, the second wiring layer 16 can be formed by removing the resist pattern.

1-4. First Insulator Layer The first insulator layer 2 is not particularly limited as long as it is provided on the semiconductor substrate 1.
Although the material of the 1st insulator layer 2 is not specifically limited, For example, it consists of a silicon oxide.
Although the thickness of the 1st insulator layer 2 is not specifically limited, For example, they are 500 nm-1000 nm.
Although the formation method of the 1st insulator layer 2 is not specifically limited, For example, it can form by CVD method.

1-5. First Plug Electrode The first plug electrode 8 is not particularly limited as long as it penetrates the first insulator layer 2 and contacts the first wiring layer 11. The first plug electrode 8 may be electrically connected to the source, drain, and gate included in the semiconductor substrate 1, and may be in contact with the second wiring layer 16 provided on the semiconductor substrate 1. Further, the first plug electrode 8 may be provided immediately above the source, drain, and gate, or may be provided immediately above the second wiring layer 16. The first plug electrode 8 may be electrically connected to a wiring layer provided between other insulator layers. The first plug electrode 8 may have a circular cross section parallel to the semiconductor substrate 1.
Although the material of the 1st plug electrode 8 will not be specifically limited if it is a conductor, For example, they are metals, such as tungsten (W).
When the 1st plug electrode 8 has a circular cross section, the diameter of a cross section is although it does not specifically limit, For example, they are 0.2 micrometer-0.5 micrometer. The diameter of this cross section may be substantially the same as the line width of the second wiring layer 16 or the line width of the first wiring layer 11.

  The method for forming the first plug electrode 8 is not particularly limited. For example, first, a resist pattern is formed on the first insulator layer 2 formed on the semiconductor substrate 1, and then the first insulator layer 2 is dry etched. Then, the first opening 17 (contact hole) is formed as shown in FIG. Thereafter, the first opening 17 is washed with a predetermined cleaning liquid, so that a product such as a polymer attached to the inner wall of the first opening 17 can be removed. Thereafter, a first plug electrode 8 can be formed by depositing a metal such as tungsten in the first opening 17 by sputtering and performing a CMP process.

1-6. First Wiring Layer The first wiring layer 11 is provided on the first insulator layer 2 and is in contact with the first plug electrode 8 and the second plug electrode 9. Further, the line width of the first wiring layer 11 may be substantially the same as the diameter of the cross section of the first plug electrode 8. Further, the line width of the first wiring layer 11 may be substantially the same as the diameter of the cross section of the second plug electrode 9. The first wiring layer 11 may be provided immediately above the first plug electrode 8.
Although the material of the 1st wiring layer 11 will not be specifically limited if it is an electroconductive material, For example, it consists of metals, such as aluminum, titanium, and tungsten.
Although the thickness of the 1st wiring layer 11 is not specifically limited, For example, they are 200 nm-500 nm.
Although the line width of the 1st wiring layer 11 is not specifically limited, For example, they are 0.2 micrometer-0.5 micrometer.
Although the formation method of the 1st wiring layer 11 is not specifically limited, For example, it can form by the method similar to the 2nd wiring layer 16. By forming the first wiring layer 11, a semiconductor substrate having a cross section as shown in FIG.

1-7. Etching Stop Layer The etching stop layer 6 is provided on the side surface of the first wiring layer 11 and covers a part on the first insulator layer 2. The etching stop layer 6 is included in the sidewall 10.
The material of the etching stop layer 6 may be a material whose etching rate for dry etching when forming the second opening 20 is slower than that of the second insulator layer 3 and the third insulator layer 4, for example. The material of the etching stop layer 6 is not particularly limited, but is, for example, silicon nitride or silicon oxynitride. For example, when the etching stop layer 6 is formed of silicon nitride and the second insulator layer 3 and the third insulator layer 4 are formed of silicon oxide, the etching selectivity of silicon nitride to silicon oxide is 1:20. be able to.

The etching stop layer 6 may have an L-shaped cross section. In the L-shaped cross section, the etching stop layer 6 on the side surface of the first wiring layer 11 can be vertical, and the etching stop layer 6 on the first insulator layer 2 can be horizontal. Further, the corners of the vertical and horizontal etching stop layers 6 may be rounded. When the length in the height direction of the side wall of the first wiring layer 11 of the vertical etching stop layer 6 is 100, the length of the horizontal etching stop layer 6 in the direction parallel to the first insulator layer 2 is set. May be 20-100.
Although the thickness of the etching stop layer 6 is not specifically limited, For example, it is 10-50 nm.

The formation method of the etching stop layer 6 is not particularly limited. For example, the CVD method is used on the first insulator layer 2 (when the formation position of the first wiring layer 11 is shifted and the first plug electrode 8 is exposed) And the first wiring layer 11 (including the upper surface and side surfaces of the first wiring layer 11). By forming the etching stop layer 6, a semiconductor substrate having a cross section as shown in FIG.
The etching stop layer 6 is partially removed when the sidewall 10 is formed.

1-8. Second Insulator Layer The second insulator layer 3 is provided on the etching stop layer 6 and is included in the sidewall 10 together with the etching stop layer 6.
The material of the second insulator layer 3 may be a material whose etching rate for dry etching when forming the second opening 20 is faster than that of the etching stop layer 6, for example, silicon oxide.
Although the thickness of the 2nd insulator layer 3 is not specifically limited, For example, it is 50-100 nm at the time of formation.
Although the formation method of the 2nd insulator layer 3 is not specifically limited, For example, it can form by CVD method. By forming the second insulator layer 3, a semiconductor substrate having a cross section as shown in FIG.
The second insulator layer 3 is partially removed when the sidewall 10 is formed.

1-9. Sidewall The sidewall 10 includes an etching stop layer 6 and a second insulator layer 3 provided on the side surface of the first wiring layer 11 and part of the first insulator layer 2. The sidewall 10 may be provided immediately above the first plug electrode 8.
The side wall 10 is a side wall film of the first wiring layer 11, and the side wall 10 is also provided on a part of the first insulator layer 2. Not provided. However, the etching stop layer 6 may partially remain on the first wiring layer 11 as long as the electrical connection between the first wiring layer 11 and the second plug electrode 9 is not hindered. It does not have to be.

  The sidewall 10 is formed by forming the etching stop layer 6 and the second insulator layer 3 in this order on the first insulator layer 2 and the first wiring layer 11, and etching stop on the first wiring layer 11. It is formed by exposing the first wiring layer 11 by dry etching the layer 6 and the second insulator layer 3. By forming the sidewall 10, a semiconductor substrate having a cross section as shown in FIG.

FIG. 4 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor substrate when the formation positions of the first wiring layer 11 and the second opening 20 are shifted from the first plug electrode 8. Exposing the first wiring layer 11 eliminates the need to remove the etching stop layer 6 in the step of forming the second opening 20. For this reason, even if the formation position of the second opening 20 penetrating the third insulator layer 4 is shifted with respect to the first wiring layer 11 as shown in FIG. It can be stopped by the etching stop layer 6 on the first insulator layer 2. Accordingly, the first plug electrode 8 can be prevented from being exposed by forming the second opening 20 that penetrates the third insulator layer 4.
As a result, erosion due to the cleaning process of the second opening 20 can be prevented, so even if a slight shift occurs in the formation position of the first wiring layer 11 or the second opening 20, as shown in FIG. In addition, a highly reliable semiconductor device in which the first plug electrode 8 is not eroded can be manufactured.

  The sidewall 10 may be formed by dry etching the etching stop layer 6 and the second insulator layer 3 on the first wiring layer 11 using an etch back technique. Further, the dry etching of the etching stop layer 6 and the second insulator layer 3 on the first wiring layer 11 may be performed without forming a resist pattern (mask).

For example, the conditions for dry-etching the etching stop layer 6 and the second insulator layer 3 on the first wiring layer 11 are RIE equipment, CF ₄ : 10 to 100 sccm, CHF ₃ : 10 to 50 sccm, O ₂ : 10-50 sccm, Ar: 50-150 sccm, high frequency output: 200-1000 W, vacuum degree 10-100 mTorr. Preferably, an RIE apparatus is used, CF ₄ : 50 sccm, CHF ₃ : 20 sccm, O ₂ : 20 sccm, Ar: 100 sccm are used as etching gases, high-frequency output: 500 W, and vacuum degree: 60 mTorr.

1-10. Third Insulator Layer The third insulator layer 4 is provided on the first insulator layer 2, the first wiring layer 11, and the sidewall 10.
Although the material of the 3rd insulator layer 4 is not specifically limited, For example, it is a silicon oxide.
Although the thickness of the 3rd insulator layer 4 is not specifically limited, For example, they are 500 nm-1000 nm.
Although the formation method of the 3rd insulator layer 4 is not specifically limited, For example, it can form by CVD method. By forming the third insulator layer 4, a semiconductor substrate having a cross section as shown in FIG.

1-11. Second Plug Electrode The second plug electrode 9 is not particularly limited as long as it penetrates the third insulator layer 4 and comes into contact with the first wiring layer 11. Further, the second plug electrode 9 may be in contact with the third wiring layer 12 provided on the third insulator layer 4. Further, the second plug electrode 9 may be provided immediately above the first wiring layer 11. Further, the second plug electrode 9 may be provided immediately above the first plug electrode 8. The second plug electrode 9 may have a circular cross section parallel to the semiconductor substrate 1.
Although the material of the 2nd plug electrode 9 will not be specifically limited if it is a conductor, For example, they are metals, such as tungsten (W).
When the 2nd plug electrode 9 has a circular cross section, the diameter of a cross section is although it does not specifically limit, For example, they are 0.2 micrometer-0.5 micrometer. The diameter of this cross section may be substantially the same as the line width of the first wiring layer 11 or the line width of the third wiring layer 12. Further, the diameter of the cross section of the second plug electrode 9 may be substantially the same as the diameter of the cross section of the first plug electrode 8.

The second plug electrode 9 is formed by dry etching to form a second opening 20 penetrating the third insulator layer 4 on the first wiring layer 11 and cleaning the second opening 20 with a predetermined cleaning liquid. It may be formed by a step and a step of forming the second plug electrode 9 in the second opening 20. Further, the second opening 20 may be provided immediately above the first wiring layer 11. More specifically, for example, first, a resist pattern 18 is formed on the third insulator layer 4 as shown in FIG. 3G, and then the third insulator layer 4 is dry-etched. The second opening 20 (via hole) is formed as in h). As a result, the first wiring layer 11 can be exposed. At this time, since the etching stop layer 6 on the first wiring layer 11 is removed, it is not necessary to remove the etching stop layer 6. For this reason, even when the formation position of the second opening 20 or the first wiring layer 11 is shifted, it is possible to prevent the first plug electrode 8 from being exposed by this dry etching. As a result, erosion of the first plug electrode 8 can be prevented.
This dry etching can be performed under etching conditions in which the etching rate for the third insulator layer 4 is faster than the etching rate for the etching stop layer 6.

  Thereafter, by cleaning the second opening 20 with a predetermined cleaning liquid, etching reaction products such as a polymer attached to the inner wall of the second opening 20 can be removed. Thereafter, a second plug electrode 9 can be formed by depositing a metal such as tungsten in the second opening 20 by sputtering and performing a CMP process. By forming the second plug electrode 9, a semiconductor substrate having a cross section as shown in FIG.

In addition, it is thought that aluminum fluoride is producing | generating as an etching reaction product.
A dilute hydrofluoric acid chemical can be used as the cleaning liquid for cleaning the second opening 20.

1-12. Third Wiring Layer The third wiring layer 12 can be provided on the third insulator layer 4. Further, the third wiring layer 12 may be electrically connected to the first wiring layer 11 via the second plug electrode 9. The third wiring layer 12 may be in contact with the second plug electrode. The third wiring layer 12 may be provided immediately above the second plug electrode 9. The line width of the third wiring layer 12 may be substantially the same as the diameter of the circular cross section of the first plug electrode 8 or the second plug electrode 9.
Although the material of the 3rd wiring layer 12 will not be specifically limited if it is an electroconductive material, For example, they are metals, such as aluminum, titanium, and tungsten.
Although the thickness of the 3rd wiring layer 12 is not specifically limited, For example, they are 200 nm-500 nm.
Although the line width of the 3rd wiring layer 12 is not specifically limited, For example, they are 0.2 micrometer-0.5 micrometer.
The method for forming the third wiring layer 12 is not particularly limited, but can be formed by a method similar to that for the second wiring layer 16, for example. By forming the third wiring layer 12, a semiconductor device having a cross section as shown in FIG. 3J can be obtained.

1: Semiconductor substrate 2: First insulator layer 3: Second insulator layer 4: Third insulator layer 6: Etching stop layer 8: First plug electrode 9: Second plug electrode 10: Side wall 11: First Wiring layer 12: Third wiring layer 15: Semiconductor device 16: Second wiring layer 17: First opening 18: Resist pattern 20: Second opening 101: Semiconductor substrate 102: ILD layer 103: IMD layer 106: First plug electrode 107: second plug electrode 110: first aluminum wiring 111: second aluminum wiring 115: semiconductor device 120: resist pattern 122: opening 124: resist pattern 126: opening 128: etching stop layer

Claims (11)

Forming a first plug electrode in a first opening penetrating a first insulator layer provided on a semiconductor substrate;
Forming a first wiring layer in contact with the first plug electrode on the first insulator layer;
Forming an etching stop layer and a second insulator layer in this order on the first insulator layer and the first wiring layer;
The first wiring layer is exposed by removing the etching stop layer and the second insulator layer on the first wiring layer using dry etching, and a part of the first insulating layer and the side surface of the first wiring layer are exposed. Forming a sidewall including an etching stop layer and a second insulator layer provided thereon;
Forming a third insulator layer on the first insulator layer, on the first wiring layer and on the sidewall;
Forming a second opening through the third insulator layer on the first wiring layer using dry etching;
Forming a second plug electrode in contact with the first wiring layer in the second opening;
Forming a third wiring layer in contact with the second plug electrode on the third insulator layer.   The method according to claim 1, wherein the second opening is cleaned with a predetermined cleaning solution before forming the second plug electrode.   The method according to claim 1, wherein the etching stop layer has a slower etching rate for dry etching used when forming the second opening than the second insulator layer and the third insulator layer. A first insulator layer provided on a semiconductor substrate;
A first wiring layer provided on the first insulator layer;
A third insulator layer provided on the first insulator layer and the first wiring layer;
A first plug electrode that penetrates the first insulator layer and contacts the first wiring layer;
A second plug electrode penetrating the third insulator layer and in contact with the first wiring layer and provided immediately above the first plug electrode;
A sidewall including an etching stop layer and a second insulator layer provided on the side surface of the first wiring layer;
The etching stop layer is a semiconductor device that covers part of the first insulator layer.   The apparatus of claim 4, wherein the first plug electrode and the second plug electrode have a circular cross section with substantially the same diameter.   6. The device according to claim 4, wherein the first plug electrode and the second plug electrode have a circular cross section having a diameter substantially the same as the line width of the first wiring layer. A second wiring layer provided on the semiconductor substrate and in contact with the first plug electrode;
The device according to claim 4, wherein the second wiring layer is electrically connected to the first wiring layer via the first plug electrode. A third wiring layer provided on the third insulator layer and in contact with the second plug electrode;
The device according to claim 4, wherein the third wiring layer is electrically connected to the first wiring layer via the second plug electrode.   The device according to any one of claims 4 to 8, wherein the third insulator layer is silicon oxide, and the etching stop layer is silicon nitride or silicon oxynitride.   The apparatus according to claim 4, wherein the etching stop layer has an L-shaped cross section.   The device according to claim 4, which is applied to a CMOS type solid-state imaging device.

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