JP2010251556A - Semiconductor device and radiating body - Google Patents

Semiconductor device and radiating body Download PDF

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Publication number
JP2010251556A
JP2010251556A JP2009100051A JP2009100051A JP2010251556A JP 2010251556 A JP2010251556 A JP 2010251556A JP 2009100051 A JP2009100051 A JP 2009100051A JP 2009100051 A JP2009100051 A JP 2009100051A JP 2010251556 A JP2010251556 A JP 2010251556A
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Prior art keywords
switching element
electrode
region
semiconductor device
pad
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JP2009100051A
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Japanese (ja)
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Kotaro Terao
幸太郎 寺尾
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Priority to JP2009100051A priority Critical patent/JP2010251556A/en
Publication of JP2010251556A publication Critical patent/JP2010251556A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can fully maintain the heat dissipation of a plurality of switching elements, while maintaining insulation between the plurality of switching elements, and to provide a radiating body which is used for the device. <P>SOLUTION: In a semicondutor device 1, a first switching element 11 and a second switching element 12 are mounted on a die pad 2. The first switching element 11 is bonded directly with the die pad 2, while the second switching element 12 is mounted on the die pad 2 through a radiating body 5. The radiating body 5 is constituted mainly of a silicon substrate 51 which excels in heat dissipation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置及び放熱体に関し、特に複数のスイッチング素子をダイパッド上に搭載する半導体装置及びそれに使用される放熱体に関する。   The present invention relates to a semiconductor device and a heat radiator, and more particularly to a semiconductor device in which a plurality of switching elements are mounted on a die pad and a heat radiator used for the semiconductor device.

家電モータの駆動回路、車載モータの駆動回路等において、直流を交流に変換する１つの回路としてハーフブリッジ回路が知られている。ハーフブリッジ回路は２つのゲート駆動回路と２つのスイッチング素子とによって構築されている。   A half-bridge circuit is known as one circuit for converting direct current into alternating current in a drive circuit for home appliance motors, a drive circuit for in-vehicle motors, and the like. The half bridge circuit is constructed by two gate drive circuits and two switching elements.

２つのスイッチング素子にはＭＯＳＦＥＴ（metal oxide semiconductor field effect transistor）やＩＧＢＴ（insulated gate bipolar transistor）が使用されている。この２つのスイッチング素子は１つのモールドパッケージ内に納められ、半導体装置として製品化がなされている。   MOSFETs (metal oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors) are used for the two switching elements. These two switching elements are housed in one mold package and are commercialized as semiconductor devices.

下記特許文献１には、この種の半導体装置に好適なマルチチップパッケージ構造を有する電力素子が開示されている。この電力素子は、リードフレーム上に絶縁テープを介在してスイッチング素子であるトランジスタチップ、コントロールＩＣチップのそれぞれを並べて取り付けている。絶縁テープにはポリイミドが使用され、この絶縁テープとの接着には導電性接着剤が使用されている。   Patent Document 1 below discloses a power element having a multichip package structure suitable for this type of semiconductor device. In this power element, a transistor chip, which is a switching element, and a control IC chip are mounted side by side with an insulating tape interposed on a lead frame. Polyimide is used for the insulating tape, and a conductive adhesive is used for adhesion to the insulating tape.

また、下記特許文献２には、集積回路装置が開示されている。この集積回路装置は、分割された引き出しリード上にそれぞれ電力トランジスタを配置している。   Patent Document 2 below discloses an integrated circuit device. In this integrated circuit device, power transistors are respectively arranged on the divided lead leads.

特開２００１−１１０９８６号公報JP 2001-110986 A 実開昭４９−４７５６７号公報Japanese Utility Model Publication No. 49-47567

しかしながら、上記特許文献１及び特許文献２においては、以下の点について配慮がなされていなかった。   However, in the said patent document 1 and the patent document 2, consideration was not made about the following points.

特許文献１に係る電力素子はトランジスタチップとその制御を行うコントロールＩＣチップとを組み合わせた回路構成である。トランジスタチップの動作に伴う発熱量は大きいので、リードフレームに直接取り付ければ、トランジスタチップの放熱性を十分に確保することができ、トランジスタチップの発熱に伴う特性劣化を防止することができる。一方、コントロールＩＣチップの動作に伴う発熱量は小さいので、放熱性を特に確保する必要がなく、リードフレーム上に絶縁テープを介してコントロールＩＣチップを取り付ければ、コントロールＩＣチップとトランジスタチップとの絶縁性を確保することができる。   The power element according to Patent Document 1 has a circuit configuration in which a transistor chip and a control IC chip for controlling the transistor chip are combined. Since the amount of heat generated by the operation of the transistor chip is large, if it is directly attached to the lead frame, the heat dissipation of the transistor chip can be sufficiently secured, and the deterioration of characteristics due to the heat generation of the transistor chip can be prevented. On the other hand, since the amount of heat generated by the operation of the control IC chip is small, it is not necessary to secure heat dissipation. If the control IC chip is attached to the lead frame via an insulating tape, the control IC chip and the transistor chip are insulated. Sex can be secured.

ところが、２つのスイッチング素子を有するハーフブリッジ回路を構築する場合、一方のスイッチング素子をリードフレームに直接取り付け、他方のスイッチング素子をリードフレーム上に絶縁テープを介して取り付けると、絶縁テープの放熱性が悪いので、他方のスイッチング素子の放熱性を十分に確保することができない。このため、他方のスイッチング素子の発熱に伴う特性劣化が発生し、一方、他方のそれぞれのスイッチング素子の特性にばらつきが生じるので、ハーフブリッジ回路に適した特性を得ることが難しかった。   However, when constructing a half-bridge circuit having two switching elements, if one switching element is directly attached to the lead frame and the other switching element is attached to the lead frame via an insulating tape, the heat dissipation of the insulating tape is improved. Since it is bad, the heat dissipation of the other switching element cannot be ensured sufficiently. For this reason, the characteristic deterioration due to heat generation of the other switching element occurs, and on the other hand, the characteristics of the other switching element vary. Therefore, it is difficult to obtain characteristics suitable for the half-bridge circuit.

また、特許文献２に係る集積回路装置を応用すれば、分割された引き出しリード上にそれぞれスイッチング素子を配置すれば、ハーフブリッジ回路は構築することができる。ところが、分割された引き出しリード間に絶縁のために離間スペースが必要であり、限られたモールド樹脂内においては分割された個々の引き出しリード自体のボリュームが小さくなる。つまり、引き出しリードにおいては放熱性を十分に確保することができないので、スイッチング素子の発熱に伴う特性劣化を避けることが難しい。   Further, if the integrated circuit device according to Patent Document 2 is applied, a half-bridge circuit can be constructed by arranging switching elements on the divided lead leads. However, a space is required for insulation between the divided lead leads, and the volume of each divided lead lead is reduced in a limited mold resin. That is, since sufficient heat dissipation cannot be ensured in the lead-out lead, it is difficult to avoid characteristic deterioration due to heat generation of the switching element.

本発明は上記課題を解決するためになされたものである。従って、本発明は、複数のスイッチング素子間の絶縁性を確保しつつ、複数のスイッチング素子の放熱性を十分に確保することができる半導体装置並びにそれに使用される放熱体を提供することである。   The present invention has been made to solve the above problems. Accordingly, the present invention is to provide a semiconductor device capable of sufficiently ensuring the heat dissipation of the plurality of switching elements while ensuring the insulation between the plurality of switching elements, and a radiator used for the semiconductor device.

上記課題を解決するために、本発明の実施例に係る第１の特徴は、半導体装置において、第１の表面に第１の主電極を有し、第１の表面に対向する第２の表面に第２の主電極を有する第１のスイッチング素子と、第３の表面に第３の主電極を有し、第３の表面に対向する第４の表面に第４の主電極を有する第２のスイッチング素子と、第５の表面を有しこの第５の表面に第１の領域及び第２の領域を有するダイパッドと、第６の表面及びそれに対向する第７の表面を有し第６の表面に第３の領域及び第４の領域を有するシリコン基板、第３の領域に配設された第１のパッド電極、及び第４の領域に配設され第１のパッド電極に電気的に接続された第２のパッド電極を有する放熱体と、を備え、ダイパッドの第１の領域において第５の表面に第２の主電極を電気的に接続して第１のスイッチング素子を搭載し、第２の領域において第５の表面にシリコン基板の第７の表面を向かい合わせて放熱体を搭載し、シリコン基板の第１のパッド電極において第４の主電極を電気的に接続して第２のスイッチング素子を搭載したことである。   In order to solve the above-mentioned problem, a first feature according to an embodiment of the present invention is that a semiconductor device has a first main electrode on a first surface and a second surface facing the first surface. A second switching element having a second main electrode, a second switching element having a third main electrode on the third surface, and a fourth main electrode on the fourth surface opposite to the third surface. A switching element, a die pad having a fifth surface and having a first region and a second region on the fifth surface, a sixth surface and a seventh surface opposite to the sixth surface. A silicon substrate having a third region and a fourth region on the surface, a first pad electrode disposed in the third region, and electrically connected to the first pad electrode disposed in the fourth region And a heat sink having a second pad electrode formed on the fifth surface in the first region of the die pad. The first switching element is mounted by electrically connecting the main electrodes of the silicon substrate, and the radiator is mounted on the fifth surface in the second region with the seventh surface of the silicon substrate facing the fifth surface. This is that the second switching element is mounted by electrically connecting the fourth main electrode in one pad electrode.

第１の特徴に係る半導体装置において、放熱体は、シリコン基板と、シリコン基板の第６の表面上において第３の領域及び第４の領域に配設された絶縁膜と、第３の領域から第４の領域に渡って絶縁膜上に配設され、第１のパッド電極、又は第１のパッド電極及び第２のパッド電極を構成する第１の金属層と、シリコン基板の第７の表面上に配設され、ダイパッドの第５の表面に接合するための第２の金属層とを更に備えることが好ましい。   In the semiconductor device according to the first feature, the heat radiator includes a silicon substrate, an insulating film disposed in the third region and the fourth region on the sixth surface of the silicon substrate, and a third region. A first metal layer constituting the first pad electrode, or the first pad electrode and the second pad electrode, disposed on the insulating film over the fourth region, and a seventh surface of the silicon substrate; It is preferable to further comprise a second metal layer disposed on the die pad and bonded to the fifth surface of the die pad.

第１の特徴に係る半導体装置において、ダイパッドの第１の領域において第５の表面に第１のスイッチング素子の第２の主電極を接合する第１の半田と、放熱体の第１のパッド電極に第２のスイッチング素子の第４の主電極を接合する第２の半田と、放熱体の第２のパッド電極に電気的に接続される配線とを更に備えることが好ましい。   In the semiconductor device according to the first feature, the first solder for joining the second main electrode of the first switching element to the fifth surface in the first region of the die pad, and the first pad electrode of the radiator It is preferable to further include a second solder for joining the fourth main electrode of the second switching element and a wiring electrically connected to the second pad electrode of the radiator.

第１の特徴に係る半導体装置において、第１のスイッチング素子の第１の主面に配設された第１の制御電極と、第２のスイッチング素子の第３の主面に配設された第２の制御電極と、を備え、第１のスイッチング素子の第１の制御電極は第１の入力端子に接続され、第２の主電極は第１の電源端子に接続され、第２のスイッチング素子の第２の制御電極は第２の入力端子に接続され、第３の主電極は第２の電源端子に接続され、第１のスイッチング素子の第１の主電極は、放熱体の第１のパッド電極及び第２のパッド電極を通して第２のスイッチング素子の第４の主電極に接続されることが好ましい。   In the semiconductor device according to the first feature, the first control electrode disposed on the first main surface of the first switching element and the first control electrode disposed on the third main surface of the second switching element. The first control electrode of the first switching element is connected to the first input terminal, the second main electrode is connected to the first power supply terminal, and the second switching element. The second control electrode is connected to the second input terminal, the third main electrode is connected to the second power supply terminal, and the first main electrode of the first switching element is connected to the first heat sink. It is preferable to be connected to the fourth main electrode of the second switching element through the pad electrode and the second pad electrode.

本発明の実施例に係る第２の特徴は、放熱体において、第１の表面及びそれに対向する第２の表面を有するシリコン基板と、シリコン基板の第１の表面上に配設された絶縁膜と、絶縁膜上の互いに異なる領域に配設され、第１のパッド電極及びこの第１のパッド電極に電気的に接続された第２のパッド電極を構成する第１の金属層と、シリコン基板の第２の表面上に配設された接合するための第２の金属層とを備える。   A second feature of the embodiment of the present invention is that, in the heat radiator, a silicon substrate having a first surface and a second surface opposite to the first surface, and an insulating film disposed on the first surface of the silicon substrate. A first metal layer constituting a first pad electrode and a second pad electrode electrically connected to the first pad electrode, disposed in different regions on the insulating film, and a silicon substrate And a second metal layer for bonding disposed on the second surface.

本発明によれば、複数のスイッチング素子間の絶縁性を確保しつつ、複数のスイッチング素子の放熱性を十分に確保することができる半導体装置並びにそれに使用される放熱体を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can fully ensure the heat dissipation of a some switching element, and the heat radiator used for it can be provided, ensuring the insulation between several switching elements.

本発明の実施例１に係る半導体装置の要部拡大断面図である。It is a principal part expanded sectional view of the semiconductor device which concerns on Example 1 of this invention. 図１に示す半導体装置の封止体の一部分を除いた平面図である。FIG. 2 is a plan view excluding a part of the sealing body of the semiconductor device shown in FIG. 1. 実施例１に係る半導体装置の放熱体の拡大断面図である。3 is an enlarged cross-sectional view of a heat radiator of a semiconductor device according to Example 1. FIG. 図３に示す放熱体の拡大平面図である。FIG. 4 is an enlarged plan view of the heat radiating body shown in FIG. 3. 実施例１に係る半導体装置の回路構成図である。1 is a circuit configuration diagram of a semiconductor device according to Example 1. FIG. 実施例１の変形例に係る半導体装置の要部拡大断面図である。FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification example of Example 1. 本発明の実施例２に係る半導体装置の回路構成図である。It is a circuit block diagram of the semiconductor device which concerns on Example 2 of this invention. 実施例２に係る半導体装置の封止体の一部分を除いた平面図である。FIG. 6 is a plan view of a semiconductor device according to Example 2 with a part of a sealing body removed. 図８に示す放熱体の拡大平面図である。It is an enlarged plan view of the heat radiator shown in FIG. 本発明の実施例３に係る半導体装置の回路構成図である。It is a circuit block diagram of the semiconductor device which concerns on Example 3 of this invention. 実施例３に係る半導体装置の封止体の一部分を除いた平面図である。FIG. 10 is a plan view of a semiconductor device according to Example 3 with a part of a sealing body removed.

次に、図面を参照して、本発明の実施例を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、現実のものとは異なる。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれている場合がある。   Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

また、以下に示す実施例はこの発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は各構成部品の配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。   Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention specifies the arrangement of each component as follows. It is not what you do. The technical idea of the present invention can be variously modified within the scope of the claims.

（実施例１）
本発明の実施例１は、ハーフブリッジ回路を構築する２つのスイッチング素子が１つの封止体により封止された半導体装置を説明するものである。 Example 1
Embodiment 1 of the present invention describes a semiconductor device in which two switching elements that construct a half-bridge circuit are sealed with one sealing body.

［半導体装置の回路構成］
図５に示すように、実施例１に係る半導体装置は、第１のスイッチング素子ＳＷ１と第２のスイッチング素子ＳＷ２とを備えている。第１のスイッチング素子ＳＷ１及び第２のスイッチング素子ＳＷ２はハーフブリッジ回路を構築するスイッチング素子である。第１のスイッチング素子ＳＷ１、第２のスイッチング素子ＳＷ２のそれぞれには実施例１においてパワーＭＯＳＦＥＴが使用されている。なお、パワーＭＯＳＦＥＴに必ずしも限定されるものではなく、第１のスイッチング素子ＳＷ１及び第２のスイッチング素子ＳＷ２にはＩＧＢＴを使用することができる。 [Circuit Configuration of Semiconductor Device]
As shown in FIG. 5, the semiconductor device according to the first embodiment includes a first switching element SW1 and a second switching element SW2. The first switching element SW1 and the second switching element SW2 are switching elements that construct a half-bridge circuit. In each of the first switching element SW1 and the second switching element SW2, a power MOSFET is used in the first embodiment. In addition, it is not necessarily limited to power MOSFET, IGBT can be used for 1st switching element SW1 and 2nd switching element SW2.

第１のスイッチング素子ＳＷ１は、第１の主電極（例えばソース電極）、第２の主電極（例えばドレイン電極）及び第１の制御電極（例えばゲート電極）を有する。同様に、第２のスイッチング素子ＳＷ２は、第３の主電極（例えばソース電極）、第４の主電極（例えばドレイン電極）及び第２の制御電極（例えばゲート電極）を有する。   The first switching element SW1 includes a first main electrode (for example, a source electrode), a second main electrode (for example, a drain electrode), and a first control electrode (for example, a gate electrode). Similarly, the second switching element SW2 includes a third main electrode (for example, a source electrode), a fourth main electrode (for example, a drain electrode), and a second control electrode (for example, a gate electrode).

第１のスイッチング素子ＳＷ１の第１の制御電極は第１の入力端子ＩＮ１に接続され、第１の主電極は、第２のスイッチング素子ＳＷ２の第４の主電極に接続されるとともに出力端子ＯＵＴに接続され、第２の主電極は電源端子（ドレイン電源）Ｐ１に接続される。第２のスイッチング素子ＳＷ２の第２の制御電極は第２の入力端子ＩＮ２に接続され、第３の主電極は第２の電源端子（ソース電源）Ｐ２に接続される。   The first control electrode of the first switching element SW1 is connected to the first input terminal IN1, the first main electrode is connected to the fourth main electrode of the second switching element SW2, and the output terminal OUT. The second main electrode is connected to a power supply terminal (drain power supply) P1. The second control electrode of the second switching element SW2 is connected to the second input terminal IN2, and the third main electrode is connected to the second power supply terminal (source power supply) P2.

［半導体装置のデバイス構造］
図１乃至図４に示すように、実施例１に係る半導体装置１は、第１の表面１１Ａに第１の主電極１１１を有し、第１の表面１１Ａに対向する第２の表面１１Ｂに第２の主電極１１２を有する第１のスイッチング素子（ＳＷ１）１１と、第３の表面１２Ａに第３の主電極１２１を有し、第３の表面１２Ａに対向する第４の表面１２Ｂに第４の主電極１２２を有する第２のスイッチング素子（ＳＷ２）１２と、第５の表面２Ａを有しこの第５の表面２Ａに第１の領域２０１及び第２の領域２０２を有するダイパッド２と、第６の表面５Ａ及びそれに対向する第７の表面５Ｂを有し第６の表面５Ａに第３の領域５０１及び第４の領域５０２を有するシリコン基板５１、第３の領域５０１に配設された第１のパッド電極５３１、及び第４の領域５０２に配設され第１のパッド電極５３１に電気的に接続された第２のパッド電極５３２を有する放熱体５とを備えている。そして、半導体装置１は、ダイパッド２の第１の領域２０１において第５の表面２Ａに第２の主電極１１２を電気的に接続して第１のスイッチング素子１１を搭載し、第２の領域２０２において第５の表面２Ａにシリコン基板５１の第７の表面５Ａを向かい合わせて放熱体５を搭載し、放熱体５の第１のパッド電極５３１において第４の主電極１２２を電気的に接続して第２のスイッチング素子１２を搭載している。 [Device structure of semiconductor device]
As shown in FIGS. 1 to 4, the semiconductor device 1 according to the first embodiment has a first main electrode 111 on a first surface 11A, and a second surface 11B opposite to the first surface 11A. The first switching element (SW1) 11 having the second main electrode 112, the third main electrode 121 on the third surface 12A, and the fourth surface 12B opposite to the third surface 12A A second switching element (SW2) 12 having four main electrodes 122; a die pad 2 having a fifth surface 2A and having a first region 201 and a second region 202 on the fifth surface 2A; A silicon substrate 51 having a sixth surface 5A and a seventh surface 5B opposite to the sixth surface 5A and having a third region 501 and a fourth region 502 on the sixth surface 5A, and the third region 501 are disposed. First pad electrode 531 and fourth region 502 And a heat radiator 5 having a second pad electrode 532 which is electrically connected to the first pad electrode 531 is disposed. Then, the semiconductor device 1 mounts the first switching element 11 by electrically connecting the second main electrode 112 to the fifth surface 2A in the first region 201 of the die pad 2, and the second region 202. The heat sink 5 is mounted with the fifth surface 2A facing the seventh surface 5A of the silicon substrate 51, and the fourth main electrode 122 is electrically connected to the first pad electrode 531 of the heat sink 5. The second switching element 12 is mounted.

図２に示すように、ダイパッド２の一側面（図２中、下辺に沿った側面）の中央部にはリード２３が一体に接続されている。このリード２３の左側には、ダイパット２に離間され電気的に分離されたリード２１及び２２が配列されている。リード２３の右側には、ダイパッド２に離間され電気的に分離されたリード２４及び２５が配列されている。ダイパッド２と、それに搭載された第１のスイッチング素子１１、第２のスイッチング素子１２及び放熱体５と、リード２１−２５のインナー部分は封止体９によって気密に封止されている。この半導体装置１は、必ずしもこの端子数に限定されるものではないが、実施例１において５端子（５ピン）を有するモールド型パッケージにより構成されている。   As shown in FIG. 2, a lead 23 is integrally connected to a central portion of one side surface of the die pad 2 (a side surface along the lower side in FIG. 2). On the left side of the lead 23, leads 21 and 22 separated from the die pad 2 and electrically separated are arranged. On the right side of the lead 23, leads 24 and 25 separated from the die pad 2 and electrically separated are arranged. The die pad 2, the first switching element 11, the second switching element 12 and the radiator 5 mounted on the die pad 2, and the inner portions of the leads 21-25 are hermetically sealed by a sealing body 9. The semiconductor device 1 is not necessarily limited to the number of terminals, but is configured by a mold type package having 5 terminals (5 pins) in the first embodiment.

ダイパッド２は、第１のスイッチング素子１１及び第２のスイッチング素子１２を搭載するとともに、それらの動作によって発生する熱を放熱する放熱板としての機能を有する。ダイパッド２は、電気伝導性に優れ、かつ熱伝導性に優れた、例えばＣｕ、Ｃｕ合金、Ｆｅ−Ｎｉ合金等の板材により構成されている。ダイパッド２は、必ずしもこの数値に限定されるものではないが、図２中、縦方向の長辺の長さを例えば１６ｍｍ−１８ｍｍに設定し、横方向の短辺の長さを例えば１２ｍｍ−１６ｍｍに設定している。ダイパット２の第５の表面２Ａと対向する裏面２Ｂは封止体９から露出され、放熱効果が高められている。ダイパッド２の第５の表面５Ａから裏面５Ｂまでの厚さは例えば１．８ｍｍ−２．２ｍｍに設定されている。なお、ダイパッド２の裏面２Ｂは必ずしも露出される必要はなく、実施例１に係る半導体装置１はダイパット２の第５の表面２Ａ並びに裏面２Ｂを封止体９により被覆するフルモールドタイプであってもよい。   The die pad 2 mounts the first switching element 11 and the second switching element 12 and has a function as a heat radiating plate that radiates heat generated by their operation. The die pad 2 is made of a plate material such as Cu, Cu alloy, or Fe—Ni alloy that has excellent electrical conductivity and excellent thermal conductivity. The die pad 2 is not necessarily limited to this value, but in FIG. 2, the length of the long side in the vertical direction is set to 16 mm-18 mm, for example, and the length of the short side in the horizontal direction is set to 12 mm-16 mm, for example. Is set. The back surface 2B facing the fifth surface 2A of the die pad 2 is exposed from the sealing body 9, and the heat dissipation effect is enhanced. The thickness from the 5th surface 5A of the die pad 2 to the back surface 5B is set to 1.8 mm-2.2 mm, for example. The back surface 2B of the die pad 2 is not necessarily exposed, and the semiconductor device 1 according to the first embodiment is a full mold type in which the fifth surface 2A and the back surface 2B of the die pad 2 are covered with the sealing body 9. Also good.

リード２１−２５のアウター部分は封止体９からその外側に延伸されている。ここでは、特に限定されるものではないが、ピン挿入型の半導体装置１が構築されている。リード２１は第１の入力端子ＩＮ１として使用され、リード２２は第１のスイッチング素子１１及び第２のスイッチング素子１２に共通の出力端子ＯＵＴとして使用されている。リード２３は第１の電源端子Ｐ１として使用され、リード２３とダイパット２とは一体に形成されているので、ダイパッド２には第１の電源端子Ｐ１から供給される電圧が印加されるようになっている。リード２４は第２の電源端子Ｐ２として使用され、リード２５は第２の入力端子ＩＮ２として使用されている。リード２１−２５は、基本的にはダイパット２と同一リードフレームから切断若しくは成形されたものであり、ダイパッド２と同一材料により構成されている。リード２１−２５の厚さはダイパッド２の厚さよりも薄く例えば０．５ｍｍ−０．８ｍｍに設定されている。   The outer portion of the leads 21-25 extends from the sealing body 9 to the outside thereof. Here, although not particularly limited, a pin insertion type semiconductor device 1 is constructed. The lead 21 is used as the first input terminal IN1, and the lead 22 is used as the output terminal OUT common to the first switching element 11 and the second switching element 12. The lead 23 is used as the first power supply terminal P1, and since the lead 23 and the die pad 2 are formed integrally, the voltage supplied from the first power supply terminal P1 is applied to the die pad 2. ing. The lead 24 is used as the second power supply terminal P2, and the lead 25 is used as the second input terminal IN2. The leads 21-25 are basically cut or molded from the same lead frame as the die pad 2 and are made of the same material as the die pad 2. The lead 21-25 is thinner than the die pad 2, for example, 0.5 mm-0.8 mm.

第１のスイッチング素子１１は、第１の主面１１Ａ及び第２の主面１１Ｂを有する基板１１０と、第１の主面１１Ａ上に配設された第１の主電極１１１及び第１の制御電極１１３と、第２の主面１１Ｂに配設された第２の主電極１１２とを備えている。基板１１０は例えば単結晶シリコン基板であり、この単結晶シリコン基板に例えばソース領域、ドレイン領域及びゲート電極を有するパワーＭＯＳＦＥＴが構築されている。第１の主電極１１１及び第１の制御電極１１３には例えばＡｌ合金が使用されている。第２の主電極１１２には、導電性を有し、基板１１０とのオーミック性を有し、半田との濡れ性が良好な、例えばＮｉ、Ｔｉ−Ｎｉ等の金属や合金を使用することができる。第２の主電極１１２は、必ずしも単層膜に限定されるものではなく、例えばＮｉとＴｉとの積層膜であってもよい。   The first switching element 11 includes a substrate 110 having a first main surface 11A and a second main surface 11B, a first main electrode 111 disposed on the first main surface 11A, and a first control. An electrode 113 and a second main electrode 112 disposed on the second main surface 11B are provided. The substrate 110 is, for example, a single crystal silicon substrate, and a power MOSFET having, for example, a source region, a drain region, and a gate electrode is constructed on the single crystal silicon substrate. For example, an Al alloy is used for the first main electrode 111 and the first control electrode 113. For the second main electrode 112, it is possible to use a metal or an alloy such as Ni or Ti-Ni that has conductivity, has ohmic properties with the substrate 110, and has good wettability with solder. it can. The second main electrode 112 is not necessarily limited to a single layer film, and may be a laminated film of Ni and Ti, for example.

第２のスイッチング素子１２は、第１のスイッチング素子１１と同一構造であり、第３の主面１２Ａ及び第４の主面１２Ｂを有する基板１２０と、第３の主面１２Ａ上に配設された第３の主電極１２１及び第２の制御電極１２３と、第４の主面１２Ｂに配設された第４の主電極１２２とを備えている。基板１２０、第３の主電極１２１、第２の制御電極１２３、第４の主電極１２２のそれぞれは、第１のスイッチング素子１１の基板１１０、第１の主電極１１１、第１の制御電極１２３、第２の主電極１１２のそれぞれと同一材料により構成されている。第１のスイッチング素子１１、第２のスイッチング素子１２は、必ずしもこの数値に限定されるものではないが、図２中、例えば縦方向の長さを３．０ｍｍ−４．０ｍｍ、横方向の長さを３．０ｍｍ−４．５ｍｍ、厚さを０．２ｍｍ−０．４ｍｍに設定している。   The second switching element 12 has the same structure as the first switching element 11, and is disposed on the substrate 120 having the third main surface 12A and the fourth main surface 12B, and the third main surface 12A. The third main electrode 121 and the second control electrode 123, and the fourth main electrode 122 disposed on the fourth main surface 12B are provided. The substrate 120, the third main electrode 121, the second control electrode 123, and the fourth main electrode 122 are respectively the substrate 110, the first main electrode 111, and the first control electrode 123 of the first switching element 11. The second main electrode 112 is made of the same material. The first switching element 11 and the second switching element 12 are not necessarily limited to these values, but in FIG. 2, for example, the length in the vertical direction is 3.0 mm to 4.0 mm, and the length in the horizontal direction. The thickness is set to 3.0 mm-4.5 mm, and the thickness is set to 0.2 mm-0.4 mm.

放熱体５は、特に図３及び図４に詳細に示すように、第２のスイッチング素子１２を搭載し、この第２のスイッチング素子１２をダイパッド２の第５の主面２Ａ上に搭載しつつ、第２のスイッチング素子１２の動作によって発生する熱をダイパッド２側に放熱する機能を有する。従って、放熱体５は、その厚さ方向において熱伝導性に優れ、絶縁体又は高抵抗体としての機能も備えている。   As shown in detail in FIG. 3 and FIG. 4 in particular, the radiator 5 has the second switching element 12 mounted thereon, and the second switching element 12 is mounted on the fifth main surface 2A of the die pad 2. The function of radiating the heat generated by the operation of the second switching element 12 to the die pad 2 side is provided. Therefore, the heat radiator 5 is excellent in thermal conductivity in the thickness direction and also has a function as an insulator or a high resistance body.

放熱体５は、第６の表面（図３中、上側表面）５Ａ及び第７の表面（図３中、下側裏面）５Ｂを有するシリコン基板５１と、シリコン基板５１の第６の表面５Ａ上に配設された絶縁膜５２と、絶縁膜５２上の互いに異なる第３の領域５０１及び第４の領域５０２に配設され、第１のパッド電極５３１及びこの第１のパッド電極５３１に電気的に接続された第２のパッド電極５３２を構成する第１の金属層５３と、シリコン基板５１の第７の表面５Ｂ上に配設された接合するための第２の金属層５５とを備える。更に、放熱体５は、第６の表面５Ａ側において、第３の領域５０１及び第４の領域５０２部分が開口され、それ以外の絶縁膜５２上及び第１の金属層５３上に配設された保護膜５４を備えている。   The radiator 5 includes a silicon substrate 51 having a sixth surface (upper surface in FIG. 3) 5A and a seventh surface (lower back surface in FIG. 3) 5B, and on the sixth surface 5A of the silicon substrate 51. And the third region 501 and the fourth region 502 which are different from each other on the insulating film 52, and are electrically connected to the first pad electrode 531 and the first pad electrode 531. The first metal layer 53 constituting the second pad electrode 532 connected to the first metal layer 53 and the second metal layer 55 for bonding disposed on the seventh surface 5B of the silicon substrate 51 are provided. Further, the heat dissipating body 5 is disposed on the insulating film 52 and the first metal layer 53 other than the third region 501 and the fourth region 502 at the sixth surface 5A side. A protective film 54 is provided.

シリコン基板５１は、放熱体５のベース基材であり、ポリイミド樹脂等の樹脂、セラミックス基板等の絶縁基板のそれぞれに比べて小さな熱伝導率を有し、熱伝導性に優れている。また、シリコン基板５１は第１のスイッチング素子１１の基板１１０や第２のスイッチング素子１２の基板１２０と同一材料であり、安価に入手することができ、半導体製造プロセスを利用して放熱体５を容易に製作することができる。シリコン基板５１は、電気伝導を目的として使用するものではなく、放熱機能を有する第２のスイッチング素子１２のベース基板、実装基板若しくは中間基板として使用されるので、単結晶に限らず、多結晶や非晶質であってもよい。また、シリコン基板５１に代えてそれと同等の機能並びに特性を有する炭化シリコン（ＳｉＣ）等の化合物半導体を使用することができる。シリコン基板５１は、第２のスイッチング素子１２を搭載し（第３の領域５０１）、かつ第２のスイッチング素子１２と第１のスイッチング素子１１との接続領域（第４の領域５０２）を必要とするので、第２のスイッチング素子１２に比べて一回り平面サイズを大きく設定している。例えばシリコン基板５１は、図２中、縦方向の長さを例えば６．０ｍｍ−８．５ｍｍ、横方向の長さを例えば４．０ｍｍ−６．５ｍｍ、厚さを例えば０．２ｍｍ−０．６ｍｍに設定している。   The silicon substrate 51 is a base material of the radiator 5 and has a small thermal conductivity as compared with each of a resin such as a polyimide resin and an insulating substrate such as a ceramic substrate, and is excellent in thermal conductivity. The silicon substrate 51 is made of the same material as the substrate 110 of the first switching element 11 and the substrate 120 of the second switching element 12 and can be obtained at a low cost. It can be easily manufactured. The silicon substrate 51 is not used for the purpose of electrical conduction, but is used as a base substrate, a mounting substrate, or an intermediate substrate of the second switching element 12 having a heat dissipation function. It may be amorphous. Further, instead of the silicon substrate 51, a compound semiconductor such as silicon carbide (SiC) having equivalent functions and characteristics can be used. The silicon substrate 51 mounts the second switching element 12 (third region 501) and requires a connection region (fourth region 502) between the second switching element 12 and the first switching element 11. Therefore, the one-dimensional plane size is set larger than that of the second switching element 12. For example, in FIG. 2, the silicon substrate 51 has a longitudinal length of, for example, 6.0 mm to 8.5 mm, a lateral length of, for example, 4.0 mm to 6.5 mm, and a thickness of, for example, 0.2 mm to 0.0 mm. It is set to 6 mm.

絶縁膜５２は、シリコン基板５１と第２のスイッチング素子１２の第４の主電極１２２との間の電気的な分離を行うことを目的として、ここでは第６の主面５Ａの全域に配設されている。絶縁膜５２は、樹脂やセラミックスに比べて小さな熱伝導率を有し、半導体製造プロセスにおいて簡易に形成することができる、シリコン酸化膜又はシリコン窒化膜により形成される。絶縁膜５２は、電気的な絶縁性を確保しつつ、熱伝導性を高めるために、例えば１．０μｍ−３．０μｍの比較的薄い膜厚により形成されている。なお、電気的な絶縁が必要なく、又耐圧を必要としない場合、絶縁膜５２は必ずしも必要なく、放熱体５をシリコン基板５１の抵抗値が支配的となる高抵抗体として機能させてもよい。   The insulating film 52 is disposed over the entire area of the sixth main surface 5A here for the purpose of electrical isolation between the silicon substrate 51 and the fourth main electrode 122 of the second switching element 12. Has been. The insulating film 52 is formed of a silicon oxide film or a silicon nitride film that has a smaller thermal conductivity than a resin or a ceramic and can be easily formed in a semiconductor manufacturing process. The insulating film 52 is formed with a relatively thin film thickness of, for example, 1.0 μm to 3.0 μm in order to increase the thermal conductivity while ensuring electrical insulation. In the case where electrical insulation is not required and the withstand voltage is not required, the insulating film 52 is not necessarily required, and the radiator 5 may function as a high-resistance body in which the resistance value of the silicon substrate 51 is dominant. .

第１の金属層５３は、第２のスイッチング素子１２の第２の主電極１２２に電気的に接続するための第１のパッド電極５３１と、この第１のパッド電極５３１をシリコン基板５１の第６の表面上において第３の領域５０１から第４の領域５０２まで引き出し第４の領域５０２において第１のスイッチング素子１１の第１の主電極１１１に接続するための第２のパッド電極５３２とを構成する。第１の金属層５３には、例えば第２のスイッチング素子１２の第４の主電極１２２との間の半田を使用した接合性を高めつつ、熱伝導性を高めるためにＮｉが使用される。Ｎｉは例えばめっき法又はスパッタリング法により成膜され、Ｎｉの膜厚は例えば０．５μｍ−１．０μｍに設定される。   The first metal layer 53 includes a first pad electrode 531 for electrically connecting to the second main electrode 122 of the second switching element 12, and the first pad electrode 531 connected to the second main electrode 122 of the silicon substrate 51. A second pad electrode 532 for leading out from the third region 501 to the fourth region 502 on the surface of 6 and connecting to the first main electrode 111 of the first switching element 11 in the fourth region 502. Constitute. For the first metal layer 53, for example, Ni is used in order to improve thermal conductivity while improving the bonding property using the solder with the fourth main electrode 122 of the second switching element 12. Ni is formed by, for example, a plating method or a sputtering method, and the thickness of Ni is set to, for example, 0.5 μm to 1.0 μm.

保護膜５４は、第１のパッド電極５３１、第２のパッド電極５３２のそれぞれの表面の保護、他の部分との電気的な分離並びに半田の流出を防止するダムを目的として構成されている。保護膜６には例えばポリイミド樹脂、ソルダーレジスト等を使用することができる。   The protective film 54 is configured for the purpose of protecting the surfaces of the first pad electrode 531 and the second pad electrode 532, electrically separating them from other parts, and preventing the solder from flowing out. For the protective film 6, for example, a polyimide resin, a solder resist, or the like can be used.

実施例１に係る半導体装置１は、これらの構成を備え、ダイパッド２の第１の領域２０１において第５の表面２Ａ上に第１の半田３１を介して第１のスイッチング素子１１の第２の主電極１１２を接合するとともに電気的に接続している。ダイパッド２の第２の領域２０２において第５の表面２Ａ上には第２の半田３２を介して放熱体５の第２の金属層５５が接合されるとともに、ダイパッド２に放熱体５が熱的に結合される。この放熱体５の第１のパッド電極５３１には、第２のスイッチング素子１２の第４の主電極１２２が第３の半田３３を介して接合されるとともに電気的に接続される。第１の半田３１−第３の半田３３には電気伝導性に優れかつ熱伝導性に優れた例えばＰｂ−Ｓｎ半田を実用的に使用するこができる。   The semiconductor device 1 according to the first embodiment includes these configurations, and the second switching element 11 of the first switching element 11 is provided on the fifth surface 2A via the first solder 31 in the first region 201 of the die pad 2. The main electrode 112 is joined and electrically connected. In the second region 202 of the die pad 2, the second metal layer 55 of the radiator 5 is joined to the fifth surface 2 </ b> A via the second solder 32, and the radiator 5 is thermally attached to the die pad 2. Combined with The fourth main electrode 122 of the second switching element 12 is joined to and electrically connected to the first pad electrode 531 of the heat radiating body 5 via the third solder 33. As the first solder 31 to the third solder 33, for example, Pb—Sn solder having excellent electrical conductivity and excellent thermal conductivity can be used practically.

第１のスイッチング素子１１の第１の制御電極１１３は配線７１を通してリード２１に電気的に接続され、第１の主電極１１１は配線７２を通してリード２２に接続される。配線７１、７２には例えばＣｕ、Ｃｕ合金、Ｆｅ−Ｎｉ合金等の導電性を有する細長い板材により構成されたストラップリードが使用されている。配線７１と第１の制御電極１１３、リード２１のそれぞれとの間は第４の半田３５により接合されるとともに電気的に接続される。配線７２と第１の主電極１１１、リード２２のそれぞれとの間は同様に第４の半田３５により接合されるとともに電気的に接続される。第４の半田３５には例えばＰｂ−Ｓｎ半田を実用的に使用することができる。   The first control electrode 113 of the first switching element 11 is electrically connected to the lead 21 through the wiring 71, and the first main electrode 111 is connected to the lead 22 through the wiring 72. For the wirings 71 and 72, for example, strap leads made of an elongated plate material having conductivity such as Cu, Cu alloy, Fe-Ni alloy or the like are used. The wiring 71 and each of the first control electrode 113 and the lead 21 are joined and electrically connected by the fourth solder 35. The wiring 72 and each of the first main electrode 111 and the lead 22 are similarly joined and electrically connected by the fourth solder 35. For example, Pb—Sn solder can be used practically for the fourth solder 35.

第２のスイッチング素子１２の第２の制御電極１２３は配線７４を通してリード２５に電気的に接続され、第３の主電極１２１は配線７３を通してリード２４に接続される。配線７３、７４は配線７１、７２と同様にストラップリードにより構成されている。また、配線７３、７４の接続にも同様に第４の半田３５が使用されている。   The second control electrode 123 of the second switching element 12 is electrically connected to the lead 25 through the wiring 74, and the third main electrode 121 is connected to the lead 24 through the wiring 73. Similar to the wirings 71 and 72, the wirings 73 and 74 are configured by strap leads. Similarly, the fourth solder 35 is used to connect the wirings 73 and 74.

そして、放熱体５の第２のパッド電極５３２は配線７５を通してリード２２に電気的に接続される。配線７５は配線７１等と同様にストラップリードにより構成され、この配線７５の接続には第４の半田３５が使用される。また、第１の主電極１１１は、リード２２を介さずに第２のパッド電極５３２に直接配線してもよい。   Then, the second pad electrode 532 of the radiator 5 is electrically connected to the lead 22 through the wiring 75. The wiring 75 is constituted by a strap lead like the wiring 71 and the like, and the fourth solder 35 is used to connect the wiring 75. Further, the first main electrode 111 may be directly wired to the second pad electrode 532 without using the lead 22.

［半導体装置の特徴］
このように構成される実施例１に係る半導体装置１においては、シリコン基板５１をベース基材とする放熱体５を備えたので、複数の第１のスイッチング素子１１と第２のスイッチング素子１２との間の絶縁性（若しくは高抵抗性）を確保しつつ、熱伝導性に優れたシリコン基板５１を利用し、複数の第１のスイッチング素子１１及び第２のスイッチング素子１２の放熱性を十分に確保することができる。従って、第１のスイッチング素子１１、第２のスイッチング素子１２のそれぞれの特性の熱によるばらつきを抑制することができるので、ハーフブリッジ回路に適した特性を実現することができる。 [Features of semiconductor devices]
Since the semiconductor device 1 according to the first embodiment configured as described above includes the radiator 5 having the silicon substrate 51 as a base material, a plurality of first switching elements 11 and second switching elements 12 are provided. The silicon substrate 51 having excellent thermal conductivity is secured while ensuring the insulating property (or high resistance) between the plurality of first switching elements 11 and the second switching elements 12 with sufficient heat dissipation. Can be secured. Therefore, variations in the characteristics of the first switching element 11 and the second switching element 12 due to heat can be suppressed, and characteristics suitable for a half-bridge circuit can be realized.

更に、実施例１に係る半導体装置１においては、放熱体５を備えたことにより、ダイパッド２の第１の領域２０１と第２の領域２０２との間を空間的に分割する必要はなく、双方の間を連結し、ダイパッド２のボリュームを増加することができるので、ダイパッド２を利用した放熱性をより一層向上することができる。   Further, in the semiconductor device 1 according to the first embodiment, since the heat dissipating body 5 is provided, it is not necessary to spatially divide the first region 201 and the second region 202 of the die pad 2. Since the volume of the die pad 2 can be increased, the heat dissipation using the die pad 2 can be further improved.

［変形例］
本発明の実施例１に係る変形例は、前述の半導体装置１において、放熱体５の構成を変えた例を説明するものである。変形例に係る半導体装置１は、基本的な構成は前述の実施例１に係る半導体装置１と同様であるが、図６に示すように、放熱体５の第２のパッド電極５３２上に第３の金属層５７が配設されている。配線７５、又はすべての配線７１−７５はボンディングワイヤにより構成されている。 [Modification]
The modification according to the first embodiment of the present invention describes an example in which the configuration of the radiator 5 is changed in the semiconductor device 1 described above. The basic configuration of the semiconductor device 1 according to the modification is the same as that of the semiconductor device 1 according to the first embodiment described above, but the second configuration is provided on the second pad electrode 532 of the radiator 5 as shown in FIG. Three metal layers 57 are provided. The wiring 75 or all of the wirings 71-75 are constituted by bonding wires.

このボンディングワイヤには例えばＡｌワイヤ、Ａｕワイヤ、Ｃｕワイヤ等が使用される。ボンディングワイヤはボンディング装置を用いて第２のパッド電極５３２、リード２２等に機械的にかつ電気的に接続される。   For example, an Al wire, an Au wire, a Cu wire or the like is used as the bonding wire. The bonding wire is mechanically and electrically connected to the second pad electrode 532, the lead 22, and the like using a bonding apparatus.

放熱体５の第２のパッド電極５３２上に配設された第３の金属層５７は配線７５とのボンダビリティを向上する機能を有する。この第３の金属層５７には例えばＡｌ膜、Ａｌ合金膜等を使用することができる。   The third metal layer 57 disposed on the second pad electrode 532 of the radiator 5 has a function of improving bondability with the wiring 75. For the third metal layer 57, for example, an Al film, an Al alloy film, or the like can be used.

このように構成される実施例１の変形例に係る半導体装置１においては、前述の実施例１に係る半導体装置１により得られる効果と同様の効果を奏することができる。   In the semiconductor device 1 according to the modification of the first embodiment configured as described above, the same effects as those obtained by the semiconductor device 1 according to the first embodiment can be obtained.

（実施例２）
本発明の実施例２は、前述の実施例１に係る半導体装置１において、スイッチング素子をＩＧＢＴに代えた例を説明するものである。 (Example 2)
Example 2 of the present invention describes an example in which the switching element is replaced with an IGBT in the semiconductor device 1 according to Example 1 described above.

［半導体装置の回路構成］
図７に示すように、実施例２に係る半導体装置１は、基本的には実施例１に係る半導体装置１と同様にハーフブリッジ回路を構築するが、第１のスイッチング素子ＳＷ１、第２のスイッチング素子ＳＷ２のそれぞれにＩＧＢＴを使用している。更に、第１のスイッチング素子ＳＷ１の主電極間にはこの第１のスイッチング素子ＳＷ１に電気的に並列に第１のダイオードＤ１が挿入されている。同様に、第２のスイッチング素子ＳＷ２の主電極間にはこの第２のスイッチング素子ＳＷ２に電気的に並列に第２のダイオードＤ２が挿入されている。第１のダイオードＤ１、第２のダイオードＤ２はいずれも例えば整流ダイオード（ＦＲＤ）である。 [Circuit Configuration of Semiconductor Device]
As shown in FIG. 7, the semiconductor device 1 according to the second embodiment basically constructs a half-bridge circuit in the same manner as the semiconductor device 1 according to the first embodiment. However, the first switching element SW1, the second An IGBT is used for each of the switching elements SW2. Further, a first diode D1 is inserted between the main electrodes of the first switching element SW1 in parallel with the first switching element SW1. Similarly, a second diode D2 is inserted between the main electrodes of the second switching element SW2 in parallel with the second switching element SW2. Both the first diode D1 and the second diode D2 are, for example, rectifier diodes (FRD).

［半導体装置のデバイス構造］
実施例２に係る半導体装置１は、図８に示すように、ダイパッド２の第１の領域２０１にＩＧＢＴにより構成された第１のスイッチング素子（ＳＷ）１１及び第１のダイオード（Ｄ１）１３を搭載し、第２の領域２０２に放熱体５を搭載している。第１のスイッチング素子１１、第１のダイオード１３、放熱体５のそれぞれの搭載方式は前述の実施例１に係る半導体装置１の第１のスイッチング素子１１の搭載方式と同様である。 [Device structure of semiconductor device]
As illustrated in FIG. 8, the semiconductor device 1 according to the second embodiment includes a first switching element (SW) 11 and a first diode (D 1) 13 formed of IGBT in the first region 201 of the die pad 2. It mounts and the heat radiator 5 is mounted in the second region 202. Each mounting method of the first switching element 11, the first diode 13, and the radiator 5 is the same as the mounting method of the first switching element 11 of the semiconductor device 1 according to the first embodiment.

放熱体５は、図８及び図９に示すように、シリコン基板５１の第６の表面５Ａ上の第３の領域５０１に第１のパッド電極５３１及び同一層でかつ同一導電性材料により構成された第３のパッド電極５３３を有し、第４の領域５０２に第２のパッド電極５３２を有する。第１のパッド電極５３１には第２のスイッチング素子１２が搭載され、第３のパッド電極５３３には第２のダイオード１４が搭載される。第２のスイッチング素子１２、第２のダイオード１４のそれぞれの搭載方式は前述の実施例１に係る半導体装置１の第２のスイッチング素子１２の搭載方式と同様である。   As shown in FIGS. 8 and 9, the heat dissipating body 5 is composed of the first pad electrode 531, the same layer, and the same conductive material in the third region 501 on the sixth surface 5 </ b> A of the silicon substrate 51. The third pad electrode 533 is provided, and the second pad electrode 532 is provided in the fourth region 502. The second switching element 12 is mounted on the first pad electrode 531, and the second diode 14 is mounted on the third pad electrode 533. Each mounting method of the second switching element 12 and the second diode 14 is the same as the mounting method of the second switching element 12 of the semiconductor device 1 according to the first embodiment.

第１のダイオード１３の一方の主電極（ここではアノード電極）はダイパッド２を通してリード２３に電気的に接続され、他方の主電極（ここではカソード電極）は配線７２を通してリード２２に電気的に接続される。第２のダイオード１４の一方の主電極（ここではアノード電極）は放熱体５の第３のパッド電極５３３、第２のパッド電極５３２、配線７５のそれぞれを通してリード２２に電気的に接続され、他端の主電極（ここではカソード電極）は配線７３を通してリード２４に電気的に接続される。配線７２、７５のそれぞれには、前述の実施例１及びその変形例に係る半導体装置１の配線７１等と同様にストラップリード又はボンディングワイヤが使用される。   One main electrode (here, the anode electrode) of the first diode 13 is electrically connected to the lead 23 through the die pad 2, and the other main electrode (here, the cathode electrode) is electrically connected to the lead 22 through the wiring 72. Is done. One main electrode (here, an anode electrode) of the second diode 14 is electrically connected to the lead 22 through each of the third pad electrode 533, the second pad electrode 532, and the wiring 75 of the radiator 5, and the other The main electrode at the end (here, the cathode electrode) is electrically connected to the lead 24 through the wiring 73. For each of the wirings 72 and 75, a strap lead or a bonding wire is used in the same manner as the wiring 71 and the like of the semiconductor device 1 according to the first embodiment and the modification thereof.

このように構成される実施例２に係る半導体装置１においては、前述の実施例１に係る半導体装置１により得られる効果と同様の効果を奏することができる。   In the semiconductor device 1 according to the second embodiment configured as described above, the same effects as those obtained by the semiconductor device 1 according to the first embodiment can be obtained.

（実施例３）
本発明の実施例３は、前述の実施例２に係る半導体装置１において、フルブリッジ回路の構築に好適な例を説明するものである。 (Example 3)
Example 3 of the present invention describes an example suitable for construction of a full bridge circuit in the semiconductor device 1 according to Example 2 described above.

［半導体装置の回路構成］
図１０に示すように、実施例３に係る半導体装置１は、前述の図７に示す実施例２に係る半導体装置１のハーフブリッジ回路と同様の第１のハーフブリッジ回路ＨＢＣ１及び第２のハーフブリッジ回路ＨＢＣ２の２個を備えている。つまり、実施例３に係る半導体装置１においてはフルブリッジ回路を構築することができる。 [Circuit Configuration of Semiconductor Device]
As shown in FIG. 10, the semiconductor device 1 according to the third embodiment includes a first half bridge circuit HBC1 and a second half bridge similar to the half bridge circuit of the semiconductor device 1 according to the second embodiment shown in FIG. Two bridge circuits HBC2 are provided. That is, a full bridge circuit can be constructed in the semiconductor device 1 according to the third embodiment.

［半導体装置のデバイス構造］
図１１に示すように、実施例３に係る半導体装置１は、第１のハーフブリッジ回路ＨＢＣ１を構築する前述の図８に示すダイパッド２、第１のスイッチング素子１１、放熱体５及び第２のスイッチング素子１２と、第２のハーフブリッジ回路ＨＢＣ２を構築する同様に図８に示すダイパッド２、第１のスイッチング素子１１、放熱体５及び第２のスイッチング素子１２とを１つの封止体９により封止したものである。実施例３において、半導体装置１は、２組のリード２１−２５を配列しており、合計１０端子を備えている。 [Device structure of semiconductor device]
As illustrated in FIG. 11, the semiconductor device 1 according to the third embodiment includes the die pad 2, the first switching element 11, the radiator 5, and the second second structure illustrated in FIG. 8 that configure the first half-bridge circuit HBC <b> 1. Similarly, the die pad 2, the first switching element 11, the heat radiating body 5, and the second switching element 12 shown in FIG. 8 are constructed by one sealing body 9 to construct the switching element 12 and the second half-bridge circuit HBC 2. It is sealed. In the third embodiment, the semiconductor device 1 has two sets of leads 21-25 arranged, and has a total of 10 terminals.

このように構成される実施例３に係る半導体装置１においては、前述の実施例１に係る半導体装置１により得られる効果と同様の効果を奏することができる。   In the semiconductor device 1 according to the third embodiment configured as described above, the same effects as those obtained by the semiconductor device 1 according to the first embodiment can be obtained.

（その他の実施例）
上記のように、本発明を実施例１乃至実施例３によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施の形態、実施例及び運用技術に適用することができる。 (Other examples)
As mentioned above, although this invention was described by Example 1 thru | or Example 3, the description and drawing which make a part of this indication do not limit this invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies.

本発明は、複数のスイッチング素子間の絶縁性を確保しつつ、複数のスイッチング素子の放熱性を十分に確保することができる半導体装置並びにそれに使用される放熱体に広く適用可能である。   The present invention can be widely applied to a semiconductor device capable of sufficiently ensuring the heat dissipation of the plurality of switching elements while ensuring the insulation between the plurality of switching elements, and the heat radiator used for the semiconductor device.

１…半導体装置
１１、ＳＷ１…第１のスイッチング素子
１１１…第１の主電極
１１２…第２の主電極
１１３…第１の制御電極
１２、ＳＷ２…第２のスイッチング素子
１２１…第３の主電極
１２２…第４の主電極
１２３…第２の制御電極
２…ダイパッド
２１−２５…リード
５…放熱体
５１…シリコン基板
５２…絶縁膜
５３…第１の金属層
５３１…第１のパッド電極
５３２…第２のパッド電極
５３３…第３のパッド電極
５４…保護膜
５５…第１の金属層
９…封止体
Ｄ１…第１のダイオード
Ｄ２…第２のダイオード
ＨＢＣ１…第１のハーフブリッジ回路
ＨＢＣ２…第２のハーフブリッジ回路 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 11, SW1 ... 1st switching element 111 ... 1st main electrode 112 ... 2nd main electrode 113 ... 1st control electrode 12, SW2 ... 2nd switching element 121 ... 3rd main electrode 122 ... Fourth main electrode 123 ... Second control electrode 2 ... Die pad 21-25 ... Lead 5 ... Radiator 51 ... Silicon substrate 52 ... Insulating film 53 ... First metal layer 531 ... First pad electrode 532 ... 2nd pad electrode 533 ... 3rd pad electrode 54 ... Protective film 55 ... 1st metal layer 9 ... Sealing body D1 ... 1st diode D2 ... 2nd diode HBC1 ... 1st half-bridge circuit HBC2 ... Second half-bridge circuit

Claims (5)

第１の表面に第１の主電極を有し、前記第１の表面に対向する第２の表面に第２の主電極を有する第１のスイッチング素子と、
第３の表面に第３の主電極を有し、前記第３の表面に対向する第４の表面に第４の主電極を有する第２のスイッチング素子と、
第５の表面を有しこの第５の表面に第１の領域及び第２の領域を有するダイパッドと、
第６の表面及びそれに対向する第７の表面を有し前記第６の表面に第３の領域及び第４の領域を有するシリコン基板、前記第３の領域に配設された第１のパッド電極、及び前記第４の領域に配設され前記第１のパッド電極に電気的に接続された第２のパッド電極を有する放熱体と、を備え、
前記ダイパッドの前記第１の領域において前記第５の表面に前記第２の主電極を電気的に接続して前記第１のスイッチング素子を搭載し、
前記第２の領域において前記第５の表面に前記シリコン基板の前記第７の表面を向かい合わせて前記放熱体を搭載し、
前記シリコン基板の前記第１のパッド電極において前記第４の主電極を電気的に接続して前記第２のスイッチング素子を搭載したことを特徴とする半導体装置。 A first switching element having a first main electrode on a first surface and a second main electrode on a second surface opposite to the first surface;
A second switching element having a third main electrode on a third surface and a fourth main electrode on a fourth surface opposite to the third surface;
A die pad having a fifth surface and having a first region and a second region on the fifth surface;
A silicon substrate having a sixth surface and a seventh surface opposite to the sixth surface and having a third region and a fourth region on the sixth surface, and a first pad electrode disposed on the third region And a radiator having a second pad electrode disposed in the fourth region and electrically connected to the first pad electrode,
Mounting the first switching element by electrically connecting the second main electrode to the fifth surface in the first region of the die pad;
In the second region, the heat sink is mounted with the fifth surface facing the seventh surface of the silicon substrate,
A semiconductor device, wherein the second switching element is mounted by electrically connecting the fourth main electrode to the first pad electrode of the silicon substrate. 前記放熱体は、
前記シリコン基板と、
前記シリコン基板の前記第６の表面上において前記第３の領域及び前記第４の領域に配設された絶縁膜と、
前記第３の領域から前記第４の領域に渡って前記絶縁膜上に配設され、前記第１のパッド電極、又は前記第１のパッド電極及び前記第２のパッド電極を構成する第１の金属層と、
前記シリコン基板の前記第７の表面上に配設され、前記ダイパッドの前記第５の表面に接合するための第２の金属層と、
を更に備えたことを特徴とする請求項１に記載の半導体装置。 The radiator is
The silicon substrate;
An insulating film disposed in the third region and the fourth region on the sixth surface of the silicon substrate;
The first pad electrode or the first pad electrode and the second pad electrode are disposed on the insulating film from the third region to the fourth region and constitute the first pad electrode or the first pad electrode and the second pad electrode. A metal layer;
A second metal layer disposed on the seventh surface of the silicon substrate and bonded to the fifth surface of the die pad;
The semiconductor device according to claim 1, further comprising: 前記ダイパッドの前記第１の領域において前記第５の表面に前記第１のスイッチング素子の前記第２の主電極を接合する第１の半田と、
前記放熱体の前記第１のパッド電極に前記第２のスイッチング素子の前記第４の主電極を接合する第２の半田と、
前記放熱体の前記第２のパッド電極に電気的に接続される配線と、
を更に備えたことを特徴とする請求項２に記載の半導体装置。 First solder for joining the second main electrode of the first switching element to the fifth surface in the first region of the die pad;
A second solder for joining the fourth main electrode of the second switching element to the first pad electrode of the radiator;
A wiring electrically connected to the second pad electrode of the radiator;
The semiconductor device according to claim 2, further comprising: 前記第１のスイッチング素子の前記第１の主面に配設された第１の制御電極と、
前記第２のスイッチング素子の前記第３の主面に配設された第２の制御電極と、を備え、
前記第１のスイッチング素子の前記第１の制御電極は第１の入力端子に接続され、前記第２の主電極は第１の電源端子に接続され、
前記第２のスイッチング素子の前記第２の制御電極は第２の入力端子に接続され、前記第３の主電極は第２の電源端子に接続され、
前記第１のスイッチング素子の前記第１の主電極は前記放熱体の前記第１のパッド電極及び前記第２のパッド電極を通して前記第２のスイッチング素子の第４の主電極に接続されることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。 A first control electrode disposed on the first main surface of the first switching element;
A second control electrode disposed on the third main surface of the second switching element,
The first control electrode of the first switching element is connected to a first input terminal, the second main electrode is connected to a first power supply terminal,
The second control electrode of the second switching element is connected to a second input terminal, and the third main electrode is connected to a second power supply terminal;
The first main electrode of the first switching element is connected to the fourth main electrode of the second switching element through the first pad electrode and the second pad electrode of the radiator. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 第１の表面及びそれに対向する第２の表面を有するシリコン基板と、
前記シリコン基板の前記第１の表面上に配設された絶縁膜と、
前記絶縁膜上の互いに異なる領域に配設され、第１のパッド電極及びこの第１のパッド電極に電気的に接続された第２のパッド電極を構成する第１の金属層と、
前記シリコン基板の前記第２の表面上に配設された接合するための第２の金属層と、
を備えたことを特徴とする放熱体。 A silicon substrate having a first surface and a second surface opposite thereto;
An insulating film disposed on the first surface of the silicon substrate;
A first metal layer constituting a first pad electrode and a second pad electrode electrically connected to the first pad electrode, disposed in different regions on the insulating film;
A second metal layer for bonding disposed on the second surface of the silicon substrate;
A heat radiator characterized by comprising:
JP2009100051A 2009-04-16 2009-04-16 Semiconductor device and radiating body Pending JP2010251556A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014490A (en) * 2016-07-08 2018-01-25 ローム株式会社 Semiconductor device manufacturing method and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018014490A (en) * 2016-07-08 2018-01-25 ローム株式会社 Semiconductor device manufacturing method and semiconductor device

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