JP2010245678A - Frequency comparison circuit, frequency control circuit, method for controlling frequency comparison circuit, and radio transmitter-receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the safety and convenience of a radio transmitter-receiver by reducing the power consumption of the radio transmitter-receiver. <P>SOLUTION: This frequency comparison circuit includes: an in-phase baseband signal extracting means for mixing an input signal with a local signal, and extracting an in-phase baseband signal having a differential frequency being a difference between the frequency of the input signal and the frequency of the local signal from the obtained signal; an orthogonal baseband signal extracting means for mixing the input signal with an orthogonal local signal being a signal obtained by shifting the phase of the local signal only by a prescribed value, and extracting an orthogonal baseband signal having the differential frequency from the obtained frequency; a polarity determining means for determining the polarity of the differential frequency from a polarity relation between the in-phase baseband signal and the orthogonal baseband signal; and an absolute value acquiring means for acquiring an absolute value of the differential frequency from a period of the in-phase baseband signal or the orthogonal baseband signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency comparison circuit, a frequency control circuit, a method for controlling a frequency comparison circuit, and a radio transmission / reception apparatus using them, which are used by a radio transmission / reception apparatus to control the frequency of a local signal.

  In a wireless communication system, a synchronous detection method is well known in which a carrier wave is reproduced from a received modulated wave signal including phase information, and a demodulation process is performed to extract a received baseband signal superimposed on the received modulated wave signal using the reproduced carrier wave. It has been.

  However, since a carrier wave recovery circuit is required, the circuit scale becomes large in the synchronous detection method. Therefore, a quasi-synchronous detection method that uses a local signal having almost the same frequency but not phase-synchronized with a carrier wave is used in a mobile station of a mobile phone system that is required to be downsized.

  In general, a mobile station of a mobile phone system causes the frequency of a local signal in the mobile station and the frequency of a clock signal as a reference to follow the frequency of a signal (downlink signal) received from a base station. The mobile station performs signal processing on the downlink signal based on the tracked reference clock and generates a signal (uplink signal) to be transmitted to the base station.

  By allowing the mobile station to follow the frequency of the reference clock in the mobile station to the carrier frequency of the received modulated wave signal from the base station, the data transmission / reception timing deviation between the base station and the mobile station can be corrected, resulting in signal demodulation. The effect of speeding up the processing and improving the signal transmission throughput can be obtained.

  In general, the reference clock generation circuit built into the base station is more stable against temperature change and vibration than the reference clock generation circuit built into the mobile station. Therefore, the frequency stability of the entire system is improved by making the frequency of the reference clock of the mobile station follow the frequency of the received signal generated based on the reference clock of the base station.

  As an example of an apparatus for controlling the frequency of such a reference clock, Patent Document 1 discloses a CDMA (Code Division Multiple Access) mobile phone apparatus.

  A CDMA mobile phone device that performs RAKE reception described in Patent Document 1 controls a reference clock by performing digital arithmetic processing using a digital baseband signal obtained by converting an analog baseband signal. In the digital arithmetic processing, the CDMA mobile phone device calculates the frequency offset amount for each finger based on the pilot data output from each finger, and based on the value obtained by weighting and adding the frequency offset amount, Correct the frequency. As a result, the frequency offset amount is updated. By repeating this digital arithmetic processing repeatedly, the frequency of the reference clock in the mobile phone device changes following the frequency of the reference clock from the base station superimposed on the received signal.

  FIG. 10 is a block diagram showing a configuration of a direct conversion WCDMA mobile phone device as another example of a device using the quasi-synchronous detection method.

  Similar to the CDMA mobile phone disclosed in Patent Document 1, this WCDMA mobile phone controls the reference clock by performing digital arithmetic processing.

  Patent Document 2 discloses an automatic frequency control device that performs automatic frequency control with a configuration different from that of Patent Document 1.

  This automatic frequency control device generates an I signal by mixing a local signal and an input signal, generates a Q signal by mixing a signal obtained by shifting the phase of the local signal by π / 2 and an input signal, The sign of the detected frequency error is determined by performing a cross product operation on the output obtained by multiplying the Q signal by four. In addition, the automatic frequency control device obtains the absolute value of the detected frequency error by performing a cross product operation on the output obtained by multiplying the I signal and the Q signal by 2 using a cross product device. The automatic frequency control device obtains a detection frequency error from these signs and absolute values, and causes the frequency of the local oscillator in the automatic frequency control device to follow the frequency of the input signal. The processing for frequency control is also digital arithmetic processing, similar to the processing of Patent Document 1.

JP 2001-157263 A JP 7-115477 A

  In the devices described in Patent Documents 1 and 2 and FIG. 10 described above, the amount of computation of digital computation processing for controlling the frequency of the reference clock is enormous. For this reason, the digital arithmetic circuit that performs the digital arithmetic processing has become large-scale, which increases the power consumption of the mobile phone device.

  Further, in the OFDM (Orthogonal Frequency Division Multiplex) system, which is expected to be developed in the future, the frequency is detected by performing fast Fourier transform on the received signal, and a further increase in the amount of digital computation is expected. As a result, there is a concern that the power consumption of these devices further increases.

  Furthermore, as a trend of the configuration of the wireless transmission / reception apparatus, a configuration in which a radio unit mainly handling high-frequency analog signals and a baseband unit specialized for digital computation are in the mainstream like the DigRF standard known as a de facto standard. ing.

  In this configuration, the wireless unit and the baseband unit perform high-speed digital data communication via the interface, but power is also consumed in this interface. Therefore, in order to reduce power consumption, it is desirable that the interface can be stopped except during transmission / reception data communication, and this can be realized by closing the function of frequency tracking control in the radio unit.

  When the power consumption increases, the circuit generates heat, which may cause harm to the user and impair safety. Further, since the duration of the battery is shortened, a larger battery is required to maintain the same duration, and convenience is impaired in the case of a portable device. It is desirable to reduce the power consumption of the wireless transceiver as much as possible.

  An object of the present invention is to improve safety and convenience by reducing power consumption of a wireless transmission / reception apparatus.

  In order to achieve the above object, the frequency comparison circuit of the present invention mixes an input signal and a local signal, and from the obtained signal, a difference frequency which is a difference between the frequency of the input signal and the frequency of the local signal. A signal obtained by mixing in-phase baseband signal extraction means for extracting only the component of the signal as an in-phase baseband signal, the input signal, and a quadrature local signal that is a signal obtained by shifting the phase of the local signal by a predetermined value An orthogonal baseband signal extracting means for extracting only a differential frequency component, which is a difference between the frequency of the input signal and the frequency of the orthogonal local signal, as an orthogonal baseband signal, the in-phase baseband signal, and the orthogonal base A polarity determination means for determining the polarity of the differential frequency from a polarity relationship with a band signal; and a period of the in-phase baseband signal or the Having an absolute value obtaining means from the period of the exchange baseband signals to obtain the absolute value of the difference frequency, a.

  The frequency control circuit of the present invention acquires the difference frequency based on the frequency comparison circuit of the present invention, the polarity acquired by the polarity acquisition means, and the absolute value output by the absolute value output means. And control means for correcting the frequency of the local signal by the difference frequency.

  The radio transmission / reception apparatus of the present invention has the frequency control circuit of the present invention, and when the received modulation wave signal carrying the received baseband signal is input to the frequency control circuit as the input signal, the orthogonal baseband signal and The received baseband signal is demodulated based on the in-phase baseband signal.

  According to the control method of the frequency comparison circuit of the present invention, the input signal and the local signal are mixed, and only the component of the difference frequency that is the difference between the frequency of the input signal and the frequency of the local signal is in-phase from the obtained signal. As a baseband signal, the input signal is mixed with an orthogonal local signal that is a signal obtained by shifting the phase of the local signal by a predetermined value. From the obtained signal, the frequency of the input signal and the orthogonal local signal are mixed. Only the difference frequency component that is the difference from the frequency of the quadrature baseband signal is extracted, and the polarity of the differential frequency is determined from the polarity relationship between the in-phase baseband signal and the quadrature baseband signal, The frequency comparison circuit control method acquires an absolute value of the difference frequency from a period of the in-phase baseband signal or the quadrature baseband signal.

  According to the present invention, the frequency comparison circuit outputs the polarity of the difference frequency and the absolute value from the analog input signal and the local signal, so that the radio transmission / reception device can generate the reference clock signal based on the output value. The frequency can be controlled with a small amount of calculation. As a result, the power consumption of the wireless transmission / reception device is reduced, and its safety and convenience are improved.

It is a block diagram which shows the example of 1 structure of the frequency control circuit of the 1st Embodiment of this invention. (a) It is a table | surface which shows the relationship between Bi and Bq in case of error frequency (DELTA) omega> 0. (b) A table showing the relationship between Bi and Bq when the error frequency Δω <0. It is a flowchart which shows operation | movement of the control circuit of the 1st Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the frequency control circuit of the 2nd Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the frequency control circuit of the 3rd Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the frequency control circuit of the 4th Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the frequency control circuit of the 5th Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the radio | wireless transmitter / receiver of the 6th Embodiment of this invention. It is a block diagram which shows the structure of the radio | wireless transmission / reception apparatus of the modification of this invention. It is a block diagram which shows the structure of a general WCDMA mobile telephone apparatus.

(First embodiment)
A first embodiment for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the frequency control circuit 100 of the present embodiment. The frequency control circuit 100 is a circuit used in a mobile station such as a cellular phone device to cause the reference clock frequency on the mobile station side to follow the reference clock frequency on the base station side.

  Referring to FIG. 1, the frequency control circuit 100 includes a frequency comparison circuit 110, a frequency synthesizer (SYNTH) 120, and a control circuit 130.

  The frequency comparison circuit 110 is a circuit that compares the frequency of the input signal S with the frequency of the in-phase local signal Li and outputs the polarity P of the difference between these frequencies and the absolute value | Δω | of the difference frequency. .

  Here, the input signal S is an analog signal having a constant frequency input from the outside of the frequency control circuit 100. For example, a downlink signal received wirelessly from the base station is input as the input signal S.

  The in-phase local signal Li is an analog signal having a constant frequency that is generated inside the frequency control circuit 100. For example, a signal having the same frequency as the downlink signal received from the base station is generated as the in-phase local signal Li.

  The frequency comparison circuit 110 includes a π / 2 phase shifter (π / 2) 111, mixers (MIX) 112 and 113, low-pass filters (LPF) 114 and 115, an edge detection circuit 116, a polarity determination circuit 117, A clock generator (Ref CLOCK) 118 and a timer circuit 119 are included.

  The frequency synthesizer (SYNTH) 120 generates an in-phase local signal Li and outputs it to the π / 2 phase shifter (π / 2) 111 and the mixer (MIX) 112. A method for generating the in-phase local signal Li will be described later.

  The π / 2 phase shifter (π / 2) 111 delays the phase of the in-phase local signal Li from the frequency synthesizer (SYNTH) 120 by π / 2 radians, and outputs it to the mixer (MIX) 113 as a quadrature local signal Lq.

  Input signals S are input to the mixers (MIX) 112 and 113.

  The mixer (MIX) 112 mixes the input signal S and the in-phase local signal Li from the frequency synthesizer (SYNTH) 120 and outputs the mixed signal as an in-phase mixer output signal Si to the low-pass filter (LPF) 114.

  The mixer (MIX) 113 mixes the input signal S and the orthogonal local signal Lq from the π / 2 phase shifter (π / 2) 111 and outputs the mixed signal to the low-pass filter (LPF) 115 as the orthogonal mixer output signal Sq.

The low-pass filter (LPF) 114 receives the in-phase mixer output signal Si, removes a component having a frequency almost twice the frequency ω _s of the input signal S, and outputs it to the polarity determination circuit 117 as the in-phase baseband signal Bi. .

The low-pass filter (LPF) 115 receives the quadrature mixer output signal Sq, removes a component having a frequency almost twice the frequency ω _s of the input signal S, and outputs it to the edge detection circuit 116 as a quadrature baseband signal Bq. .

  The edge detection circuit 116 monitors the amplitude polarity of the orthogonal baseband signal Bq and detects a rising edge and a falling edge. When the edge detection circuit 116 detects an edge, the edge detection circuit 116 outputs an edge detection signal (for example, a pulse signal) indicating that the edge has been detected to the polarity determination circuit 117 and the timer circuit 119.

  Here, the rising edge means that the amplitude polarity of the signal is inverted from negative to positive, and the falling edge is that the amplitude polarity of the signal is inverted from positive to negative.

  The edge detection signal may be any signal indicating the type of edge (whether it is rising or falling) and the edge detection timing.

  For example, the edge detection circuit 116 outputs a logic signal that becomes a high level when the amplitude of the orthogonal baseband signal Bq is + and becomes a low level when the amplitude is − as an edge detection signal. Alternatively, the edge detection circuit 116 outputs a pulse at the timing when the rising edge or the falling edge occurs, outputs a signal indicating whether the edge is rising or falling, and sets these output signals. Is an edge detection signal.

  The polarity determination circuit 117 determines the polarity of the error frequency Δω based on the amplitude polarity of the in-phase baseband signal Bi detected when the edge detection signal is output from the edge detection circuit 116. Details of the method of determining the polarity of the error frequency Δω will be described later.

Here, the error frequency Δω is a difference between the angular frequency ω _s of the input signal S and the angular frequency ω _L of the in-phase local signal Li. For example, when the input signal S is used as a reference, the error frequency Δω can be obtained from the following equation (1).

Therefore, when ω _L is larger than ω _s , the polarity of the error frequency Δω is “+”, and conversely, when ω _L is smaller than ω _s , the polarity of the error frequency Δω is “−”. The polarity determination circuit 117 outputs the determined polarity P to the control circuit 130.

  The clock generator (Ref CLOCK) 118 generates a reference clock signal having a predetermined frequency and outputs the reference clock signal to the frequency synthesizer 120 and the time measuring circuit 119.

  The time measuring circuit 119 uses the reference clock signal from the clock generator (Ref CLOCK) 118 to measure the period in which the rising edge is detected by the edge detection circuit 116 or the period in which the falling edge is detected. The reciprocal of the measured value is output to the control circuit 130 as the absolute value | Δω | of the error frequency.

  The control circuit 130 obtains the error frequency Δω from the polarity P and the absolute value | Δω |. The control circuit 130 generates a frequency control signal for controlling the frequency synthesizer (SYNTH) 120 so as to correct the frequency of the in-phase local signal Li by the error frequency, and the frequency synthesizer (SYNTH). 120 is output.

  For example, the control circuit 130 has a table (not shown) in which the error frequency Δω is associated with a correction amount related to frequency correction, and the frequency control signal is generated using the table. The control circuit 130 can also calculate a correction amount from the error frequency by using a predetermined arithmetic expression. These calculations and tables can have a gain setting function for arbitrarily setting a gain for determining a correction amount for one round of frequency correction.

  In addition, the control circuit 130 may have a truncation function that does not generate a frequency control signal when the absolute value | Δω | of the error frequency is less than a preset threshold value.

  Further, the control circuit 130 detects the absolute value | Δω | of the error frequency exceeding a certain threshold value in order to avoid the influence of the jumping noise, and the limiter function for suppressing the value or the error frequency Δω May be integrated in the time axis direction and averaged.

  All or a part of the operations for calculating these correction amounts may be realized by executing a computer program, or may be realized by hardware.

  The frequency synthesizer (SYNTH) 120 generates an in-phase local signal Li and outputs it to the π / 2 phase shifter (π / 2) 111 and the mixer (MIX) 112. The frequency synthesizer (SYNTH) 120 refers to the frequency of the reference clock signal and corrects the frequency of the in-phase local signal Li according to the frequency control signal from the control circuit 130.

  Next, the operation of the frequency control circuit 100 will be described with reference to FIGS. First, it is assumed that the input signal S and the in-phase local signal Li represented by the following expressions (2) and (3) are input to the frequency comparison circuit 110.

In the above equations (2) and (3), “ω _s ” is the angular frequency (rad / s) of the input signal S, “Δω” is the error frequency (rad / s), and “t” is the time ( s), it is assumed that Δω is sufficiently smaller than ω _s .

  The input signal S and the in-phase local signal Li are input to the mixer (MIX) 112, and the mixer (MIX) 112 mixes them to output an in-phase mixer output signal Si. Since this mixing corresponds to a multiplication operation, the in-phase mixer output signal Si is obtained by the following equation (4).

As shown in the above equation (4), the in-phase mixer output signal Si has a component having a frequency almost twice the frequency ω _s of the input signal S and a component having a frequency equal to the error frequency Δω. .

This in-phase mixer output signal Si is input to a low-pass filter (LPF) 114, where a component having a frequency approximately twice the frequency ω _s is removed. As a result, an in-phase baseband signal Bi expressed by the following equation (5) is output.

  On the other hand, the in-phase local signal Li is input to the π / 2 phase shifter (π / 2) 111, and a quadrature local signal Lq expressed by the following equation (6) is output.

  The input signal S and the orthogonal local signal Lq are input to the mixer (MIX) 113, and the mixer (MIX) 113 mixes them to output an orthogonal mixer output signal Sq. Since this mixing corresponds to a multiplication operation, the orthogonal mixer output signal Sq is obtained by the following equation (7).

As shown in the above equation (7), the quadrature mixer output signal Sq has a component having a frequency approximately twice the frequency ω _s of the input signal S and a component having a frequency equal to the error frequency Δω.

This quadrature mixer output signal Sq is input to a low-pass filter (LPF) 115 where a component having a frequency approximately twice the frequency ω _s is removed. As a result, an orthogonal baseband signal Bq expressed by the following equation (8) is output.

  From the above equations (5) and (8), the amplitude polarity of the in-phase baseband signal Bi and the quadrature baseband signal Bq at each time can be calculated.

  FIG. 2A shows the time change of the amplitude polarity of the in-phase baseband signal Bi and the quadrature baseband signal Bq when the error frequency Δω> 0, that is, when the polarity P is positive.

  FIG. 2B shows a time change of the amplitude polarity of the in-phase baseband signal Bi and the quadrature baseband signal Bq when the error frequency Δω <0, that is, when the polarity P is negative.

  2A and 2B, the downward white arrow is a falling edge of the orthogonal baseband signal Bq, and the upward white arrow is a rising edge.

  Referring to FIGS. 2A and 2B, in the case of error frequency Δω> 0, the amplitude polarity of the in-phase baseband signal Bi is positive when a falling edge is detected in the orthogonal baseband signal Bq. In contrast, when the error frequency Δω <0, when the falling edge is detected in the quadrature baseband signal Bq, the amplitude polarity of the in-phase baseband signal Bi is negative. This is because the phases of the orthogonal baseband signal Bq and the in-phase baseband signal Bi are shifted by π / 2 as shown in the above equations (5) and (8).

  For the same reason, the amplitude polarity of the in-phase baseband signal Bi is negative when a rising edge is detected in the quadrature baseband signal Bq when the error frequency Δω> 0. On the other hand, when the error frequency Δω <0, when the rising edge is detected in the orthogonal baseband signal Bq, the amplitude polarity of the in-phase baseband signal Bi is positive.

  Therefore, the polarity P of the error frequency Δω can be determined by observing the amplitude polarity of the in-phase baseband signal Bi at the timing when the orthogonal baseband signal Bq is inverted.

  The polarity determination circuit 117 outputs the polarity P determined in this way. The timer circuit 119 measures the period of the rising edge or the period of the falling edge of the orthogonal baseband signal Bq expressed by the above equation (8). The timer circuit 119 outputs the reciprocal of the measured time as the absolute value | Δω | of the error frequency.

  FIG. 3 is a flowchart showing the operation of the control circuit 130. Referring to the figure, this operation starts when the frequency control circuit 100 is powered on. The control circuit 130 inputs the absolute value | Δω | (step S0). The control circuit 130 determines whether or not the absolute value | Δω | is equal to or less than a preset lower limit value (step S1).

  If the absolute value | Δω | of the error frequency is not less than or equal to the lower limit in the determination of step S1, the control circuit 130 determines whether or not the absolute value | Δω | of the error frequency exceeds the upper limit (step S2). If the absolute value | Δω | of the error frequency exceeds the upper limit value in the determination of step S2, the control circuit 130 sets the upper limit value as the absolute value | Δω | of the error frequency (step S3). Subsequently, the control circuit 130 calculates a correction amount of the frequency of the local signal Li corresponding to the combination of the absolute value | Δω | of the error frequency and the polarity P using a predetermined arithmetic expression or table (step S4). ). Then, the control circuit 130 outputs a frequency control signal indicating the calculated correction amount to the frequency synthesizer (SYNTH) 120, and updates the frequency of the local signal Li (step S5). Thereafter, the process returns to step S0.

  On the other hand, if the absolute value | Δω | of the error frequency is equal to or lower than the lower limit value in the determination in step S1, the control circuit 130 returns to the input in step S0. If the absolute value | Δω | of the error frequency is equal to or lower than the upper limit value in the determination in step S2, the control circuit 130 does not perform step S3 but proceeds to step S4.

  In the present embodiment, the frequency comparison circuit 110 determines the polarity of the error frequency Δω from the amplitude polarity of the in-phase baseband signal Bi when the edge of the quadrature baseband signal Bq is detected. However, the frequency comparison circuit 110 may determine the polarity of the error frequency Δω from the amplitude polarity of the orthogonal baseband signal Bq when the edge of the in-phase baseband signal Bi is detected.

  In this embodiment, the frequency comparison circuit 110 obtains the absolute value | Δω | of the error frequency from the period of the rising edge or the falling edge of the orthogonal baseband signal Bq, but the rising edge of the in-phase baseband signal Bi. The absolute value | Δω | of the error frequency may be obtained from the period of the edge or the falling edge.

  Furthermore, the upper limit value and lower limit value of the absolute value | Δω | of the error frequency may be set for each value of the polarity P.

  In the present embodiment, the edge detection circuit 116 outputs an edge detection signal, the polarity determination circuit 117 determines the polarity using the signal, and the timer circuit 119 measures the edge cycle.

  However, in the polarity determination, the signal from the edge detection circuit 116 is not used, and the polarity determination circuit 117 itself detects the rising edge or the falling edge of the orthogonal baseband signal Bq, and the in-phase baseband signal at the time of edge detection. The polarity P can also be obtained from the polarity of Bi. Even when the edge period is counted, the signal from the edge detection circuit 116 is not used, and the timing circuit 119 itself detects the rising edge or the falling edge of the orthogonal baseband signal Bq, and also counts the period of the edge. Good.

  As described above, according to the present embodiment, the frequency comparison circuit 110 can detect the error P (difference frequency) Δω from the analog input signal S and the local signal Li by a simple circuit, and the error. Since the absolute value | Δω | of the frequency is output, the frequency can be controlled with a small amount of calculation by the frequency control circuit 100 correcting the reference clock signal based on the output value. As a result, power consumption is reduced in the wireless transmission / reception apparatus provided with the frequency control circuit 100.

  For example, in the general wireless transmission / reception apparatus described in FIG. 10, in the case of WCDMA, the clock frequency of the FINGER circuit, the RAKE circuit, the frequency offset circuit, the delay profile circuit, and the timing generation circuit is several hundred MHz. The update frequency of the accumulator output is at most tens of Hz.

  According to the present embodiment, the frequency control circuit having a clock frequency of several hundred MHz and the accumulator having several tens of Hz can be replaced with the frequency control circuit 100 having about several tens of Hz.

  As described above, in the wireless transmission / reception apparatus using the frequency control circuit 100 of the present embodiment, the digital calculation amount for frequency control is about 1/1000 in terms of clock, which is consumed in comparison with a general wireless transmission / reception apparatus. The power is greatly reduced.

  Further, according to the present embodiment, the frequency comparison circuit 110 uses the edge detection signal from the edge detection circuit 116, the polarity determination circuit 117 determines the polarity P, and the timing circuit 119 has the absolute value of the error frequency | Since Δω | is output, the polarity P and the absolute value | Δω | can be accurately obtained.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the frequency control circuit 100a of this embodiment. Referring to the figure, the configuration of the frequency control circuit 100a is the same as the configuration of the frequency control circuit 100 of the first embodiment, except that A / D converters (A / D) 121 and 122 are further provided. .

  The low pass filter (LPF) 114 outputs the in-phase baseband signal Bi to the A / D converter (A / D) 121 in addition to the polarity determination circuit 117. The low pass filter (LPF) 115 outputs the orthogonal baseband signal Bq to the A / D converter (A / D) 122 in addition to the edge detection circuit 116.

  The A / D converter (A / D) 121 converts the in-phase baseband signal Bi from the low-pass filter (LPF) 114 into an in-phase digital baseband signal and outputs it. The A / D converter (A / D) 122 converts the orthogonal baseband signal Bq from the low-pass filter (LPF) 115 into an orthogonal digital baseband signal and outputs it. These digital baseband signals are input to a demodulation circuit or the like in the wireless transmission / reception device.

  As described above, according to the present embodiment, the frequency control circuit 100a converts the in-phase baseband signal Bi and the quadrature baseband signal Bq into the in-phase digital baseband signal and the quadrature digital baseband signal, respectively. The frequency control circuit 100a can be used for a receiving circuit of a wireless transmission / reception device. Therefore, by incorporating the frequency control circuit 100a in the wireless transmission / reception device, the circuit scale in the wireless transmission / reception device can be reduced as compared with a configuration in which a reception circuit is provided separately from the frequency control circuit.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the frequency control circuit 100b of this embodiment. Referring to the figure, the configuration of the frequency control circuit 100b is such that low-pass filters (LPF) 123 and 124 are further provided, and these output signals are input to A / D converters (A / D) 121 and 122. The configuration is the same as that of the frequency control circuit 100a of the second embodiment.

  The mixer 112 outputs the in-phase mixer output signal Si to the low-pass filter (LPF) 123 in addition to the low-pass filter (LPF) 114. The mixer (MIX) 113 outputs the orthogonal mixer output signal Sq to the low-pass filter (LPF) 124 in addition to the low-pass filter (LPF) 115.

  The low-pass filters (LPF) 123 and 124 have pass characteristics specialized for the reception processing of communication signals. The low-pass filter (LPF) 123 removes unnecessary waves from the in-phase baseband signal Bi and outputs it to the A / D converter (A / D) 121. The low-pass filter (LPF) 124 removes unnecessary waves from the orthogonal baseband signal Bq and outputs it to the A / D converter (A / D) 122.

  The radio transmission / reception apparatus may use different baseband bandwidths when performing frequency control and when receiving a communication signal as the radio transmission / reception apparatus. Therefore, a filter having characteristics suitable for one of frequency control processing and communication signal reception processing is not necessarily suitable for the other.

  However, according to the present embodiment, the wireless transmission / reception apparatus using the frequency control circuit 100b includes the low-pass filters (LPF) 114, 115, 123, 124 having pass characteristics specialized for frequency control and communication signal reception. By using it, it is possible to improve the communication signal reception performance while maintaining the frequency tracking performance.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the frequency control circuit 100c of this embodiment. Referring to the figure, the configuration of the frequency control circuit 100c is the second except that low-pass filters (LPF) 114c and 115c and a control circuit 130c are provided in place of the low-pass filters (LPF) 114 and 115 and the control circuit 130. This is the same as the frequency control circuit 100a of the embodiment.

  When switching between frequency control and communication signal reception, the control circuit 130c outputs a control signal for switching the characteristics of the low-pass filter to the low-pass filters (LPF) 114c and 115c.

  The control circuit 130c may use the time zone stored in advance by the control circuit 130c as the timing of switching between frequency control and communication signal reception (or the time zone during which each operation is performed) or an external device. The timing received from may be used.

  The low-pass filters (LPF) 114c and 115c switch their pass characteristics according to the control signal from the control circuit 130c.

  For example, the frequency control circuit 100c uses a method in which each low-pass filter has a plurality of built-in filters and switches, and the built-in filters are switched by the switches.

  The frequency control circuit 100c may have a plurality of filter components and switches in each low-pass filter, and a method of switching the filter components may be used. By switching the filter components, the filter characteristics can be switched.

  Alternatively, the frequency control circuit 100c includes a part of the constituent elements that determine the characteristics of each low-pass filter as an element (for example, a varactor diode) whose characteristics are changed by an external electric signal, and changes the characteristics of the elements. It is also possible to use a method of changing the characteristics of the low-pass filter.

  As described above, according to the present embodiment, since only two low-pass filters are required, frequency control and communication signal reception are performed as compared with the third embodiment in which four low-pass filters are used. It is possible to simplify the circuit for performing the above.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of the frequency control circuit 100d of this embodiment. Referring to the figure, the configuration of the frequency control circuit 100d is the same as that of the first embodiment except that the clock generator (Ref CLOCK) 118d and the control circuit 130d are provided in place of the clock generator (Ref CLOCK) 118 and the control circuit 130. This is the same as the frequency control circuit 100 of the embodiment.

  The control circuit 130d outputs a control signal for controlling not the frequency synthesizer (SYNTH) 106 but the clock generator (Ref CLOCK) 118d to the clock generator (Ref CLOCK) 118d.

  The correction amount of the reference clock frequency is obtained from the error frequency Δω. As in the case of the first embodiment, the control circuit 130d obtains the correction amount by using a table in which the error frequency Δω is associated with the correction amount, a predetermined arithmetic expression, or the like.

  The clock generator (Ref CLOCK) 118d outputs a reference clock signal whose frequency is corrected in accordance with a control signal from the control circuit 130d.

  As described above, according to the present embodiment, the frequency control circuit 100d can obtain the absolute value | Δω | more accurately than in the first embodiment by correcting the frequency itself of the reference clock signal. it can.

  In addition, when the circuit that refers to the reference clock frequency is other than the frequency synthesizer, the frequency control circuit 100d can also correct the frequency at which these circuits operate.

(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration of the wireless transmission / reception device 1 of the present embodiment. The wireless transmission / reception device 1 is a device having a function of transmitting / receiving a wireless signal, such as a mobile phone device.

  The wireless transmission / reception device 1 includes a wireless unit 10, an antenna 11, and a baseband unit 20. The radio unit 10 includes a duplexer (DUP) 101, a low noise amplifier (LNA) 102, a band pass filter (BPF) 103, a frequency control circuit 100a, a D / A converter (D / A) 141, a low pass filter (LPF) 142, A frequency synthesizer (SYNTH) 143, a mixer (MIX) 144, a bandpass filter (BPF) 145, and a power amplifier 146 are included. The frequency control circuit 100a is connected to the baseband unit 20, and has the same configuration as the frequency control circuit 100a of the second embodiment, except that a reference clock signal and a frequency control signal are supplied to a frequency synthesizer (SYNTH) 143. .

  The antenna 11 receives a high-frequency radio signal and outputs it to a duplexer (DUP) 101 as a received high-frequency signal.

  The antenna 11 transmits a transmission high-frequency signal from the duplexer (DUP) 101 to the base station. A method for generating a transmission high-frequency signal will be described later.

  The duplexer (DUP) 101 outputs a transmission high-frequency signal from the power amplifier (PA) 146 to the antenna 11, and outputs a reception high-frequency signal from the antenna 11 to the low noise amplifier (LNA) 102.

  The low noise amplifier (LNA) 102 amplifies the received high frequency signal from the duplexer (DUP) 101 and outputs the amplified signal to the band pass filter (BPF) 103.

  The band pass filter (BPF) 103 extracts a high frequency component of a predetermined band from the received high frequency signal, and outputs it as an input signal S to the frequency control circuit 100a.

  The frequency control circuit 100a outputs the in-phase digital baseband signal and the orthogonal digital baseband signal after A / D conversion to the baseband unit (CPU & BB) 20.

  The control circuit 130 receives frequency information and frequency comparison timing information from the baseband unit (CPU & BB) 20.

  Here, the frequency information is information indicating the frequency of each of the reception high-frequency signal, transmission high-frequency signal, pilot signal, and marker signal. In the case of communication using a subcarrier, the frequency information includes information indicating the offset frequency.

  The pilot signal and marker signal are signals that are transmitted and received as indices of frequency and signal timing.

  The frequency comparison timing information is information indicating the timing (time zone) at which the reception high-frequency signal, transmission high-frequency signal, pilot signal, marker signal, and subcarrier (subcarrier) are communicated, or the timing (time zone) used. It is.

  The control circuit 130 performs frequency control based on these frequency information and frequency comparison timing information. The control circuit 130 stores frequency information and frequency comparison timing information, and autonomously uses the stored information even when input of information from the baseband unit (CPU & BB) 20 is stopped. Can work.

  The control circuit 130 controls the frequency synthesizer (SYNTH) 143 in the same manner as the frequency synthesizer (SYNTH) 120 in the frequency control. The clock generator (Ref CLOCK) 118 outputs a reference clock signal to the frequency synthesizer (SYNTH) 143 in addition to the timer circuit 119 and the frequency synthesizer (SYNTH) 120.

  The baseband unit (CPU & BB) 20 extracts received data from the in-phase digital baseband signal and the quadrature digital baseband signal from the radio unit 10, and generates a transmission digital baseband signal including transmission data to be sent to the base station. , Output to the radio unit 10.

  In addition, the baseband unit (CPU & BB) 20 generates frequency information and frequency comparison timing information, and outputs them to the control circuit 130.

  The baseband unit (CPU & BB) 20 inputs the generated frequency information and frequency comparison timing information to the control circuit 130 to instruct the frequency of the input signal S to be frequency-compared and the timing (time zone) to be compared. For example, in an OFDM signal, a subcarrier used as a pilot signal may change with time. The baseband unit (CPU & BB) 20 instructs the control circuit 130 on the frequency of the subcarrier and the frequency comparison timing so as to compare the frequencies of the subcarriers serving as pilot signals.

  Further, when the wireless transmission / reception device 1 performs frequency correction during data communication, the communication may be interrupted. In order to avoid this, the baseband unit (CPU & BB) 20 can instruct the control circuit 130 to stop (or prohibit) the frequency control function so as not to perform the frequency control operation during data communication.

  The D / A converter (D / A) 141 converts the transmission digital baseband signal from the baseband unit (CPU & BB) 20 into an analog signal, and outputs the analog signal to the low-pass filter (LPF) 142 as a transmission analog baseband signal.

  The low pass filter (LPF) 142 extracts a predetermined band from the transmission analog baseband signal from the D / A converter (D / A) 141, and outputs it to the mixer (MIX) 144.

  The frequency synthesizer (SYNTH) 143 generates a transmission local signal based on the frequency of the reference clock signal from the clock generator (Ref CLOCK) 118 according to the frequency control signal from the control circuit 130. This transmission local signal is used as a carrier signal of an uplink signal (transmission high frequency signal) to be transmitted to the base station. The frequency synthesizer (SYNTH) 143 outputs the transmission local signal to the mixer (MIX) 144.

  The mixer (MIX) 144 mixes the transmission analog baseband signal from the low-pass filter (LPF) 142 and the transmission local signal from the frequency synthesizer (SYNTH) 143, generates a transmission high-frequency signal, and generates a bandpass filter (BPF). ) Output to 145.

  The band pass filter (BPF) 145 extracts a predetermined band from the transmission high-frequency signal from the mixer (MIX) 144 and outputs it to the power amplifier (PA) 146.

  The power amplifier (PA) 146 amplifies the transmission high frequency signal from the band pass filter (BPF) 145 and outputs the amplified signal to the duplexer (DUP) 101.

  In the present embodiment, the wireless transmission / reception apparatus 1 uses the frequency control circuit 100a of the second embodiment. However, as illustrated in FIG. 9, the wireless transmission / reception device 1 may use the frequency control circuit 100 d of the fifth embodiment that controls the reference clock frequency. The same applies to the frequency control circuits of the third and fourth embodiments.

  As described above, according to the present embodiment, by using the low-power-consumption frequency control circuit 100a in the wireless transmission / reception device 1, the power consumption of the entire wireless transmission / reception device 1 is reduced, and the safety and Convenience is improved.

DESCRIPTION OF SYMBOLS 1 Radio transmission / reception apparatus 10 Radio | wireless part 20 Baseband part 100, 100a, 100b, 100c, 100d Frequency control circuit 101 Duplexer 102 Low noise amplifier 103, 145 Band pass filter 110 Frequency comparison circuit 111 π / 2 phase shifter 112, 113, 144 Mixer 114, 115, 123, 124, 114c, 115c, 142 Low-pass filter 116 Edge detection circuit 117 Polarity determination circuit 118, 118d Clock generator 119 Clock circuit 120, 143 Frequency synthesizer 121, 122 A / D converters 130, 130c, 130d Control circuit 141 D / A converter 146 Power amplifier S0 to S5 Step

Claims (16)

In-phase baseband signal extraction means for mixing an input signal and a local signal and extracting an in-phase baseband signal having a difference frequency which is a difference between the frequency of the input signal and the frequency of the local signal from the obtained signal ,
An orthogonal baseband signal extraction that mixes the input signal and an orthogonal local signal that is a signal obtained by shifting the phase of the local signal by a predetermined value, and extracts an orthogonal baseband signal having the difference frequency from the obtained signal Means,
From the polarity relationship between the in-phase baseband signal and the quadrature baseband signal, polarity determination means for determining the polarity of the difference frequency;
Absolute value acquisition means for acquiring the absolute value of the difference frequency from the period of the in-phase baseband signal or the period of the quadrature baseband signal;
A frequency comparison circuit.   The polarity determination means determines the polarity of the difference frequency from the amplitude polarity of the other signal when one of the in-phase baseband signal and the quadrature baseband signal rises or falls. The frequency comparison circuit according to claim 1.   The absolute value acquisition unit measures a period in which rising occurs or a period in which falling occurs in the in-phase baseband signal or the quadrature baseband signal, and the reciprocal of the measured period is set as the absolute value of the difference frequency. The frequency comparison circuit according to claim 1 or 2. Further comprising detection means for monitoring the amplitude polarity of the in-phase baseband signal or the quadrature baseband signal and detecting rising or falling of the monitored signal;
The polarity determination unit detects the difference frequency from the amplitude polarity of the other signal when the detection unit detects a rising or falling edge of one of the quadrature baseband signal and the in-phase baseband signal. The frequency comparison circuit according to claim 2, wherein the polarity is determined. Further comprising detection means for monitoring the amplitude polarity of the in-phase baseband signal or the quadrature baseband signal and detecting rising or falling of the monitored signal;
The absolute value acquisition means uses the reciprocal of the period in which the rising edge detected by the detecting means or the reciprocal of the period in which the falling occurs detected by the detection means as the absolute value of the difference frequency. 4. The frequency comparison circuit according to 3. The in-phase baseband signal extraction means includes:
A first mixer that outputs a signal obtained by mixing the input signal and the local signal as an in-phase mixer output signal;
A first filter for extracting the in-phase baseband signal by removing a component having a frequency twice the frequency of the local signal from the in-phase mixer output signal output by the first mixer;
Have
The orthogonal baseband signal extraction means includes
A second mixer that outputs a signal obtained by mixing the input signal and the orthogonal local signal as an orthogonal mixer output signal;
A second filter for extracting the quadrature baseband signal by removing a component having a frequency twice the frequency of the local signal from the quadrature mixer output signal output by the second mixer;
The frequency comparison circuit according to claim 1, comprising: A frequency comparison circuit according to claim 6;
Local signal generating means for supplying a local signal to the frequency comparison circuit;
The difference frequency is acquired based on the polarity determined by the polarity determination unit and the absolute value acquired by the absolute value acquisition unit, and the local signal generation unit generates the difference frequency according to the difference frequency. Control means for correcting the frequency of the local signal;
A frequency control circuit.   The frequency control circuit according to claim 7, further comprising a conversion circuit that converts the in-phase baseband signal and the quadrature baseband signal into an in-phase digital baseband signal and a quadrature digital baseband signal, respectively. The frequency comparison circuit includes:
A third filter having different characteristics from the first filter and removing a predetermined component from the in-phase baseband signal;
A fourth filter having characteristics different from those of the second filter and removing a predetermined component from the orthogonal baseband signal;
Have
The conversion circuit converts the in-phase baseband signal and the quadrature baseband signal from which predetermined components are removed by the third filter and the fourth filter into an in-phase digital baseband signal and a quadrature digital baseband signal, respectively. 9. The frequency control circuit according to claim 8, wherein the frequency control circuit performs conversion. The control means transmits a filter control signal for changing the characteristics of the filter to the first filter and the second filter,
The frequency control circuit according to claim 8, wherein the first filter and the second filter change characteristics according to the filter control signal transmitted by the control circuit. A frequency comparison circuit according to any one of claims 1 to 5,
Local signal generating means for supplying a local signal to the frequency comparison circuit;
The difference frequency is acquired based on the polarity determined by the polarity determination unit and the absolute value acquired by the absolute value acquisition unit, and the local signal generation unit generates the difference frequency according to the difference frequency. Control means for correcting the frequency of the local signal;
A frequency control circuit.   12. The frequency control circuit according to claim 11, further comprising a conversion circuit that converts the in-phase baseband signal and the quadrature baseband signal into an in-phase digital baseband signal and a quadrature digital baseband signal, respectively. A reference clock signal generating means for generating a reference clock signal;
The local signal generating means generates the local signal based on the reference clock signal;
The frequency control circuit according to claim 7, wherein the control unit corrects the frequency of the reference clock signal according to the acquired difference frequency. The control means obtains a correction value of the frequency of the local signal according to the difference frequency, and transmits a frequency control signal indicating the correction value to the local signal generation means,
The frequency control circuit according to any one of claims 7 to 12, wherein the local signal generation unit generates the local signal whose frequency is corrected by the correction value indicated by the frequency control signal. A frequency control circuit according to any one of claims 7 to 14,
A radio transmission / reception apparatus that inputs the input signal carrying a signal wave to the frequency control circuit and demodulates the signal wave based on the quadrature baseband signal and the in-phase baseband signal. Mix the input signal and local signal,
From the obtained signal, an in-phase baseband signal having the frequency of the input signal and the frequency of the local signal is extracted,
Mixing the input signal and an orthogonal local signal that is a signal obtained by shifting the phase of the local signal by a predetermined value;
Extracting an orthogonal baseband signal having the difference frequency from the obtained signal,
From the polarity relationship between the in-phase baseband signal and the quadrature baseband signal, determine the polarity of the difference frequency,
A method for controlling a frequency comparison circuit, wherein an absolute value of the difference frequency is acquired from a period of the in-phase baseband signal or the quadrature baseband signal.

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