JP2015076778A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that the power consumption becomes larger in conventional semiconductor devices.SOLUTION: A semiconductor device includes: a digital signal processing section 10 shifting the frequency of a first baseband signal B1 according to a first frequency shift signal and outputting a second baseband signal B2; an analog front-end section 11 converting the second baseband signal B2 into an analog signal and generating a third baseband signal B3; an analog front-end section 12 modulating the third baseband signal B3 by a local signal and generating a carrier signal to be transmitted; and a local signal generating section 13 generating the local signal and shifting the frequency of the local signal from a fundamental local frequency according to a second frequency shift signal. The semiconductor device has a function that offsets the frequency of the first baseband signal B1 and the frequency of the local signal and shifts the frequency of a harmonic component corresponding to the carrier signal.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including a transmission circuit that outputs a modulation signal as a radio signal.

  In a semiconductor device including a transmission circuit used for wireless communication, it is required to reduce the signal intensity of unnecessary waves such as harmonics that are output together with a carrier signal. Therefore, Patent Document 1 discloses a technique for reducing unnecessary waves.

  In Patent Document 1, a notch filter is formed between a mixer that modulates an I signal and a Q signal to generate a modulated signal and an amplifier that amplifies the modulated signal, thereby suppressing the signal intensity of unnecessary waves.

U.S. Pat. No. 8,428,545

  The inventors have found various problems in developing a semiconductor device including a transmission circuit. Each embodiment disclosed in the present application provides a semiconductor device suitable for a receiving device or the like, for example.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment has a function of shifting the frequency of a harmonic component corresponding to a carrier signal by offsetting both the frequency of a baseband signal and the frequency of a local signal.

  According to one embodiment, it is possible to provide a high-quality semiconductor device that is suitable for a transmission circuit or the like, for example.

1 is a block diagram of a semiconductor device according to a first embodiment; 3 is a block diagram of a frequency shift unit of the semiconductor device according to the first embodiment; FIG. FIG. 3 is a diagram illustrating a communication spectrum when no frequency shift is performed in the semiconductor device according to the first embodiment. FIG. 3 is a diagram illustrating a communication spectrum when a frequency shift is performed in the semiconductor device according to the first embodiment. FIG. 3 is a block diagram of a semiconductor device according to a second embodiment. FIG. 6 is a block diagram of an IQ image correction unit of a semiconductor device according to a second embodiment; FIG. 10 is a diagram illustrating a communication spectrum when IQ image correction is performed in the semiconductor device according to the second embodiment. FIG. 6 is a block diagram of an oscillation circuit of a semiconductor device according to a third embodiment. 6 is a timing chart showing frequency switching timing of a local signal in a semiconductor device according to a third embodiment; FIG. 6 is a block diagram of a semiconductor device according to a fourth embodiment. 10 is a flowchart of DC offset correction coefficient determination processing in a semiconductor device according to a fourth embodiment; 10 is a flowchart of IQ image correction coefficient determination processing in a semiconductor device according to a fourth embodiment; FIG. 10 is a diagram illustrating a spectrum of a signal input to a mixer in the IQ image correction coefficient determination process of the semiconductor device according to the fourth embodiment; 12 is a flowchart of a correction coefficient determination process for a notch filter in a semiconductor device according to a fourth embodiment; FIG. 10 is a diagram illustrating a spectrum of a signal input to a mixer in a correction coefficient determination process for a notch filter of a semiconductor device according to a fourth embodiment;

  Hereinafter, specific embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiment. In addition, for clarity of explanation, the following description and drawings are simplified as appropriate.

<Preliminary examination by the inventors>
The semiconductor device according to the embodiment generates a wireless signal used in wireless communication from a baseband signal. In recent years, in wireless communication, in addition to the increase in the number of users and the number of terminals, transmission speed has been increased. Under such circumstances, a problem of insufficient frequency resources has become apparent in wireless communication. In order to solve such a problem, efficient use of frequency resources is required in wireless communication. In mobile phones or smartphones, services such as the LTE (Long Term Evolution) method have been started as the 3.9th generation communication method, and the fourth generation LTE-A (Long Term Evolution-Advanced) method has been started. Service is scheduled to start. In LTE and LTE-A, a signal can be transmitted in a unit of a frequency band of 180 kHz called a resource block (RB) so as to flexibly cope with traffic that changes every moment. The resource block can be changed during a single communication according to the traffic situation, thereby avoiding unnecessary frequency resources and frequency interference.

  However, in wireless communication systems represented by LTE and LTE-A, when wireless communication traffic is congested, resource blocks allocated for each user are reduced, and the frequency band that can be used by one user is narrowed. Therefore, when wireless communication traffic is congested, C-IM3 (3rd Order Counter Intermodulation) occurs as a narrow band sharp spectrum at a frequency relatively far from the desired wave. Since this C-IM3 is generated at a frequency relatively distant from the desired wave, there is a case where it enters into another adjacent band as an unnecessary wave, which causes a problem.

  As a specific example, when using the uplink frequency (1920-1980 MHz) of band 1 in LTE, the frequency C-88 is included in the frequency (1884.5-1919.6 MHz) used in PHS (Personal Handy-phone System). IM3 may occur. In another example, when the uplink frequency (777-787 MHz) of band 13 is used, a C-IM3 component may be generated in the public safety band (769-775 MHz).

  The C-IM3 is becoming a problem as a result of recent progress in noise reduction technology. In recent high-frequency ICs for wireless communication, a noise reduction technique for suppressing noise outside the band used by the device itself is used. In this noise reduction technique, for example, a configuration with a simple analog circuit configuration and a relatively high S / N ratio by increasing the signal level (S) in the analog circuit is used. Specifically, an analog mixer unit used for frequency conversion such as frequency up-conversion and down-conversion uses a method of increasing the apparent signal amplitude by switching the mixer using a rectangular wave as a local signal. There are many cases. When a rectangular wave is used for the local signal, a third harmonic is generated due to the characteristic of the rectangular wave. Since the modulation signal component frequency-converted by the third harmonic by the mixer becomes an unnecessary wave, a technique for suppressing the harmonic becomes a problem.

  With respect to this problem, in Patent Document 1, an inductor and a capacitor are arranged at the mixer output to form a notch filter, thereby suppressing unwanted waves associated with the third harmonic of the local signal.

  The main cause of the increase in C-IM3 is that the third harmonic component of the local signal that is a rectangular wave is amplified by the third distortion component generated by a power amplifier or the like connected to the subsequent stage of the mixer. I know. On the other hand, it is known that the third order distortion in the power amplifier is reduced by increasing the power consumption of the power amplifier and improving the linear characteristics of the power amplifier. Therefore, there is a method for realizing reduction of C-IM3 by increasing the power consumption of the power amplifier. However, in this case, the power consumption of the semiconductor device increases, which is a problem.

<Configuration of Semiconductor Device According to First Embodiment>
In the semiconductor device 1 according to the first embodiment, the influence on the other band of the C-IM 3 is prevented by a method different from the addition of a notch filter or an increase in power consumption of the power amplifier. Specifically, in the semiconductor device 1 according to the first embodiment, the frequency of the baseband signal and the frequency of the local signal are shifted in the opposite direction by the same shift amount. Thereby, in the semiconductor device 1 according to the first embodiment, the position of the C-IM 3 with respect to the frequency band of the desired wave is shifted, thereby reducing the influence of the C-IM 3 on other bands. A specific configuration of the semiconductor device 1 according to the first embodiment will be described in detail below.

  FIG. 1 shows a block diagram of a semiconductor device 1 according to the first embodiment. The block diagram of the semiconductor device 1 shown in FIG. 1 shows a transmission circuit portion of the semiconductor device, and the semiconductor device 1 includes other circuits not shown.

  As illustrated in FIG. 1, the semiconductor device 1 according to the first embodiment includes a digital signal processing unit 10, an analog back end unit 11, an analog front end unit 12, a local signal generation unit 13, and a frequency control unit 14. The semiconductor device 1 according to the first embodiment modulates a baseband signal with a local signal and outputs a carrier signal Sout. This baseband signal includes a Q signal that is an in-phase component and an I signal that is a quadrature component.

  The digital signal processing unit 10 shifts the frequency of the first baseband signal B1 according to the first frequency shift signal (for example, the frequency shift signal FS1), and outputs the second baseband signal B2. In FIG. 1, the shift amount given by the frequency shift signal FS1 is x. The digital signal processing unit 10 includes a frequency shift unit 20, amplifier conversion circuits 21 and 22, low-pass filters 23 and 24, down-conversion circuits 25 and 26, and adders 27 and 28.

  The amplifier conversion circuit 21, the low-pass filter 23, and the down-conversion circuit 25 convert the sampling frequency of the Q signal SQ0 in the first baseband signal B1 by three circuits and output the Q signal SQ1. In addition, the amplifier conversion circuit 22, the low-pass filter 24, and the down-conversion circuit 26 convert the sampling frequency of the I signal SI0 in the first baseband signal B1 by three circuits, and output the I signal SI1.

  The frequency shift unit 20 shifts the frequencies of the Q signal SQ1 and the I signal SI1 based on the shift amount x given by the frequency shift signal FS1, and outputs the Q signal SQ2 and the I signal SI2. That is, when the frequency of the Q signal SQ1 and the I signal SI1 is w, the frequency shift unit 20 sets the frequency of the Q signal SQ2 and the I signal SI2 to w + x. A detailed description of the frequency shift unit 20 will be described later.

  The adder 27 corrects the DC offset of the Q signal SQ2 according to the offset correction coefficient indicated by the DC offset correction signal DOC, and outputs the corrected signal to the analog back end unit 11 at the subsequent stage. The adder 28 corrects the DC offset of the I signal SI <b> 2 according to the offset correction coefficient indicated by the DC offset correction signal DOC and outputs the corrected signal to the subsequent analog back end unit 11. A signal including the Q signal output from the adder 27 and the I signal output from the adder 28 becomes the second baseband signal B2.

  The analog back end unit 11 converts the second baseband signal B2 into an analog signal, and generates a third baseband signal B2. The analog back end unit 11 includes digital-analog conversion circuits 31 and 32 and low-pass filters 33 and 34.

  The digital-analog conversion circuit 31 converts the Q signal in the second baseband signal B2 into an analog signal. The low-pass filter 33 performs a low-pass filter process on the Q signal converted into an analog signal by the digital-analog conversion circuit 31, and outputs a Q signal SQ3. The digital-analog conversion circuit 32 converts the I signal of the second baseband signal B2 into an analog signal. The low-pass filter 34 performs a low-pass filter process on the Q signal converted into an analog signal by the digital-analog conversion circuit 32 and outputs an I signal SI3. A signal including the Q signal SQ3 and the I signal SI3 becomes the third baseband signal B3.

  The analog front end unit 12 modulates the third baseband signal B3 with the local signal fLo to generate a carrier signal Sout to be transmitted. Here, the local signal fLo includes a first local signal fLo1 and a second local signal fLo2. The first local signal fLo1 and the second local signal fLo2 are signals that are orthogonal to each other. The analog front end unit 12 includes a power amplifier 40 and mixers 41 and 42.

  The mixer 41 outputs a modulation signal obtained by modulating the Q signal SQ3 of the third baseband signal B3 with the local signal fLo1. The mixer 42 outputs a modulation signal obtained by modulating the I signal SI3 with the local signal fLo2 in the third baseband signal B3. The power amplifier 40 amplifies the modulation signal output from the mixer 41 and the mixer 42 and outputs a carrier signal Sout.

  The local signal generator 13 generates a local signal. Further, the local signal generation unit 13 changes the frequency of the local signal fLo from the basic local frequency according to a second frequency shift signal (for example, the frequency shift signal FS2) instructing a frequency shift in a direction opposite to the frequency shift signal FS1. Shift. The local signal generation unit 13 includes an oscillator 50 and a frequency dividing circuit 51.

  The oscillator 50 outputs a clock signal that is a source of the local signal fLo. The frequency of the clock signal output from the oscillator 50 is determined according to the frequency shift signal FS2, and the frequency when the shift amount indicated by the frequency shift signal FS2 is zero is set as a basic frequency. That is, in the first embodiment, it is assumed that the value indicating the fundamental frequency and the value indicating the shift amount are included by the frequency shift signal FS2. The frequency dividing circuit 51 divides the clock signal output from the oscillator 50 and outputs the local signal fLo1 and the local signal fLo2.

  The local signal fLo1 and the local signal fLo2 are signals having phases that are orthogonal to each other. Further, the frequency of the local signal fLo1 and the local signal fLo2 and the frequency of the clock signal output from the oscillator 50 have a ratio corresponding to the frequency dividing ratio of the frequency dividing circuit 51. That is, in the first embodiment, when the shift amount of the local signals fLo1 and fLo2 is x and the frequency division ratio of the frequency divider circuit 51 is N, the shift amount given to the oscillator 50 by the frequency shift signal FS2 is xN. In FIG. 1, the shift amount x indicated by the frequency shift signal FS2 is shown as indicating the shift amounts of the local signals fLo1 and fLo2.

  The frequency control unit 14 outputs a first frequency shift signal (for example, the frequency shift signal FS1) and a second frequency shift signal (for example, the frequency shift signal FS2). Further, the frequency control unit 14 determines the frequency shift amount x indicated by the frequency shift signal FS1 and the frequency shift signal FS2 according to the frequency of the carrier signal Sout. Specifically, the frequency control unit 14 determines the frequency shift amount x according to the occupied band of the carrier signal Sout in the communication channel and the arrangement of the carrier signal Sout in the communication channel. Note that the frequency control unit 14 receives, for example, an instruction for designating the frequency band of the carrier signal Sout from a base station or the like, and sets the frequency band of the carrier signal Sout based on the instruction.

  The frequency control unit 14 includes a memory 52 and a control instruction circuit 53. The memory 52 stores a shift amount setting table that defines the relationship between the frequency of the carrier signal and the frequency shift amount. The control instruction circuit 53 outputs a frequency designation signal for designating the frequency of the carrier signal Sout to the memory 52 in accordance with a signal for designating the frequency band of the carrier signal Sout given from the outside. The memory 52 outputs the frequency shift amount associated with the frequency designation signal as the frequency shift amount component of the frequency shift signal FS2 and the frequency shift signal FS1.

  Next, details of the frequency shift unit 20 will be described. FIG. 2 is a block diagram of the frequency shift unit 20 according to the first embodiment. As illustrated in FIG. 20, the frequency shift unit 20 generates the Q signal SQ2 and the I signal SI2 based on the expressions expressed by the expressions (1) and (2). The frequency shift unit 20 has a circuit configuration for realizing the expressions (1) and (2).

SI2 = cos (xt) * SI1-sin (xt) * SQ1 (1)

SQ2 = sin (st) * SI1 + cos (xt) * SQ1 (2)

  The frequency shift unit 20 includes multipliers 60, 61, 66, and 68, sign inversion circuits 62 and 63, selectors 64 and 65, adders 67 and 69, and sine wave tables 70 and 71. The sine wave table 70 is a memory, for example, and stores table information for generating a sine wave according to the shift amount x indicated by the frequency shift signal FS1. The cosine wave table 71 is a memory, for example, and stores table information for generating a cosine wave according to the shift amount x indicated by the frequency shift signal FS2.

  The multiplier 60 outputs a value obtained by multiplying the Q signal SQ1 by a value (for example, sin (xt)) output from the sine wave table 70. The sign inversion circuit 62 inverts the sign of the value output from the multiplier 60 and outputs the result. The selector 64 selects either the output value of the multiplier 60 or the output value of the sign inverting circuit 62 according to the code value sig indicating the sign component of the frequency shift amount x given as the frequency shift signal FS1. Output. Specifically, if the sign value sig is positive, the selector 64 selects and outputs the output value of the sign inverting circuit 62 input to the “L” side. On the other hand, if the sign value sig is negative, the selector 64 selects and outputs the output value of the multiplier 60 input to the “H” side.

  The multiplier 66 outputs a value obtained by multiplying the I signal SI1 by a value (for example, cos (xt)) output from the cosine wave table 71. Adder 67 outputs a value obtained by adding the output value of multiplier 66 and the output value of selector 64 as I signal SI2. That is, the value output from the adder 67 is the value indicated by the expression (1).

  The multiplier 61 outputs a value obtained by multiplying the I signal SI1 by a value (for example, sin (xt)) output from the sine wave table 70. The sign inversion circuit 63 inverts the sign of the value output from the multiplier 61 and outputs the result. The selector 65 selects either the output value of the multiplier 61 or the output value of the sign inverting circuit 63 according to the code value sig indicating the sign component of the frequency shift amount x given as the frequency shift signal FS1. Output. Specifically, the selector 65 selects and outputs the output value of the multiplier 61 input to the “L” side if the code value sig is positive. On the other hand, if the sign value sig is negative, the selector 65 selects and outputs the output value of the sign inverting circuit 62 input to the “H” side.

  The multiplier 68 outputs a value obtained by multiplying the Q signal SQ1 by a value output from the cosine wave table 71 (for example, cos (xt)). The adder 69 outputs a value obtained by adding the output value of the multiplier 68 and the output value of the selector 65 as the Q signal SQ2. That is, the value output from the adder 69 is the value indicated by the expression (2).

  Next, the operation of the semiconductor device 1 according to the first embodiment will be described. First, FIG. 3 shows a diagram showing a communication spectrum when no frequency shift is performed in the semiconductor device 1 according to the first embodiment.

  The example shown in FIG. 3 is an example in which communication using the band 13 (band frequency band = 777 MHz to 787 MHz) as a communication channel is performed. In this case, an emergency radio channel having a frequency band of 769 MHz to 775 MHz is defined under 2 MHz of the band 13. The emergency radio channel is also called a public safety band (PS band).

  In the example shown in FIG. 3, resource blocks in a frequency band near the end of a frequency band (hereinafter simply referred to as a band frequency band) used as a communication channel are allocated to the user. In FIG. 3, the frequency band assigned to the user is shown as a desired wave. In this case, when the frequency shift is not performed, the frequency of the local signal fLo is 782 MHz, which is the center frequency of the band frequency band. Therefore, C-IM3 is generated in a frequency band that is lower than the local signal fLo and has a frequency difference that is three times the frequency difference between the local signal fLo and the center frequency of the desired wave. At this time, the frequency band in which the C-IM 3 is generated falls within the PS band frequency band, which is a problem.

  On the other hand, in the semiconductor device 1 according to the first embodiment, the frequency band generated by the C-IM 3 is shifted by shifting the frequencies of the first baseband signal B1 and the local signal fLo by the frequency shift signals FS1 and FS2. Let FIG. 4 shows a communication spectrum when the frequency shift is performed in the semiconductor device 1 according to the first embodiment.

  The example shown in FIG. 4 uses the desired wave in the same frequency band as the band frequency band shown in FIG. As shown in FIG. 4, in the semiconductor device 1 according to the first embodiment, the frequency shift amount of the frequency of the local signal fLo is set to + x by the frequency shift signal FS2, and the frequency shift amount of the frequency of the first baseband signal B3 is set. Is −x. As a result, the signal output from the semiconductor device 1 according to the first embodiment has the same frequency as that of the carrier signal (for example, a desired wave) before the shift of the local signal fLo while shifting the frequency of the local signal fLo upward. Maintain bandwidth.

  Then, by performing such frequency shift, in the semiconductor device 1 according to the first embodiment, the frequency difference between the local signal fLo and the desired wave is reduced, and the frequency band generated by the C-IM 3 is changed to the PS band frequency band. And a band frequency band. As a specific numerical value, for example, when the local signal fLo is shifted upward by 2 MHz, the frequency band generated by the C-IM 3 is shifted upward by 8 MHz.

  3 and 4, the carrier leak and the IQ image signal are also shown in the drawing. Carrier leak is noise generated in the same frequency band as the local signal fLo. The IQ image signal is a signal generated in the frequency band on the opposite side across the local signal fLo, in which the frequency difference with the local signal fLo is the same frequency band as the desired wave.

  From the above description, the semiconductor device 1 according to the first embodiment can shift the frequencies of the first baseband signal B1 and the local signal fLo in the reverse direction by the same shift amount. And the semiconductor device 1 concerning Embodiment 1 can shift the frequency band of C-IM3, maintaining the band of a carrier frequency using the said frequency shift function. As a result, the semiconductor device 1 according to the first embodiment has the C-IM3 in the case where the carrier signal is at the end of the band frequency band and the C-IM 3 becomes an interference wave to the frequency band of another band. By shifting the frequency band of IM3 outside the frequency band of other bands, it is possible to prevent an interference wave from being output by the carrier signal output from the own apparatus.

  In addition, since the semiconductor device 1 according to the first embodiment can prevent interference waves to other band frequency bands by shifting the frequency band of the C-IM 3, for example, a notch filter as in Patent Document 1 is used. There is no need to provide it. That is, the semiconductor device 1 according to the first embodiment can prevent the influence of unnecessary waves on other bands without increasing the circuit area.

  Further, the semiconductor device 1 according to the first embodiment shifts the frequency band of the C-IM 3 by shifting the frequencies of the first baseband signal B1 and the local signal. Therefore, for example, the influence of the C-IM 3 on other band frequency bands can be reduced without taking measures such as setting the power consumption of the power amplifier high to reduce the third-order distortion of the power amplifier. . That is, the semiconductor device 1 according to the first embodiment prevents the C-IM 3 generated due to the carrier signal output from the own device from affecting other bands without increasing the power consumption. Can do.

Embodiment 2
In the second embodiment, another form of the semiconductor device 1 according to the first embodiment will be described. FIG. 5 shows a block diagram of the semiconductor device 2 according to the second embodiment. In the description of the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  As illustrated in FIG. 5, the semiconductor device 2 according to the second embodiment includes a digital signal processing unit 10 a instead of the digital signal processing unit 10 of the first embodiment. The digital signal processing unit 10a is obtained by adding a first correction circuit (for example, an IQ image correction unit 29) to the digital signal processing unit 10.

  The IQ image correction unit 29 first corrects a phase error and an amplitude error between an in-phase component signal (for example, Q signal) and a quadrature component signal (for example, I signal) included in the first baseband signal B1. Correction is performed according to a coefficient (for example, a correction coefficient included in the IQ image correction signal IQC). In the semiconductor device 2 according to the second embodiment, it is assumed that the IQ image correction signal IQC includes two correction coefficients, an amplitude correction coefficient and a phase correction coefficient. In the second embodiment, it is assumed that the amplitude correction coefficient and the phase correction coefficient are determined in advance based on errors measured by measurement or the like.

  The IQ image signal is generated due to a phase difference and an amplitude difference between the Q signal and the I signal. Therefore, in the semiconductor device 2 according to the second embodiment, the signal intensity of the IQ image signal is suppressed to be small by performing correction so as to reduce the phase difference and the amplitude difference between the Q signal and the I signal.

  Therefore, details of the IQ image correction unit 29 will be described. FIG. 6 is a block diagram of the IQ image correction unit 29 according to the second embodiment. As illustrated in FIG. 6, the IQ image correction unit 29 includes an amplitude correction unit 81 and a phase correction unit 82. The amplitude and phase corrected by the IQ image correction unit 29 are used to correct errors that occur in the entire path through which the Q signal and the I signal are transmitted in the semiconductor device 2, and the Q signal output from the IQ image correction unit 29 and The error in the amplitude and phase of the I signal is not necessarily smaller than the Q signal and the I signal input to the IQ image correction unit 29.

  The amplitude correction unit 81 corrects the amplitude level of the Q signal so as to match the amplitude level of the I signal. More specifically, the amplitude correction unit 81 includes a multiplier 83. The multiplier 83 multiplies the amplitude correction coefficient ACC included in the IQ image correction signal IQC and the Q signal SQ2, and outputs the result as a Q signal SQ21. Then, by performing signal processing by the subsequent circuit on the Q signal SQ21, all the amplitudes of the signals output from the mixers 41 and 42 are made uniform.

  The phase correction unit 82 manipulates the phase of the I signal so that the relationship between the phase of the I signal and the phase of the Q signal is orthogonal. More specifically, the phase correction unit 82 includes a multiplier 84 and an adder 85. Then, the multiplier 84 outputs a value obtained by multiplying the phase correction coefficient PCC included in the IQ image correction signal IQC and the Q signal SQ2. Adder 85 adds I signal SI2 and the output value of multiplier 84, and outputs the result as I signal SI21. Then, by performing signal processing by the subsequent circuit on the I signal SI21, all the amplitudes of the signals output from the mixers 41 and 42 are made uniform.

  Next, the operation of the semiconductor device 2 according to the second embodiment will be described. FIG. 7 shows a communication spectrum when IQ image correction is performed in the semiconductor device 2 according to the second embodiment.

  The example shown in FIG. 7 shows a state that can occur, for example, by performing frequency switching processing of a desired wave from the communication state shown in FIG. For example, in LTE, the number of resource blocks in the resource block arrangement changes during communication according to the state of communication traffic. The example shown in FIG. 7 shows a case where the status of communication traffic is changed and the arrangement of resource blocks is changed to the low frequency side in the communication state shown in FIG. When such a resource block change occurs, no problem occurs if the frequency of the local signal fLo can be changed immediately. However, when the frequency of the local signal fLo is switched, transient noise occurs. This transient noise must be suppressed except during a period in which it is allowed to occur. For this reason, there is a case where the local signal fLo cannot be switched in order to suppress the generation of this transient noise. That is, the example shown in FIG. 7 shows a case where only the frequency switching of the resource block is performed and the frequency of the local signal fLo cannot be changed from the frequency shown in FIG.

  In such a case, as shown in FIG. 7, the IQ image signal generated in the opposite frequency band across the local signal fLo is transferred to another band frequency band adjacent to the band frequency band used by the own apparatus. Will occur.

  However, in the semiconductor device 2 according to the second embodiment, by correcting the IQ image using the IQ image correction unit 29, the signal intensity of the IQ image signal generated in the other band frequency band can be suppressed. In this way, by suppressing the signal strength, it is possible to reduce the influence of the IQ image signal generated in its own communication on other communications using other band frequency bands.

  From the above description, the semiconductor device 2 according to the second embodiment has the IQ image correction unit 29 to increase the frequency difference between the carrier signal Sout and the local signal fLo. Even if it occurs in the frequency band, the influence of the IQ image signal on other band frequency bands can be suppressed.

  Further, the semiconductor device 2 according to the second embodiment does not need to add a notch filter or increase the power of the power amplifier, like the semiconductor device 1 according to the first embodiment. Reduction of power consumption can be realized.

Embodiment 3
In the third embodiment, another form of the oscillator 50 of the first and second embodiments will be described. A block diagram of the oscillator 50 according to the third embodiment is shown in FIG. As illustrated in FIG. 8, the oscillator 50 according to the third embodiment includes a phase detector 90, a loop filter 91, a voltage control oscillator 92, and a frequency divider circuit 93.

  The phase detector 90 compares the phases of the reference clock RCLK and the feedback clock output from the frequency dividing circuit 93, and outputs a voltage having a magnitude corresponding to the phase difference between the two clock signals. The loop filter 91 performs a filtering process on the voltage output from the phase detector 90 and outputs it to the voltage controlled oscillator 92. Further, the loop filter 91 can change the band of the filter. The change of the filter band of the loop filter 91 is performed by a processing unit such as the frequency control unit 14 according to the communication status, for example. The voltage controlled oscillator 92 outputs the clock signal CLKo at an oscillation frequency corresponding to the voltage value output from the loop filter 91. The clock signal CLKo is frequency-divided by the frequency dividing circuit 51 to become a local signal fLo. The frequency dividing circuit 93 divides the clock signal CLKo to generate a feedback clock. The frequency dividing circuit 93 switches the frequency dividing ratio according to the fundamental frequency and the frequency shift amount x indicated by the frequency shift signal FS2. The frequency of the clock signal CLKo is determined based on the frequency division ratio and the frequency of the reference clock RCLK.

  Here, in the first and second embodiments, the oscillation frequency of the local signal fLo is switched. However, in switching the oscillation frequency of the oscillator 50, transient noise is generated in the time until the oscillation frequency converges, and the time until the oscillation frequency converges may be longer than the transient period in which the transient noise is allowed. There is.

  For example, in LTE, one slot, which is a unit used for communication, is 500 μsec, and a period of 20 μsec before and after the boundary between slots is defined as a transient period (TP). In the semiconductor device according to the third embodiment, during the transition period, the loop band of the loop filter 91 of the oscillator 50 is widened so that the convergence of the oscillation frequency of the oscillator 50 is accelerated.

  FIG. 9 shows a timing chart showing local signal frequency switching timing in the semiconductor device according to the third embodiment. As shown in FIG. 9, in LTE, the transition period TP is set to 20 μsec before and after the slot boundary. In the semiconductor device according to the third embodiment, the frequency switching period Tw is set to a period shorter than the sum of two transition periods positioned at the boundary between adjacent slots. The semiconductor device according to the third embodiment can switch the frequency within the frequency switching period Tw by setting the loop gain of the oscillator 50 high during the frequency switching period Tw.

  From the above description, in the semiconductor device according to the third embodiment, the frequency switching period Tw is set to a period shorter than the total time of the transient periods located at the boundary between the two slots, and the loop filter of the oscillator 50 is set in the frequency switching period Tw. The loop band of 91 is widened. Thereby, the semiconductor device according to the third embodiment can frequently switch the frequency of the local signal fLo.

Embodiment 4
In the fourth embodiment, another form of the semiconductor device 2 according to the second embodiment will be described. FIG. 10 shows a block diagram of the semiconductor device 3 according to the fourth embodiment. In the description of the fourth embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals as those in the first and second embodiments, and the description thereof is omitted.

  As shown in FIG. 10, in the semiconductor device 3 according to the fourth embodiment, a correction coefficient determination circuit 100 is added to the semiconductor device 2 according to the second embodiment, and an analog front end unit 12 a is substituted for the analog front end unit 12. Is used.

  The analog front end unit 12 a is obtained by adding a notch filter 43 to the analog front end unit 12. The notch filter 43 is a band rejection filter which is provided between the mixers 41 and 42 and the amplifier 43 and whose frequency characteristics are corrected according to a second correction coefficient (for example, a filter correction coefficient NOC). The notch filter 43 has an inductance and a capacitance arranged in parallel between differential wirings to which a differential signal that is an output signal of the mixer is transmitted. The notch filter 43 has a plurality of capacitors arranged in an array, for example. Each capacitor is composed of a transistor, and the capacitance is switched between valid and invalid by a voltage applied to a control terminal (for example, gate) of the transistor. The capacitance of the notch filter 43 becomes a variable capacitance by having such a configuration. The notch filter 43 changes the frequency characteristic by switching the number of capacitors that are enabled by the filter correction signal NOC.

  In recent years, many wireless devices that support a plurality of bands have been proposed. For this reason, it is conceivable that there will be a band that cannot be solved simply by performing frequency shift control on generation of unnecessary waves such as C-IM3 in other bands. When using a band in which generation of C-IM3 in other bands is inevitable, suppression of C-IM3 is necessary, and measures such as mounting a filter after the mixer output are required. The C-IM 3 can be suppressed by suppressing the third harmonic of the local frequency fLo at the outputs of the mixers 41 and 42. From the viewpoint of low noise, a notch filter 43 composed of an inductance and a capacitance is effective as a filter for suppressing the third harmonic of the mixer output. However, the notch frequency in the notch filter is generally highly sensitive due to sample variations, and it may be difficult to ensure the degree of suppression. In order to solve this, the notch frequency in the notch filter may be corrected.

  The correction of the notch frequency of the notch filter can be calculated using, for example, a process common to the correction coefficient indicated by the IQ image correction signal IQC applied to the IQ image correction unit 29. Therefore, in the semiconductor device 3 according to the fourth embodiment, the correction coefficient determining circuit 100 determines the correction coefficient indicated by the DC offset correction signal DOC, the IQ image correction signal IQC, and the filter correction signal NOC within the own apparatus. A decision circuit 100 is used.

  As illustrated in FIG. 10, the correction coefficient determination circuit 100 includes an amplifier 101, a mixer 102, a switch 103, a low-pass filter 104, a DC prevention filter 105, an analog-digital conversion circuit 106, a band-pass filter 107, and a correction coefficient determination unit 108. .

  The amplifier 101 amplifies the output signals of the mixers 41 and 42 and outputs the amplified signals to the mixer 102. The amplifier 101 includes a low gain mode for amplifying a signal with a low gain and a high gain mode for amplifying a signal with a high gain.

  The mixer 102 outputs a demodulated signal obtained by demodulating the output signal of the mixers 41 and 42 with the output signal of the mixer 102 according to the correction value determination mode, or outputs the output signals of the mixers 41 and 42 to the local signal fLo1 and the local signal fLo2. The output of the demodulated signal demodulated is switched. Specifically, in the first correction value determination mode in which the mixer 102 determines the DC offset correction value indicated by the DC offset correction signal DOC, the output signal of the mixers 41 and 42 is either the local signal fLo1 or the local signal fLo2. On the other hand, the demodulated demodulated signal is output. Further, in the second correction value determination mode in which the mixer 102 determines the correction value indicated by the IQ image correction signal IQC and the filter correction signal NOC, the demodulation is performed by demodulating the output signals of the mixers 41 and 42 with the output signal of the mixer 102. Output a signal. Note that the mixing processing in the second correction value determination mode is referred to as self-mixing.

  By performing this self-mixing, the correction coefficient determination circuit 100 detects a phase error and an amplitude error between the Q signal and the I signal included in the first baseband signal B1, and converts them into the phase error and the amplitude error. A first correction coefficient (for example, an amplitude correction coefficient ACC and a phase correction coefficient PCC indicated by the IQ image correction signal IQC) is determined. In addition, the correction coefficient determination circuit 100 performs a self-mixing to artificially reproduce the third harmonic component included in the carrier signal, and the second correction coefficient (for example, the third harmonic component is suppressed) (for example, The filter correction coefficient indicated by the filter correction signal NOC) is determined.

  The switch 103 switches between enabling and disabling a path that bypasses the low-pass filter 104 and the DC prevention filter 105. The switch 103 is turned on in the first correction value determination mode, and enables a path that bypasses the low-pass filter 104 and the direct current prevention filter 105. The switch 103 is turned off in the second correction value determination mode, and invalidates the path bypassing the low-pass filter 104 and the direct current prevention filter 105.

  The low pass filter 104 reduces high frequency noise in the output signal of the mixer 102 and outputs the reduced signal to the DC prevention filter 105. The direct current prevention filter 105 is, for example, a capacitor, and removes the direct current component of the output signal of the low pass filter 104 and transmits it to the subsequent analog-digital conversion circuit 106.

  The analog-digital conversion circuit 106 outputs a digital value corresponding to the analog voltage level of the input signal. The band pass filter 107 attenuates and outputs a signal component in a band other than a predetermined band with respect to the output value of the analog-digital conversion circuit 106.

Based on the output value of the analog-to-digital conversion circuit 106 and the output value of the band-pass filter 107, the correction coefficient determination unit 108 is configured to detect the DC offset, IQ, The image signal and the signal level or signal intensity of the C-IM 3 are determined to determine an optimum correction coefficient. The correction coefficient determination unit 108 holds the determined correction value and outputs the correction value held in the normal state of the semiconductor device 3 to each circuit block.

  Next, correction value determination processing in the semiconductor device 3 according to the fourth embodiment will be described. First, FIG. 11 shows a flowchart of DC offset correction coefficient determination processing in the semiconductor device 3 according to the fourth embodiment.

  As shown in FIG. 11, when determining a DC offset correction coefficient, the semiconductor device 3 first performs an initialization step S1. In this initialization step S1, the semiconductor device 3 sets the circuit state as follows. The Q signal SQ0 and the I signal QI0 are stopped. The frequency shift signal FS1 is a fixed value. The DC offset correction signal DOC is set to an initial value. The amplitude correction coefficient ACC and the phase correction signal PCC are set to initial values. A filter correction coefficient (hereinafter referred to as filter correction coefficient NOC) indicated by the filter correction signal NOC is set to an initial value. The amplifier 101 is stopped. A local signal fLo is input to the mixer 102. The switch 103 is turned on.

  By this initialization process, the semiconductor device 3 enters a state in which no signal is output except for the adders 27 and 28 which are DC offset correction units of the digital signal processing unit 10a. Therefore, in the semiconductor device 3, the component that was DC at the input of the mixers 41 and 42 becomes only the carrier leak signal component at the output of the mixers 41 and 42. This signal is down-converted by using the local signal that is originally up-converted by the detection mixer 102, so that it becomes the original I-phase or Q-phase DC component. For the DC components of the I phase and the Q phase, the I phase and the Q phase are distinguished depending on whether a sine wave or a cosine wave from the local oscillation unit is input to the signal on one side of the mixer 102 for detection. It is possible.

  In steps S2 to S4, the semiconductor device 3 according to the fourth embodiment searches for a DC offset setting value at which the DC component at the output of the detection mixer 102 becomes zero. More specifically, in step S2, the DC offset amount is evaluated based on the output value of the mixer 102. In step S3, it is determined whether the minimum value of the DC offset amount has been determined. In step S4, the DC offset correction coefficient DOC is updated using the candidate value set as a candidate. When it is determined in step S3 that the minimum value of the DC offset amount has been determined, the correction coefficient determination unit 108 sets the DC offset correction coefficient DOC in the state of the minimum value as a setting value that reflects at the start of communication. Hold.

  Subsequently, an IQ image correction coefficient determination process in the semiconductor device 3 according to the fourth embodiment will be described. First, FIG. 12 shows a flowchart of IQ image correction coefficient determination processing in the semiconductor device 3 according to the fourth embodiment.

  As shown in FIG. 12, when determining the IQ image correction coefficient, the semiconductor device 3 first performs the initialization step S11. In this initialization step S11, the semiconductor device 3 sets the circuit state as follows. The Q signal SQ0 and the I signal QI0 are stopped. The frequency shift signal FS1 is set to the sweep mode, and the frequency shift unit 29 is caused to output the continuous wave CW. The DC offset correction signal DOC is set to the applied correction coefficient determined in the process of FIG. The amplitude correction coefficient ACC and the phase correction signal PCC are set to initial values. A filter correction coefficient (hereinafter referred to as filter correction coefficient NOC) indicated by the filter correction signal NOC is set to an initial value. The amplifier 101 is operated in the low gain mode. The input of the local signal fLo to the mixer 102 is stopped, and the output value of the amplifier 101 is input. The switch 103 is turned off.

  The semiconductor device 3 is in a state where self-mixing is performed in which the output signal of the mixers 41 and 42 is mixed by the output signal of the mixers 41 and 42 in the mixer 102 by the above circuit configuration. This IQ image correction is performed in a period before the start of communication. In the IQ image correction coefficient determination process, the semiconductor device 3 generates CW (Continuous Wave) at the outputs of the mixers 41 and 42 using the sine wave table 70 and the cosine wave table 71 in the frequency shift unit 29. At this time, if the signal level is set low so that distortion does not occur in the analog circuit, there is no fear of unnecessary waves, which is convenient. At this time, if the current of the amplifier 101 is increased, the occurrence of distortion in the analog circuit can be further suppressed.

  FIG. 13 shows a spectrum of a signal input to the mixer 102 when determining the IQ image correction coefficient. As shown in FIG. 13, when determining the correction coefficient of the IQ image, since the generation of distortion in the amplifier 101 is suppressed in order to suppress the generation of distortion in the amplifier 101, the output signal of the amplifier 101 is C-IM3 or IM3 components do not occur, and the output signals of the mixers 41 and 42 and the output signal of the amplifier 101 have substantially the same spectrum.

  Here, it is assumed that the sine wave table 70 and the cosine wave table 71 are set so that the continuous wave CW is generated at a position 1 MHz from the local frequency. In this case, the down-conversion components output from the detection mixer 102 include the following components. The first component is a DC component generated by multiplication of the continuous wave CW output from the mixers 41 and 42 and the continuous wave CW output from the amplifier 101. The second component includes the continuous wave CW output from the mixers 41 and 42 and the image IQ output from the amplifier 101, or the image IQ output from the mixers 41 and 42 and the continuous wave CW output from the amplifier 101. This is a 2 MHz signal component generated by multiplication. The third component includes the continuous wave CW output from the mixers 41 and 42, the continuous wave output from the amplifier 101, the carrier leak CL of the signal output from the mixers 41 and 42, and the signal output from the amplifier 101. It is a 1 MHz signal component generated by the carrier leak CL. The fourth component is output from the amplifier 101, the image IQ of the signal output from the mixer 41, the image IQ of the signal output from the amplifier 101, the carrier leak CL of the signal output from the mixer 41, 42, and the amplifier 101. 1 MHz signal component generated by carrier leak CL of the signal. The signal component of 2 MHz included in the output of the detection mixer 102 outputs a level depending on the power of the image IQ of the signal output from the mixers 41 and 42 and the image IQ of the signal output from the amplifier 101. Therefore, by extracting the 2 MHz level through the band-pass filter 107 after the analog-digital conversion circuit 106, the image IQ of the signal output indirectly from the mixers 41 and 42 and the image of the signal output from the amplifier 101 are extracted. IQ level can be observed. It is possible to automatically correct the IQ image by sweeping the amplitude correction coefficient ACC and the phase correction coefficient PCC of the IQ image correction unit 29 and searching for a setting that minimizes the 2 MHz level.

  Therefore, in the semiconductor device 3 according to the fourth embodiment, the signal intensity evaluation process of the IQ image for extracting 2 MHz included in the output of the detection mixer 102 is performed in step S12. Further, the semiconductor device 3 determines whether or not the minimum value of the signal intensity of the IQ image has been determined in step S13. Further, the semiconductor device 3 updates the amplitude correction coefficient ACC and the phase correction coefficient PCC until the minimum value of the signal intensity of the IQ image is determined in step S13 (step S14).

  When it is determined in step S13 that the minimum value of the signal intensity of the IQ image has been determined, the correction coefficient determination unit 108 starts communication with the amplitude correction coefficient ACC and the phase correction coefficient PCC in the state where the minimum value has been reached. It is held as a setting value that is sometimes reflected (step S15).

  Subsequently, a filter correction coefficient determination process in the semiconductor device 3 according to the fourth embodiment will be described. First, FIG. 14 shows a flowchart of IQ image correction coefficient determination processing in the semiconductor device 3 according to the fourth embodiment.

  As shown in FIG. 14, when determining the filter correction coefficient, the semiconductor device 3 first executes the initialization step S21. In this initialization step S21, the semiconductor device 3 sets the circuit state as follows. The Q signal SQ0 and the I signal QI0 are stopped. The frequency shift signal FS1 is set to the sweep mode, and the frequency shift unit 29 is caused to output the continuous wave CW. The DC offset correction signal DOC is set to the applied correction coefficient determined in the process of FIG. The amplitude correction coefficient ACC and the phase correction signal PCC are set to the applied correction coefficient determined in the process of FIG. The filter correction coefficient NOC is set to an initial value. The amplifier 101 is operated in the high gain mode. The input of the local signal fLo to the mixer 102 is stopped, and the output value of the amplifier 101 is input. The switch 103 is turned off.

  The semiconductor device 3 is in a state where self-mixing is performed in which the output signal of the mixers 41 and 42 is mixed by the output signal of the mixers 41 and 42 in the mixer 102 by the above circuit configuration. This filter correction is performed in a period before the start of communication. In the filter correction coefficient determination process, the semiconductor device 3 generates CW (Continuous Wave) at the outputs of the mixers 41 and 42 using the sine wave table 70 and the cosine wave table 71 in the frequency shift unit 29. At this time, if the signal level is set to be high so that distortion occurs in the analog circuit, it is convenient that an unnecessary wave can be generated in a pseudo manner. At this time, if the current of the amplifier 101 is reduced, distortion in the analog circuit can be further generated.

  FIG. 15 shows a spectrum of a signal input to the mixer 102 when determining the filter correction coefficient NOC. As shown in FIG. 15, when determining the filter correction coefficient NOC, in order to intentionally generate distortion in the amplifier 101, a component of C-IM3 or IM3 is generated in the output signal of the amplifier 101, and the mixer 41, There is a difference between the output signal of 42 and the output signal of the amplifier 101 as to whether or not C-IM3 and IM3 exist.

  Here, it is assumed that the sine wave table 70 and the cosine wave table 71 are set so that the continuous wave CW is generated at a position of 0.5 MHz from the local frequency. Among the signals after down-conversion by the detection mixer 102, the largest signals depending on the C-IM3 include the continuous wave CW output from the mixers 41 and 42 and the C-IM3 included in the signal output from the amplifier 101. There is 2 MHz resulting from multiplication. As another component down-converted to 2 MHz, there is a component generated by multiplication of the image IQ included in the output signals of the mixers 41 and 42 and IM3 included in the output signal of the amplifier 101. In order to reduce the component due to the image IQ as much as possible, the IQ image correction is performed before the notch filter correction, and the notch filter correction is performed with the level of the image IQ included in the output signals of the mixers 41 and 42 lowered. And good. 2 MHz generated in the continuous wave CW output from the mixers 41 and 42 and the C-IM3 (1007) included in the output signal of the amplifier 101 is an analog-to-digital conversion circuit 106 and a band-pass filter 107 that are common paths for IQ image correction. Extracted after processing. The semiconductor device 3 can automatically correct the notch filter 43 by sweeping the capacitance value of the notch filter 43 and searching for a setting that minimizes the level of 2 MHz that is a component caused by the C-IM 3. It is.

  Therefore, in the semiconductor device 3 according to the fourth embodiment, the signal intensity evaluation process of the C-IM 3 for extracting 2 MHz included in the output of the detection mixer 102 is performed in step S22. Further, the semiconductor device 3 determines whether or not the minimum value of the signal intensity of the C-IM 3 has been determined in step S23. Further, the semiconductor device 3 updates the filter correction coefficient NOC until the minimum value of the signal intensity of the C-IM 3 is determined in step S23 (step S24).

  When it is determined in step S23 that the minimum value of the signal intensity of C-IM3 has been determined, the correction coefficient determination unit 108 is configured to reflect the filter correction coefficient NOC in the state of the minimum value at the start of communication. It holds as a value (step S25).

  From the above description, the semiconductor device 3 according to the fourth embodiment has the notch filter 43, so that even if it is not possible to cope with only the frequency shift, the signal intensity of the C-IM 3 is suppressed, The influence of C-IM3 can be reduced.

  Further, the semiconductor device 3 according to the fourth embodiment includes the correction coefficient determination circuit 100, so that the optimum correction coefficient can be determined by the processing of the own apparatus. The optimum correction coefficient varies depending on the situation (for example, the situation such as temperature) where the semiconductor device is placed. However, according to the semiconductor device 3, by determining the correction coefficient by itself, it is possible to determine the optimum correction coefficient corresponding to the change in the situation where the semiconductor device is placed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1-3 Semiconductor device 10, 10a Digital signal processing part 11 Analog back end part 12, 12a Analog front end part 13 Local signal generation part 14 Frequency control part 20 Frequency shift part 21, 21 Amplifier conversion circuit 23, 24 Low pass filter 25, 26 Down-conversion circuit 27, 28 Adder 29 IQ image correction unit 31, 32 Digital-analog conversion circuit 33, 34 Low-pass filter 40 Power amplifier 41, 42 Mixer 43 Notch filter 50 Oscillator 51 Dividing circuit 52 Memory 53 Control instruction circuit 60, 61, 66, 68 Multiplier 62, 62 Sign inversion circuit 64, 65 Selector 67, 69 Adder 70 Sine wave table 71 Cosine wave table 81 Amplitude correction unit 82 Phase correction unit 83, 84 Multiplier 85 Adder 90 Phase detector 91 Loop filter 92 Voltage controlled oscillator 93 Dividing circuit 100 Correction coefficient determination circuit 101 Amplifier 102 Mixer 103 Switch 104 Low pass filter 105 DC prevention filter 106 Analog-digital conversion circuit 107 Band pass filter 108 Correction coefficient determination unit FS1 Frequency shift signal FS2 Frequency shift signal DOC DC offset correction signal IQC IQ image correction signal NOC filter correction signal

Claims (7)

A digital signal processor that shifts the frequency of the first baseband signal according to the first frequency shift signal and outputs the second baseband signal;
An analog front-end unit that converts the second baseband signal into an analog signal to generate a third baseband signal;
An analog front-end unit that modulates the third baseband signal with a local signal to generate a carrier signal to be transmitted;
Generating the local signal and generating a local signal that shifts the frequency of the local signal from the basic local frequency in response to a second frequency shift signal that instructs a frequency shift in a direction opposite to the first frequency shift signal And
A frequency controller that outputs the first frequency shift signal and the second frequency shift signal,
The said frequency control part is a semiconductor device which determines the frequency shift amount instruct | indicated by the said 1st frequency shift signal and the said 2nd frequency shift signal according to the frequency of the said carrier signal.   The semiconductor device according to claim 1, wherein the frequency control unit determines the frequency shift amount according to an occupied band of the carrier signal in a communication channel and an arrangement of carrier signals in the communication channel.   2. The semiconductor according to claim 1, wherein the frequency control unit changes the difference between the frequency of the carrier signal and the frequency of the local signal while maintaining the frequency of the carrier signal by changing the frequency shift amount. apparatus.   The semiconductor device according to claim 1, wherein the frequency control unit determines the frequency shift amount based on a shift amount setting table that defines a relationship between the frequency of the carrier signal and the frequency shift amount. The analog front end is
A mixer that modulates the third baseband signal with a local signal to generate a modulated signal;
An amplifier that amplifies the modulated signal to generate the carrier signal,
The digital signal processor is
A first correction circuit that corrects a phase error and an amplitude error between the in-phase component signal and the quadrature component signal included in the first baseband signal according to a first correction coefficient;
The semiconductor device includes:
A phase error and an amplitude error between the in-phase component signal and the quadrature component signal included in the first baseband signal are detected by self-mixing the modulation signal, and the phase error and the amplitude error are used to detect the phase error and the amplitude error. The semiconductor device according to claim 1, further comprising a correction coefficient determination circuit that determines a first correction coefficient. The analog front end is
A mixer that modulates the third baseband signal with a local signal to generate a modulated signal;
An amplifier for amplifying the modulated signal to generate the carrier signal;
A band rejection filter provided between the mixer and the amplifier and having a frequency characteristic corrected in accordance with a second correction coefficient,
The semiconductor device includes:
A correction coefficient determination circuit that artificially reproduces the third harmonic component included in the carrier signal by self-mixing the modulation signal and determines the second correction coefficient for suppressing the third harmonic component. The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 1, wherein the local signal generation unit widens a loop band in accordance with switching of a slot that defines a communication cycle.

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