JP2010245673A - Transmitter and semiconductor integrated circuit available to the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure an operation margin when satisfying a standard of time mask specification in a transmission slot of time division multiple access system during RF transmission of an EDGE system. <P>SOLUTION: A transmitter includes a digital modulator 10, ramp generator 14, digital multiplier Mult, D/A converter 15, PLL 11, and AM modulator 13. The modulator 10 generates digital amplitude R and a digital phase θ in response to transmission data. The Mult responds to a ramp control signal of the ramp generator, an output thereof is supplied to the D/A converter, and an output thereof is supplied to the AM modulator. An RF carrier signal of the PLL is transferred to the AM modulator to generate an RF transmission signal of the EDGE system. A ramp up operation of the first half of a transmission time slot increases an analog signal of the D/A converter, and a ramp down operation of the latter half decreases the analog signal. A gain of the AM modulator is controlled to a low value while transmission power is lower than a predetermined value due to ramp up/down operation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a transmitter and a semiconductor integrated circuit that can be used for the transmitter, and in particular, to secure an operation margin when satisfying the time mask specification standard in a transmission slot of a time division multiple access system in EDGE RF transmission. It relates to technology that is useful to facilitate.

  In a communication terminal device such as a mobile phone terminal, each time slot of a plurality of time slots can be set to any of an idle state, a reception operation from the base station, and a transmission operation to the base station. Time division multiple access (TDMA) systems are known. TDMA is an abbreviation for Time-Division Multiple Access. As one of the TDMA systems, a GSM system or a GMSK system that uses only phase modulation is known. GSM is an abbreviation for Global System for Mobile Communications. GMSK is an abbreviation for Gaussian minimum Shift Keying. A method for improving the communication data transfer rate as compared with the GSM method or the GMSK method is also known. As an improvement method, an EDGE method that uses amplitude modulation together with phase modulation has recently attracted attention. Note that EDGE is an abbreviation for Enhanced Data for GSM Evolution; Enhanced Data for GPRS, and GPRS is an abbreviation for General Packet Radio Service.

  As a method of realizing the EDGE method, after a transmission signal to be transmitted is separated into a phase component and an amplitude component, feedback control is performed in each of the phase control loop and the amplitude control loop, and the phase component and amplitude component after the feedback control are performed. A polar loop method is known in which an amplifier is combined.

  Non-Patent Document 1 below describes a polar loop transmitter having a phase control loop and an amplitude control loop and supporting an EDGE transmission function. It is described that power efficiency is an important market issue in a cellular phone, and that the polar loop system has an advantage that the power efficiency is good because the RF power amplifier operates near saturation. Further, it is described that an additional advantage of the polar loop method from the saturation operation of the RF power amplifier is low noise characteristics.

  Non-Patent Document 2 below introduces several circuits and architectures as an EDGE transmitter.

  The first architecture is a system that performs polar modulation (PM) in front of an RF power amplifier (PA). In this method, a digital phase signal and a digital amplitude signal generated from a modulator are input to a ΣΔ modulator and a D / A converter, respectively. The output signal of the ΣΔ modulator is supplied to one input terminal of a phase locked loop (PLL), the output signal of the PLL is supplied to a voltage controlled oscillator (VCO), and the output signal of the VCO is connected to the other input terminal of the PLL and the mixer To one of the input terminals. The analog output signal of the D / A converter is supplied to the other input terminal of the mixer via a low-pass filter, and the output signal of the mixer is supplied to the antenna via a driver, an RF power amplifier (PA), and an isolator. .

  The second architecture is a polar transmitter system that controls the amplitude of an open-loop RF power amplifier (PA). In the second architecture, the mixer and driver of the first architecture are omitted, and the analog output signal of the D / A converter is directly supplied to the RF power amplifier (PA) through a low-pass filter. Therefore, in the RF power amplifier (PA), the bias current and / or the collector voltage are controlled via the analog control input terminal, and the amplitude modulation in the RF power amplifier (PA) is directly executed.

  The third architecture is a polar loop transmitter, and the transmission intermediate frequency signal (IF) generated from the output terminal of the modulator to which the I and Q transmission baseband signals are supplied is a phase locked loop ( PLL) and one input terminal of the amplitude control loop. The output signal of the PLL is supplied to the control input of the voltage controlled oscillator (VCO), and the output signal of the VCO is supplied to the RF signal input terminal of the RF power amplifier (PA). The output signal of the amplitude control loop is supplied to the control input terminal of the RF power amplifier (PA), and the RF output signal and power of the RF power amplifier (PA) are connected to one input terminal and the other input terminal of the down conversion gain controller. Control signals are respectively supplied. The intermediate frequency output signal of the down conversion gain controller is supplied to the negative feedback terminal of the PLL and the negative feedback terminal of the amplitude control loop, and the gain of the RF power amplifier (PA) is controlled by the output signal of the amplitude control loop.

  Further, Non-Patent Document 3 below describes a polar modulation transmitter. In this transmitter, digital transmission data is stored in a FIFO memory, and the FIFO memory is supplied to an EDGE I / Q mapping unit that generates I and Q transmission digital baseband signals. The I and Q transmitted digital baseband signals are supplied to a digital CORDIC system that converts them into amplitude and phase components. Note that CORDIC is an abbreviation for Coordinate Rotation Digital Calculation.

  The transmitter also includes a generator that generates a ramp digital control signal for performing the ramp operation of the RF power amplifier (PA), and digital multiplication is performed between the ramp digital control signal and digital amplitude information that is an amplitude component of the digital CORDIC system. Supplied to the vessel. The digital amplitude modulation information generated from the output of the digital multiplier is supplied to a regulator that controls the power supply voltage of the RF power amplifier (PA) via the D / A converter. Digital frequency modulation information, which is a phase component of the digital CORDIC system, is supplied to a digital PLL fractional frequency divider.

  Further, the following Non-Patent Document 4 describes a Polar Modulator transmitter that is different from the Polar Modulation transmitter described in Non-Patent Document 3 below. In the transmitter described in Non-Patent Document 4 below, the digital amplitude modulation information generated from the output of the digital multiplier is transmitted to the RF power amplifier (PA) via the D / A converter as described in Non-Patent Document 3 below. Instead of being supplied to a regulator that controls the power supply voltage, it is supplied to an analog multiplier. The output terminal of the analog multiplier is connected to the RF signal input terminal of the RF power amplifier (PA), and the input terminal of the analog multiplier is connected to the output of the PLL oscillator and the input of the frequency divider.

Earl McCune, “High-Efficiency, Multi-Mode, Multi-Band Terminal Power Amplifiers”, IEEE microwave magazine, March 2005, PP. 44-55. Tirdad Sowlati et al, “Quad-Band GSM / GPRS / EDGE Polar Loop Transmitter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004, PP. 2179-2189. Alex W. Hietala, “A Quad-Band 8PSK / GMSK Polar Transceiver”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006, PP. 1133-1141. Christian Mayer, “A Robst GSM / EDGE Transmitter Usage Polar Modulation Techniques”, The European Conference on Wireless Technology, 2005, 3-4 Oc. 93-96.

  Prior to the present invention, the present inventors have developed a next-generation RF signal processing supporting GSM / EDGE / WCDMA multimode and multiband transmission / reception functions capable of digital RF interface with a baseband signal processing LSI. Engaged in research and development of large-scale semiconductor integrated circuits.

  In this research and development, as the next-generation RF signal processing large-scale semiconductor integrated circuit becomes multifunctional, it is necessary to reduce the circuit scale and power consumption. As a result of the study, the adoption of a polar modulator transmitter described in Non-Patent Document 4 was studied.

  FIG. 1 is a diagram showing a configuration of a polar modulator transmitter studied by the present inventors prior to the present invention.

  The polar modulator transmitter shown in FIG. 1 includes an RF signal processing semiconductor integrated circuit (hereinafter referred to as RFIC) 1, a balun 2, and an RF power module 3.

  The RFIC 1 includes a digital modulator 10, a phase locked loop 11, a buffer / frequency divider 12, an AM modulator 13, a ramp generator 14, a digital subtractor Sub, a digital multiplier Mult, a D / A converter 15, and an A / D. A converter 16, a switch SW1, and low-pass filters 17 and 18 are included.

  The digital modulator 10 to which the digital transmission data Tx_Data is supplied outputs a digital amplitude component R and a digital phase component θ as in the digital CORDIC system described in Non-Patent Document 3. The digital amplitude component R is supplied to one input terminal of the digital multiplier Mult, and the digital phase component θ is supplied to one input terminal of the all digital phase locked loop (ADPLL) 11.

  For the ramp-up operation and the ramp-down operation of the RF power amplifier (PA) 31 included in the RF power module 3, the ramp data Ramp_Data is supplied from the baseband signal processing LSI via the digital RF interface of the RFIC 1 to the ramp generator 14. To the input terminal. Therefore, the ramp control digital signal generated from the output terminal of the ramp generator 14 is supplied to one input terminal of the digital subtracter Sub. On the other hand, since the RF power detector (DET) 32 of the RF power module 3 detects the level of the transmission output power Pout at the output terminal of the RF power amplifier (PA) 31, the analog transmission output of the RF power detector (DET) 32 is detected. The detection voltage Vdet is supplied to the input terminal of the A / D converter 16. As a result, the digital transmission output detection signal at the output terminal of the A / D converter 16 is supplied to the other input terminal of the digital subtractor Sub, and the digital output signal of the digital subtractor Sub is input to the other input of the digital multiplier Mult. Supplied to the terminal. The digital multiplication output signal at the output terminal of the digital multiplier Mult is supplied to the input terminal of the D / A converter 15, and the analog output signal of the D / A converter 15 is supplied to the input terminal of the switch SW1. In the GSM GMSK transmission mode, the analog signal at one output terminal of the switch SW1 is supplied to the RF power amplifier (PA) 31 through the low-pass filter 18 as the automatic power control voltage Vapc. On the other hand, in the EDGE transmission mode, the analog signal at the other output terminal of the switch SW 1 is supplied to one input terminal of the AM modulator 13 via the low-pass filter 17.

  The digital phase component θ generated from the digital modulator 10 is supplied to one input terminal of the all digital phase locked loop (ADPLL) 11. As shown in the lower part of FIG. 1, the all-digital phase-locked loop (ADPLL) 11 includes a phase digital converter 111 having a phase comparison function, a digital loop filter 112, a digital control oscillator 113, a fractional frequency divider 114, and a ΣΔ modulation. Instrument 115 is included.

  A reference frequency signal REF controlled to a stable frequency generated from a reference oscillator (not shown) is supplied to one input terminal of the phase digital converter 111, while the other input terminal of the phase digital converter 111 is supplied. The oscillation output signal of the digitally controlled oscillator 113 is supplied as negative feedback via the fractional frequency divider 114. Further, the digital conversion output signal of the phase digital converter 111 is supplied to the oscillation control input terminal of the digital control oscillator 113 via the digital loop filter 112, and the frequency of the oscillation output signal of the digital control oscillator 113 is controlled. Further, when negatively feeding back the oscillation output signal of the digital control oscillator 113 to the other input terminal of the phase digital converter 111, the fractional frequency divider 114 sets the two frequency division ratios 1 / N and 1 / (N + 1). It is what you have. Normally, in response to the digital output signal “0” of the ΣΔ modulator 115, the frequency division ratio of the fractional frequency divider 114 is set to one value 1 / N, while the digital output signal “1” from the ΣΔ modulator 115 is set. Is generated, the frequency division ratio of the fractional frequency divider 114 is set to the other value 1 / (N + 1). Further, in response to the digital phase component θ supplied from the digital modulator 10, the ΣΔ modulator 115 generates a digital output signal “1” with a predetermined duty ratio. Therefore, in the all-digital phase-locked loop (ADPLL) 11, the average frequency division ratio is set to a value less than a small number by a predetermined duty ratio and the two frequency division ratios 1 / N and 1 / (N + 1). As a result, the ADPLL 11 can function as a frequency synthesizer that can precisely control the frequency of the oscillation output signal of the digitally controlled oscillator 113 with extremely high frequency resolution.

  The oscillation output signal of the digital control oscillator 113 is supplied to the other input terminal of the AM modulator 13 through the buffer / frequency divider 12. The frequency of the oscillation output signal of the digital control oscillator 113 is set to a value of about 2 GHz. Therefore, when the polar modulator transmitter of FIG. 1 generates the transmission output power Pout of the transmission frequency of about 1 GHz low band (GSM850, GSM900), the buffer / frequency divider 12 is a frequency divider of 2. Operate. In addition, when the polar modulator transmitter of FIG. 1 generates transmission output power Pout at a transmission frequency of approximately 2 GHz high band (DCS1800, PCS1900), the buffer / divider 12 operates as a buffer with a division number of 1. To do.

  Therefore, when the polar modulator transmitter shown in FIG. 1 executes the EDGE transmission mode, the AM modulator 13 sets the amplitude of the phase modulated carrier signal in response to the digital phase component θ from the digital modulator 10 to AM. It modulates according to the modulation control signal. This AM modulation control signal includes an analog conversion output signal by the D / A converter 15 of the digital multiplication output by the digital multiplier Mult between the digital amplitude component R of the digital modulator 10 and the ramp control digital signal of the ramp generator 14. It is out. The phase-modulated carrier wave signal is an oscillation output signal of the digitally controlled oscillator 113 of the ADPLL 11 that responds to the digital phase component θ from the digital modulator 10.

  The RF transmission differential output signal generated at the differential output terminal of the AM modulator 13 is converted into a single-ended RF transmission signal by the balun 2. As is well known, the balun 2 has a function of converting a balanced differential input signal to an unbalanced single-ended output signal. A single-end RF transmission signal generated from the balun 2 is amplified by an RF power amplifier (PA) 31 of the RF power module 3, and the transmission output power Pout of the RF power amplifier (PA) 31 is a front-end module incorporating an antenna switch or the like. It is transmitted to the base station via (FEM) and a transmission antenna.

  FIG. 2 shows a GSM / EDGE multi-mode and high-frequency transmission using an RFIC 1 and an RF power module 3 that constitute the polar modulator transmitter shown in FIG. 1, a front-end module (FEM) 4 incorporating an antenna switch and the like, and a transmission antenna 5. FIG. 5 is a diagram showing a state in which a mobile phone communication terminal having a / low multiband transmission function is configured.

  2 shows the minimum transmission input power Mini_Pin supplied from the output terminal of the RFIC 1 to the input terminal of the RF power module 3, the gain when the RF power module 3 is turned off and when it is turned on, and the front end module. The gain when (FEM) 4 is off and when it is on is shown.

  FIG. 3 is a diagram for explaining a ramp-up operation and a ramp-down operation in the transmission slot of the EDGE transmission mode by the polar modulator transmitter of the mobile phone communication terminal shown in FIG.

  That is, in the TDMA (Time Division Multiple Access) system, as described at the beginning, it is possible to change the setting of a plurality of time slots to any one of the idle state, the reception operation from the base station, and the transmission operation to the base station. It becomes possible. In particular, when switching from another time slot to a transmission operation time slot, the signal strength of the RF transmission signal must be increased at an increase rate determined by the 3GPP (3rd Generation Partnership Project) standard. The increase in signal strength of the RF transmission signal at this time is called ramp-up. When the ramp-up increase rate is larger than the 3GPP standard, unnecessary radiation increases and an adjacent channel power leakage ratio (ACPR) increases. Conversely, when switching from a transmission operation time slot to another time slot, the signal strength of the RF transmission signal must be reduced at a reduction rate defined by the 3GPP standard. The decrease in signal strength of the RF transmission signal at this time is called ramp-down. If the ramp-down reduction rate is larger than the 3GPP standard, unnecessary radiation also increases and the adjacent channel power leakage ratio (ACPR) increases. The ramp voltage for ramp-up and ramp-down is generated from digital ramp data from the baseband signal processing LSI.

  As shown in FIG. 3, the 3GPP standard defines that the increase in signal strength of the RF transmission signal changes between the characteristics L31 and L32 during the first half of the transmission operation time slot Tx-slot ramp-up. Furthermore, the 3GPP standard defines that the decrease in signal strength of the RF transmission signal changes between the characteristics L31 and L32 during the ramp-down in the second half of the transmission operation time slot Tx-slot. Note that the horizontal axis in FIG. 3 indicates time lapse [μSec], and the vertical axis in FIG. 3 indicates transmission power [dBm] at the input of the transmission antenna 5. The change in the RF transmission signal defined by the 3GPP standard between the characteristic L31 and the characteristic L32 in FIG. 3 is called a time mask specification.

  In the ramp-up operation and the ramp-down operation of the transmission slot shown in FIG. 3, two control methods were examined. As shown in <Case 1> in FIG. 3, the first control method is as follows. At the time of ramp-up, the RF power module (PA) 3 is first switched from the off state to the on state, and then the front end module (FEM) 4 is turned on. It is switched from the off state to the on state. Further, at the time of the ramp down, the front end module (FEM) 4 is first switched from the on state to the off state, and then the RF power module (PA) 3 is switched from the on state to the off state.

  In the first control method indicated by <case 1> in FIG. 3, the transmission power [dBm] at the input of the transmission antenna 5 immediately before the start of ramp-up is −41 dBm of the minimum transmission input power Mini_Pin and the RF power module 3 is turned on. It is the sum of the gain at the time +30 dB and the gain at the time of turning off the front end module (FEM) 4 -20 dB. This sum is −41 dBm + 30 dB−20 dB = −31 dBm, and the time mask specification standard −48 dBm cannot be satisfied.

  Further, in the first control method shown in <case 1> of FIG. 3, the transmission power [dBm] at the input of the transmission antenna 5 immediately after the start of ramp-up is −41 dBm of the minimum transmission input power Mini_Pin and the RF power module 3 Is the sum of the on-state gain +30 dB and the front-end module (FEM) 4 on-state gain -2 dB. This sum is −41 dBm + 30 dB−2 dB = −13 dBm, and the time mask specification standard of −20 dBm cannot be satisfied.

  Further, in the first control method shown in <case 1> of FIG. 3, the transmission power [dBm] at the subsequent ramp-up can satisfy the standard of the time mask specification, but transmission is performed in the period of 10 μSec immediately before the end of the ramp-down. The power [dBm] is −13 dBm, and the standard of time mask specification −20 dBm cannot be satisfied.

  Furthermore, in the first control method shown in <case 1> of FIG. 3, the transmission power [dBm] is -31 dBm in the period immediately after the end of the ramp-down, and the time mask specification standard -48 dBm cannot be satisfied.

  In the next control method, as shown in <Case 2> in FIG. 3, when ramping up, the front end module (FEM) 4 is first switched from the OFF state to the ON state, and then the RF power module (PA). 3 is switched from the off state to the on state. Further, at the time of ramping down, the RF power module (PA) 3 is first switched from the on state to the off state, and then the front end module (FEM) 4 is switched from the on state to the off state.

  In the control method indicated by <case 2> in FIG. 3, the transmission power [dBm] at the input of the transmission antenna 5 immediately before the start of ramp-up is −41 dBm of the minimum transmission input power Mini_Pin and when the RF power module 3 is off. This is the sum of the gain of -30 dB and the gain of the front end module (FEM) 4 when it is off -20 dB. This sum is −41 dBm−30 dB−20 dB = −91 dBm, which satisfies the time mask specification of −48 dBm.

  Further, in the control method indicated by <case 2> in FIG. 3, the transmission power [dBm] at the input of the transmission antenna 5 immediately after the start of ramp-up is −41 dBm of the minimum transmission input power Mini_Pin and the RF power module 3 is turned off. The sum of the gain at the time −30 dB and the gain at the time when the front end module (FEM) 4 is turned on is −2 dB. This sum is −41 dBm−30 dB−2 dB = −73 dBm, and the time mask specification of −20 dBm can be satisfied.

  Further, in the control method indicated by <case 2> in FIG. 3, the transmission power [dBm] at the input of the transmission antenna 5 during the subsequent ramp-up period of 8 μSec is −41 dBm of the minimum transmission input power Mini_Pin and the RF power. The sum of the on-state gain of the module 3 +30 dB and the on-state gain of the front end module (FEM) 4 -2 dB. This sum is −41 dBm + 30 dB−2 dB = −13 dBm, and can sufficiently satisfy the standard of time mask specification—1 dBm.

  Further, the transmission power [dBm] is −13 dBm even during the subsequent ramp-down period of 8 μSec, which can sufficiently satisfy the standard of the time mask specification −1 dBm, and the transmission power [dBm] is −10 μsec immediately before the end of the ramp-down. It is 73 dBm, and the time mask specification standard of −20 dBm can be satisfied.

  Further, in the control method indicated by <case 2> in FIG. 3, the transmission power [dBm] is -91 dBm in the period immediately after the end of the ramp-down, and the time mask specification standard -48 dBm can be satisfied.

  As described above, in the first control method shown in <case 1> in FIG. 3, the standard of the time mask specification may be satisfied at the time of the first half of the transmission operation time slot Tx-slot during the ramp-up and the second half of the ramp-down. Can not.

  On the other hand, according to the control method shown in <case 2> in FIG. 3, the standard of the time mask specification can be satisfied at the time of the first half ramp-up and the second half ramp-down of the transmission operation time slot Tx-slot. There is a risk of violating the standard of the time mask specification with a deviation of. That is, in the control method shown in <Case 2> in FIG. 3, the switching transient noise from the OFF to the ON of the RF power amplifier (PA) 31 of the RF power module 3 during the ramp-up is changed to the front-end module (FEM) in the ON state. ) There is a high risk of being transmitted to the transmitting antenna 5 via 4. Similarly to the ramp-up, switching transient noise from the on-off of the RF power amplifier (PA) 31 of the RF power module 3 during the ramp-down is also transmitted through the front-end module (FEM) 4 in the on-state. The risk of being transmitted to 5 is high.

  As a result, as shown in FIG. 3, the control method <case 2> satisfies the standard of the time mask specification with the portion indicated by the symbol P_ru at the time of ramp-up and the portion indicated by the symbol P_rd at the time of ramp-down. The operating margin is insufficient.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above.

  Therefore, an object of the present invention is to easily secure an operation margin when satisfying the time mask specification standard in a time division multiple access transmission slot in EDGE RF transmission.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the representative digital modulator (10), ramp generator (14), digital multiplier (Mult), D / A converter (15), PLL (11), and AM modulator (13) of the present invention are provided. It is a transmitter capable of generating an EDGE RF transmission signal.

  The digital modulator (10) generates a digital amplitude component (R) and a digital phase component (θ) in response to transmission data (Tx_Data). The digital amplitude component (R) is supplied to the digital multiplier (Mult), the digital phase component (θ) is supplied to one input terminal of the PLL (11), and the other input of the PLL (11). A reference frequency signal (REF) is supplied to the terminal.

  The ramp generator 14 generates a ramp control digital control signal in response to the ramp data (Ramp_Data). The digital multiplier (Mult) responds to the ramp control digital control signal, and the output signal of the digital multiplier (Mult) is supplied to the input terminal of the D / A converter (15).

  The analog output signal of the D / A converter (15) is supplied to the AM modulator (13).

  An RF carrier signal based on the oscillation output signal of the PLL (11) is transmitted to the AM modulator (13), and the RF transmission signal of the EDGE system is generated from the output terminal of the AM modulator (13) ( (See FIGS. 1 and 4).

  In the first half of the ramp-up operation of the transmission operation time slot (Tx-slot) of the RF transmission signal of the EDGE system, the AM modulator (13) in response to the ramp data supplied to the ramp generator (14). ) Increases the analog output signal of the D / A converter (15) supplied to one input terminal. In the ramp-down operation in the latter half of the transmission operation time slot (Tx-slot), the signal is supplied to one input terminal of the AM modulator (13) in response to the ramp data supplied to the ramp generator (14). The analog output signal of the D / A converter (15) is decreased.

  In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is lower than a predetermined value (−7 dBm), the gain (Gain_AMMOD) of the AM modulator (13) is a low value (Gain (Low)). (See FIG. 5C, FIG. 8, and FIG. 9).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to easily secure an operation margin when satisfying the time mask specification standard in the transmission slot of the time division multiple access system in the EDGE system RF transmission.

FIG. 1 is a diagram showing a configuration of a polar modulator transmitter studied by the present inventors prior to the present invention. FIG. 2 shows a GSM / EDGE multi-mode and high-frequency transmission using an RFIC 1 and an RF power module 3 that constitute the polar modulator transmitter shown in FIG. 1, a front-end module (FEM) 4 incorporating an antenna switch and the like, and a transmission antenna 5. FIG. 5 is a diagram showing a state in which a mobile phone communication terminal having a / low multiband transmission function is configured. FIG. 3 is a diagram for explaining a ramp-up operation and a ramp-down operation in the transmission slot of the EDGE transmission mode by the polar modulator transmitter of the mobile phone communication terminal shown in FIG. FIG. 4 is a diagram showing the configuration of the polar modulator transmitter according to the first embodiment of the present invention. FIG. 5 is a diagram showing waveforms at various parts of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing a configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 7 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 8 is a diagram showing an operation of the AM modulator 13 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 9 is a diagram for explaining a ramp-up operation and a ramp-down operation in the transmission slot in the EDGE transmission mode by the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 10 is a timing for explaining a state in which various operation modes such as an idle state, a reception operation, and a transmission operation are set in the time slot according to time division multiple access (TDMA) in the polar modulator transmitter according to the second embodiment of the present invention. It is a figure of a chart. FIG. 11 is a diagram for explaining an operation sequence in the transmission mode of the EDGE system of the polar modulator transmitter according to the second embodiment of the present invention. FIG. 12 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 13 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. FIG. 14 is a diagram showing a configuration of a polar modulator transmitter for supporting multiband according to Embodiment 3 of the present invention. FIG. 15 is a diagram illustrating an operation of the AM modulator 13 when a DC offset of about 4 mV is generated due to the element pair deviation of the AM modulator 13 in the RFIC 1 illustrated in FIG. 14. FIG. 16 is a diagram illustrating the operation of the AM modulator 13 when the input DC offset is reduced to about 2 mV or less by performing the DC offset calibration operation twice before and after the polarity inversion of the first AM modulator 133. is there. FIG. 17 is a block diagram showing a configuration of a mobile phone supporting multiband according to the fourth embodiment of the present invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical embodiment of the present invention includes a digital modulator (10), a ramp generator (14), a digital multiplier (Mult), a D / A converter (15), a phase lock It is a transmitter capable of generating an EDGE-type RF transmission signal including a droop (11) and an AM modulator (13).

  The digital modulator (10) generates a digital amplitude component (R) and a digital phase component (θ) in response to transmission data (Tx_Data).

  The digital amplitude component (R) generated from the digital modulator (10) is supplied to one input terminal of the digital multiplier (Mult), and the digital phase component generated from the digital modulator (10). (θ) is supplied to one input terminal of the phase locked loop (11), and a reference frequency signal (REF) is supplied to the other input terminal of the phase locked loop (11).

  The ramp generator 14 generates a ramp control digital control signal in response to the ramp data (Ramp_Data).

  The other input terminal of the digital multiplier (Mult) responds to the ramp control digital control signal generated from the ramp generator (14), and the output signal of the digital multiplier (Mult) becomes the D / A. It is supplied to the input terminal of the converter (15).

  The analog output signal of the D / A converter (15) can be supplied to one input terminal of the AM modulator (13).

  An RF carrier signal based on the oscillation output signal of the phase-locked loop (11) can be transmitted to the other input terminal of the AM modulator (13), so that the output terminal of the AM modulator (13) The RF transmission signal of the EDGE method can be generated (see FIGS. 1 and 4).

  In the first half of the ramp-up operation of the transmission operation time slot (Tx-slot) of the RF transmission signal of the EDGE system, the AM modulator (13) in response to the ramp data supplied to the ramp generator (14). ) Increases the analog output signal of the D / A converter (15) supplied to one input terminal.

  In the ramp-down operation in the latter half of the transmission operation time slot (Tx-slot) of the RF transmission signal of the EDGE method, the AM modulator (in response to the ramp data supplied to the ramp generator (14)). The analog output signal of the D / A converter (15) supplied to one input terminal of 13) decreases.

  When the transmission power of the transmitter is lower than a predetermined value (−7 dBm) in the ramp-up operation and the ramp-down operation, the gain (Gain_AMMOD) of the AM modulator (13) is a low value (Gain (Low)). ) Is controlled.

  In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is higher than the predetermined value (−7 dBm), the gain (Gain_AMMOD) of the AM modulator (13) is lower than the lower value. Is also controlled to a large and high value (Gain (High)) (see FIGS. 5C, 8 and 9).

  According to the embodiment, it is possible to easily secure an operation margin when satisfying the time mask specification standard in the transmission slot of the time division multiple access method in the EDGE RF transmission.

  The preferred embodiment further comprises a control unit (19) for comparing the ramp data (Ramp_Data) with reference ramp data (Ref_Ramp_Data).

  The reference ramp data (Ref_Ramp_Data) corresponds to the predetermined value of the transmission power, and when the value of the ramp data is larger than the value of the reference ramp data, the output signal of the control unit (19) The gain of the AM modulator (13) is controlled to the high value.

  In another preferred embodiment of the AM modulator (13) during the ramp-up operation in response to completion of a first count-up of pulses of a clock signal of a predetermined frequency associated with the ramp-up operation. The gain is controlled to the high value.

  Further, the gain of the AM modulator (13) is low during the ramp-down operation in response to completion of a second count-up of the pulses of the clock signal of the predetermined frequency associated with the ramp-down operation. The value is controlled (see FIG. 11).

  In a more preferred embodiment, the ramp-up operation is controlled by a ramp-up start command (Ramp_Up Start).

  The gain of the AM modulator (13) during the ramp-up operation in response to the completion of the first count-up of the pulses of the clock signal of the predetermined frequency initiated by the ramp-up start command Is controlled to the high value.

  The ramp down operation is controlled by a ramp down start command (Ramp_Down Start).

  The gain of the AM modulator (13) during the ramp down operation in response to the completion of the second count up of the pulses of the clock signal of the predetermined frequency initiated by the ramp down start command Is controlled to the low value (see FIG. 11).

  In another preferred embodiment, the AM modulator (13) includes a first transistor pair (M1, M2), a second transistor pair (M3, M4), and a third transistor pair constituting a Gilbert cell. (M5, M6).

  A non-inverted input signal (AMMODi / p (T)) and an inverted input signal, which are the analog output signals of the D / A converter (15), are connected to both control electrodes of the first transistor pair (M1, M2). (AMMODi / p (B)) is supplied.

  The control electrodes of the second transistor pair (M3, M4) and the third transistor pair (M5, M6) have a non-inverted transmission RF that is the RF carrier signal based on the oscillation output signal of the phase-locked loop. A carrier signal and an inverted transmission RF carrier signal are supplied (see FIG. 6).

  In a specific embodiment, a DC offset voltage difference between the non-inverted input signal and the inverted input signal, which is the analog output signal of the D / A converter (15), and the D / A converter (15). The AC amplitude component of the non-inverted input signal and the inverted input signal, which is the analog output signal, increases in proportion to the increase in the value of the ramp data.

  In another specific embodiment, the input electrodes of the first transistor pair (M1, M2) are connected to the ground potential via a resistor pair (R1, R2).

  One output electrode and the other output electrode of the first transistor pair (M1, M2) are connected to both input electrodes of the second transistor pair (M3, M4) and the third transistor pair (M5, M6). Are connected to both input electrodes.

  One output electrode of the second transistor pair (M3, M4) and one output electrode of the third transistor pair (M5, M6) are common to one output terminal of the AM modulator (13). It is connected to the.

  The other output electrode of the second transistor pair (M3, M4) and the other output electrode of the third transistor pair (M5, M6) are common to the other output terminal of the AM modulator (13). It is connected to the.

  In a more specific embodiment, the gain of the AM modulator (13) is controlled by controlling the resistance value of the resistor pair (R1, R2) or the transistor of the first transistor pair (M1, M2). This is realized by controlling the number of parallel connections of group pairs (M11, M12... M1N, M21, M22... M2N) (see FIGS. 6, 7, and 12).

  In another more specific embodiment, the control of the gain of the AM modulator (13) is such that the signal of the output electrode of the first transistor pair (M1, M2) is applied to an AC ground node (Vdd). Control is performed by a gain control circuit (132) including bypassing elements (M7, M8, M9, M10) (see FIG. 13).

  Another specific embodiment is a DC offset voltage measuring circuit (136) for detecting an output DC offset voltage between the one output terminal and the other output terminal of the AM modulator (13). Is further provided.

  The DC offset voltage measuring circuit is supplied to the control electrodes of the first transistor pair (M1, M2) so that the output DC offset voltage is minimized during a DC offset calibration operation. An input DC offset voltage between the non-inverted input signal and the inverted input signal, which is the analog output signal of the D / A converter (15), can be adjusted (see FIG. 14).

  In a most specific embodiment, the DC offset calibration operation by the DC offset voltage measurement circuit can be executed in an idle mode preceding the transmission operation time slot or at a timing immediately before the transmission operation time slot. It is said that.

  [2] A typical embodiment of another aspect of the present invention can be used in a transmitter capable of generating an EDGE RF transmission signal, and includes a digital modulator (10) and a ramp generator (14). ), A digital multiplier (Mult), a D / A converter (15), a phase-locked loop (11), and an AM modulator (13).

  The digital modulator (10) generates a digital amplitude component (R) and a digital phase component (θ) in response to transmission data (Tx_Data).

  The digital amplitude component (R) generated from the digital modulator (10) is supplied to one input terminal of the digital multiplier (Mult), and the digital phase component generated from the digital modulator (10). (θ) is supplied to one input terminal of the phase locked loop (11), and a reference frequency signal (REF) is supplied to the other input terminal of the phase locked loop (11).

  The ramp generator 14 generates a ramp control digital control signal in response to the ramp data (Ramp_Data).

  The other input terminal of the digital multiplier (Mult) responds to the ramp control digital control signal generated from the ramp generator (14), and the output signal of the digital multiplier (Mult) becomes the D / A. It is supplied to the input terminal of the converter (15).

  The analog output signal of the D / A converter (15) can be supplied to one input terminal of the AM modulator (13).

  An RF carrier signal based on the oscillation output signal of the phase-locked loop (11) can be transmitted to the other input terminal of the AM modulator (13), so that the output terminal of the AM modulator (13) The RF transmission signal of the EDGE method can be generated (see FIGS. 1 and 4).

  In the first half of the ramp-up operation of the transmission operation time slot (Tx-slot) of the RF transmission signal of the EDGE system, the AM modulator (13) in response to the ramp data supplied to the ramp generator (14). ) Increases the analog output signal of the D / A converter (15) supplied to one input terminal.

  In the ramp-down operation in the latter half of the transmission operation time slot (Tx-slot) of the RF transmission signal of the EDGE method, the AM modulator (in response to the ramp data supplied to the ramp generator (14)). The analog output signal of the D / A converter (15) supplied to one input terminal of 13) decreases.

  When the transmission power of the transmitter is lower than a predetermined value (−7 dBm) in the ramp-up operation and the ramp-down operation, the gain (Gain_AMMOD) of the AM modulator (13) is a low value (Gain (Low)). ) Is controlled.

  In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is higher than the predetermined value (−7 dBm), the gain (Gain_AMMOD) of the AM modulator (13) is lower than the lower value. Is also controlled to a large and high value (Gain (High)) (see FIGS. 5C, 8 and 9).

  According to the embodiment, it is possible to easily secure an operation margin when satisfying the time mask specification standard in the transmission slot of the time division multiple access method in the EDGE RF transmission.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of polar modulator transmitter>
FIG. 4 is a diagram showing the configuration of the polar modulator transmitter according to the first embodiment of the present invention.

  The polar modulator transmitter shown in FIG. 4 includes an RFIC 1, a balun 2, and an RF power module 3 in the same manner as the polar modulator transmitter of FIG.

  4 is similar to the RFIC 1 of FIG. 1 in that the digital modulator 10, the phase-locked loop 11, the buffer / divider 12, the AM modulator 13, the ramp generator 14, the digital subtractor Sub, and the digital multiplier Mult. , A D / A converter 15, an A / D converter 16, a switch SW 1, and low-pass filters 17 and 18. The phase-locked loop 11 of the RFIC 1 in FIG. 4 is not shown in FIG. 4, but the phase digital converter 111, the digital loop filter 112, the digital control oscillator 113, the fractional frequency divider 114, and the ΣΔ modulation are the same as in FIG. Instrument 115 is included.

  The RFIC 1 in FIG. 4 has a control unit 19 that is not included in the RFIC 1 in FIG. Ramp data Ramp_Data and reference ramp data Ref_Ramp_Data supplied from the baseband signal processing LSI to the ramp generator 14 via the digital RF interface of the RFIC 1 are supplied to one input terminal and the other input terminal of the control unit 19, respectively. Is done. The reference ramp data Ref_Ramp_Data corresponds to the power level (−7 dBm) at the input of the transmitting antenna 5 immediately before the end of the ramp-up and immediately after the start of the ramp-down in the transmission slot of the time division multiple access method.

  When the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the gain Gain_AMMOD of the AM modulator 13 is set to a low value in response to the low level gain control signal Gain_Cnt generated from the control unit 19. However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the gain Gain_AMMOD of the AM modulator 13 is set to a high value in response to the high level gain control signal Gain_Cnt generated from the control unit 19.

《Polar modulator transmitter waveform》
FIG. 5 is a diagram showing waveforms at various parts of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  Each horizontal axis in FIG. 5A, FIG. 5B, and FIG. 5C indicates the value of the ramp data Ramp_Data. Furthermore, the vertical axis of FIG. 5A shows the analog display value of the digital output signal Output_Mult of the digital multiplier Mult, and the vertical axis of FIG. 5B shows the two analog output signals of the D / A converter 15. The vertical axis of FIG. 5C indicates the gain Gain_AMMOD of the AM modulator 13.

  As shown in FIG. 5A, the digital output signal Output_Mult of the digital multiplier Mult includes a DC component R_dc and an AC component R_ac of the digital amplitude component R generated from the digital modulator 11. In proportion to the increase in the value of the ramp data Ramp_Data, the DC component R_dc and the AC amplitude component R_ac of the digital output signal Output_Mult of the digital multiplier Mult increase.

  As shown in FIG. 5B, the two analog conversion output signals of the D / A converter 15 are the non-inverted input signal AMMODi / p (T) and the inverted input signal AMMODi / p (B) of the AM modulator 13. It will be. As a characteristic operation of the D / A converter 15, the DC offset difference and the AC amplitude component of the two analog conversion output signals increase in proportion to the increase in the value of the ramp data Ramp_Data. That is, the DC component of the non-inverted input signal AMMODi / p (T) of the AM modulator 13 as one analog conversion output signal of the D / A converter 15 increases in proportion to an increase in the value of the ramp data Ramp_Data. On the other hand, the DC component of the inverted input signal AMMODi / p (B) of the AM modulator 13 as the other analog conversion output signal of the D / A converter 15 decreases in proportion to an increase in the value of the ramp data Ramp_Data. Is.

  As shown in FIG. 5C, when the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the gain Gain_AMMOD of the AM modulator 13 is set to a low value Gain (Low). However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High).

<Configuration of AM modulator>
FIG. 6 is a diagram showing a configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  As shown in FIG. 6, the AM modulator 13 includes six N-channel MOS transistors M1 to M6 constituting a Gilbert cell. First, the sources of the transistor pairs M1 and M2 are connected to the ground potential via resistors R1 and R2, respectively. The resistance values of the resistors R1 and R2 can be controlled in response to a gain control signal Gain_Cnt generated from the control unit 19. A non-inverted input signal AMMODi / p (T) and an inverted input signal AMMODi / p (B) which are two analog conversion output signals of the D / A converter 15 are respectively connected to the gate of the transistor M1 and the gate of the transistor M2. Supplied.

  The drain of transistor M1 is connected to the sources of transistor pair M3, M4, while the drain of transistor M2 is connected to the sources of transistor pair M5, M6. The gate of the transistor M3 and the gate of the transistor M6 are supplied with the non-inverted transmission RF carrier signal from the frequency divider 121 via the capacitor C1 and the buffer 122, while the gate of the transistor M4 and the gate of the transistor M5 are connected to the capacitor C2. The inverted transmission RF carrier signal is supplied from the frequency divider 121 via the buffer 122. Further, the gate of the transistor M3 and the gate of the transistor M6 are connected to the capacitor C3 through the resistor R3, and the gate of the transistor M4 and the gate of the transistor M5 are connected to the capacitor C4 through the resistor R4, and both ends of the capacitor C3. Bias voltages Vb3 and Vb4 that are substantially equal to each other and between both ends of the capacitor C4 are supplied.

  The drain of the transistor M3 and the drain of the transistor M5 are connected to the external power supply Ext. The drain of the transistor M4 and the drain of the transistor M6 are connected to the external power supply Ext. Connected to Vdd. One end of the inductor L1 and one end of the inductor L2 are connected to the external power supply Ext. While connected to Vdd, the other end of the inductor L1 and the other end of the inductor L2 are connected to one end and the other end of the capacitor C5, respectively. One end and the other end of the capacitor C5 are connected to one end of the capacitor C6 and one end of the capacitor C7, respectively, while the other end of the capacitor C6 and the other end of the capacitor C7 are connected to one end and the other end of the capacitor C8, respectively. The One end and the other end of the capacitor C8 are respectively connected to one input terminal and the other input terminal as balanced differential input terminals of the balun 2, and the unbalanced single-ended output signal of the balun 2 is the RF power module 3. RF power amplifier (PA).

  During the positive half cycle of the non-inverted transmit RF carrier signal, the DC component and AC amplitude component of the drain current of the transistor M1 flow to the inductor L1 via the transistor M3, and the DC component and AC amplitude of the drain current of the transistor M2 The component flows to the inductor L2 through the transistor M6. During the positive half-cycle period of the inverted transmission RF carrier signal, the DC component and AC amplitude component of the drain current of the transistor M1 flow to the inductor L2 via the transistor M4, and the DC component and AC amplitude component of the drain current of the transistor M2 Flows to the inductor L1 through the transistor M5. As a result, the analog transmission amplitude component of the D / A converter 15 is RF-transmitted by the AM modulator 13 to which the non-inverted transmission RF carrier signal and the inverted transmission RF carrier signal are supplied from the frequency divider 121 via the buffer 122. Can be upconverted to a signal.

  In the AM modulator 13 composed of a Gilbert cell shown in FIG. 6, the bias voltages of the gates of the transistor pairs M1 and M2 are equal, the pair characteristics of the transistor pairs M1 and M2, and the resistances R1 and R2 When the pair characteristics are in an ideal state, the differential AC signals at both drains of the transistor pairs M3 and M4 are completely canceled by the differential AC signals at both drains of the transistor pairs M5 and M6. In this complete cancellation state, the output power of the AM modulator 13 becomes an ideal minimum output power. Further, in response to the bias voltage of the gate of the transistor pair M1 becoming higher than the bias voltage of the gate of the transistor pair M2, the differential AC signals of both drains of the transistor pairs M3 and M4 are both drained of the transistor pairs M5 and M6. Therefore, the output power of the AM modulator 13 increases from the ideal minimum output power.

  As shown in FIG. 5C, when the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is set to a low level. Accordingly, in response to the low-level gain control signal Gain_Cnt, the resistors R1 and R2 are set to a large resistance value, and the gain Gain_AMMOD of the AM modulator 13 is set to a low value Gain (Low). However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is set to a high level. Accordingly, in response to the high level gain control signal Gain_Cnt, the resistors R1 and R2 are set to a small resistance value, and the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High).

  FIG. 7 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  The AM modulator 13 shown in FIG. 7 is different from the AM modulator 13 shown in FIG. 6 in that the variable resistors R1 and R2 in FIG. 6 are first replaced with fixed resistors R1 and R2 in FIG. is there. Next, the transistor pairs M1 and M2 in FIG. 6 are replaced with transistor group pairs M11, M12... M1N, M21, M22... M2N in FIG. 7, and the number of parallel connections of this transistor group pair is responsive to the gain control signal Gain_Cnt. To change.

  As shown in FIG. 5C, when the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is set to a low level. Therefore, in response to the low level gain control signal Gain_Cnt, the parallel connection number of the transistor group pair is set to a small value, and the gain Gain_AMMOD of the AM modulator 13 is set to a low value Gain (Low). However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is set to a high level. Therefore, in response to the high level gain control signal Gain_Cnt, the parallel connection number of the transistor group pair is set to a large value, and the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High).

  FIG. 12 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  The AM modulator 13 shown in FIG. 12 differs from the AM modulator 13 shown in FIG. 6 in that the variable resistors R1 and R2 in FIG. 6 are a plurality of fixed resistors R11, R12... R1N, R21, R22. R2N and a plurality of switches SW11, SW12... SW1N, SW21, SW22.

  As shown in FIG. 5C, when the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the multi-bit gain control signal Gain_Cnt generated from the control unit 19 has a small number of high-level “1” bits. The number of bits of low level “0” is set to a large state. Accordingly, in response to the multi-bit gain control signal Gain_Cnt in this state, the gain Gain_AMMOD of the AM modulator 13 is set to a low value Gain (Low). However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the multi-bit gain control signal Gain_Cnt has a small number of low level “0” bits and a large number of high level “1” bits. Accordingly, in response to the multi-bit gain control signal Gain_Cnt in this state, the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High).

  FIG. 13 is a diagram showing another configuration of the AM modulator 13 included in the RFIC 1 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  The AM modulator 13 shown in FIG. 13 is different from the AM modulator 13 shown in FIG. 6 in that the variable resistors R1 and R2 in FIG. 6 are first replaced with a plurality of fixed resistors R1 and R2 in FIG. It is. Next, a gain control circuit 132 controlled by a gain control signal Gain_Cnt generated from the control unit 19 is added to the AM modulator 13 shown in FIG.

  The gain control circuit 132 includes a first transistor pair M7, M8, a second transistor pair M9, M10, three capacitors C9, C10, C11, two resistors R5, R6, a bias voltage Vbb, and a switch 132_SW. It is out.

  The drain of the transistor M1 of the AM modulator 13 is connected to the source of the first transistor pair M7, M8 of the gain control circuit 132, while the drain of the transistor M2 of the AM modulator 13 is the second of the gain control circuit 132. It is connected to the sources of the transistor pair M9, M10. The gate of the transistor M7 and the gate of the transistor M10 are supplied with the non-inverted transmission RF carrier signal from the frequency divider 121 via the capacitor C9 and the buffer 122, while the gate of the transistor M8 and the gate of the transistor M9 are connected to the capacitor C10. The inverted transmission RF carrier signal is supplied from the frequency divider 121 via the buffer 122. Further, the gate of the transistor M7 and the gate of the transistor M10 are connected to the bias voltage Vbb via the resistor R5, and the gate of the transistor M8 and the transistor M9 are connected to the bias voltage Vbb via the resistor R6. A capacitor C11 and a switch 132_SW are connected in parallel between both ends of the bias voltage Vbb. Further, the bias voltage Vbb is set substantially equal to the bias voltages Vb3 and Vb4. Further, the switch 132_SW is controlled by a gain control signal Gain_Cnt generated from the control unit 19. The drain of the transistor M7 and the drain of the transistor M9 are connected to the power supply voltage Vdd, while the drain of the transistor M8 and the drain of the transistor M10 are also connected to the power supply voltage Vdd.

  As shown in FIG. 5C, when the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is in a low level “0” state. Accordingly, in response to the gain control signal Gain_Cnt in this state, the switch 132_SW is controlled to be in the OFF state, and the DC component and the AC amplitude component of the drain current of the transistor M1 are the gain of the transistor pair M3 and M4 of the AM modulator 13 and the gain. The current is diverted to the transistor pairs M7 and M8 of the control circuit 132 at substantially equal flow rates. At this time, the DC component and the AC amplitude component of the drain current of the transistor M2 are shunted at substantially equal flow rates to the transistor pairs M5 and M6 of the AM modulator 13 and the transistor pairs M9 and M10 of the gain control circuit 132, respectively. Accordingly, in response to the gain control signal Gain_Cnt in this state, the gain Gain_AMMOD of the AM modulator 13 is set to a low value Gain (Low).

  However, when the value of the ramp data Ramp_Data becomes larger than the reference ramp data Ref_Ramp_Data, the gain control signal Gain_Cnt generated from the control unit 19 is set to the high level “1”. Accordingly, in response to the gain control signal Gain_Cnt, the switch 132_SW is controlled to be in an ON state, and the DC component and the AC amplitude component of the drain current of the transistor M1 are not shunted to the transistor pair M7 and M8 of the gain control circuit 132, It flows only into the transistor pair M3 and M4 of the AM modulator 13. At this time, the DC component and the AC amplitude component of the drain current of the transistor M2 are not shunted to the transistor pair QM9 and M10 of the gain control circuit 132, and only the transistor pair M5 and M6 of the AM modulator 13 is flowed. Accordingly, in response to the gain control signal Gain_Cnt in this state, the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High).

<< Operation of AM Modulator 13 >>
FIG. 8 is a diagram showing an operation of the AM modulator 13 of the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  The horizontal axis of FIG. 8 represents the DC of the non-inverted input signal AMMODi / p (T) and the inverted input signal AMMODi / p (B) of the AM modulator 13 which are two analog conversion output signals of the D / A converter 15. Offset difference. As described above, the DC offset difference and the AC amplitude component increase in proportion to an increase in the value of the ramp data Ramp_Data.

  The vertical axis in FIG. 8 represents the output power of the AM modulator 13. The output power of the AM modulator 13 shown on the vertical axis in FIG. 8 includes the on-state gain of the RF power amplifier (PA) 31 of the RF power module 3 +30 dBm and the on-state gain of the front end module (FEM) 4 -2 dB. Is added to the transmission power [dBm] at the input of the transmission antenna 5.

  In FIG. 8, the output power of the AM modulator 13 when the gain Gain_AMMOD of the AM modulator 13 is set to a high value Gain (High) is indicated by the characteristic L1, while the gain Gain_AMMOD of the AM modulator 13 is low. The output power of the AM modulator 13 when set to Gain (Low) is indicated by the characteristic L2. 8 shows the actual output power of the AM modulator 13 in the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. 4 as a characteristic L3. In FIG. 8, the switching between the characteristic L1 and the characteristic L2 occurs when the DC offset difference on the horizontal axis in FIG. 8 is approximately 10 mV. The approximately 10 mV DC offset difference corresponds to the reference ramp data Ref_Ramp_Data supplied to the ramp generator 14.

  When the value of the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the DC offset difference and the AC amplitude component of the two analog conversion output signals of the D / A converter 15 are small values. The actual output power of the AM modulator 13 at this time is characteristic L3, and the output power of the low gain Gain (Low) AM modulator 13 is determined by the characteristic L2. However, when the value of the ramp data Ramp_Data is larger than the reference ramp data Ref_Ramp_Data, the DC offset difference and the AC amplitude component of the two analog conversion output signals of the D / A converter 15 are large values. The actual output power of the AM modulator 13 at this time is determined by the characteristic L3, and the output power of the AM modulator 13 having a high gain Gain (High) is determined by the characteristic L1.

<< Transmission Slot Operation in EDGE Transmission Mode >>
FIG. 9 is a diagram for explaining a ramp-up operation and a ramp-down operation in the transmission slot in the EDGE transmission mode by the polar modulator transmitter according to the first embodiment of the present invention shown in FIG.

  FIG. 9 also shows an increase upper limit characteristic L91 and an increase lower limit characteristic L92 of the signal strength of the RF transmission signal during the ramp-up of the first half of the transmission operation time slot Tx-slot defined by the 3GPP standard according to the time mask specification. A decrease upper limit characteristic L91 and a decrease lower limit characteristic L92 of the signal strength of the RF transmission signal at the time of ramp-down in the latter half of the transmission operation time slot Tx-slot are shown.

  As the transmission slot control method in the EDGE transmission mode shown in FIG. 9, the same control method <case1> as <case1> described in FIG. 3 is adopted. As shown in FIG. 9, at the time of ramp-up, the RF power module (PA) 3 is first switched from the off state to the on state, and then the front end module (FEM) 4 is switched from the off state to the on state. Further, at the time of the ramp down, the front end module (FEM) 4 is first switched from the on state to the off state, and then the RF power module (PA) 3 is switched from the on state to the off state.

  Since the polar modulator transmitter according to the first embodiment of the present invention shown in FIG. 4 adopts the control method <case 1> of FIG. 3 in the EDGE transmission mode, as described with reference to FIG. The transmission power [dBm] at the input of the transmission antenna 5 needs to satisfy the time mask specification standard -48 dBm. Immediately before the ramp-up, the RF power module 3 is turned on and has an on-time gain of +30 dB, and the front end module (FEM) 4 is turned off and has an off-time gain of −20 dB. Accordingly, the target value of the minimum output power of the AM modulator 13 immediately before the ramp-up of the RFIC1 of the polar modulator transmitter of FIG. 4 is −48 dBm−30 dB + 20 dB = −58 dBm. The minimum output power of the AM modulator 13 immediately before the ramp-up of the target value of −58 dBm is shown in FIG. Since the characteristic L1 in FIG. 8 cannot satisfy the target value of −58 dBm, when the ramp data Ramp_Data is smaller than the reference ramp data Ref_Ramp_Data, the output power of the low gain AM modulator 13 is determined by the characteristic L2. is there. That is, in the characteristic L1 of FIG. 8, the minimum output power of the AM modulator 13 is reduced only to −53 dBm. On the other hand, in the characteristic L2 of FIG. 8, the minimum output power of the AM modulator 13 can be reduced to −65 dBm.

  Therefore, the transmission power [dBm] at the input of the transmission antenna 5 immediately before the start of ramp-up in the EDGE transmission mode shown in FIG. 9 is −65 dBm, which is the minimum output power of the AM modulator 13 having the characteristic L2 in FIG. And the gain when the RF power module 3 is turned on + 30 dB and the gain when the front end module (FEM) 4 is turned off−20 dB. This sum is −65 dBm + 30 dB−20 dB = −55 dBm, and the time mask specification of −48 dBm can be satisfied.

  Furthermore, in the EDGE transmission mode shown in FIG. 9, the transmission power [dBm] of the input of the first transmission antenna 5 in the period of 10 μSec immediately after the start of ramp-up is the AM modulator 13 shown by the characteristic L2 in FIG. The sum of the minimum output power of −65 dBm, the RF power module 3 on-time gain of +30 dB, and the front-end module (FEM) 4 on-time gain of −2 dB. This sum is −65 dBm + 30 dB−2 dB = −37 dBm, and the time mask specification of −20 dBm can be satisfied.

  Further, in the EDGE transmission mode shown in FIG. 9, the transmission power [dBm] at the input of the transmission antenna 5 increases to a predetermined value of −7 dBm at approximately the intermediate timing of the subsequent ramp-up 8 μSec period. That is, at the timing when the transmission power [dBm] increases to the predetermined value -7 dBm, the ramp data Ramp_Data supplied to the ramp generator 14 becomes larger than the value of the reference ramp data Ref_Ramp_Data corresponding to the predetermined value -7 dBm. Therefore, as shown in FIG. 8, the gain Gain_AMMOD of the AM modulator 13 is switched from the low Gain (Low) state of the characteristic L2 (L3) to the high Gain (High) state of the characteristic L1.

  That is, the output power of the AM modulator 13 changes from approximately −47 dBm to −35 dBm by switching from the characteristic L2 (L3) to the characteristic L1 in FIG. 8 at a timing approximately in the middle of the ramp-up 8 μSec period. At this time, the transmission power [dBm] of the input of the transmission antenna 5 is -35 dBm of the output power of the AM modulator 13, the gain when the RF power module 3 is on +30 dB, and the time when the front end module (FEM) 4 is on. And a gain of -2 dB. This sum is −35 dBm + 30 dB−2 dB = −7 dBm, and the standard of time mask specification—1 dBm can also be satisfied. Even the transmission power [dBm] in the subsequent ramp-up operation can satisfy the standard of the time mask specification.

  Further, the transmission power [dBm] can satisfy the standard of the time mask specification even during a period of 10 μSec immediately after the ramp-down start in the latter half of the transmission operation time slot Tx-slot. Further, the transmission power [dBm] at the input of the transmission antenna 5 decreases to a predetermined value −7 dBm or less at a timing approximately in the middle of the subsequent ramp-down period of 8 μSec. That is, the ramp data Ramp_Data supplied to the ramp generator 14 becomes smaller than the value of the reference ramp data Ref_Ramp_Data corresponding to the predetermined value −7 dBm at the timing when the transmission power [dBm] decreases to a predetermined value −7 dBm or less. Accordingly, as shown in FIG. 8, the gain Gain_AMMOD of the AM modulator 13 is switched from a high Gain (High) state with the characteristic L1 to a low Gain (Low) state with the characteristic L2 (L3). Accordingly, the transmission power [dBm] of the input of the transmission antenna 5 immediately before the end of the ramp-down is −65 dBm which is the minimum output power of the AM modulator 13 having the characteristic L2 in FIG. 8 and the gain when the RF power module 3 is on +30 dB. This is the sum of the gain when the front end module (FEM) 4 is on and -2 dB. This sum is −65 dBm + 30 dB−2 dB = −37 dBm, and the time mask specification of −20 dBm can be satisfied. Further, the transmission power [dBm] at the input of the transmission antenna 5 immediately after the end of the ramp-down is −65 dBm which is the minimum output power of the AM modulator 13 having the characteristic L2 in FIG. 8 and the gain when the RF power module 3 is turned on + 30 dB. And the gain when the front end module (FEM) 4 is turned off is -20 dB. This sum is −65 dBm + 30 dB−20 dB = −55 dBm, and the time mask specification of −48 dBm can be satisfied.

  Note that the characteristic L93 in FIG. 9 indicates that the polar modulator transmitter according to the first embodiment of the present invention in FIG. 4 described above adopts the control method <case1> in the EDGE transmission mode, thereby allowing the ramp-up and ramp-down. This shows that the standard of the time mask specification determined by the upper limit characteristic L91 and the lower limit characteristic L92 can be satisfied.

[Embodiment 2]
<Other configuration of polar modulator transmitter>
Another configuration of the polar modulator transmitter according to the second embodiment of the present invention will be described with reference to FIG.

  In the polar modulator transmitter according to the second embodiment of the present invention, the control unit 19 that generates the gain control signal Gain_Cnt for controlling the gain of the AM modulator 13 has an operation command for setting various operation modes of the RFIC 1. Is supplied.

《Various operation modes》
FIG. 10 is a timing for explaining a state in which various operation modes such as an idle state, a reception operation, and a transmission operation are set in the time slot according to time division multiple access (TDMA) in the polar modulator transmitter according to the second embodiment of the present invention. It is a figure of a chart.

<Idle mode immediately after power-on>
When a mobile phone communication terminal equipped with RFIC1 of the polar modulator transmitter according to the second embodiment of the present invention is turned on, a command called Word4 is transmitted from the baseband signal processing LSI to the control unit via the digital RF interface, for example. 19 is supplied. Then, various control registers in the RFIC 1 are reset, and the RFIC 1 is set to an idle mode operation mode that is a sleep state waiting for a command.

《Warm-up mode》
Next, for example, a warm-up command called Word 1 is supplied from the baseband signal processing LSI to the control unit 19 via the digital RF interface. Then, the all digital phase-locked loop (ADPLL) 11 of the RFIC 1 is activated, and the oscillation operation of the digital control oscillator 113 inside the ADPLL 11 is started. This warm-up command Word1 also includes a bit for instructing reception or transmission of the next operation mode. When the digitally controlled oscillator 113 operates in a plurality of frequency bands, the frequency band to be used is selected. , ADPLL11 transitions to the locked state.

<Receive mode>
Thereafter, for example, a reception command called Word 2 is supplied from the baseband signal processing LSI to the control unit 19 via the digital RF interface. Then, the RFIC 1 is set to the reception mode, and the RF reception circuit system of the RFIC 1 performs signal processing for amplification and demodulation of the RF reception signal, and the reception baseband signal is transferred from the RFIC 1 to the baseband signal processing LSI via the digital RF interface. Supplied. When reception is completed, a warm-up command called Word 1 is supplied from the baseband signal processing LSI to the control unit 19 via the digital RF interface. Therefore, the RFIC 1 transitions to the warm-up mode.

<Transmission mode>
Thereafter, for example, a transmission command called Word3 is supplied from the baseband signal processing LSI to the control unit 19 via the digital RF interface. Then, the RFIC 1 is set to the transmission mode, the RF transmission circuit system of the RFIC 1 modulates and amplifies the RF transmission signal, and the RF transmission signal is supplied from the RFIC 1 to the RF power amplifier (PA) in the RF power module 3. When the transmission is completed, a warm-up command called Word 1 is supplied from the baseband signal processing LSI to the control unit 19 via the digital RF interface.

<< Transmission operation in EDGE transmission mode >>
FIG. 11 is a diagram for explaining an operation sequence in the transmission mode of the EDGE system of the polar modulator transmitter according to the second embodiment of the present invention. The operation sequence of the EDGE transmission mode shown in FIG. 11 shows details of the transmission mode started in response to a transmission command called Word3 in the time chart shown in FIG.

《Transmit data upload command》
At time T1 in FIG. 11, the transmission data upload command Tx_data Up_Load is transferred from the baseband signal processing LSI to the RFIC1 via the digital RF interface, and the transmission data Tx_Data of the digital baseband transmission signal is also transferred. This transmission data Tx_Data is valid data of 168 symbols, and is held in an internal memory such as a built-in RAM or data register of the digital RF interface of RFIC1.

  In GSM data communication, one symbol of a transmission / reception baseband signal is composed of 4 bits. If the last fourth bit of one symbol is “1”, it is EDGE transmission data, and the first three bits indicate the amplitude by AM modulation. If the last 4th bit of one symbol is “0”, it is GMSK transmission data using only phase modulation, and the first 3 bits have a constant amplitude of “111 (all“ 1 ”)”, for example. In GSM data communication, one bit of four bits of one symbol is called a quarter bit. When a system clock frequency of 26 MHz is used, one quarter bit (1Qb) indicates a time of 923.08 nanoseconds.

<Transmission mode on command>
At time T2 in FIG. 11, the transmission mode ON command Tx_Mode ON is transferred from the baseband signal processing LSI to the RFIC 1 via the digital RF interface. Then, the operation of the polar modulator transmitter according to the second embodiment of the present invention is started. Further, the RF power amplifier activation signal PA_ON for starting to supply the power supply voltage and the bias voltage to the RF power amplifier (PA) in the RF power module 3 changes from the low level to the high level.

<< Transmission data internal transfer instruction >>
At time T3 in FIG. 11, the transmission data internal transfer command Tx_Data ON is transferred from the baseband signal processing LSI to the RFIC 1 via the digital RF interface. When a predetermined delay time elapses from time T3, reading of 168 symbols of effective data of transmission data Tx_Data held in an internal memory such as the built-in RAM of RFIC1 or a data register is started.

《Ramp up start command》
At time T4 in FIG. 11, a ramp-up start command Ramp_Up Start is transferred from the baseband signal processing LSI to the RFIC 1 via the digital RF interface. Then, loading of the digital ramp data Ramp_Up Data for ramp-up from the baseband signal processing LSI to the internal RAM of the RFIC 1 or the internal memory of the data register is started. Accordingly, in response to an increase in the digital value of the loaded digital ramp data Ramp_Up Data, the ramp data Ramp_Data supplied to the input terminal of the ramp generator 14 of the polar modulator transmitter according to the second embodiment of the present invention shown in FIG. The digital value of is determined.

  The ramp control digital signal at the output terminal of the ramp generator 14 is supplied to the input terminal of the D / A converter 15 via the digital subtracter Sub and the digital multiplier Mult. Therefore, the analog output signal Output_DAC of the D / A converter 15 supplied to one input terminal of the AM modulator 13 increases in response to an increase in the digital value of the digital ramp data Ramp_Up Data.

  In response to the ramp-up start command Ramp_Up Start, the front-end module activation signal FEM_ON for starting the operation of the front-end module (FEM) 4 changes from the low level to the high level.

  On the other hand, the control unit 19 starts counting the system clock pulse with a frequency of 26 MHz in response to the ramp-up start command Ramp_Up Start supplied at the timing of time T4 in FIG. The control unit 19 performs gain control signal Gain_Cnt supplied to the other input terminal of the AM modulator 13 after elapse of a count-up time (13 × 0.923 μSec = 11.999 μSec≈12 μSec) corresponding to 13 quarter bits (13Qb). From low level to high level. Therefore, as shown in FIG. 8, the gain Gain_AMMOD of the AM modulator 13 is switched from the low Gain (Low) state of the characteristic L2 (L3) to the high Gain (High) state of the characteristic L1. Also, the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb) is 2 μSec, which is approximately a quarter of the 10 μSec period immediately after the ramp-up start shown in FIG. 9 and the subsequent 8 μSec period of the ramp-up. The gain switching from the low gain (low) state of the characteristic L2 (L3) of the AM modulator 13 to the high gain (high) state of the characteristic L1 corresponds to the ramp-up start timing. This means that it is performed within a period of 10 to 18 μSec from T4.

  As a result, the output power of the AM modulator 13 is changed from approximately −47 dBm by switching from the characteristic L2 (L3) to the characteristic L1 in FIG. 8 at the timing of the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb). It changes to -35 dBm. Similar to the ramp-up operation shown in FIG. 9, the transmission power [dBm] of the input of the transmission antenna 5 at the timing immediately after the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb) is The sum of the output power of −35 dBm, the gain when the RF power module 3 is on +30 dB, and the gain when the front end module (FEM) 4 is on is −2 dB. This sum is −35 dBm + 30 dB−2 dB = −7 dBm, and the standard of the time mask specification—1 dBm can be satisfied. Even the transmission power [dBm] in the subsequent ramp-up operation can satisfy the standard of the time mask specification.

<Transmission of transmission data after ramp-up is completed>
A total of 148 symbols of transfer data is transmitted between the completion of ramp-up at time T5 and the ramp-down start at time T6 in FIG. The total 148 symbols of transfer data corresponds to EDGE transmission data Tx_Data supplied to the digital modulator 10.

《Ramp down start command》
At time T6 in FIG. 11, a ramp-down start command Ramp_Down Start is transferred from the baseband signal processing LSI to the RFIC 1 via the digital RF interface. Then, loading of the digital ramp data Ramp_Down Data for ramping down from the baseband signal processing LSI to the internal RAM of the RFIC 1 or the internal memory of the data register is started. As a result, an internal operation sequence similar to the internal operation sequence of the RFIC 1 between time T4 and time T5 is executed between time T6 and time T7. Accordingly, the analog output signal Output_DAC of the D / A converter 15 supplied to one input terminal of the AM modulator 13 decreases in response to a decrease in the digital value of the digital ramp data Ramp_Down Data for ramping down. .

  On the other hand, the control unit 19 starts counting a system clock pulse with a frequency of 26 MHz in response to a ramp-down start command Ramp_Down Start supplied at the timing of time T6 in FIG. The control unit 19 is supplied to the other input terminal of the AM modulator 13 at a timing preceding the count-up time (≈12 μSec) of 13 quarter bits (13Qb) before the transmission mode off Tx_Mode OFF timing at time T7 in FIG. The gain control signal Gain_Cnt is switched from the high level to the low level. Accordingly, as shown in FIG. 8, the gain Gain_AMMOD of the AM modulator 13 is switched from a high Gain (High) state with the characteristic L1 to a low Gain (Low) state with the characteristic L2 (L3). Also, the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb) is 2 μSec, which is approximately 1/4 of the period of 10 μSec immediately before the end of the ramp-down shown in FIG. 9 and the period of 8 μSec after the ramp-down. The gain switching from the high Gain (High) state of the characteristic L1 of the AM modulator 13 to the low Gain (Low) state of the characteristic L2 (L3) is performed at the ramp-down start timing. This means that it is performed within a period of 10 to 18 μSec from T6.

  As a result, the output power of the AM modulator 13 is changed from approximately −35 dBm by switching the characteristic L1 in FIG. 8 to the characteristic L2 (L3) at the timing of the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb). Change to -47 dBm. Similar to the ramp-down operation shown in FIG. 9, the transmission power [dBm] of the input of the transmission antenna 5 at the timing immediately before the count-up time (≈12 μSec) corresponding to 13 quarter bits (13Qb) is The sum of the output power of −35 dBm, the gain when the RF power module 3 is on +30 dB, and the gain when the front end module (FEM) 4 is on is −2 dB. This sum is −35 dBm + 30 dB−2 dB = −7 dBm, and the standard of the time mask specification—1 dBm can be satisfied. Even the transmission power [dBm] in the subsequent ramp-down operation can satisfy the standard of the time mask specification.

  In response to the ramp-down start command Ramp_Down Start, the front-end module activation signal FEM_ON changes from high level to low level in order to stop the operation of the front-end module (FEM) 4 after elapse of a predetermined delay time.

<Transmission mode off command>
At time T7 in FIG. 11, a transmission mode off command Tx_Mode OFF is transferred from the baseband signal processing LSI to the RFIC 1 via the digital RF interface. Then, the RF power amplifier activation signal PA_ON for stopping the supply of the power supply voltage and the bias voltage to the RF power amplifier (PA) inside the RF power module 3 changes from the high level to the low level.

[Embodiment 3]
<Configuration of polar modulator transmitter supporting multi-band>
FIG. 14 is a diagram showing a configuration of a polar modulator transmitter for supporting multiband according to Embodiment 3 of the present invention.

  The polar modulator transmitter shown in FIG. 14 includes an RFIC 1, a balun 2, and an RF power module 3, similarly to the polar modulator transmitter shown in FIG.

  Although not shown in the RFIC 1 of FIG. 14, the digital modulator 10, the phase locked loop 11, the ramp generator 14, the digital subtractor Sub, the digital multiplier Mult, and the D / A converter 15 are not shown. A / D converter 16, switch SW1, and low-pass filters 17 and 18 are included. 14 is not shown, the phase digital converter 111, the digital loop filter 112, the digital control oscillator 113, the fractional frequency divider 114, and the ΣΔ modulator 115 are not shown. Is included.

  In particular, the AM modulator 13 incorporated in the RFIC 1 in FIG. 14 is compatible with the first AM modulator 133 corresponding to the low band (GSM850, GSM900) of approximately 1 GHz and the high band (DCS1800, PCS1900) of approximately 2 GHz. The second AM modulator 134 is included.

  The first AM modulator 133 corresponding to the low band of about 1 GHz is similar to the AM modulator 13 shown in FIG. 7 in that the number of parallel connection of the transistor group pairs M11, M12... M1N, M21, M22. The method changes in response to Gain_Cnt.

  The gates of the transistors M11, M12... M1N and the gates of the transistors M22... M2N of the first AM modulator 133 and the non-inverted input signal AMMODi / p (T) which are two analog conversion output signals of the D / A converter 15 The inverted input signal AMMODi / p (B) is supplied. The gate of the transistor M3 and the gate of the transistor M6 of the first AM modulator 133 are supplied with a non-inverted transmission RF carrier signal from the frequency divider 121 via the capacitor C1 and the buffer 122, while the gate of the transistor M4 and the transistor M5 The inverted transmission RF carrier signal is supplied from the frequency divider 121 via the capacitor C2 and the buffer 122. Further, the gate of the transistor M3 and the gate of the transistor M6 are connected to the capacitor C3 through the resistor R3, and the gate of the transistor M4 and the gate of the transistor M5 are connected to the capacitor C4 through the resistor R4, and both ends of the capacitor C3. Bias voltages Vb3 and Vb4 that are substantially equal to each other and between both ends of the capacitor C4 are supplied. Further, the second AM modulator 134 for supporting the high band of about 2 GHz can be configured in the same manner as the first AM modulator 133.

  The AM modulator 13 includes a DC offset voltage measurement circuit 136 and a DC offset voltage measurement controller 135 connected to the differential output terminal of the first AM modulator 133 and the differential output terminal of the second AM modulator 134. The DC offset voltage measurement circuit 136 includes a first and second switch pair sw1, sw2, a differential amplifier AMP, and a voltage comparator CMP. The differential input terminal of the differential amplifier AMP is connected to the differential output terminal of the first AM modulator 133 via the first switch pair sw1, and the difference between the second AM modulator 134 via the second switch pair sw2. Connected to the dynamic output terminal. The differential output signal of the differential amplifier AMP is supplied to the differential input terminal of the voltage comparator CMP, and the output signal Addccal_out of the voltage comparator CMP is stored in the register 21.

  Various control signals are supplied from the control register 22 to the DC offset voltage measurement controller 135 that controls the differential amplifier AMP and the voltage comparator CMP of the DC offset voltage measurement circuit 136 of the AM modulator 13. These various control signals include a calibration on signal Addccal_on, a polarity signal Calo_pol, and the like. A calibration clock Addccal_clk generated from a clock generator clock built in the D / A converter 15 is supplied to the voltage comparator CMP. Further, the polarity change signal Polarity change is supplied from the control register 22 to the bias voltage generator that generates the bias voltages Vb3 and Vb4 by the AM modulator 13. The registers 21 and 22 are connected to another control register 23 via the bus 24. A buffer cutoff signal Buffer_off generated from another control register 23 is supplied to the buffer 122. An 8-bit DC offset control signal DC-offset control generated from another control register 23 is supplied to a variable voltage source built in the D / A converter 15.

<< DC offset calibration of AM modulator 13 >>
In the above-described various embodiments of the present invention, the time mask specification standard in the transmission slot is satisfied by switching the gain Gain_AMMOD of the AM modulator 13 immediately before the end of ramp-up of the transmission slot or immediately after the start of ramp-down. This makes it easy to ensure a sufficient operating margin.

  However, even if the gain Gain_AMMOD of the AM modulator 13 is switched in this way, the elements constituting the AM modulator 13 (particularly, the transistor differential pair pairs (M11, M21), (M12, M22), (M1N M2N), resistance pair R1, R2, etc.), when the input DC offset occurs due to the pair deviation, the problem that the minimum output power of the AM modulator 13 is limited is apparent from the study by the present inventors. It was said.

  FIG. 15 is a diagram illustrating an operation of the AM modulator 13 when an input DC offset of about 4 mV is generated due to the element pair deviation of the AM modulator 13 in the RFIC 1 illustrated in FIG.

  In response to a decrease in the value of the ramp data Ramp_data supplied to the ramp generator 14, the difference in DC offset voltage between the two analog conversion output signals Output_DAC from the D / A converter 15 is reduced in the RFIC 1 shown in FIG. . However, as shown in FIG. 15, the DC offset voltage difference between the non-inverted input signal AMMODi / p (T) and the inverted input signal AMMODi / p (B) of the AM modulator 13 is less than or equal to the input DC offset voltage difference of about 4 mV. Even if it decreases, the output power of the AM modulator 13 cannot be reduced.

  Also in the AM modulator 13 shown in FIG. 14, when the bias voltages of the gates of the transistor pairs M11, M12... M1N, M2, M22. It is completely canceled by the differential AC signal at both drains of M5 and M6. In this complete cancellation state, the output power of the AM modulator 13 becomes an ideal minimum output power. However, due to the input DC offset voltage difference of about 4 mV of the AM modulator 13, the minimum output power in a completely canceled state cannot be obtained. As a result, as shown in FIG. 15, the DC offset voltage difference between the non-inverted input signal AMMODi / p (T) and the inverted input signal AMMODi / p (B) of the AM modulator 13 is less than or equal to the input DC offset voltage difference of about 4 mV. Even if it decreases, the output power of the AM modulator 13 cannot be reduced, and the target value −58 dBm of the minimum output power of the AM modulator 13 cannot be satisfied.

  Therefore, in the RFIC 1 according to the third embodiment of the present invention shown in FIG. 14, in order to further reduce the minimum output power of the AM modulator 13, for example, the idle mode immediately after power-on is set in advance of the time slot of the transmission operation. Thus, the DC offset calibration operation is executed, and it is also possible to execute the DC offset calibration every time at the timing immediately before the time slot of the transmission operation in consideration of the power supply voltage, temperature dependency and the like.

  In this DC offset calibration operation, the 8-bit DC offset control signal DC-offset control supplied from the other control register 23 to the variable voltage source built in the D / A converter 15 is updated. The variable voltage source built in the D / A converter 15 generates a variable voltage of −127 mV to +127 mV in response to the 8-bit DC offset control signal DC-offset control. Accordingly, the output DC offset voltage difference between the two analog conversion output signals of the D / A converter 15 is changed, and the DC offset voltage of the differential output terminal of the first AM modulator 133 of the AM modulator 13 is changed to the DC offset voltage measuring circuit. Measured by 136 differential amplifier AMP and voltage comparator CMP. The D / A converter 15 incorporates an 8-bit DC offset control signal DC-offset control so that the DC offset voltage of the differential output terminal of the first AM modulator 133 of the AM modulator 13 to be measured is minimized. The variable voltage level of the variable voltage source is set.

  In a specific embodiment, the polarity (voltage magnitude relationship) of the bias voltages Vb3 and Vb4 of the gates of the transistor pairs M3 and M4 and the transistor pairs M5 and M6 of the first AM modulator 133 is reversed in the DC offset calibration operation. Is done. This polarity inversion is enabled by level inversion of the polarity change signal Polarity change supplied from the control register 22 to the bias voltage generator that generates the bias voltages Vb3 and Vb4 of the AM modulator 13. Therefore, the DC offset calibration operation is performed twice before and after the polarity inversion, and the variable voltage level of the variable voltage source of the D / A converter 15 which is the calibration result of the two DC offset calibration operations is averaged. The Therefore, the influence due to the deviation of the circuit constants of the differential amplifier AMP and the voltage comparator CMP of the DC offset voltage measuring circuit 136 of the AM modulator 13 can be reduced.

  In addition, between two DC offset calibration operations, the buffer 122 is controlled to be in the cutoff state by supplying the buffer cutoff signal Buffer_off generated from the control register 23 to the buffer 122. Accordingly, the non-inverted transmission RF carrier signal and the inverted transmission RF carrier signal from the frequency divider 121 are transmitted to the gates of the transistor pairs M3, M4, M5, and M6 between the two DC offset calibration operations. It is prohibited.

  With the above-described DC offset calibration operation, the DC offset calibration of the first AM modulator 133 of the AM modulator 13 corresponding to the low band (GSM850, GSM900) of about 1 GHz is completed. Next, the DC offset calibration of the second AM modulator 134 of the AM modulator 13 for supporting the high band (DCS1800, PCS1900) of approximately 2 GHz is performed, and the DC offset calibration operation for the first AM modulator 133 is performed. Can be executed as well. For example, a second variable voltage source for the second AM modulator 134 is disposed inside the D / A converter 15 and the variable voltage level of the second variable voltage source is determined by two DC offset calibration operations. Can be set by averaging. Further, the DC offset calibration of the second AM modulator 134 can be executed in the idle mode immediately after the power is turned on, for example, immediately before the transmission operation time slot, and the power supply voltage, temperature dependency, etc. are taken into consideration. It is also possible to execute DC offset calibration every time at the timing immediately before the time slot of the transmission operation.

  FIG. 16 shows the operation of the AM modulator 13 when the input DC offset is reduced to about 2 mV or less by performing the DC offset calibration operation twice before and after the polarity inversion of the first AM modulator 133 described above. FIG.

  As a result of the two DC offset calibration operations before and after the polarity inversion, as shown in FIG. 16, the DC offset of the non-inverted input signal AMMODi / p (T) and the inverted input signal AMMODi / p (B) of the AM modulator 13 The voltage difference can be reduced to an input DC offset voltage difference of about 2 mV, the output power of the AM modulator 13 can be reduced, and the target value of the minimum output power of the AM modulator 13 is −58 dBm. Can do.

[Embodiment 4]
<Configuration of mobile phone>
FIG. 17 is a block diagram showing a configuration of a mobile phone supporting multiband according to the fourth embodiment of the present invention.

  The mobile phone corresponding to the multiband shown in FIG. 17 is an RFIC 1 including a polar modulator transmitter for EDGE transmission according to any one of the first to third embodiments of the present invention described above, and baseband signal processing. An LSI 6, an RF power module (PM) 3, an analog front end module (FEM) 4, and an antenna (ANT) 5 are included.

  In FIG. 17, a common input / output terminal of an analog front end module (FEM) 4 is connected to a transmitting / receiving antenna (ANT) 5 of a mobile phone. A front end module activation signal FEM_ON is supplied from the RFIC 1 to the analog front end module (FEM) 4. The flow of the RF signal from the transmission / reception antenna (ANT) 5 to the common input / output terminal of the analog front end module (FEM) 4 becomes the reception operation RX of the mobile phone, and the transmission / reception antenna (ANT) 5 from the common input / output terminal. The flow of the RF signal to is the transmission operation TX of the mobile phone.

  The RFIC 1 performs frequency up-conversion of the transmission baseband signal from the baseband signal processing LSI 6 to an RF transmission signal, and conversely, frequency-converts the RF reception signal received by the transmission / reception antenna (ANT) 5 into a reception baseband signal. To the baseband signal processing LSI 6.

  For GMSK communication and EDGE communication, the antenna switch in the analog front end module (FEM) 4 is connected between a common input / output terminal and one of the transmission terminals Tx1, Tx2, the reception terminals Rx1, Rx2, Rx3, and Rx4. Then, a signal path is established, and either reception operation RX or transmission operation TX is performed. The switch for receiving and transmitting the RF signal is composed of HEMT (High Electron Mobility Transistor), and the antenna switch is composed of a microwave monolithic integrated circuit (MMIC) using a compound semiconductor such as GaAs. The antenna switch MMIC can obtain necessary isolation by setting the impedance of a signal path other than the signal path established for either the reception operation RX or the transmission operation TX to an extremely high value. In the field of antenna switches, a common input / output terminal is called a single pole, and a total of six terminals of transmission terminals Tx1, Tx2 and reception terminals Rx1, Rx2, Rx3, Rx4 are 6 throws (6 throw). ). Therefore, the MMIC of this antenna switch is a single pole 6 throw (SP6T) type switch.

  On the other hand, for code-division multiple access (CDMA) in WCDMA communication, a duplexer in the analog front-end module (FEM) 4 performs a transmission operation TX between a common input / output terminal and a transmission terminal Tx3. And establishes a parallel signal path with the receiving operation RX between the common input / output terminal and the receiving terminal Rx5.

  From the reception terminal Rx5 of the analog front end module (FEM) 4, a WCDMA Band I RF reception input signal of 2110 to 2170 MHz or a WCDMA Band II RF reception input signal of 1930 to 1990 MHz is output, and is output to the WCDMA reception unit 141 of the RFIC1. Supplied.

  An RF reception input signal of PCS1900 of 1930 to 1990 MHz is output from the reception terminal Rx4 of the analog front end module (FEM) 4 and supplied to the GSM / EDGE reception unit 142 of the RFIC1. PCS is an abbreviation for Personal Communication System.

  An RF reception input signal of DCS 1800 of 1805 to 1880 MHz is output from the reception terminal Rx3 of the analog front end module (FEM) 4 and supplied to the GSM / EDGE reception unit 142 of RFIC1. DCS is an abbreviation for Digital Cellular System.

  From the reception terminal Rx2 of the analog front end module (FEM) 4, an RF reception input signal of 925 to 960 MHz of GSM900 is output and supplied to the GSM / EDGE reception unit 142 of RFIC1.

  An RF reception input signal of GSM850 of 869 to 894 MHz is output from the reception terminal Rx1 of the analog front end module (FEM) 4 and supplied to the GSM / EDGE reception unit 142 of RFIC1.

  The reception analog baseband signal generated by the WCDMA reception unit 111 or the GSM / EDGE reception unit 142 is converted into an A / D converter of the A / D conversion / D / A conversion unit 146 via an analog front end unit (AFE) 145. To be supplied. Accordingly, the A / D converter of the A / D conversion / D / A conversion unit 116 generates a received digital baseband signal of the low voltage differential signal interface (LVDS / IF), and the digital RF of the baseband signal processing LSI 6. Supplied to interface Dig RF. Note that LVDS is an abbreviation for Low Voltage Differential Signaling.

  The digital RF interface Dig RF between the RFIC 1 and the baseband signal processing LSI 6 includes signals conforming to the DigRF specification such as a system clock signal Sysclk and a system clock enable signal Sysclken.

  The transmission digital baseband signal of the low-voltage differential signal interface (LVDS / IF) from the baseband signal processing LSI 6 is supplied to the D / A converter of the A / D conversion / D / A conversion unit 146. Accordingly, the transmission analog baseband signal output from the D / A converter of the A / D conversion / D / A conversion unit 146 is supplied to the analog front end unit (AFE) 145. The GSM or EDGE transmission analog baseband signal is supplied from the analog front end unit (AFE) 145 to the GSM / EDGE transmission unit 143. The GSM / EDGE transmission unit 143 includes a polar modulator transmitter for EDGE transmission according to any one of the first to third embodiments of the present invention described above.

  The RF transmission output signal of GSM850 of 824 to 849 MHz or the RF transmission output signal of GSM900 of 880 to 915 MHz generated from the GSM / EDGE transmission unit 143 is the first RF power amplifier PA1 of the transmission terminal Tx1 and the RF power module (PM) 3. And an analog front end module (FEM) 4 and a transmission / reception antenna (ANT) 5.

  The RF transmission output signal of the DCS 1800 of 1710 to 1785 MHz and the RF transmission output signal of the PCS 1900 of 1850 to 1910 MHz generated from the GSM / EDGE transmission unit 143 are the second RF power amplifier PA2 of the transmission terminal Tx2 and the RF power module (PM) 3. And an analog front end module (FEM) 4 and a transmission / reception antenna (ANT) 5.

  The WCDMA transmission analog baseband signal is supplied from the analog front end unit (AFE) 145 to the WCDMA transmission unit 114. The 1920 to 1980 MHz WCDMA Band I RF transmission signal or the 1850 to 1910 MHz WCDMA Band II RF transmission signal includes the transmission terminal Tx2, the third RF power amplifier PA3 of the RF power module (PM) 3, and the analog front end module (FEM). 4 and a transmission / reception antenna (ANT) 5.

  Further, an automatic power control voltage Vapc, an RF power amplifier activation signal PA_ON, and a frequency band selection signal Band_sel are supplied from the RFIC 1 to the RF power module (PM) 3.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

[Other embodiments]
For example, in the RFIC 1 of FIG. 4, the phase locked loop 11 is not limited to the all-digital phase locked loop. That is, in the phase-locked loop 11, the phase digital converter 111 can be replaced with a phase comparator, the digital loop filter 112 can be replaced with an analog loop filter, and the digital controlled oscillator 113 is a voltage controlled oscillator. (VCO) can be substituted.

  In FIG. 6, the transistors M1 to M6 of the Gilbert cell of the AM modulator 13 are not limited to N-channel MOS transistors, but can be replaced by NPN bipolar transistors.

  Further, in FIG. 17, the interface between the RFIC 1 and the baseband signal processing LSI 6 is not limited to the digital RF interface, and an analog reception baseband signal and an analog transmission baseband signal are transmitted between the two. It is also possible to adopt an analog interface.

  For example, in FIG. 6, the RFIC output is converted into a single-ended RF transmission signal using differential inductors L1 and L2 and a balun 2, but the inductor and balun are incorporated in the RFIC1. It is also possible to output a single-ended RF transmission signal from the RFIC 1.

1. RF signal processing semiconductor integrated circuit (RFIC)
2 ... Balun 3 ... RF power module 31 ... RF power amplifier (PA)
32 ... RF power detector (DET)
4. Front end module (FEM)
5 ... Transmitting antenna 6 ... Baseband signal processing LSI
10 ... Digital modulator 11 ... All-digital phase-locked loop (ADPLL)
DESCRIPTION OF SYMBOLS 12 ... Buffer / frequency divider 13 ... AM modulator 14 ... Ramp generator Sub ... Digital subtractor Multi ... Digital multiplier 15 ... D / A converter 16 ... A / D converter SW1 ... Switch 17, 18 ... Low pass filter DESCRIPTION OF SYMBOLS 19 ... Control unit 111 ... Phase digital converter 112 ... Digital loop filter 113 ... Digital control oscillator 114 ... Fractional frequency divider 115 ... Sigma-delta modulator

Claims (22)

A transmitter capable of generating an EDGE RF transmission signal, comprising a digital modulator, a ramp generator, a digital multiplier, a D / A converter, a phase-locked loop, and an AM modulator,
In response to the transmission data, the digital modulator generates a digital amplitude component and a digital phase component,
The digital amplitude component generated from the digital modulator is supplied to one input terminal of the digital multiplier, and the digital phase component generated from the digital modulator is supplied to one input terminal of the phase-locked loop. A reference frequency signal is supplied to the other input terminal of the phase-locked loop,
The ramp generator generates a ramp control digital control signal in response to the ramp data,
The other input terminal of the digital multiplier responds to the ramp control digital control signal generated from the ramp generator, and the output signal of the digital multiplier is supplied to the input terminal of the D / A converter;
The analog output signal of the D / A converter can be supplied to one input terminal of the AM modulator,
Since the RF carrier signal based on the oscillation output signal of the phase-locked loop can be transmitted to the other input terminal of the AM modulator, the RF transmission signal of the EDGE system is generated from the output terminal of the AM modulator. Is possible,
In the ramp-up operation in the first half of the transmission time slot of the RF transmission signal of the EDGE system, the ramp signal is supplied to the one input terminal of the AM modulator in response to the ramp data supplied to the ramp generator. The analog output signal of the D / A converter increases;
In the ramp-down operation in the latter half of the transmission operation time slot of the RF transmission signal of the EDGE method, the ramp signal is supplied to the one input terminal of the AM modulator in response to the ramp data supplied to the ramp generator. The analog output signal of the D / A converter decreases,
In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is lower than a predetermined value, the gain of the AM modulator is controlled to a low value,
In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is higher than the predetermined value, the gain of the AM modulator is controlled to a higher value than the low value. . A control unit for comparing the lamp data with the reference lamp data;
The reference ramp data corresponds to the predetermined value of the transmission power, and the gain of the AM modulator is determined by an output signal of the control unit when the value of the ramp data is larger than the value of the reference ramp data. The transmitter according to claim 1, wherein is controlled to the high value. The gain of the AM modulator is controlled to the high value during the ramp-up operation in response to completion of a first count-up of a pulse of a predetermined frequency clock signal associated with the ramp-up operation. Yes,
Further, during the ramp down operation, the gain of the AM modulator is controlled to the low value in response to completion of a second count up of the pulse of the clock signal at the predetermined frequency associated with the ramp down operation. The transmitter according to claim 1. The ramp-up operation is controlled by a ramp-up start command,
In response to the completion of the first count up of the pulses of the clock signal of the predetermined frequency initiated by the ramp up start command, the gain of the AM modulator is high during the ramp up operation. Is controlled by the value,
The ramp down operation is controlled by a ramp down start command,
In response to the completion of the second count up of the pulse of the clock signal at the predetermined frequency initiated by the ramp down start command, the gain of the AM modulator is low during the ramp down operation. 4. The transmitter according to claim 3, which is controlled by a value. The AM modulator includes a first transistor pair, a second transistor pair, and a third transistor pair constituting a Gilbert cell,
A non-inverting input signal and an inverting input signal, which are the analog output signals of the D / A converter, are supplied to both control electrodes of the first transistor pair,
The control electrodes of the second transistor pair and the third transistor pair have a non-inverted transmission RF carrier signal and an inverted transmission RF carrier signal that are the RF carrier signals based on the oscillation output signal of the phase-locked loop. The transmitter according to claim 1, which is supplied.   A DC offset voltage difference between the non-inverting input signal that is the analog output signal of the D / A converter and the inverting input signal, the non-inverting input signal that is the analog output signal of the D / A converter, and the The transmitter according to claim 5, wherein the AC amplitude component with the inverting input signal increases in proportion to an increase in the value of the ramp data. The input electrodes of the first transistor pair are connected to a ground potential through a resistor pair;
One output electrode and the other output electrode of the first transistor pair are connected to both input electrodes of the second transistor pair and both input electrodes of the third transistor pair, respectively.
One output electrode of the second transistor pair and one output electrode of the third transistor pair are connected in common to one output terminal of the AM modulator,
The transmitter according to claim 6, wherein the other output electrode of the second transistor pair and the other output electrode of the third transistor pair are commonly connected to the other output terminal of the AM modulator. .   The transmission according to claim 7, wherein the gain control of the AM modulator is realized by controlling a resistance value of the resistor pair or controlling a parallel connection number of a transistor group pair of the first transistor pair. Machine.   The transmission according to claim 7, wherein the gain control of the AM modulator is controlled by a gain control circuit including an element that bypasses a signal of the output electrode of the first transistor pair to an AC ground node. Machine. A DC offset voltage measuring circuit for detecting an output DC offset voltage between the one output terminal and the other output terminal of the AM modulator;
The DC offset voltage measuring circuit supplies the D / A converter supplied to the control electrodes of the first transistor pair so that the output DC offset voltage is minimized during a DC offset calibration operation. The transmitter according to claim 7, wherein an input DC offset voltage between the non-inverted input signal and the inverted input signal which is the analog output signal is adjustable.   11. The DC offset calibration operation by the DC offset voltage measurement circuit can be executed in an idle mode preceding the transmission operation time slot or at a timing immediately before the transmission operation time slot. Transmitter. The present invention can be used for a transmitter capable of generating an EDGE type RF transmission signal, and includes a digital modulator, a ramp generator, a digital multiplier, a D / A converter, a phase-locked loop, an AM modulator, A semiconductor integrated circuit comprising:
In response to the transmission data, the digital modulator generates a digital amplitude component and a digital phase component,
The digital amplitude component generated from the digital modulator is supplied to one input terminal of the digital multiplier, and the digital phase component generated from the digital modulator is supplied to one input terminal of the phase-locked loop. A reference frequency signal is supplied to the other input terminal of the phase-locked loop,
The ramp generator generates a ramp control digital control signal in response to the ramp data,
The other input terminal of the digital multiplier responds to the ramp control digital control signal generated from the ramp generator, and the output signal of the digital multiplier is supplied to the input terminal of the D / A converter;
The analog output signal of the D / A converter can be supplied to one input terminal of the AM modulator,
Since the RF carrier signal based on the oscillation output signal of the phase-locked loop can be transmitted to the other input terminal of the AM modulator, the RF transmission signal of the EDGE system is generated from the output terminal of the AM modulator. Is possible,
In the ramp-up operation in the first half of the transmission time slot of the RF transmission signal of the EDGE system, the ramp signal is supplied to the one input terminal of the AM modulator in response to the ramp data supplied to the ramp generator. The analog output signal of the D / A converter increases;
In the ramp-down operation in the latter half of the transmission operation time slot of the RF transmission signal of the EDGE method, the ramp signal is supplied to the one input terminal of the AM modulator in response to the ramp data supplied to the ramp generator. The analog output signal of the D / A converter decreases,
In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is lower than a predetermined value, the gain of the AM modulator is controlled to a low value,
In the ramp-up operation and the ramp-down operation, when the transmission power of the transmitter is higher than the predetermined value, the gain of the AM modulator is controlled to a higher value that is higher than the lower value. circuit. A control unit for comparing the lamp data with the reference lamp data;
The reference ramp data corresponds to the predetermined value of the transmission power, and the gain of the AM modulator is determined by an output signal of the control unit when the value of the ramp data is larger than the value of the reference ramp data. 13. The semiconductor integrated circuit according to claim 12, wherein is controlled to the high value. The gain of the AM modulator is controlled to the high value during the ramp-up operation in response to completion of a first count-up of a pulse of a predetermined frequency clock signal associated with the ramp-up operation. Yes,
Further, during the ramp down operation, the gain of the AM modulator is controlled to the low value in response to completion of a second count up of the pulse of the clock signal at the predetermined frequency associated with the ramp down operation. The semiconductor integrated circuit according to claim 12. The ramp-up operation is controlled by a ramp-up start command,
In response to the completion of the first count up of the pulses of the clock signal of the predetermined frequency initiated by the ramp up start command, the gain of the AM modulator is high during the ramp up operation. Is controlled by the value,
The ramp down operation is controlled by a ramp down start command,
In response to the completion of the second count up of the pulse of the clock signal at the predetermined frequency initiated by the ramp down start command, the gain of the AM modulator is low during the ramp down operation. The semiconductor integrated circuit according to claim 14, which is controlled by a value. The AM modulator includes a first transistor pair, a second transistor pair, and a third transistor pair constituting a Gilbert cell,
A non-inverting input signal and an inverting input signal, which are the analog output signals of the D / A converter, are supplied to both control electrodes of the first transistor pair,
The control electrodes of the second transistor pair and the third transistor pair have a non-inverted transmission RF carrier signal and an inverted transmission RF carrier signal that are the RF carrier signals based on the oscillation output signal of the phase-locked loop. The semiconductor integrated circuit according to claim 12, which is supplied.   A DC offset voltage difference between the non-inverting input signal that is the analog output signal of the D / A converter and the inverting input signal, the non-inverting input signal that is the analog output signal of the D / A converter, and the 17. The semiconductor integrated circuit according to claim 16, wherein the AC amplitude component with the inverting input signal increases in proportion to an increase in the value of the ramp data. The input electrodes of the first transistor pair are connected to a ground potential through a resistor pair;
One output electrode and the other output electrode of the first transistor pair are connected to both input electrodes of the second transistor pair and both input electrodes of the third transistor pair, respectively.
One output electrode of the second transistor pair and one output electrode of the third transistor pair are connected in common to one output terminal of the AM modulator,
18. The semiconductor integrated circuit according to claim 17, wherein the other output electrode of the second transistor pair and the other output electrode of the third transistor pair are commonly connected to the other output terminal of the AM modulator. circuit.   19. The semiconductor according to claim 18, wherein the gain control of the AM modulator is realized by controlling a resistance value of the resistor pair or controlling a parallel connection number of a transistor group pair of the first transistor pair. Integrated circuit.   19. The semiconductor according to claim 18, wherein the gain control of the AM modulator is controlled by a gain control circuit including an element that bypasses a signal of the output electrode of the first transistor pair to an AC ground node. Integrated circuit. A DC offset voltage measuring circuit for detecting an output DC offset voltage between the one output terminal and the other output terminal of the AM modulator;
The DC offset voltage measuring circuit supplies the D / A converter supplied to the control electrodes of the first transistor pair so that the output DC offset voltage is minimized during a DC offset calibration operation. 19. The semiconductor integrated circuit according to claim 18, wherein an input DC offset voltage between the non-inverted input signal and the inverted input signal which is the analog output signal is adjustable.   The DC offset calibration operation by the DC offset voltage measurement circuit can be executed in an idle mode preceding the transmission operation time slot or at a timing immediately before the transmission operation time slot. Semiconductor integrated circuit.

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