JP2010245425A - Resistance change-type nonvolatile storage device, and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resistance change-type nonvolatile storage device capable of suppressing a resistance variation and improving a manufacturing yield. <P>SOLUTION: The resistance change-type nonvolatile storage device is equipped with: a substrate 21; first and second diffusion layers 22a, 29a formed on the substrate 21; interlayer insulating layers formed on the first and second diffusion layers 22a, 29a; a resistance change element 36 formed at the interlayer insulating layers; and wiring 26 formed on the interlayer insulating layers. The impedance of a first electrical connection path from the wiring 26 to a first diffusion layer 22a through the resistance change element 36 is higher than the impedance of a second electrical connection path from the wiring 26 to the second diffusion layer 29a, and a first region 34 constituting the first electrical connection path is a plane layout separable from a second region 38 constituting the second electrical connection path. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a variable resistance nonvolatile memory device using a state change material whose resistance value changes according to a given pulse voltage and a method for manufacturing the variable resistance nonvolatile memory device.

  2. Description of the Related Art In recent years, electronic devices such as portable information devices and information home appliances have become more sophisticated with the progress of digital technology. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a nonvolatile memory element capable of high-speed reading / writing with low power consumption as a memory element is rapidly expanding. An element having a configuration using a resistance change layer as a memory portion of the element is disclosed (for example, see Patent Document 1).

  As a conventional example, a nonvolatile resistance memory element disclosed in Non-Patent Document 1 will be described with reference to FIG.

  FIG. 10 is a cross-sectional view of a resistance change memory which is a nonvolatile resistance memory element according to a conventional example. A lower electrode 6 having a contact plug shape is formed on the first wiring 2, and a resistance change film 1 and an upper electrode 4 made of a two-element oxide are disposed thereon. Further, a contact 3 for drawing out a potential to the second wiring 5 is disposed on the upper electrode 4.

JP 2004-87069 A

IEDM2005 Session 31-4: Multi-layer Cross-point BinaryOxide Resistive Memory (OxRRAM) for Post-NAND Storage Application

  FIG. 11 is a diagram showing the relationship between the oxygen content and the resistance when the variable resistance layer is made of a transition metal oxide. FIG. 11 shows that the resistance increases as the oxygen content increases. Therefore, by determining the oxygen profile in the resistance change layer (which part in the resistance change layer creates a region containing oxygen at a high concentration, for example, forming a high oxygen content region near the upper electrode). The initial resistance can be adjusted.

  In addition, the resistance change element usually has a capacitor-like structure with a resistance change film sandwiched between the upper and lower electrodes. However, if the structure is symmetrical in the vertical direction, the operation is completely opposite to the voltage application direction. Sometimes For example, when a negative voltage is applied to the upper electrode, there are cases where the resistance decreases and the resistance increases. In such an unstable state, a resistance change occurs near the interface between the upper and lower electrodes and the resistance change film, and the resistance changes near the upper interface or changes at the lower interface due to process variations. Therefore, it is desirable to avoid it from the viewpoint of circuit design. Therefore, various asymmetric variable resistance element structures have been proposed in order to stabilize the operation in the direction of the applied voltage. For example, the oxygen concentration of the resistance change film in the vicinity of the interface where resistance change is desired is increased.

  However, there is a problem that the predicted initial resistance cannot be obtained even if the variable resistance layer is formed so as to have a desired oxygen profile.

  FIG. 12 shows dry etching or film deposition for processing a wiring formed after the resistance change element into a resistance change element in which the oxygen content in the upper resistance change layer is higher than the oxygen content in the lower layer. It is a figure which shows the influence when charge damage is added by plasma CVD etc. for. The graph shown on the right is an example of a result of measuring the distribution of the oxygen content rate in the depth direction of the resistance change layer by Auger analysis (AES). The solid line indicates the oxygen profile at the beginning of the production of the variable resistance layer, and the dotted line indicates the oxygen profile after the charge damage.

  When negative charge damage is applied to the upper electrode side, the negatively charged oxygen ions are attracted to the lower layer side. Since oxygen ions move in the resistance change layer in this way, the initially produced oxygen profile (solid line) is destroyed (broken line).

  In particular, as shown in FIG. 11, as the oxygen content increases, the degree of change in resistance increases. Therefore, the movement of oxygen ions in the upper resistance change layer having a high oxygen content greatly affects the resistance. As a result, there arises a problem that the expected initial resistance cannot be obtained.

  The present invention solves the above-described problems, and an object thereof is to provide a variable resistance nonvolatile memory device that reduces variations in initial resistance and dramatically improves the manufacturing yield of variable resistance elements.

  To achieve the above object, a variable resistance nonvolatile memory device according to the present invention includes a substrate, a first diffusion layer and a second diffusion layer formed on the substrate, the first diffusion layer, and A resistance change element formed by laminating an interlayer insulating layer formed on the second diffusion layer, a lower electrode, a resistance change layer made of a metal oxide, and an upper electrode in this order, formed in the interlayer insulating layer And a wiring formed on the interlayer insulating layer, and an impedance of a first electrical connection path from the wiring to the first diffusion layer through the resistance change element is The impedance is higher than the impedance of the second electrical connection path to the second diffusion layer, and the second diffusion layer and the wiring are configured in a planar layout that is easy to electrically separate.

  With this configuration, the charge damage current after forming the variable resistance element flows to the second diffusion layer having a lower impedance than the variable resistance element, and hardly flows to the variable resistance element. .

  In a preferred embodiment, the second diffusion layer and the wiring are described in a plane layout that can be electrically separated in one cross section.

  With this configuration, the charge damage current after forming the resistance change element flows to the diffusion layer having a lower impedance than the resistance change element, and it is difficult to flow to the resistance change element, so that the destruction of the oxygen profile due to charge damage can be prevented, and The second connection path that is not required during device operation can be easily separated from the element portion, and the element area can be reduced. Further, the possibility of malfunction caused by the second connection path during device operation can be completely eliminated.

  In one preferable embodiment, the substrate is a p-type semiconductor, the first diffusion layer and the second diffusion layer are n-type semiconductors, and the variable resistance layer is on the lower electrode side. A laminated structure comprising a first variable resistance layer and a second variable resistance layer disposed on the upper electrode side, wherein the oxygen content of the second variable resistance layer is the first variable resistance; It is characterized by being higher than the oxygen content of the layer.

  In a preferred embodiment, a third diffusion layer is provided between the substrate and the first diffusion layer, the substrate and the first diffusion layer are p-type semiconductors, The second diffusion layer and the third diffusion layer are n-type semiconductors, and the variable resistance layer is a first variable resistance layer disposed on the lower electrode side and a second variable layer disposed on the upper electrode side. It has a laminated structure composed of a resistance change layer, and the oxygen content of the second resistance change layer is higher than the oxygen content of the first resistance change layer.

  In a preferred embodiment, a third diffusion layer is provided between the substrate and the second diffusion layer, the substrate and the second diffusion layer are p-type semiconductors, The first diffusion layer and the third diffusion layer are n-type semiconductors, and the variable resistance layer is a first variable resistance layer disposed on the lower electrode side and a second variable layer disposed on the upper electrode side. It has a laminated structure composed of a resistance change layer, and the oxygen content of the second resistance change layer is lower than the oxygen content of the first resistance change layer.

  Further, in a preferred embodiment, a third diffusion layer is provided between the substrate and the first diffusion layer and the second diffusion layer, and the substrate, the first diffusion layer, and the The second diffusion layer is a p-type semiconductor, the third diffusion layer is an n-type semiconductor, and the resistance change layer includes the first resistance change layer and the upper electrode side disposed on the lower electrode side. And the second resistance change layer has a lower oxygen content than that of the first resistance change layer.

  In a preferred embodiment, the area of the second diffusion layer is larger than the area of the first diffusion layer.

  The method of manufacturing a variable resistance nonvolatile memory device according to the present invention includes a step of forming a first diffusion layer and a second diffusion layer on a substrate, and the first diffusion layer and the second diffusion layer. Forming a first interlayer insulating layer thereon, forming a first contact plug penetrating through the first interlayer insulating layer and reaching the first diffusion layer, and the first interlayer insulating layer Forming a resistance change element by sequentially stacking a lower electrode, a resistance change layer, and an upper electrode on a portion of the layer where the first contact plug is formed; and the resistance change element and the first interlayer insulation Forming a second interlayer insulating layer on the layer; forming a second contact plug passing through the second interlayer insulating layer and reaching the upper electrode; and the second interlayer insulating layer and The second diffusion layer penetrating through the first interlayer insulating layer Forming a third contact plug reaching the second contact plug; forming a wiring electrically connected to the second contact plug and the third contact plug on the second interlayer insulating layer; A step of electrically separating the contact plug and the wiring from the wiring to the first diffusion layer via the second contact plug, the variable resistance element, and the first contact plug. The impedance of one electrical connection path is higher than the impedance of the second electrical connection path from the wiring to the second diffusion layer through the third contact plug.

  With this configuration, the charge damage current after formation of the resistance change element flows to the second diffusion layer having a lower impedance than the resistance change element, and does not easily flow to the resistance change element. And the 2nd connection path | route which becomes unnecessary at the time of device operation | movement can be easily cut | disconnected from an element part, and an element area can be reduced. Further, the possibility of malfunction caused by the second connection path during device operation can be completely eliminated.

  In a preferred embodiment, a dicing method is used in the step of electrically separating the third contact plug and the wiring.

  In a preferred embodiment, an etching method is used in the step of electrically separating the third contact plug and the wiring.

  Since the variable resistance nonvolatile memory device of the present invention includes a diffusion layer having a lower impedance in parallel, current due to charge damage hardly flows through the variable resistance layer, so that the oxygen profile is not destroyed. . As a result, variations in initial resistance can be reduced, and the production yield of the variable resistance nonvolatile memory device can be greatly improved.

Sectional drawing of the variable resistance nonvolatile memory device in the first embodiment of the invention Explanatory drawing of the effect of the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Process sectional drawing which shows the manufacturing method of the variable resistance nonvolatile memory device of this invention Sectional drawing of the variable resistance nonvolatile memory device in the second embodiment of the present invention Sectional drawing of the variable resistance nonvolatile memory device in the third embodiment of the invention Sectional drawing of the variable resistance nonvolatile memory device in the fourth embodiment of the invention Layout schematic diagram of variable resistance nonvolatile memory device according to fifth embodiment of the invention Layout schematic diagram of variable resistance nonvolatile memory device according to fifth embodiment of the invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change type non-volatile memory device used in the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the resistance change non-volatile memory device used in the 7th Embodiment of this invention Sectional drawing of the non-volatile memory element which concerns on a prior art example Explanatory drawing of the relationship between oxygen content and resistance in the resistance variable layer Explanatory diagram of the influence of charge content damage and oxygen content distribution in the variable resistance layer

  Hereinafter, a variable resistance nonvolatile memory device according to an embodiment of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component and description may be abbreviate | omitted. In addition, in the drawings, there are portions in which the scale is exaggerated for easy understanding.

(First embodiment)
FIG. 1 is a cross-sectional view of a variable resistance nonvolatile memory device 100 according to the first embodiment of the present invention.

  As shown in FIG. 1, in the nonvolatile memory device 100, the first n-type diffusion layer 22a and the n-type impurity such as As are formed on the main surface of the substrate 21 having the p-type conductivity by the n-type impurity such as As. A second n-type diffusion layer 29a is provided. On the substrate 21, a first interlayer insulating layer 23 made of a silicon oxide film with a thickness of 350 nm, a lower electrode 27 with a thickness of 30 nm made of TaN, etc., an oxide of a first transition metal (for example, a first transition metal) A first resistance change layer 24a having a thickness of 40 nm and a second resistance change layer 24b having a thickness of 10 nm made of a second transition metal oxide (for example, a second tantalum oxide). , Pt and the like upper electrode 28 having a thickness of 50 nm and a second interlayer insulating layer 25 made of a silicon oxide film having a thickness of 350 nm are sequentially arranged from the bottom. On the second interlayer insulating layer 25, a wiring 26 made of an Al material having a thickness of 500 nm and a width of 0.3 μm is provided.

  Here, the lower electrode 27, the first and second resistance change layers 24 a and 24 b, and the upper electrode 28 constitute a resistance change element 36.

  Further, in the region where the first n-type diffusion layer 22a and the wiring 26 are connected via the upper electrode 28, the first and second resistance change layers 24b and 24a, and the lower electrode 27, two upper and lower diameters of 0.25 μm are provided. Contact holes 32 and 31 are provided. A contact hole 33 having a diameter of 0.25 μm is provided in a region connecting the wiring 26 and the second n-type diffusion layer 29a via the first and second interlayer insulating layers 23 and 25. Contact plugs made of tungsten (W) and titanium nitride (TiN) materials are embedded in the contact holes 31, 32, 33 so as to penetrate one or both of the first and second interlayer insulating layers 23, 25. ing.

  In order to operate a part of the first and second resistance change layers 24a and 24b as a memory portion of the resistance change element, an electric pulse is applied to the first and second resistance change layers 24a and 24b. A material that stably increases or decreases the resistance value of the storage unit is used. At this time, the resistance value of the memory unit can stably have two different resistance values depending on the characteristics of the applied electric pulse.

  When the first and second resistance change layers 24a and 24b are made of the same transition metal oxide, the initial resistance changes according to the oxygen content.

In the present embodiment, the second resistance change layer 24b contains oxygen at a higher concentration than the first resistance change layer 24a (in other words, the tantalum oxide constituting the first resistance change layer 24a is TaO. _x, when expressed as TaO _y tantalum oxide constituting the second resistance layer 24b, x <a y) so prepared was the structure to prevent charge damage to the variable resistance element in the case will be described.

  In the nonvolatile memory device 100, the impedance of the second connection path from the wiring 26 to the substrate 21 through the contact plug provided in the contact hole 33 and the second n-type diffusion layer 29a is as follows. To the substrate 21 via the contact plug provided in the contact hole 32, the resistance change element 36, the contact plug provided in the contact hole 31, and the first n-type diffusion layer 22a. It is configured to be lower than the impedance.

  In order to configure the impedance of the second connection path to be lower than that of the first connection path, for example, the second n-type diffusion layer 29a is installed in a larger area than the first n-type diffusion layer 22a. Is effective. The area of the second n-type diffusion layer 29a is designed to be as large as the restrictions on miniaturization allow (for example, twice or more than the area of the first n-type diffusion layer 22a).

  Here, a positive charge damage current from the wiring 26 toward the substrate 21 generated by processing by a plasma process such as dry etching of the wiring 26 manufactured after the first and second resistance change layers 24a and 24b are formed. This facilitates the movement of oxygen ions from the first resistance change layer 24a having a low oxygen content to the second resistance change layer 24b having a high oxygen content, but the first and second resistance change layers 24a and 24b This is the direction in which the difference in the oxygen content is emphasized, and the oxygen profile of the resistance change element is less likely to be destroyed, and the influence is small.

  On the other hand, the negative charge damage current from the substrate 21 to the wiring 26 includes the first connection path including the first and second resistance change layers 24a and 24b, and the second impedance having a lower impedance than the first connection path. By providing the connection path in parallel, the flow mainly flows to the second connection path. As a result, the negative charge damage current flowing in the first and second resistance change layers 24a and 24b is reduced, and the destruction of the oxygen profile can be reduced.

  The provision of the second n-type diffusion layer 29a having a large area also allows an overcurrent to flow without destroying the nonvolatile memory device 100 when a large charge damage that drives the overcurrent is applied. It is valid.

  During the operation of the nonvolatile memory device 100, the change and determination of the resistance state of the variable resistance element 36 (data writing and reading) are performed by applying a bias voltage through the first connection path. The two connection paths are not related to the operation of the nonvolatile memory device 100.

  For example, the second n-type diffusion layer 29a is set in an open (floating) state, or the non-volatile memory device 100 is set with a reverse bias voltage of a pn diode formed by a junction between the substrate 21 and the second n-type diffusion layer 29a. By operating, current does not flow through the second connection path, and the second connection path does not hinder the operation of the nonvolatile memory device 100.

  FIG. 2 shows a comparison of the initial resistance of the variable resistance element when the second connection path of this embodiment is provided and when it is not provided. The points in the figure indicate the median value of the resistance at 44 points in the wafer surface, and the error bar indicates the range of 1σ of the resistance at the 44 points in the wafer surface. As can be seen from FIG. 2, when the second connection path is provided, the median value is maintained at a high resistance, and the variation is reduced.

  Therefore, the oxygen content distribution in the first and second resistance change layers 24a and 24b can be maintained as originally designed, variation in initial resistance can be reduced, and the production yield of the resistance change type nonvolatile memory device can be reduced. Can be improved dramatically.

  Next, FIG. 3 shows a process cross-sectional view of the method for manufacturing the nonvolatile memory device 100 shown in the present embodiment. 3A to 3F sequentially show the process flow of the nonvolatile memory device 100.

As shown in FIG. 3A, first and second n-type diffusion layers are formed by ion-implanting n-type impurities such as As on the main surface of the substrate 21 with an energy of 20 keV and a dose of 1 × 10 ¹⁵ / cm ² , for example. 22a and 29a are formed, and a first interlayer insulating layer 23 made of a silicon oxide film is formed on the substrate 21 by a CVD method or the like.

  Note that the dose amount of the second n-type diffusion layer 29a may be larger than the dose amount of the first n-type diffusion layer 22a. By increasing the dose amount, the resistance value of the second n-type diffusion layer 29a becomes smaller than the resistance value of the first n-type diffusion layer 22a, so that the impedance of the second connection path is set to the first connection path. It is effective to make it low compared to.

Although not shown, a silicide layer such as a cobalt silicide (CoSi ₂ ) layer having a thickness of several nm may be formed on the second n-type diffusion layer 29a. By interposing the silicide layer, the contact resistance between the second n-type diffusion layer 29a and a contact plug provided in the contact hole 33 in a later step is reduced, so that the impedance of the second connection path is reduced to the first This is effective for a low configuration compared to the connection path.

  Continue to explain the manufacturing method.

  Further, as shown in FIG. 3B, the contact hole 31 having a diameter of 0.25 μm is dug through the first interlayer insulating layer 23 until it reaches the first n-type diffusion layer 22a by dry etching.

  Further, as shown in FIG. 3C, the contact hole 31 is deposited with titanium (hereinafter referred to as W) after depositing titanium nitride (hereinafter referred to as TiN) by a CVD method, and deposited over the first interlayer insulating layer 23 and then subjected to CMP. Using technology, W and TiN on the first interlayer insulating layer 23 are removed and the surface is planarized. As a result, a contact plug made of W and TiN is formed at the position of the contact hole 31.

  Further, as shown in FIG. 3D, TaN serving as the lower electrode 27 is deposited with a thickness of 30 nm by the CVD method, and an oxide of transition metal such as Ta serving as the resistance change layers 24a and 24b is formed by the reactive sputtering method. Films are formed at 40 nm and 10 nm, respectively, and Pt to be the upper electrode 28 is deposited by sputtering to a thickness of 50 nm, and then the resistance change including the upper electrode 28, the resistance change layers 24a and 24b, and the lower electrode 27 is performed by dry etching. An element is formed. The resistance change layer 24b may be formed by changing the oxygen concentration of the reactive sputtering after the resistance change layer 24a is formed by the reactive sputtering method, or the surface of the resistance change layer 24a may be formed by the plasma oxidation method. Oxidation may be performed with such as.

  Further, as shown in FIG. 3E, a silicon oxide film is deposited by a CVD method or the like, and then a second interlayer insulating layer 25 having a thickness of 350 nm is formed by using a CMP technique. Thereafter, contact holes 32 and 33 having a diameter of 0.25 μm are formed by a dry etching method. In the contact hole 32, the contact hole passes through the second interlayer insulating layer 25 and reaches the upper electrode 28. In 33, digging is performed until the second n-type diffusion layer 29a is reached through the second and first interlayer insulating layers 25 and 23.

  Further, as shown in FIG. 3F, after the contact holes 32 and 33 are deposited by Ti after vapor deposition of TiN by CVD method and deposited on the second interlayer insulating layer 25, the second interlayer is formed by using the CMP technique. W and TiN on the insulating layer 25 are removed and the surface is planarized. As a result, contact plugs made of W and TiN are formed in the contact holes 32 and 33. A wiring 26 made of an Al material or the like is formed on these contact plugs by a vapor deposition method and a dry etching method with a width of 0.3 μm and a thickness of 500 nm.

  The nonvolatile memory device 100 is manufactured by the above process flow. By this manufacturing process, the second connection path having a lower impedance than the first connection path is provided in parallel with the first connection path including the resistance change element 36 before the dry etching for processing the wiring 26 is performed. Therefore, a current caused by charge damage caused by processing of the wiring 26 by dry etching or the like is mainly guided to the diffusion layer through the second connection path, and as a result, flows to the first and second resistance change layers 24a and 24b. Charge damage current decreases.

  Therefore, the oxygen content distributions in the first and second resistance change layers 24a and 24b can be maintained as originally designed, variation in initial resistance can be reduced, and the manufacturing yield of the nonvolatile memory device can be dramatically increased. Can be improved.

(Second Embodiment)
FIG. 4 is a cross-sectional view of a variable resistance nonvolatile memory device 200 according to the second embodiment of the present invention.

  As shown in FIG. 4, in the nonvolatile memory device 200, the third n-type diffusion layer 37 made of impurities such as As on the main surface of the substrate 21 having p-type conductivity, and the second p-type impurities made of B or the like. 1 p-type diffusion layer 22b and a second n-type diffusion layer 29a made of impurities such as As are provided. A first interlayer insulating layer 23 made of a silicon oxide film with a thickness of 350 nm, a lower electrode 27 made of TaN with a thickness of 30 nm, and an oxide of a transition metal (for example, tantalum oxide) are further formed on the substrate 21. First variable resistance layer 24a having a thickness of 40 nm, second variable resistance layer 24b having a thickness of 10 nm made of transition metal oxide (for example, tantalum oxide), upper electrode 28 having a thickness of 50 nm made of Pt, and thickness A second interlayer insulating layer 25 made of a silicon oxide film having a thickness of 350 nm is sequentially arranged from the bottom. On the second interlayer insulating layer 25, a wiring 26 made of an Al material having a thickness of 500 nm and a width of 0.3 μm is provided.

  Here, the lower electrode 27, the first and second resistance change layers 24 a and 24 b, and the upper electrode 28 constitute a resistance change element 36.

  Further, in the region connecting the first p-type diffusion layer 22b and the wiring 26 via the upper electrode 28, the first and second resistance change layers 24b and 24a, and the lower electrode 27, two upper and lower diameters of 0.25 μm are provided. Contact holes 32 and 31 are provided. A contact hole 33 having a diameter of 0.25 μm is provided in a region connecting the wiring and the second n-type diffusion layer 29a through the first and second interlayer insulating layers 23 and 25. Contact plugs made of tungsten (W) and titanium nitride (TiN) materials are embedded in the contact holes 31, 32, 33 so as to penetrate one or both of the first and second interlayer insulating layers 23, 25. ing.

  In order to operate a part of the first and second resistance change layers 24a and 24b as a memory portion of the resistance change element, an electric pulse is applied to the first and second resistance change layers 24a and 24b. A material that stably increases or decreases the resistance value of the storage unit is used. At this time, the resistance value of the memory unit can stably have two different resistance values depending on the characteristics of the applied electric pulse.

  When the first and second resistance change layers 24a and 24b are formed of transition metal oxides, the initial resistance changes according to the oxygen content.

  In the present embodiment, a configuration for preventing charge damage to the resistance change element when the second resistance change layer 24b is made to contain oxygen at a higher concentration than the first resistance change layer 24a will be described. .

  The positive charge damage current from the wiring 26 to the substrate 21 generated by processing by a plasma process such as dry etching of the wiring 26 produced after the first and second resistance change layers 24a and 24b are formed is oxygen The oxygen content of the first and second resistance change layers 24a and 24b, which facilitates the movement of oxygen ions from the first resistance change layer 24a having a low content to the second resistance change layer 24b having a high oxygen content. The height difference is emphasized, and it is difficult to destroy the oxygen profile of the resistance change element, and the influence is small.

  On the other hand, the negative charge damage current from the substrate 21 to the wiring 26 is caused by the third n-type diffusion layer 37 and the first p in the first connection path including the first and second resistance change layers 24a and 24b. The pn diode formed by the junction with the type diffusion layer 22b is blocked in the reverse direction and flows mainly to the second connection path. That is, in the nonvolatile memory device 200, the impedance of the second connection path is configured to be lower than the impedance of the first connection path with respect to a negative charge damage current.

  A first connection path including the first and second resistance change layers 24a and 24b and a second connection path having a lower impedance than the first connection path with respect to a negative charge damage current are provided in parallel. As a result, a negative charge damage current mainly flows in the second connection path. As a result, almost no negative charge damage current flows through the first and second resistance change layers 24a and 24b, and the destruction of the oxygen profile can be prevented.

  Therefore, the oxygen content distributions in the first and second resistance change layers 24a and 24b can be maintained as originally designed, variation in initial resistance can be reduced, and the manufacturing yield of the resistance change nonvolatile memory device can be reduced. It can be improved dramatically.

(Third embodiment)
FIG. 5 is a sectional view of a variable resistance nonvolatile memory device 300 according to the third embodiment of the present invention.

  As shown in FIG. 5, in the nonvolatile memory device 300, the third n-type diffusion layer 37 made of impurities such as As and the first n-type impurities made of As or the like are formed on the main surface of the substrate 21 having p-type conductivity. N-type diffusion layers 22a, second p-type diffusion layers 29b made of impurities such as B are provided. A first interlayer insulating layer 23 made of a silicon oxide film with a thickness of 350 nm, a lower electrode 27 made of TaN with a thickness of 30 nm, and an oxide of a transition metal (for example, tantalum oxide) are further formed on the substrate 21. First variable resistance layer 24c having a thickness of 40 nm, second variable resistance layer 24d having a thickness of 10 nm made of transition metal oxide (for example, tantalum oxide), upper electrode 28 having a thickness of 50 nm made of Pt, and thickness A second interlayer insulating layer 25 made of a silicon oxide film having a thickness of 350 nm is sequentially arranged from the bottom. On the second interlayer insulating layer 25, a wiring 26 made of an Al material having a thickness of 500 nm and a width of 0.3 μm is provided.

  Here, the lower electrode 27, the first and second resistance change layers 24 c and 24 d, and the upper electrode 28 constitute a resistance change element 36.

  Further, in the region connecting the first n-type diffusion layer 22a and the wiring 26 via the upper electrode 28, the first and second resistance change layers 24c and 24d, and the lower electrode 27, two upper and lower diameters of 0.25 μm are provided. Contact holes 32 and 31 are provided. A contact hole 33 having a diameter of 0.25 μm is provided in a region connecting the wiring and the second p-type diffusion layer 29b through the first and second interlayer insulating layers 23 and 25. Contact plugs made of tungsten (W) and titanium nitride (TiN) materials are embedded in the contact holes 31, 32, 33 so as to penetrate one or both of the first and second interlayer insulating layers 23, 25. ing.

  In order to operate a part of the first and second resistance change layers 24c and 24d as a memory portion of the resistance change element, an electric pulse is applied to the first and second resistance change layers 24c and 24d. A material that stably increases or decreases the resistance value of the storage unit is used. At this time, the resistance value of the memory unit can stably have two different resistance values depending on the characteristics of the applied electric pulse.

  When the first and second resistance change layers 24c and 24d are made of transition metal oxides, the initial resistance changes according to the oxygen content.

  In the present embodiment, a configuration for preventing charge damage to the resistance change element when the first resistance change layer 24c is made to contain oxygen at a higher concentration than the second resistance change layer 24d will be described. To do.

  Here, a negative charge damage current from the substrate 21 to the wiring 26 generated by processing by a plasma process such as dry etching of the wiring 26 manufactured after the first and second resistance change layers 24c and 24d are formed. This facilitates the movement of oxygen ions from the second variable resistance layer 24d having a low oxygen content to the first variable resistance layer 24c having a high oxygen content, but the first and second variable resistance layers 24c and 24d This is the direction in which the difference in the oxygen content is emphasized, and the oxygen profile of the resistance change element is less likely to be destroyed, and the influence is small.

  On the other hand, a positive charge damage current from the wiring 26 to the substrate 21 is caused by the p-type substrate 21 and the first n-type diffusion layer in the first connection path including the first and second resistance change layers 24c and 24d. Although the pn diode formed by the junction with 22a is blocked in the opposite direction, a positive charge damage current flows in the second connection path by grounding the third n-type diffusion layer 37. That is, in the nonvolatile memory device 300, the impedance of the second connection path is configured to be lower than the impedance of the first connection path with respect to the positive charge damage current.

  A first connection path including the first and second resistance change layers 24c and 24d and a second connection path having a lower impedance than the first connection path with respect to positive charge damage current are provided in parallel. As a result, a positive charge damage current mainly flows in the second connection path. As a result, almost no positive charge damage current flows through the first and second resistance change layers 24c and 24d, and the destruction of the oxygen profile can be prevented.

  Therefore, it is possible to maintain the oxygen content distribution in the first and second resistance change layers 24c and 24d as originally designed, to reduce variations in initial resistance, and to improve the manufacturing yield of the resistance change type nonvolatile memory device. It can be improved dramatically.

(Fourth embodiment)
FIG. 6 shows a sectional view of a variable resistance nonvolatile memory device 400 according to the fourth embodiment of the present invention.

  As shown in FIG. 6, in the nonvolatile memory device 400, the third n-type diffusion layer 37 made of impurities such as As and the first p-type impurities such as B are formed on the main surface of the substrate 21 having p-type conductivity. P-type diffusion layer 22b and second p-type diffusion layer 29b made of impurities such as B are provided. A first interlayer insulating layer 23 made of a silicon oxide film with a thickness of 350 nm, a lower electrode 27 made of TaN with a thickness of 30 nm, and an oxide of a transition metal (for example, tantalum oxide) are further formed on the substrate 21. First variable resistance layer 24c having a thickness of 40 nm, second variable resistance layer 24d having a thickness of 10 nm made of transition metal oxide (for example, tantalum oxide), upper electrode 28 having a thickness of 50 nm made of Pt, and thickness A second interlayer insulating layer 25 made of a silicon oxide film having a thickness of 350 nm is sequentially arranged from the bottom. On the second interlayer insulating layer 25, a wiring 26 made of an Al material having a thickness of 500 nm and a width of 0.3 μm is provided.

  Here, the lower electrode 27, the first and second resistance change layers 24 c and 24 d, and the upper electrode 28 constitute a resistance change element 36.

  Further, in the region connecting the first p-type diffusion layer 22b and the wiring 26 through the upper electrode 28, the first and second resistance change layers 24d and 24c, and the lower electrode 27, two upper and lower diameters of 0.25 μm are provided. Contact holes 32 and 31 are provided. A contact hole 33 having a diameter of 0.25 μm is provided in a region connecting the wiring and the second p-type diffusion layer 29b through the first and second interlayer insulating layers 23 and 25. Contact plugs made of tungsten (W) and titanium nitride (TiN) materials are embedded in the contact holes 31, 32, 33 so as to penetrate one or both of the first and second interlayer insulating layers 23, 25. ing.

  In order to operate a part of the first and second resistance change layers 24c and 24d as a memory portion of the resistance change element, an electric pulse is applied to the first and second resistance change layers 24c and 24d. A material that stably increases or decreases the resistance value of the storage unit is used. At this time, the resistance value of the memory unit can stably have two different resistance values depending on the characteristics of the applied electric pulse.

  When the first and second resistance change layers 24c and 24d are made of transition metal oxides, the initial resistance changes according to the oxygen content.

  In the present embodiment, a configuration for preventing charge damage to the resistance change element when the first resistance change layer 24c is made to contain oxygen at a higher concentration than the second resistance change layer 24d will be described.

  In the fourth embodiment, as in the first embodiment, in order to configure the impedance of the second connection path to be lower than that of the first connection path, as an example, the second n-type diffusion layer 29b. Is installed in a larger area than the first n-type diffusion layer 22a.

  Here, a negative charge damage current from the substrate 21 to the wiring 26 generated by processing by a plasma process such as dry etching of the wiring 26 manufactured after the first and second resistance change layers 24c and 24d are formed. This facilitates the movement of oxygen ions from the second variable resistance layer 24d having a low oxygen content to the first variable resistance layer 24c having a high oxygen content, but the first and second variable resistance layers 24c and 24d This is the direction in which the difference in the oxygen content is emphasized, and the oxygen profile of the resistance change element is less likely to be destroyed, and the influence is small.

  On the other hand, the positive charge damage current from the wiring 26 to the substrate 21 has a second connection impedance that is lower than that of the first connection path including the first and second resistance change layers 24c and 24d and the first connection path. By providing the connection path in parallel, the flow mainly flows to the second path. As a result, the positive charge damage current flowing in the first and second resistance change layers 24c and 24d is reduced, and the destruction of the oxygen profile can be reduced.

  Therefore, it is possible to maintain the oxygen content distribution in the first and second resistance change layers 24c and 24d as originally designed, to reduce variations in initial resistance, and to improve the manufacturing yield of the resistance change type nonvolatile memory device. It can be improved dramatically.

(Fifth embodiment)
In this embodiment, a preferred layout in the case where a plurality of variable resistance nonvolatile memory devices described in any of the first to fourth embodiments is provided over a substrate will be described.

  7A and 7B are examples of schematic plan layout diagrams when the variable resistance nonvolatile memory device according to this embodiment is viewed from above the substrate.

  29a represents the second diffusion layer in FIG. The first region 34 includes first diffusion regions 22a and 22b in FIG. 1, a contact plug 38 electrically connected to the first diffusion region, and a resistance change element electrically connected to the contact plug 38. 36 and a contact plug 39 electrically connected to the resistance change element 36.

  In the variable resistance nonvolatile memory device shown in FIG. 7A, when viewed from above the substrate, the second diffusion layer 29a and the first region 34 are separated by a single straight line, and the wiring 26 is It can be separated in one section. That is, the layout is such that the third contact plug 30 and the second diffusion region 29a and the wiring 26 in the variable resistance nonvolatile memory devices of the first to fourth embodiments can be easily electrically separated. On the other hand, FIG. 7B has a layout in which the second diffusion layer 29a and the first region 34 are in contact with each other in an intricate manner, and the wiring 26 cannot be separated in one section. That is, the layout is such that the third contact plug 30 and the second diffusion region 29a and the wiring 26 are not easily separated from each other. As described above, when the second diffusion layer 29a and the first region 34 are in contact with each other in an intricate manner, the unnecessary portion cannot be separated by a simple method such as dicing. On the other hand, in the case of FIG. 7A, the first region 34 and the second region 38 are laid out by a straight line, and the second connection path that has become unnecessary can be easily formed by the straight cut surface 35. Can be separated. This completely eliminates the possibility of malfunction caused by the second connection path during device operation. Moreover, the element area can be reduced by arranging in this way.

(Sixth embodiment)
In the present embodiment, the second diffusion region 29a and the wiring 26 are electrically separated when the first to fourth nonvolatile memory devices are configured on the substrate in the planar layout shown in the fifth embodiment. The steps up to this will be described with reference to cross-sectional views.

  FIG. 8 is a process cross-sectional view of the method of manufacturing the variable resistance nonvolatile memory device. 8A to 8G sequentially show the process flow of the variable resistance nonvolatile memory device.

As shown in FIG. 8A, an n-type impurity such as As is ion-implanted on the main surface of the substrate 21 at an energy of 20 keV and a dose of 1E15 / cm ² to thereby form the first and second n-type diffusion layers 22a and 29a. A first interlayer insulating layer 23 made of a silicon oxide film is formed on the substrate 21 by CVD or the like. Here, the first n-type diffusion layer 22 a is formed in the first region 34 (memory cell region), and the second n-type diffusion layer 29 a is formed in a region not including the first region 34. . In addition, here, the first n-type diffusion layer 22a and the second n-type diffusion layer 29a are formed at the same time. However, the ion implantation process may be divided into diffusion layers having different implantation energy and dose amount.

  Further, as shown in FIG. 8B, a contact hole 31 having a diameter of 0.25 μm is dug through the first interlayer insulating layer 23 by the dry etching method until it reaches the first n-type diffusion layer 22a.

  Further, as shown in FIG. 8C, the contact hole 31 is deposited with titanium (hereinafter referred to as W) after depositing titanium nitride (hereinafter referred to as TiN) by a CVD method, and deposited over the first interlayer insulating layer 23 and then subjected to CMP. Using technology, W and TiN on the first interlayer insulating layer 23 are removed and the surface is planarized. As a result, a contact plug made of W / TiN is formed at the position of the contact hole 31.

  Further, as shown in FIG. 8D, TaN serving as the lower electrode 27 is vapor-deposited by a CVD method with a thickness of 30 nm, and the first transition metal oxide film 24a such as TaOx and the second transition metal oxide film 24b are made reactive. Films are formed with a thickness of 40 nm and 10 nm, respectively, by sputtering, and Pt to be the upper electrode 28 is deposited with a thickness of 50 nm by sputtering. Then, the upper electrode 28, the resistance change layers 24a and 24b, and the lower electrode 27 are deposited by dry etching. A variable resistance element is formed.

  Further, as shown in FIG. 8E, a silicon oxide film is deposited by a CVD method or the like, and then a second interlayer insulating layer 25 having a thickness of 350 nm is formed by using a CMP technique. Thereafter, contact holes 32 and 33 having a diameter of 0.25 μm are formed by dry etching. In the contact hole 32, the contact hole penetrates through the second interlayer insulating layer 25 and reaches the upper electrode 28. In 33, digging is performed until the second n-type diffusion layer 29a is reached through the second and first interlayer insulating layers 25 and 23.

  Further, as shown in FIG. 8F, the contact holes 32 and 33 are deposited by CVD after depositing TiN by the CVD method and deposited on the second interlayer insulating layer 25, and then the second interlayer using the CMP technique. W and TiN on the insulating layer 25 are removed and the surface is planarized. Thereby, contact plugs made of W / TiN are formed in the contact holes 32 and 33. A wiring 26 made of an Al material is formed on these contact plugs with a width of 0.3 μm and a thickness of 500 nm by vapor deposition and dry etching.

  Further, as shown in FIG. 8G, dicing is performed so as to cut the wiring 26, and a region that is not required during device operation is removed from the first region 34.

  The variable resistance nonvolatile memory device is manufactured by the above process flow. With this manufacturing process, before performing dry etching for processing the wiring 26, a contact plug that connects the wiring 26 and the diffusion layer 29 a having a lower impedance than the resistance change layers 24 a and 24 b is connected to the resistance change element. Since they are connected in parallel, a current caused by charge damage generated by processing such as dry etching of the wiring 26 formed above the resistance change layers 24a and 24b is guided to the diffusion layer. As a result, the resistance change layers 24a and 24b It is possible to pass almost no current. Therefore, the oxygen content distribution in the resistance change layers 24a and 24b can be maintained as originally designed, variation in initial resistance can be reduced, and the yield of nonvolatile memory devices can be dramatically improved. In addition, since the portion where the charge damage current is introduced becomes unnecessary during device operation, the device area can be reduced by cutting and removing the device by dicing. In addition, the possibility of malfunction caused by the second connection path during device operation can be completely eliminated.

  In the present embodiment, the method for separating the unnecessary portion after manufacturing the nonvolatile memory device 100 according to the first embodiment has been described. However, according to the second, third, and fourth embodiments. Even when a nonvolatile memory device is configured, unnecessary portions can be cut by the above method.

(Seventh embodiment)
In this embodiment, a modification of the sixth embodiment is shown. The difference from the sixth embodiment is the method for cutting the wiring 26. This will be described below. FIG. 9 is a process cross-sectional view of the method of manufacturing the variable resistance nonvolatile memory device. 9A to 9G sequentially show the process flow of the variable resistance nonvolatile memory device.

As shown in FIG. 9A, the first and second n-type diffusion layers 22a and 29a are formed on the main surface of the substrate 21 by ion-implanting n-type impurities such as As at an energy of 20 keV and a dose of 1E15 / cm ^2. A first interlayer insulating layer 23 made of a silicon oxide film is formed on the substrate 21 by CVD or the like. Here, the first n-type diffusion layer 22 a is formed in the first region 34 (memory cell region), and the second n-type diffusion layer 29 a is formed in a region not including the first region 34. . In addition, here, the first n-type diffusion layer 22a and the second n-type diffusion layer 29a are formed at the same time. However, the ion implantation process may be divided into diffusion layers having different implantation energy and dose amount.

  Further, as shown in FIG. 9B, a contact hole 31 having a diameter of 0.25 μm is dug through the first interlayer insulating layer 23 until it reaches the first n-type diffusion layer 22a by dry etching.

  Further, as shown in FIG. 9C, the contact hole 31 is deposited with titanium (hereinafter referred to as W) after depositing titanium nitride (hereinafter referred to as TiN) by the CVD method, and deposited on the first interlayer insulating layer 23 and then subjected to CMP. Using technology, W and TiN on the first interlayer insulating layer 23 are removed and the surface is planarized. As a result, a contact plug made of W / TiN is formed at the position of the contact hole 31.

  Further, as shown in FIG. 9D, TaN serving as the lower electrode 27 is vapor-deposited with a thickness of 30 nm by the CVD method, and the first transition metal oxide film 24a such as TaOx and the second transition metal oxide film 24b are made reactive. Films are formed with a thickness of 40 nm and 10 nm, respectively, by sputtering, and Pt to be the upper electrode 28 is deposited with a thickness of 50 nm by sputtering. Then, the upper electrode 28, the resistance change layers 24a and 24b, and the lower electrode 27 are deposited by dry etching. A variable resistance element is formed.

  Further, as shown in FIG. 9E, a silicon oxide film is deposited by the CVD method or the like, and then a second interlayer insulating layer 25 having a thickness of 350 nm is formed by using a CMP technique. Thereafter, contact holes 32 and 33 having a diameter of 0.25 μm are formed by dry etching. In the contact hole 32, the contact hole penetrates through the second interlayer insulating layer 25 and reaches the upper electrode 28. In 33, digging is performed until the second n-type diffusion layer 29a is reached through the second and first interlayer insulating layers 25 and 23.

  Further, as shown in FIG. 9F, after the contact holes 32 and 33 are deposited by Ti after vapor deposition of TiN by CVD method and deposited up to the second interlayer insulating layer 25, the second interlayer is formed by using the CMP technique. W and TiN on the insulating layer 25 are removed and the surface is planarized. Thereby, contact plugs made of W / TiN are formed in the contact holes 32 and 33. A wiring 26 made of an Al material is formed on these contact plugs with a width of 0.3 μm and a thickness of 500 nm by vapor deposition and dry etching.

  Further, as shown in FIG. 9G, patterning is performed so as to cut the wiring 26, and the wiring 26 is cut by a wet etching method or a dry etching method with sufficiently reduced charge damage.

  The variable resistance nonvolatile memory device is manufactured by the above process flow. With this manufacturing process, before performing dry etching for processing the wiring 26, a contact plug that connects the wiring 26 and the diffusion layer 29 a having a lower impedance than the resistance change layers 24 a and 24 b is connected to the resistance change element. Since they are connected in parallel, a current caused by charge damage generated by processing such as dry etching of the wiring 26 formed above the resistance change layers 24a and 24b is guided to the diffusion layer. As a result, the resistance change layers 24a and 24b It is possible to pass almost no current. Therefore, the oxygen content distribution in the resistance change layers 24a and 24b can be maintained as originally designed, variation in initial resistance can be reduced, and the yield of nonvolatile memory devices can be dramatically improved. In addition, since the portion that has led to the charge damage current is not necessary during device operation, the possibility of malfunction caused by the second connection path during device operation can be completely eliminated by cutting and removing it by etching.

  In the present embodiment, the method for separating the unnecessary portion after manufacturing the nonvolatile memory device 100 according to the first embodiment has been described. However, according to the second, third, and fourth embodiments. Even when a nonvolatile memory device is configured, unnecessary portions can be cut by the above method.

  As described above, the variable resistance nonvolatile memory device of the present invention has been described based on the embodiment, but the present invention is not limited to the above embodiment. Unless departing from the gist of the present invention, a variable resistance nonvolatile memory device in which various modifications conceived by those skilled in the art can be applied to the above embodiment, and a variable resistance nonvolatile memory device that combines the above embodiment are also included in the present invention. It is included in the range.

  In the second and third embodiments, in order to configure the impedance of the second connection path to be lower than the impedance of the first connection path, the reverse characteristics of the pn diode included in the first connection path are used. By combining this configuration with the configuration in which the second n-type diffusion layer 29a described in the first and fourth embodiments is installed in a larger area than the first n-type diffusion layer 22a, for example, When a large charge damage that drives current is applied, an effect of allowing overcurrent to flow without destroying the nonvolatile memory device 100 can be added.

  In the first to seventh embodiments described above, the transition metal oxide (for example, tantalum oxide is described as an example of the variable resistance layer material. However, other transition metals such as Ni, Ti, Hf, Oxides such as Zr and Fe may be used.

  Moreover, although Al is used as the wiring material, Cu, Pt, Ir, W, or the like used in the Si semiconductor process may be used.

  Further, although W is used as the contact plug and TaN is used as the lower electrode, other electrode materials such as Cu, Pt, Ir, Al, TiN, TaN, TiAlN, and W may be used.

  The variable resistance nonvolatile memory device according to the present invention is useful as a next-generation nonvolatile memory oriented to low power, high-speed writing, high-speed erasing, and large capacity.

1 resistance change film 2 wiring 3 contact 4 upper electrode 5 wiring 6 lower electrode 21 substrate 22a first n-type diffusion layer 22b first p-type diffusion layer 23 first interlayer insulating layer 24a first resistance change layer 24b first 2 variable resistance layer 24c first variable resistance layer 24d second variable resistance layer 25 second interlayer insulating layer 26 wiring 27 lower electrode 28 upper electrode 29a second n-type diffusion layer 29b second p-type diffusion layer 30, 38, 39 Contact plug 31, 32, 33 Contact hole 34 First region 35 Cut surface 36 Resistance change element 37 Third n-type diffusion layer 100, 200, 300, 400 Nonvolatile memory device

Claims (10)

A substrate,
A first diffusion layer and a second diffusion layer formed on the substrate;
An interlayer insulating layer formed on the first diffusion layer and the second diffusion layer;
A variable resistance element formed in the interlayer insulating layer, and formed by laminating a lower electrode, a variable resistance layer made of a metal oxide, and an upper electrode in this order;
Wiring formed on the interlayer insulating layer,
The impedance of the first electrical connection path from the wiring to the first diffusion layer via the variable resistance element is:
Higher than the impedance of the second electrical connection path from the wiring to the second diffusion layer;
The second diffusion layer and the wiring are configured in a plane layout that is easy to electrically separate,
A variable resistance nonvolatile memory device. The variable resistance nonvolatile memory device according to claim 1, wherein the second diffusion layer and the wiring are configured in a planar layout that can be electrically separated in one cross section. The substrate is a p-type semiconductor;
The first diffusion layer and the second diffusion layer are n-type semiconductors;
The variable resistance layer has a laminated structure including a first variable resistance layer disposed on the lower electrode side and a second variable resistance layer disposed on the upper electrode side,
3. The variable resistance nonvolatile memory device according to claim 1, wherein an oxygen content of the second variable resistance layer is higher than an oxygen content of the first variable resistance layer. Having a third diffusion layer between the substrate and the first diffusion layer;
The substrate and the first diffusion layer are p-type semiconductors;
The second diffusion layer and the third diffusion layer are n-type semiconductors;
The variable resistance layer has a laminated structure including a first variable resistance layer disposed on the lower electrode side and a second variable resistance layer disposed on the upper electrode side,
3. The variable resistance nonvolatile memory device according to claim 1, wherein an oxygen content of the second variable resistance layer is higher than an oxygen content of the first variable resistance layer. Having a third diffusion layer between the substrate and the second diffusion layer;
The substrate and the second diffusion layer are p-type semiconductors;
The first diffusion layer and the third diffusion layer are n-type semiconductors;
The variable resistance layer has a laminated structure including a first variable resistance layer disposed on the lower electrode side and a second variable resistance layer disposed on the upper electrode side,
3. The variable resistance nonvolatile memory device according to claim 1, wherein an oxygen content of the second variable resistance layer is lower than an oxygen content of the first variable resistance layer. A third diffusion layer between the substrate and the first diffusion layer and the second diffusion layer;
The substrate, the first diffusion layer, and the second diffusion layer are p-type semiconductors,
The third diffusion layer is an n-type semiconductor;
The variable resistance layer has a laminated structure including a first variable resistance layer disposed on the lower electrode side and a second variable resistance layer disposed on the upper electrode side,
3. The variable resistance nonvolatile memory device according to claim 1, wherein an oxygen content of the second variable resistance layer is lower than an oxygen content of the first variable resistance layer. The variable resistance nonvolatile memory device according to claim 1, wherein an area of the second diffusion layer is larger than an area of the first diffusion layer. Forming a first diffusion layer and a second diffusion layer on a substrate;
Forming a first interlayer insulating layer on the first diffusion layer and the second diffusion layer;
Forming a first contact plug penetrating the first interlayer insulating layer and reaching the first diffusion layer;
Forming a resistance change element by sequentially laminating a lower electrode, a resistance change layer, and an upper electrode on a portion of the first interlayer insulating layer where the first contact plug is formed;
Forming a second interlayer insulating layer on the variable resistance element and the first interlayer insulating layer;
Forming a second contact plug that penetrates the second interlayer insulating layer and reaches the upper electrode;
Forming a third contact plug that penetrates the second interlayer insulating layer and the first interlayer insulating layer and reaches the second diffusion layer;
Forming a wiring electrically connected to the second contact plug and the third contact plug on the second interlayer insulating layer; and electrically separating the third contact plug and the wiring. Including and
The impedance of the first electrical connection path from the wiring to the first diffusion layer through the second contact plug, the variable resistance element, and the first contact plug is from the wiring to the third A method of manufacturing a variable resistance nonvolatile memory device, wherein the impedance is higher than an impedance of a second electrical connection path that reaches the second diffusion layer through the contact plug. 9. The method of manufacturing a variable resistance nonvolatile memory device according to claim 8, wherein a dicing method is used in the step of electrically separating the third contact plug and the wiring. 9. The method of manufacturing a variable resistance nonvolatile memory device according to claim 8, wherein an etching method is used in the step of electrically separating the third contact plug and the wiring.

Images