JP2010245159A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has a plurality of thresholds and suppresses a decrease in yield and a decrease in reliability due to dust and local variance of impurities, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device has an MOSFET of a first conductivity type and an MOSFET of a second conductivity type formed on a semiconductor substrate (Sub.), wherein the MOSFET of the first conductivity type has a first gate electrode 15a containing impurities of the first conductivity type and a second gate electrode 15b containing impurities of the second conductivity type, and the MOSFET of the second conductivity type has a third gate electrode 15c containing the impurities of the first conductivity type and a fourth gate electrode 15d containing the impurities of the second conductivity type. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a MOSFET whose performance is improved by, for example, impurity pre-doping, and a semiconductor device having a plurality of threshold values, and a method for manufacturing the same.

  In recent years, with the miniaturization of semiconductor devices such as CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor), high performance has been achieved by pre-doping the gate electrode. For example, after a polysilicon film to be a gate electrode is formed on a semiconductor substrate, depletion of the gate electrode is performed by performing pre-doping of P-type and N-type impurities in the respective regions of the P-type MOSFET and the N-type MOSFET. Conversion rate can be reduced (see, for example, Patent Document 1).

  On the other hand, in a semiconductor device such as a CMOSFET, various methods for making elements having a plurality of threshold values together have been studied. For example, channel impurity implantation is performed a plurality of times in the respective regions of the P-type MOSFET and the N-type MOSFET on the semiconductor substrate to adjust the threshold value to a desired value (see, for example, Patent Document 2).

  However, in the case of forming a transistor with a particularly high threshold, since high-concentration impurity implantation is necessary, local variations in impurities become large, and reliability is lowered due to NBTI (Negative Bias Temperature Instability). Occurs. Further, as the number of channel impurity implantation steps increases, the number of steps for stripping the photoresist increases by the increased number of steps, and there is a problem that dust caused by the photoresist increases.

JP 2004-214387 A ([Claim 1] etc.) JP 2000-323587 A ([Claim 1] etc.)

  An object of the present invention is to provide a semiconductor device having a plurality of thresholds, capable of suppressing a decrease in yield due to local variations in dust and impurities, and improving reliability, and a method for manufacturing the same. It is.

  According to one aspect of the present invention, a first conductivity type MOSFET and a second conductivity type MOSFET formed on a semiconductor substrate are included, and the first conductivity type MOSFET includes a first conductivity type impurity. 1 gate electrode and a second gate electrode containing a second conductivity type impurity, and the second conductivity type MOSFET comprises a third gate electrode containing a first conductivity type impurity, and a second conductivity type. There is provided a semiconductor device comprising a fourth gate electrode containing a type impurity, wherein the first conductivity type MOSFET and the second conductivity type MOSFET each have a plurality of threshold values.

  According to one embodiment of the present invention, a first conductivity type MOSFET region and a second conductivity type MOSFET region are formed on a semiconductor substrate, an insulating film serving as a gate insulating film on the semiconductor substrate, a gate electrode, A conductive film in the first region in the first conductivity type MOSFET region and a conductive film in the first region in the second conductivity type MOSFET region are selectively formed. The first conductivity type impurity is implanted into the semiconductor substrate under conditions that do not reach the semiconductor substrate, and a second region conductor film in the first conductivity type MOSFET region and a second conductivity type MOSFET region in the second conductivity type MOSFET region. A second conductivity type impurity is selectively implanted into the region of the conductor film under a condition that does not reach the semiconductor substrate, and the insulator film and the conductor film are selectively removed to form a gate electrode. The first conductivity type The MOSFET region and the MOSFET region of the second conductivity type, production method of the respective semiconductor device, which comprises injecting a channel impurity is provided.

  According to one embodiment of the present invention, in a semiconductor device having a plurality of threshold values and a manufacturing method thereof, it is possible to suppress a decrease in yield due to local variations in dust and impurities and improve reliability.

FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. FIG. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a cross-sectional view of a CMOSFET which is a semiconductor device of this embodiment. An N-type MOSFET region 11 and a P-type MOSFET region 12 are formed on a semiconductor substrate (Sub.) Made of bulk Si, and each is isolated by an element isolation region 13 such as STI (Shallow Trench Isolation). In each element isolated by the element isolation region 13, a gate electrode is formed on the semiconductor substrate (Sub.) Via a gate insulating film 14.

  In the N-type MOSFET region 11, a gate electrode 15a into which phosphorus as an N-type impurity is implanted and a gate electrode 15b into which boron as a P-type impurity is implanted are formed. In the P-type MOSFET region 12, a gate electrode 15c into which phosphorus as an N-type impurity is implanted and a gate electrode 15d into which boron as a P-type impurity is implanted are formed. A gate sidewall 16 is formed on each of the gate electrodes 15a, 15b, 15c, and 15d.

  In the semiconductor substrate (Sub.), A shallow junction 17 and a source-drain diffusion layer 18 are formed with the gate electrodes 15a, 15b, 15c, and 15d interposed therebetween. An interlayer insulating film 19 is formed on the semiconductor substrate (Sub.), And further, contacts that pass through the interlayer insulating film 19 and are connected to the gate electrodes 15a, 15b, 15c, 15d, and the source-drain diffusion layer 18. 20 is formed.

  Such a semiconductor device is formed as follows. 2A to 2G are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment. First, as shown in FIG. 2A, a device isolation region 13 is formed in a semiconductor substrate (Sub.), And a photoresist film (not shown) in which an opening is provided on a region to be an N-type MOSFET region by lithography. Then, for example, boron is implanted to form a P-well that becomes the N-type MOSFET region 11. After peeling off the photoresist film (not shown), the region which becomes the P-type MOSFET region is masked with an opened photoresist film (not shown) by lithography, for example, phosphorus is implanted, and the P-type MOSFET After forming the N well which becomes the region 12, the photoresist film (not shown) is peeled off.

  Next, as shown in FIG. 2B, on the semiconductor substrate (Sub.) On which the N-type MOSFET region 11 and the P-type MOSFET region 12 are formed, for example, a thermal oxide film 21 or the like that becomes the gate insulating film 14 is formed. For example, a polysilicon film 22 to be the gate electrodes 15a, 15b, 15c, 15d is deposited.

Next, as shown in FIG. 2C, the polysilicon film 22 is masked with a photoresist film 23 having openings in predetermined regions on the N-type MOSFET region 11 and the P-type MOSFET region 12 by lithography. Is pre-doped. At this time, the implantation condition is a condition that does not reach the semiconductor substrate (Sub.), For example, 7 KeV, 6.0E + 15 (cm ⁻² ). Then, the photoresist film 23 is removed by wet etching.

Next, as shown in FIG. 2D, by lithography, the polysilicon film is masked with a photoresist film 24 having openings in predetermined regions on the N-type MOSFET region 11 and the P-type MOSFET region 12, respectively. For example, boron is predoped with 22. At this time, the implantation condition is a condition that does not reach the semiconductor substrate (Sub.), For example, 1 KeV, 2.0E + 15 (cm ⁻² ). Then, the photoresist film 24 is peeled off by wet etching.

  Next, as shown in FIG. 2E, the polysilicon film 22 into which the impurity has been implanted is masked with a photoresist film (not shown) in which a gate electrode pattern is formed by lithography, and an anisotropic process such as RIE (Reactive Ion Etching) is performed. The gate insulating film 14 and the gate electrodes 15a, 15b, 15c, and 15d are formed by performing etching.

Then, as shown in FIG. 2F, for example, arsenic is injected directly under the gate electrodes 15a and 15b, and BF ₂ is injected with the gate electrodes 15c and 15d directly under each other, thereby forming an extension structure. Further, BF ₂ and arsenic are implanted into deeper regions to form a halo structure. In this manner, shallow junctions 17 are formed in the elements of the N-type MOSFET region 11 and the P-type MOSFET region 12, respectively.

  Next, as shown in FIG. 2G, for example, a Si oxide film and a Si nitride film are deposited, and anisotropic etching such as RIE is performed to form gate sidewalls 16 on the gate electrodes 15a, 15b, 15c, and 15d, respectively. . Then, in each element of the N-type MOSFET region 11 and the P-type MOSFET region 12, phosphorus and boron are respectively implanted to form the source-drain diffusion layer 18.

  Then, after an interlayer film 19 such as PMD (Pre-Metal Dielectric) is deposited on the upper layer, it reaches the gate electrodes 15a, 15b, 15c, 15d, the source-drain diffusion layer 18, and is formed in a multilayer wiring ( A contact 20 to be connected to a not-shown is formed. In this way, a CMOSFET as shown in FIG. 1 is formed.

  Among the formed CMOSFETs, the N-type MOSFET and the P-type MOSFET have two threshold values because the work functions of the gate electrode 15a and the gate electrode 15b and the gate electrode 15c and the gate electrode 15d are different. As shown in FIG. 3, the element a in which phosphorus is injected into the gate electrode 15a in the N-type MOSFET and the element d in which boron is injected into the gate electrode 15d in the P-type MOSFET have a low threshold, for example, I Used for / O circuit and the like. Further, the element a in which boron is implanted into the gate electrode 15b in the N-type MOSFET and the element d in which phosphorus is implanted into the gate electrode 15c in the P-type MOSFET have a high threshold, and for example, a low leakage current is required. Used in circuits.

  In such a CMOSFET, the channel impurity concentration of the N-type MOSFET and the P-type MOSFET is substantially equal between the element a and the element b, the element c and the element d, and is determined by SIMS (Secondary Ion Mass Spectroscopy) or the like. Can be confirmed. The element a and the element b, the element c and the element d have different elements injected into the gate electrode, and can be confirmed by EPMA (Electron Probe Micro Analyzer), SCM (Scanning Capacitance Microscope) or the like. Further, the element a and the element b, the element c and the element d have different crystal grain sizes of polysilicon in the gate electrode, and can be confirmed by TEM (Transmission Electron Microscope) or the like.

  In the CMOSFET having a plurality of threshold values formed in this way, the threshold value can be increased without requiring high-concentration impurity implantation, so that the channel impurity concentration can be reduced. Can be suppressed. As a result, the scale of a large-scale memory device such as SRAM (Static Random Access Memory) can be increased. Furthermore, since high-concentration impurity implantation is not required, it is possible to suppress a decrease in reliability due to NBTI.

  In addition, since a plurality of thresholds can be provided by two pre-dopings as in the case of a single threshold semiconductor device without increasing the number of channel impurity implantation steps, the manufacturing cost is not increased and the mask is used as a mask. It is possible to reduce dust generated when the resist film is peeled off and suppress a decrease in yield.

Thus, by reducing the depletion rate of the gate electrode by pre-doping and making the impurity implanted into the MOSFET of the same conductivity type have a different conductivity type, the threshold value of the MOSFET can be changed. . At this time, the pre-doping needs to be performed under conditions that do not reach the semiconductor substrate. This is because when the impurities reach the semiconductor substrate due to the pre-doping, the impurities penetrate the gate insulating film and cause variations in the characteristics of the device. As such pre-doping conditions, for example, when the thickness of polysilicon is 80-150 nm and the impurity is boron, 0.5-1 KeV, 1E + 15-2E + 15 (cm ⁻² ), and when the impurity is phosphorus, 5-10 eV, 3E + 15-7E + 15 (cm ⁻² ).

  In the present embodiment, in the N-type MOSFET region and the P-type MOSFET region, two regions, a region for pre-doping with N-type impurities and a region for pre-doping with P-type impurities, are provided. You may wrap. In this case, regions where both N-type impurities and P-type impurities are implanted are formed in the N-type MOSFET region and the P-type MOSFET region, respectively. Since the work function in this region is different from that in which only N-type impurities and only P-type impurities are implanted, regions having different threshold values can be formed.

  Note that such N-type and P-type impurity pre-doping is not necessarily performed in both the N-type MOSFET region and the P-type MOSFET region, but only in one of the N-type MOSFET region and the P-type MOSFET region. May be.

  In addition, the conventional method of increasing the threshold value by controlling the channel impurity concentration may be used together. In this case, as compared with the case of controlling only the channel impurity concentration, the addition of processes is reduced or the number of thresholds is increased. It becomes possible to make it.

In this embodiment, phosphorus is used as the N-type impurity and boron is used as the P-type impurity. However, the present invention is not limited to these, and impurities such as As and BF ₂ that are usually used for pre-doping can be used. . Further, although a Si substrate is used as a semiconductor substrate, a bulk single crystal Si wafer is not necessarily used, and an epitaxial Si wafer, an SOI wafer, or the like can be used.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 11 ... N-type MOSFET area | region 12 ... P-type MOSFET area | region 13 ... Element isolation region 14 ... Gate insulating film 15a, 15b, 15c, 15d ... Gate electrode 16 ... Gate side wall 17 ... Shallow junction 18 ... Source-drain diffused layer 19 ... Interlayer Insulating film 20 ... Contact 21 ... Thermal oxide film 22 ... Polysilicon film 23, 24 ... Photoresist film

Claims (5)

A first conductivity type MOSFET and a second conductivity type MOSFET formed on a semiconductor substrate;
The first conductivity type MOSFET includes a first gate electrode containing a first conductivity type impurity, and a second gate electrode containing a second conductivity type impurity,
The second conductivity type MOSFET includes a third gate electrode containing a first conductivity type impurity and a fourth gate electrode containing a second conductivity type impurity.   2. The semiconductor device according to claim 1, wherein the first conductivity type MOSFET includes a third gate electrode including a first conductivity type impurity and a second conductivity type impurity. 3.   3. The semiconductor device according to claim 1, wherein the first conductivity type impurity is phosphorus, and the second conductivity type impurity is boron. Forming a first conductivity type MOSFET region and a second conductivity type MOSFET region on a semiconductor substrate;
An insulating film to be a gate insulating film and a conductor film to be a gate electrode are sequentially formed on a semiconductor substrate,
The first conductivity type impurity is selectively applied to the first region conductor film in the first conductivity type MOSFET region and the first region conductor film in the second conductivity type MOSFET region. Injecting under conditions that do not reach the semiconductor substrate,
The second conductivity type impurity is selectively introduced into the second region conductor film in the first conductivity type MOSFET region and the second region conductor film in the second conductivity type MOSFET region. Injecting under conditions that do not reach the semiconductor substrate,
Selectively removing the insulator film and the conductor film to form a gate electrode;
A method of manufacturing a semiconductor device, wherein channel impurities are implanted into the first conductivity type MOSFET region and the second conductivity type MOSFET region, respectively.   The first region in the first conductivity type MOSFET region, the second region in the first conductivity type MOSFET region, the first region in the second conductivity type MOSFET region, and the second conductivity. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the second region in the type MOSFET region includes a third region in which the first region and the second region overlap each other.

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