JP2010244451A5

JP2010244451A5 -

Info

Publication number: JP2010244451A5
Application number: JP2009094637A
Authority: JP
Filing date: 2009-04-09
Publication date: 2012-05-10
Anticipated expiration: 2029-04-09

Claims

A first input register configured to be capable of reading and writing first setting data;
A second input register configured to be capable of reading and writing second setting data;
The result of the multiplication process using the first setting data set in the first input register and the second setting data set in the second input register is expressed in the first fixed-point format. A first processing unit that outputs as multiplication data;
The result of the multiplication process using the first setting data set in the first input register and the second setting data set in the second input register is expressed as a second in a floating-point format. A second processing unit for outputting as multiplication data;
A first output register in which the first multiplication data is stored;
A second output register in which the second multiplication data is stored;
For each given execution cycle, the first processing unit stores the first multiplication data in the first output register, and the second processing unit stores the second multiplication data in the first output register. An information processing apparatus characterized by storing in a second output register.

In claim 1,
A third input register configured to be able to read and write third setting data;
A fourth input register configured to be able to read and write fourth setting data;
The result of the multiplication process using the third setting data set in the third input register and the fourth setting data set in the fourth input register is the third fixed data in the fixed-point format. A third processing unit for outputting as multiplication data;
The result of the multiplication process using the third setting data set in the third input register and the fourth setting data set in the fourth input register is expressed in the fourth floating-point format. A fourth processing unit for outputting as multiplication data;
A third output register in which the third multiplication data is stored;
A fourth output register in which the fourth multiplication data is stored;
For each given execution cycle, the third processing unit stores the third multiplication data in the third output register, and the fourth processing unit stores the fourth multiplication data in the third output register. 4. An information processing apparatus that stores the information in an output register.

In claim 2,
The third processing unit comprises:
A fixed-point output format conversion unit that converts the fourth multiplication data into the third multiplication data in a fixed-point format;
The fourth processing unit comprises:
An information processing apparatus comprising: a first floating-point multiplication unit that performs floating-point multiplication processing using the third setting data and the fourth setting data and outputs the fourth multiplication data .

In claim 2,
The third processing unit comprises:
A first fixed-point input format converter for converting the third setting data into third input data in a fixed-point format;
A second fixed-point input format converter for converting the fourth setting data into fourth input data in a fixed-point format;
And a second fixed-point multiplication unit that performs fixed-point multiplication processing using the third input data and the fourth input data and outputs the third multiplication data. apparatus.

In any of claims 2 to 4 ,
The number of bits of the third input register is the same as the number of bits of the fourth input register;
At least one of the third output register and the fourth output register is:
An information processing apparatus comprising two accumulators having the same number of bits as the third input register.

In any one of Claims 1 thru | or 5,
The first processing unit comprises:
Performing a fixed point multiplication process using the first setting data and the second setting data;
A first fixed-point multiplication unit that outputs the first multiplication data;
The second processing unit comprises:
An information processing apparatus comprising: a floating-point output format conversion unit that converts the first multiplication data into the second multiplication data in a floating-point format.

In any one of Claims 1 thru | or 5,
The first processing unit comprises:
A first fixed-point multiplication unit that performs fixed-point multiplication processing using the first setting data and the second setting data and outputs the second multiplication data;
The second processing unit comprises:
A first floating point input format conversion unit for converting the first setting data into first input data in a floating point format;
A second floating-point input format converter for converting the second setting data into second input data in a floating-point format;
An information processing apparatus comprising: a second floating-point multiplication unit that performs floating-point multiplication processing using the first input data and the second input data and outputs the second multiplication data .

In any one of Claims 1 thru | or 7,
The number of bits of the first input register is the same as the number of bits of the second input register;
At least one of the first output register and the second output register is:
An information processing apparatus comprising two accumulators having the same number of bits as the first input register.

In any one of Claims 1 thru | or 8.
Including an instruction decode unit for decoding the fetched instruction data;
An information processing apparatus that stores a processing result of each processing unit in any of the plurality of output registers regardless of a decoding result of the instruction decoding unit.

In claim 9,
The instruction decode unit
An information processing apparatus for decoding a data transfer instruction and a branch instruction excluding an arithmetic operation instruction, a logical operation instruction, and a shift operation instruction.

In any one of Claims 1 thru | or 10.
An information processing apparatus configured to be able to transfer multiplication data stored in the output register to any of the input registers.

A plurality of input registers each configured to allow reading and writing of configuration data; and
A first processing unit and a second processing unit for outputting a result of multiplication processing using setting data set in any of the plurality of input registers;
An arithmetic processing method of an information processing apparatus including a plurality of output registers storing at least first multiplication data from the first processing unit and second multiplication data from the second processing unit,
A processing step in which the first processing unit outputs the first multiplication data in a fixed-point format, and the second processing unit outputs the second multiplication data in a floating-point format;
For each given execution cycle, the first processing unit stores the first multiplication data in the first output register, and the second processing unit stores the second multiplication data in the first output register. Storing in a second output register;
In the processing step,
The first processing unit includes first setting data set in a first register assigned to the first processing unit among the plurality of input registers, and the second among the plurality of input registers. Output the result of the multiplication process using the second setting data set in the second register assigned to the processing unit as the first multiplication data in the fixed-point format,
The second processing unit outputs a result of multiplication processing using the first setting data set in the first input register and the second setting data set in the second input register. And outputting as second multiplication data in a floating-point format.

A memory for storing programs and data;
An electronic apparatus comprising: the information processing apparatus according to claim 1, which performs arithmetic processing corresponding to the program and the data.