JP2003216411A5 - - Google Patents
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- JP2003216411A5 JP2003216411A5 JP2002013697A JP2002013697A JP2003216411A5 JP 2003216411 A5 JP2003216411 A5 JP 2003216411A5 JP 2002013697 A JP2002013697 A JP 2002013697A JP 2002013697 A JP2002013697 A JP 2002013697A JP 2003216411 A5 JP2003216411 A5 JP 2003216411A5
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- JP
- Japan
- Prior art keywords
- arithmetic processing
- multiplier
- register
- multiple length
- length arithmetic
- Prior art date
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Claims (7)
所定ビット数のデータからなるワード単位での乗算処理を実行する乗算器と、
前記乗算器に対する入力データを格納するレジスタであり、１レジスタに１ワードを格納する構成を有する多段構成の第１のシフトレジスタと、
前記乗算器における乗算処理後のデータを格納するレジスタであり、１レジスタに１ワードを格納する構成を有する多段構成の第２のシフトレジスタと、
を有することを特徴とする多倍長演算処理装置。In the multiple length arithmetic processing unit,
A multiplier for performing multiplication processing in units of words composed of data of a predetermined number of bits;
A register for storing input data to the multiplier, a first shift register having a multi-stage configuration having a configuration in which one word is stored in one register;
A register for storing data after multiplication processing in the multiplier, a second shift register having a multi-stage configuration having a configuration in which one word is stored in one register;
A multiple length arithmetic processing apparatus comprising:
前記乗算器に対する入力データを格納する１ワード格納用レジスタと、
前記乗算器の乗算処理の停止クロックタイミングに、前記１ワード格納用レジスタに対するメモリからのデータセット処理を実行する制御部と、
を有する構成であることを特徴とする請求項１に記載の多倍長演算処理装置。The multiple length arithmetic processing device further includes:
A 1-word storage register for storing input data to the multiplier;
A control unit that executes data set processing from the memory for the one-word storage register at a stop clock timing of the multiplication processing of the multiplier;
The multiple length arithmetic processing device according to claim 1, wherein the multiple length arithmetic processing device is provided.
前記乗算器の乗算処理の停止クロックタイミングに、前記多段構成の第１のシフトレジスタに対するメモリからのデータセット処理を実行する制御部を有する構成であることを特徴とする請求項１に記載の多倍長演算処理装置。The multiple length arithmetic processing device further includes:
The multi-unit according to claim 1, further comprising a control unit that executes a data set process from a memory for the first shift register having the multi-stage configuration at a stop clock timing of the multiplication process of the multiplier. Double length arithmetic processing unit.
前記乗算器の計算結果を入力し、該入力に基づく加算処理を実行する加算器を有することを特徴とする請求項１に記載の多倍長演算処理装置。The multiple length arithmetic processing device further includes:
The multiple length arithmetic processing apparatus according to claim 1, further comprising an adder that inputs a calculation result of the multiplier and executes an addition process based on the input.
前記第１のシフトレジスタの前段に、
セレクタと、１ワード格納用レジスタを交互に構成した回路構成を有することを特徴とする請求項１に記載の多倍長演算処理装置。The multiple length arithmetic processing device further includes:
In the preceding stage of the first shift register,
2. The multiple length arithmetic processing apparatus according to claim 1, wherein the multiple length arithmetic processing apparatus has a circuit configuration in which selectors and one word storage registers are alternately configured.
乗算器に対する入力データを、１レジスタに１ワードを格納する構成を有する多段構成の第１のシフトレジスタに格納するステップと、 Storing input data to the multiplier in a first shift register having a multi-stage configuration having a configuration in which one word is stored in one register;
所定ビット数のデータからなるワード単位での乗算処理を、前記第１のシフトレジスタから入力して乗算器において実行する乗算処理ステップと、 A multiplication process step of inputting a multiplication process in units of words composed of data of a predetermined number of bits from the first shift register and executing in a multiplier;
前記乗算器における乗算処理後のデータを、１レジスタに１ワードを格納する構成を有する多段構成の第２のシフトレジスタに格納するステップと、 Storing data after multiplication processing in the multiplier in a second shift register having a multi-stage configuration having a configuration in which one word is stored in one register;
を有することを特徴とする多倍長演算処理方法。 A multiple length arithmetic processing method characterized by comprising:
乗算器に対する入力データを、１レジスタに１ワードを格納する構成を有する多段構成の第１のシフトレジスタに格納するステップと、 Storing input data for the multiplier in a first shift register having a multi-stage configuration in which one word is stored in one register;
所定ビット数のデータからなるワード単位での乗算処理を、前記第１のシフトレジスタから入力して乗算器において実行する乗算処理ステップと、 A multiplication process step of inputting a multiplication process in units of words composed of data of a predetermined number of bits from the first shift register and executing in a multiplier;
前記乗算器における乗算処理後のデータを、１レジスタに１ワードを格納する構成を有する多段構成の第２のシフトレジスタに格納するステップと、 Storing data after multiplication processing in the multiplier in a second shift register having a multi-stage configuration having a configuration in which one word is stored in one register;
を有することを特徴とするプログラム。 The program characterized by having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002013697A JP2003216411A (en) | 2002-01-23 | 2002-01-23 | Multiple length arithmetic processor and ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002013697A JP2003216411A (en) | 2002-01-23 | 2002-01-23 | Multiple length arithmetic processor and ic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003216411A JP2003216411A (en) | 2003-07-31 |
| JP2003216411A5 true JP2003216411A5 (en) | 2005-08-04 |
Family
ID=27650591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002013697A Pending JP2003216411A (en) | 2002-01-23 | 2002-01-23 | Multiple length arithmetic processor and ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003216411A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050088506A (en) * | 2004-03-02 | 2005-09-07 | 삼성전자주식회사 | Scalable montgomery modular multiplier supporting multiple precision |
| US7916864B2 (en) | 2006-02-08 | 2011-03-29 | Nvidia Corporation | Graphics processing unit used for cryptographic processing |
| DE102006060760A1 (en) | 2006-09-29 | 2008-04-10 | Siemens Ag | Subscribers authenticating method for radio frequency identification communication system, involves encrypting calculated response and certificate associated with subscriber in randomized manner, and decrypting and authenticating response |
| JP4989354B2 (en) * | 2007-08-09 | 2012-08-01 | 三洋電機株式会社 | Data flow graph generation device, setting data generation device, processing device, and data flow graph generation method |
| JP6193699B2 (en) * | 2013-09-27 | 2017-09-06 | 株式会社ソシオネクスト | Arithmetic circuit |
-
2002
- 2002-01-23 JP JP2002013697A patent/JP2003216411A/en active Pending
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