JP2010244205A - Compiler program and compiler device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the executing performance of a program by effectively using a cache memory. <P>SOLUTION: An optimization part 32 analyzes an intermediate language text converted by a source analyzing part 31 from a source program to be executed by an information processor 40 on which a cache memory with a sector function is loaded. Concretely, the optimization part 32 determines the presence/absence of reusability in executing the loop processing of a data group to be processed by each group. Then, the optimization part 32 determines a sector division rate and a sector number from the number of ways required for storing the data group of which the presence/absence of reusability is determined and the maximum number of ways of a system. The optimization part 32 inserts a sector division instruction and an instruction sentence to which a sector number is added in a loop whose sector division rate and sector number have been determined. A file generation part 33 generates an object file from an intermediate language text into which the instruction sentence is inserted. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compiler program and a compiler apparatus.

  Conventionally, a cache memory having a small storage capacity but capable of high-speed access has been used in order to eliminate a data delay occurring between a CPU (Central Processing Unit) and a main memory and improve program execution processing ( For example, see Patent Documents 1 to 5).

  Here, as will be described below, there is known a technique for improving program execution processing by leaving specific data as much as possible or leaving certain data on a cache memory as much as possible.

  The first technique is the weakest way method. The weakest way method is a method in which when data is transferred to a cache memory by a memory access instruction, the data to be evicted first in the same index (in the same way) can be indicated. In the weakest way method, non-reusable data such as stream data and other data are not ejected (replaced) by the same LRU method, but non-reusable data is preferentially ejected. This makes it easy for reusable data to remain in the cache. In the LRU (Least Recently Used) method, the data of the way that has been used for the longest time is selected, and the selected data is replaced with new data. The way is a unit when the cache line is divided into a plurality of by the set associative method.

  The second technique is a local memory system (see, for example, Patent Documents 6 and 7). In the local memory system, the cache memory area is divided into a normal cache memory area and a local memory (or scratch pad) area. In the local memory method, reusable data is arranged in the local memory area. Therefore, in the local memory method, reusable data can be prevented from being evicted from the cache memory by non-reusable data such as stream data.

  The third technique is a cache line lock method or a cache way lock method. In the cache line lock method, a specific cache line is locked, and in the cache way lock method, a specific cache way is locked. Then, in the cache line lock method or the cache way lock method, similar to the local memory method, the cache line or the cache way in which reusable data is written is locked, so that reusability such as stream data can be achieved. It is possible to prevent reusable data from being evicted from the cache memory due to missing data.

JP 62-233864 A Special table 2008-525919 JP 2005-122506 A JP 2008-102733 A JP 2002-49529 A JP-A-10-187533 JP-A-4-175946

  By the way, the above-mentioned local memory system requires a special store instruction for a local memory area different from the normal cache memory area and the main memory. In the above-mentioned local memory system, it is necessary to perform control for maintaining data consistency between the normal cache area and scratch pad area and the main memory. In the local memory system described above, a large overhead is required when changing the area size of the local memory during program execution.

  Also, with the above cache line lock method or cache way lock method, if the programmer forgets to unlock (unlock) or locks all the cache areas by mistake, the cache system may not operate normally. There is sex. In addition, the above-described cache line lock method or cache way lock method requires a dedicated hardware mechanism for unlocking, which increases the additional cost.

  In addition, the weakest way method described above is a priority eviction, and the probability that reusable data remains in the cache memory is lower than the local memory method, the cache line lock method, or the cache way lock method. . The weakest way method described above cannot be implemented simultaneously with the local memory method.

  That is, the above-described conventional technique has a problem that the execution performance of the program may be deteriorated because the cache memory cannot always be effectively used.

  Therefore, the disclosed technique has been made to solve the above-described problems of the prior art, and a compiler program and a compiler that can improve the execution performance of a program by effectively using a cache memory An object is to provide an apparatus.

  In order to solve the above-described problems and achieve the object, the program disclosed in the present application is, in one aspect, by analyzing a source program executed by an information processing apparatus equipped with a cache memory with a sector function. Necessary for determining whether or not the data set, which is a set of data arrays processed in each loop of the source program, is reusable when loop processing is executed, and storing the data set for which the reusability is determined A determination procedure for determining a sector division ratio in the cache memory and a sector number for specifying a sector storing the data set from the capacity and the capacity of the cache memory, and the sector division ratio and In the loop in which the sector number is determined, the sector division ratio and the sector number It is a requirement that the computer execute an insertion procedure for inserting an instruction control statement based on the source program and a file generation procedure for generating an object file from the source program in which the instruction control statement is inserted by the insertion procedure. .

  In another aspect, the program disclosed in the present application is a reception procedure for receiving a source program in which a sector division ratio is specified in a loop by a creator when stored in a cache memory with a sector function, and the reception procedure An extraction procedure for extracting sequence data used in a loop in which the sector division ratio is specified by the creator in the source program from the source program accepted by the source program, and the sequence data extracted by the extraction procedure In the loop in which the sector number is determined by the determination procedure, and a determination procedure for determining a sector number for storing the array data in the cache memory based on the presence or absence of reusability and the sector division ratio The determined sector number and the cell specified by the creator. And causing a computer to execute an insertion procedure for inserting an instruction control statement based on a data division ratio into the source program and a file generation procedure for generating an object file from the source program into which the instruction control statement has been inserted by the insertion procedure. Is a requirement.

  According to the disclosed program, it is possible to improve the execution performance of the program by effectively using the cache memory.

FIG. 1 is a diagram for explaining the weakest way method in a cache system with a sector function. FIG. 2 is a diagram for explaining a local memory system in a cache system with a sector function. FIG. 3 is a diagram for explaining the concept of sector division processing by the compiler apparatus according to the first embodiment. FIG. 4 is a block diagram illustrating the configuration of the compiler apparatus according to the first embodiment. FIG. 5 is a diagram for explaining the source program storage unit according to the first embodiment. FIG. 6 is a diagram for explaining the archidata storage unit. FIG. 7 is a flowchart for explaining the overall processing of the compiler apparatus according to the first embodiment. FIG. 8 is a flowchart for explaining the overall processing of the optimization unit shown in FIG. FIG. 9 is a flowchart for explaining the sector division ratio, sector division ratio effective range, and sector number determination process shown in FIG. FIG. 10 is a flowchart for explaining the process of determining the sector division ratio effective range shown in FIG. FIG. 11 is a flowchart for explaining the determination processing of the data set and the necessary number of ways to be handled as the reusable memory access data shown in FIG. FIG. 12 is a flowchart for explaining the data set handling as the stream data shown in FIG. 9 and the necessary way number determination processing. FIG. 13 is a diagram for explaining the three types of output patterns shown in FIG. FIG. 14 is a diagram for explaining the optimization result storage unit. FIG. 15 is a diagram for explaining an example of a cache control statement used in the second embodiment. FIG. 16 is a diagram for explaining an example of sector division designation by the weakest way method. FIG. 17 is a diagram for explaining an example of designation of sector division by the local memory method. FIG. 18 is a diagram for explaining an example of sector division designation by the weakest way method and the local memory method. FIG. 19 is a diagram for explaining a modification of the control area designation. FIG. 20 is a diagram for explaining an example of sector division designation by the quasi-local memory method. FIG. 21 is a diagram for explaining the source analysis unit according to the second embodiment. FIG. 22 is a flowchart for explaining the sector determination process of the optimization unit according to the second embodiment. FIG. 23 is a diagram illustrating a computer that executes the compiler program according to the first embodiment.

  Exemplary embodiments of a compiler program and a compiler apparatus disclosed in the present application will be described below in detail with reference to the accompanying drawings. In the following, a compiler apparatus that executes a compiler program disclosed in the present application will be described as an embodiment.

  First, main terms used in this embodiment will be described. The “cache memory system with a sector function” used in the present embodiment is a system that can instruct a cache memory in which a cache line is divided into a plurality of ways by a set associative method to be divided into a plurality of sectors even during program execution. That's it.

  Specifically, in the “cache memory system with sector function”, when the cache memory is divided into sectors, a sector division ratio (hereinafter referred to as a sector division ratio) can be designated. Further, in the “cache memory system with a sector function”, it is possible to indicate a sector to be used for each subsequent memory access instruction (specifically, a sector number that identifies each divided sector). As a result, in the “cache memory system with sector function”, the usage of each sector can be instructed indirectly (or directly).

  In addition, the “LRU method” is a method in which data that has been used for the longest time (LRU: Last Recently Used) is sequentially removed from the cache memory and new data is taken in. The “weakest way method” is a method for instructing data to be first ejected in the same index (in the same way) when data is transferred to the cache memory by a memory access instruction. The “local memory method” is a method in which the cache memory area is divided into a normal cache memory area and a local memory (or scratch pad) area, and reusable data is arranged in the local memory area. It is.

  Further, the “weakest way method in a cache memory system with a sector function” is, for example, the weakest way method when executing a program using a cache memory divided into two sectors (sector 0 and sector 1). It is a system that adopts. The “weakest way method in the cache memory system with a sector function” will be described below with reference to FIG. FIG. 1 is a diagram for explaining the weakest way method in the cache system with a sector function.

  In the “weakest way method in a cache memory system with a sector function”, as shown in FIG. 1A, the sum of the maximum number of ways of sector 0 and sector 1 is larger than the maximum number of ways of the system. The sector division ratio is designated as follows. For example, as shown in FIG. 1B, when the maximum number of ways in a system (cache memory) in which one way is 512 KB is “10”, the maximum number of ways in sector 0 is the maximum number of ways in the system. The same number “10” is set, and the maximum number of ways in sector 1 is “5”.

  For example, when the source program shown in FIG. 1C is executed, stream data array a and array b, which are continuous data for sequentially accessing adjacent areas, are allocated to sector 1. As shown in FIG. 1C, the array c, which is reusable data, is assigned to sector 0 in the do loop. Thus, when the “weakest way method” is executed in the “cache memory system with sector function”, the data of the array a and the array b are stored in different sectors, so that the data of the array c is cache memory. It is possible to reduce the probability of being evicted from.

  The “local memory system in a cache memory system with a sector function” is a local memory system that prevents a reusable array from causing an unplanned cache conflict and being evicted from the cache memory. It is a method to realize. In general, the local memory often uses a high-speed memory different from the normal cache memory. However, in the cache memory system with a sector function, the same operation as the local memory system is realized only by the cache control. The “local memory system in the cache memory system with a sector function” will be described below with reference to FIG. FIG. 2 is a diagram for explaining a local memory system in a cache system with a sector function.

  In the “local memory system in the cache memory system with sector function”, when the cache memory with sector function is used as the local memory, as shown in FIG. However, the sector division ratio is specified so that it becomes the same value as the maximum number of ways of the system. For example, as shown in FIG. 2B, when the maximum number of ways in a system (cache memory) where 1 way is 512 KB is “10”, the maximum number of ways in sector 0 is “9”. The maximum number of ways in sector 1 is “1” obtained by subtracting “9” from “10”.

  For example, when the source program shown in FIG. 2C is executed, the reusable array c is allocated to the sector 1, and the stream data arrays a and b are allocated to the sector 0. In the source program shown in FIG. 1C, the declaration size of the array c is dynamic (do i = 1, m), whereas in the source program shown in FIG. Is declared statically as “do i = 1,1000”.

  Here, when the access width (size) of the array c is less than or equal to the size 512 KB of the sector 1, the data that uses the sector 1 is only the array c. Therefore, the probability that the array c is evicted from the sector 1 due to a cache conflict. Is 0%. In this way, by handling sector 1 as a local memory in the “cache memory system with sector function”, it is possible to prevent the reusable array c from being evicted from the cache. Even if the number of rotations of the loop is not clear as in the source program shown in FIG. 2C, if the declaration size of the array c is statically specified, “cache memory with sector function” The “local memory system in the system” is executable.

  The “quasi-local memory method in the cache memory system with a sector function” is a method used when the access size of the reusable array allocated to the cache memory having the sector number as the local memory is unknown. . In the “quasi-local memory system in the cache memory system with the sector function”, the sum of the maximum number of ways of the sector 0 and the sector 1 becomes the maximum number of ways of the system as in the “local memory system in the cache memory system with the sector function” A split ratio is specified.

  For example, in the source program shown in FIG. 1A, the access size and declaration size of the array c are unknown. When the “quasi-local memory method in the cache memory system with a sector function” is used, for example, sector division as shown in FIG. That is, when the access size of the reusable array c is unknown, for example, as shown in FIG. 2C, when the maximum number of ways of the system is “10”, the maximum number of ways of sector 0 is , “6”, and the maximum number of ways in sector 1 is “4” obtained by subtracting “6” from “10”. That is, the sector division ratio shown in FIG. 2C has a margin in the maximum number of ways in sector 1 compared to the local memory method shown in FIG. It is specified to have.

  However, the “semi-local memory system in the cache memory system with a sector function” has the following two problems. The first problem is that, since the access width of a reusable array is unknown, there is a possibility of causing a cache conflict in the sector 1 to which the reusable array is allocated by the LRU method. Further, the second problem is that if the maximum number of ways in sector 1 is increased due to concern about cache conflict, the maximum number of ways in sector 0 decreases, and the on-cache rate of stream data decreases.

  Because of these two problems, in the “semi-local memory method in the cache memory system with sector function”, for example, it is necessary to determine the sector division ratio based on PA information collected by a PA (performance analyzer) tool. There is. For this reason, the programmer needs to devise such as an optional operation instead of the default, and the “cache memory system with sector function” may not be easily used. In other words, since there is no compiler device that can automatically determine the sector division ratio and effective range (start position and end position) and set the sector number for each memory access data, programmers can effectively use the cache memory with sector function Can not do it.

  Therefore, the compiler apparatus according to the present embodiment executes sector division processing as described below with reference to FIG. FIG. 3 is a diagram for explaining the concept of sector division processing by the compiler apparatus according to the first embodiment.

  As shown in FIG. 3, the compiler apparatus according to the present embodiment has various factors (factor 1) such as the data access method in the loop, the size of the data array used in the loop, the number of ways of the cache memory, the size of the cache memory ~ N) is analyzed. Then, as shown in FIG. 3, the compiler apparatus according to the present embodiment uses the respective factors as analysis results as parameters to set the sector division ratio, the effective range of the sector division ratio (start position and end position), and the sector number of each data. Enter the decision function to be determined.

  From the output result of the decision function, the compiler apparatus according to the present embodiment determines the sector division ratio, the sector division ratio effective range, and the sector number of each data, as shown in FIG. An optimization process for adding a sector number to a memory access instruction is executed. Note that the compiler apparatus according to the present embodiment changes the decision function according to a new factor analyzed for each source program.

  Next, the configuration of the compiler apparatus in this embodiment will be described with reference to FIG. FIG. 4 is a block diagram illustrating the configuration of the compiler apparatus according to the first embodiment.

  As shown in FIG. 4, the compiler apparatus 10 according to the first embodiment includes a source program input unit 11, an object file output unit 12, a communication unit 13, an input / output control I / F unit 14, a storage unit 20, And a processing unit 30. Further, the compiler apparatus 10 in this embodiment is connected to the information processing apparatus 40 as shown in FIG.

  The information processing apparatus 40 is a computer that has a “cache memory with sector function” and executes the object file output from the compiler apparatus 10. In the present embodiment, the case where the compiler apparatus 10 and the information processing apparatus 40 are independent apparatuses will be described. However, the present embodiment is not limited to this, and the compiler apparatus 10 is included in the information processing apparatus 40. It may be a case where it is incorporated.

  The source program input unit 11 receives a source program created by a programmer, and the object file output unit 12 outputs the object file generated by the processing unit 30 to the information processing apparatus 40. The communication unit 13 receives archedata described later from the information processing apparatus 40.

  The communication unit 13 receives archedata described later from the information processing apparatus 40.

  The input / output unit I / F unit 14 controls data transfer among the source program input unit 11, the object file output unit 12 and the communication unit 13, and the storage unit 20 and the processing unit 30.

  The storage unit 20 stores the source program received by the source program input unit 11 and various processing results by the processing unit 15 described later. Here, the storage unit 20 is particularly closely related to the present embodiment. As shown in FIG. 4, the source program storage unit 21, the source analysis result storage unit 22, the archi data storage unit 23, and the optimum And a conversion result report storage unit 24.

  The source program storage unit 21 stores the source program received by the source program input unit 11. For example, the source program storage unit 21 stores source programs as shown in (A), (B), and (C) of FIG. FIG. 5 is a diagram for explaining the source program storage unit according to the first embodiment.

  Note that the three types of source programs shown in FIG. 5 will be described in detail later.

  The source analysis result storage unit 22 stores intermediate language text converted by a source analysis unit 31 (to be described later) into a language expression that can be handled by the compiler apparatus 10.

  The archi data storage unit 23 stores archi data as hardware information of the information processing apparatus 40 received by the communication unit 13. The archedata is information on the size of the cache memory mounted on the information processing apparatus 40, the number of cache ways, and the number of cache sectors. For example, as shown in FIG. 6, the archive data storage unit 23 has a cache size of “5 MB”, a cache way number of “10 WAY”, and a cache cache as the archive data of the secondary cache memory of the information processing apparatus 40. Information that the number of sectors is “2” is stored. The number of cache ways is the maximum number of ways of the system, and the number of cache sectors is the number of sector divisions.

  The optimization result storage unit 24 stores the processing result of the optimization unit 32 described later. The contents stored in the optimization result storage unit 24 will be described in detail later.

  The processing unit 30 executes various processes when the source program transferred from the input / output unit I / F unit 14 is stored in the source program storage unit 21. Here, the processing unit 30 includes a source analysis unit 31, an optimization unit 32, and a file generation unit 33, as shown in FIG. 4, particularly as closely related to the present embodiment.

  Here, FIG. 7 is used as a rough flow of the entire processing executed by the compiler apparatus 10 according to the first embodiment using the source analysis unit 31, the optimization unit 32, and the file generation unit 33 shown in FIG. I will explain. FIG. 7 is a flowchart for explaining the overall processing of the compiler apparatus according to the first embodiment.

  As shown in FIG. 7, when a source program is input (Yes in step S101), the source analysis unit 31 performs source analysis for converting the source program stored in the source program storage unit 21 into an intermediate language file (step S102). ).

  Then, the optimization unit 32 performs the optimization process by the sector division process described with reference to FIG. 3 based on the intermediate language file and the arche data (step S103).

  After that, the file generation unit 33 generates an object file from the intermediate language file that has been optimized by the optimization unit 32 and outputs the object file to the object file output unit 12 (step S104), and the compiler apparatus 10 according to the first embodiment. Ends the process.

  Here, the process of step S103 performed by the optimization unit 32 illustrated in FIG. 7 will be described in detail with reference to the flowcharts of FIGS. 8 is a flowchart for explaining the overall processing of the optimization unit shown in FIG. 7. FIG. 9 shows the sector division ratio, sector division ratio effective range and sector number determination processing shown in FIG. It is a flowchart for demonstrating. FIG. 10 is a flowchart for explaining the process of determining the sector division ratio effective range shown in FIG. 9. FIG. 11 shows a data set treated as reusable memory access data shown in FIG. It is a flowchart for demonstrating the determination process of required way number. FIG. 12 is a flowchart for explaining the data set handling as the stream data shown in FIG. 9 and the necessary way number determination processing.

  As shown in FIG. 8, the optimization unit 32 in the first embodiment stores the arc division data and the intermediate language text (Yes in step S201), and sets the sector division ratio, the sector division ratio effective range, and the sector number of each data. Determine (step S202). Here, since there are complex multiple loops in the program loop, the optimization unit 32 determines whether there is an array depending on the loop control variable and a user procedure for each loop in the program. First, a loop for inserting a cache division instruction is determined.

  Specifically, as shown in FIG. 9, the optimization unit 32 first determines a sector division ratio effective range (loop set LSET) (step S301).

  More specifically, as shown in FIG. 10, the optimization unit 32 searches all loops in the intermediate language text (step S401), and there is no array depending on the loop control variable in the loop L to be processed. Or whether there is a user procedure (function) (step S402).

  If there is an array that depends on the loop control variable in the loop L and there is no user procedure (function) (No in step S402), the optimization unit 32 sets the loop L to the sector division ratio effective range (loop set LSET). Is registered (step S403).

  On the other hand, when there is no array that depends on the loop control variable in the loop L, or when there is a user procedure (function) in the loop L (Yes in step S402), the optimization unit 32 excludes the loop L from processing. To do.

  Then, the optimization unit 32 determines whether or not all the loops searched in step S401 have been processed (step S404). If there is an unprocessed loop (No in step S404), the optimization unit 32 returns to step S402 and proceeds to the next step. Perform processing for the loop.

  On the other hand, if all loops searched in step S401 have been processed (Yes in step S404), a sector division ratio effective range (loop set LSET) that is a set of registered loops is determined (step S405), and FIG. The process proceeds to step S302.

  Returning to FIG. 9, the optimizing unit 32 starts processing one by one for the loops in the determined loop set LSET (step S302), and statically knows the size of all the arrays in the loop. It is determined whether or not the size is smaller (step S303).

  When all the array sizes in the loop are statically known and all the array sizes are smaller than the cache size (Yes at Step S303), the optimization unit 32 determines that the sector is not used and adopts the LRU method. Determine (step S310).

  On the other hand, when there is an array whose array size is not known statically or there is an array whose array size is equal to or larger than the cache size (No at Step S303), the optimization unit 32 treats it as reusable memory access data. The data set (S) and the required number of ways (SW) are determined (step S304).

  Specifically, as shown in FIG. 11, the optimization unit 32 starts processing for each data (each data array) in the loop (step S501), and the reusable data is “1” or more. It is determined whether or not there is (step S502).

  When the reusable data in the loop is “0” (No at Step S502), the optimization unit 32 determines “S = NULL” and “SW = 0” (Step S511).

  On the other hand, when the reusable data in the loop is “1” or more (Yes in step S502), the optimization unit 32 determines whether or not the reusable data in the loop is “1”. Determination is made (step S503).

  If the reusable data in the loop is “1” (Yes at Step S503), the optimization unit 32 determines “S” and determines an SB for determining SW (Step S504). That is, the optimizing unit 32 determines one reusable data as “S” and determines that the size of the reusable data is statically known by the access size or the declaration size as “SB, unit. : Byte ". Here, when the size of reusable data is statically known from both the access size and the declaration size, the optimization unit 32 sets the small value as SB.

  On the other hand, when the reusable data in the loop is “2” or more (No in step S503), the optimization unit 32 determines whether or not the reusable array can be allocated to the continuous area ( Step 505). For example, the optimization unit 32 determines whether another non-reusable array 3 is interrupted between the reusable array 1 and the array 2.

  Here, when a reusable array cannot be assigned to a continuous area (No at Step 505), the optimization unit 32 determines “S = NULL” and “SW = 0” (Step S511).

  On the other hand, when a reusable array can be assigned to a continuous region (Yes in step 505), the optimization unit 32 determines “S”, which is a set of two or more reusable arrays, SB for determining SW is determined (step S506). The optimization unit 32 determines the SB by summing up (SUM) the declaration size of the data of the reusable array.

  When S and SB are determined in steps S504 and S506, the optimization unit 32 determines whether or not the determined SB is within a range from a preset lower limit threshold to an upper limit threshold (step S507). .

  Here, when the determined SB is not within the range from the preset lower limit threshold to the upper limit threshold (No at Step S507), the optimization unit 32 assumes that the determined set S is not used for the subsequent processing, and “S = “NULL” and “SW = 0” are determined (step S511).

  On the other hand, when the determined SB is within the range between the preset lower limit threshold value and the upper limit threshold value (Yes at Step S507), the number of ways into which the SB byte enters is determined as SW (Step S508).

  Further, the optimization unit 32 calculates the reusable data number ratio (AR) by dividing the number of reusable data by the total number of data (step S509), and the calculated AR is set in advance. It is determined whether it is within the range of the upper limit threshold from the set lower limit threshold (step S510). Note that the threshold set for AR and the threshold set for SB described above are different values.

  Here, when the calculated AR is not within the range between the preset lower limit threshold value and the upper limit threshold value (No in step S510), the optimization unit 32 assumes that the determined set S is not used for the subsequent processing, and “S = “NULL” and “SW = 0” are determined (step S511).

  On the other hand, when the calculated AR is within the range from the preset lower limit threshold to the upper limit threshold (Yes at Step S510), the optimization unit 32 sets the set S determined at Step S504 or Step S506 and the SW determined at Step S508. Is determined (step S512).

  The optimization unit 32 proceeds to step S305 after S and SW are determined in steps S511 and S512.

  Returning to FIG. 9, the optimizing unit 32 determines whether or not the data set S of reusable memory access data determined by the processing of step S304 (FIG. 11) is empty (NULL). Step S305).

  If the data set S is not empty (No at Step S305), the optimization unit 32 determines to generate a new algorithm of the local memory method (Step S307). That is, the optimizing unit 32 can allocate reusable data to the continuous area, and determines that the local memory method can be adopted.

  Specifically, the optimizing unit 32 determines the sector division ratio “sector number 0: sector number 1 = from the cache way number“ 10 ”shown in FIG. 10-SW: SW ". Further, the optimization unit 32 determines that the data array registered in the data set S is stored in the sector number 1 and that the data array not included in the data set S in the loop L is stored in the sector number 0. The optimization unit 32 determines that the data stored in each sector is sequentially replaced with new data using the LRU method.

  On the other hand, when the data set S is empty (Yes at step S305), the optimization unit 32 determines the data set (T) to be handled as stream data (continuous adjacent access data) and the required number of ways (TW) ( Step S306).

  Specifically, as shown in FIG. 12, the optimization unit 32 starts processing for each data (each data array) in the loop (step S601), and determines whether there is stream data (step S601). S602).

  When there is no stream data in the loop (No at Step S602), the optimization unit 32 determines “T = NULL” and “TW = 0” (Step S610).

  On the other hand, when there is stream data in the loop (Yes in step S602), the optimization unit 32 determines whether there is data other than stream data in the loop (step S603).

  If there is only stream data in the loop (No at step S603), the optimization unit 32 determines that “T = NULL” and “TW = 0” (step S610).

  On the other hand, when stream data and data other than stream data are mixed in the loop (Yes in step S603), the optimization unit 32 determines “T” and TB for determining TW (step S604). ). That is, the optimizing unit 32 determines a set of stream data as “T”, and calculates the maximum access width from the total access size of the stream data from the number of rotations or the declaration size, thereby obtaining TB (unit: bytes). calculate.

  Here, when TB is calculated and clarified (No in step S605), it is determined whether or not TB is within a range from a preset lower limit threshold to an upper limit threshold (step S606). The threshold value set for TB and the threshold value set for SB described above may be different values or the same value.

  If TB is not within the range from the preset lower limit threshold to the upper limit threshold (No at Step S606), the optimization unit 32 determines “T = NULL” and “TW = 0” (Step S610).

  On the other hand, when the TB is not calculated and is unknown (Yes at Step S605), and when the calculated TB is within the range from the preset lower limit threshold to the upper limit threshold (Yes at Step S606), the optimization unit 32 Calculates the stream data number ratio (step S607). That is, the optimization unit 32 calculates BR by dividing the number of stream data by the total number of data.

  Then, the optimization unit 32 determines whether or not the calculated BR is within a range from a preset lower limit threshold value to an upper limit threshold value (step S608). Note that the threshold value set for BR and the threshold value set for TB described above are different values.

  Here, when BR is not within the range from the preset lower limit threshold to the upper limit threshold (No at Step S608), the optimization unit 32 assumes that the determined set T is not used for the subsequent processing, and “S = NULL”. And “SW = 0” is determined (step S610).

  On the other hand, when BR is within the range from the preset lower threshold to the upper threshold (Yes at Step S608), the optimization unit 32 multiplies the total number of ways of the cache memory by AR and a preset threshold. TW is calculated (step S609). The threshold used for calculating TW is arbitrarily set by the programmer.

  Then, the optimization unit 32 determines T determined in step S604 and TW calculated in step S609 (step S611).

  Subsequently, the optimization unit 32 proceeds to step S308 after T and TW are determined in steps S610 and S611.

  Returning to FIG. 9, the optimizing unit 32 determines whether or not the data set T to be handled as stream data determined by the process of step S306 (FIG. 12) is empty (NULL) (step S308).

  Here, when the data set T is empty (Yes at Step S308), the optimization unit 32 determines that the sector is not used and determines to adopt the LRU method (Step S310).

  On the other hand, when the data set T is not empty (No at Step S308), the optimization unit 32 determines to generate a new algorithm of the weakest way method (Step S309).

  Specifically, the optimizing unit 32 determines the sector division ratio “sector number 0: sector number 1 = from the cache way number“ 10 ”shown in FIG. 10: TW ". Further, the optimization unit 32 determines that the data array registered in the data set T is stored in the sector number 1 and the data array not included in the data set T in the loop L is stored in the sector number 0. The optimization unit 32 determines that the data stored in each sector is sequentially replaced with new data using the LRU method.

  Then, after making any determination of step S307, step S309, or step S310, the optimization unit 32 proceeds to the process of step S203 shown in FIG.

  Here, the three types of patterns determined in FIG. 9 will be specifically described with reference to FIG. FIG. 13 is a diagram for explaining the three types of determination patterns shown in FIG.

  When the source program shown in FIG. 5A is stored, the optimization unit 32 determines the effective range of the sector division ratio as “do J” as shown in FIG. Is determined as an array c. Further, the optimization unit 32 divides the SB byte by the number of bytes of 1 way because the SB calculated from the declaration size of the array c is within the threshold range and the AR is within the threshold range. , “SW = 1”. Then, from the cache way number “10” shown in FIG. 6, the optimization unit 32 sets the sector division ratio to “sector number 0: sector number 1 ==” by the local memory method as shown in FIG. 9: 1 ". Further, the optimization unit 32 determines that the array c registered in the data set S is stored in the sector number 1 and the arrays a and b not included in the data set S in the loop L are stored in the sector number 0.

  When the source program shown in FIG. 5B is stored, the optimization unit 32 determines the effective range of the sector division ratio as “do J” as shown in FIG. Is determined to be empty. Furthermore, the optimization unit 32 determines a data set T whose elements are the array a that is continuous adjacent access data. In addition, since the BR of the array a whose TB is unknown is within the threshold range, the optimization unit 32 multiplies the total number of ways (cache way number), BR, and the threshold value to obtain “TW = 5”. And decide. Then, from the cache way number “10” shown in FIG. 6, the optimization unit 32 sets the sector division ratio to “sector number 0: sector number 1” by the weakest way method as shown in FIG. = 10: 5 ". Further, the optimization unit 32 determines that the array a registered in the data set T is stored in the sector number 1 and the arrays c and b not included in the data set T in the loop L are stored in the sector number 0.

  When the source program shown in (C) of FIG. 5 is stored, the optimization unit 32 clearly shows that all the array sizes in the loop are smaller than the cache size. Therefore, as shown in (C) of FIG. In addition, it is determined that the LRU method is adopted as “no sector division data”.

  Returning to FIG. 8, the optimization unit 32 inserts a sector division instruction and adds a sector number to the memory access instruction in accordance with the determined sector division process after the process of FIG. 9 (step S203). The process is terminated.

  That is, the optimization unit 32 inserts a sector division command and adds a sector number according to the determined sector division ratio control range, sector division ratio, and sector number for each data, for example, as shown in FIG. The processing result is stored in the optimization result storage unit 24. FIG. 14 is a diagram for explaining the optimization result storage unit.

  For example, when the loop division L1 shown on the left side of FIG. 14 is within the effective range of the sector division ratio, the optimization unit 32 inserts an instruction for instructing division at the sector division ratio (9: 1) of the local memory method. Further, as shown in FIG. 14, the optimization unit 32 inserts an instruction for returning to the normal LRU method after the loop L1. Further, as shown in FIG. 14, the optimization unit 32 designates sector numbers (sector0, sector1) to be used for the “load, store” instruction within the sector division ratio effective range. Then, the optimization unit 32 stores the data shown on the right side of FIG. 14 in the optimization result storage unit 24. Note that the instruction specifying the sector number may be a prefetch instruction “prefetch”.

  Then, when the process of the optimization unit 32 ends in step S203 (FIG. 8), the file generation unit 33 generates an object file in step S104 (FIG. 7).

  As described above, according to the first embodiment, the optimization unit 32 performs the intermediate language text converted by the source analysis unit 31 from the source program executed by the information processing apparatus 40 that includes the cache memory with the sector function. Is analyzed. Specifically, the optimization unit 32 determines whether or not there is reusability when executing loop processing of a data set that is a set of data arrays processed in each loop. Then, the optimizing unit 32 determines the sector division ratio and the sector number from the number of ways required to store the data set for which reusability is determined and the maximum number of ways of the system. Then, the optimization unit 32 inserts an instruction sentence in which the sector number is added to the sector division instruction and the memory access instruction in the loop in which the sector division ratio and the sector number are determined. Then, the file generation unit 33 generates an object file from the intermediate language text in which the command sentence is inserted.

  Therefore, the compiler unit 10 can automatically determine the sector division ratio, the sector division ratio effective range, and the sector number, and can effectively execute the program execution performance by effectively using the cache memory, particularly the cache memory with the sector function. It becomes possible to improve. Also, even when the access size of reusable data is unknown, the sector division ratio and sector number can be determined automatically, reducing the burden on the programmer and providing a sector function. The cache memory can be used effectively.

  In the first embodiment, the optimization unit 32 determines a sector division ratio and a sector number by a local memory method for a data set that is determined to be reusable and can be continuously allocated. As a result, reusable data can be prevented from being evicted from the cache memory by the LRU method by data other than reusable data, and the cache memory with sector function can be used more effectively. Become.

  Further, in the first embodiment, the optimization unit 32 includes a data set that is determined as stream data that is not reusable (continuous adjacent access data) in a loop in which there is no data array that has reusability. For the data set determined as stream data, the sector division ratio and the sector number are determined by the weakest way method. As a result, reusable data can be prevented from being unscheduled out of the cache memory due to a conflict in the cache line, and the cache memory with a sector function can be used more effectively.

  In the present embodiment, as shown in FIG. 11, the case where S is determined to be “NULL” when a reusable data array cannot be allocated to a continuous area has been described. Is not limited to this. For example, if the data arrays 1 and 2 of the reusable data arrays 1, 2, and 3 can be allocated to the continuous area, the optimization unit 32 sets the data arrays 1 and 2 as S and the subsequent steps S506 The process may be executed.

  In the first embodiment described above, the case where the sector division ratio is automatically determined by the compiler apparatus 10 has been described. In the second embodiment, the case where the sector division ratio is specified by the programmer will be described.

  The compiler apparatus 10 in the second embodiment has the same configuration as the compiler apparatus 10 in the first embodiment described with reference to FIG. However, in the second embodiment, the contents of the source program received by the source program input unit 11 and the processing contents of the source analysis unit 31 and the optimization unit 32 are different from the first embodiment. Hereinafter, these will be mainly described.

  In the second embodiment, a cache control statement that allows the programmer to specify the sector division of the cache memory not at the assembler notation level but at the source program notation level and that can be understood by the compiler apparatus 10 is used. An example of the cache control statement used in the second embodiment will be described with reference to FIG. Note that the cache control statement described below is merely an example, and may be in any format as long as the compiler device 10 can decode the sector division ratio specified by the programmer.

  First, in the cache control statement, “! Ocl sector_cache_begin” is used as a control statement meaning the start of sector control (see (1) in FIG. 15). The notation “! Ocl” is a control statement that gives instructions to the compiler, generally called an optimization control line, and is supported by many vendors. That is, in the cache control statement shown in FIG. 15, the sector is specified by “! Ocl”.

  In the cache control statement, the sector division ratio is indicated together with the sector number by “! Ocl sector0_max (m), sector1_max (n)” (see (2) in FIG. 15). Here, in (2) of FIG. 15, it is specified that the maximum number of ways in sector 0 is m and the maximum number of ways in sector 1 is n. Here, the compiler apparatus 10 according to the second embodiment determines that the programmer specifies the local memory method if “m + n” is the same as the maximum number of ways of the system as a cache method determination rule. Further, the compiler apparatus 10 according to the second embodiment determines that the programmer designates the weakest way method if “m + n” is larger than the maximum number of ways of the system as a cache method determination rule.

  In the cache control statement, “! Ocl sector0 (array1), sector1 (array2, array3)” designates the array name of data stored for each sector number (see (3) in FIG. 15). Here, in (3) of FIG. 15, array1 is designated as an array assigned to sector 0, and arrays2 and array3 are designated as arrays assigned to sector 1.

  As shown in (3) of FIG. 15, it is possible to leave the array designation to the compiler (compile device 10). Here, if it is determined that the cache method is the weakest way method, the compiler determines that stream data is allocated to sector 1 and data other than the stream data in the loop is allocated to sector 0. Further, if the cache method is determined to be the local memory method, the compiler determines that reusable data is allocated to sector 1 and data other than the reusable data in the loop is allocated to sector 0. . Note that reusable data and stream data are determined in the same manner as described in the first embodiment.

  In the cache control statement, “! Ocl sector_cache_end” is used as a control statement meaning the end of sector control (see (4) in FIG. 15). That is, the designation of the sector division ratio effective range described in the first embodiment is determined by the programmer based on “! Ocl sector_cache_begin” and “! Ocl sector_cache_end”. In the following description, the area from the control start position to the control end position is referred to as a control area instead of the sector division ratio effective range used in the first embodiment.

  Also, in the cache control statement, “! Ocl loop sector_cache” may be used as a control statement that can be instructed to the subsequent loop instead of specifying the control area by “! Ocl sector_cache_begin” and “! Ocl sector_cache_end”. (See (5) in FIG. 15).

  In addition to the rules described above, in the cache control statement, as shown in FIG. 15, a rule that “nesting of sectors is not allowed” or a rule that “sector_cache_end must be reached from sector_cache_begin” is adopted. .

  Here, various sector division designation examples by the cache control statement shown in FIG. 15 will be described with reference to FIGS. FIG. 16 is a diagram for explaining an example of designation of sector division by the weakest way method, and FIG. 17 is a diagram for explaining an example of designation of sector division by the local memory method. FIG. 18 is a diagram for explaining a specification example of sector division by the weakest way method and the local memory method, and FIG. 19 is a diagram for explaining a modification example of control area specification. FIG. 20 is a diagram for explaining an example of designation of sector division by the quasi-local memory method.

  In the designation examples shown in FIG. 16 and subsequent figures, it is assumed that the number of sectors is “2” and the maximum number of ways of the system is “10”.

  In the cache control statement shown in FIG. 16, non-reusable stream data (arrays a and b) is stored in the 5-way sector 1, and data including reusable data other than stream data (array c) is stored. It is specified that data is stored in sector 0 of 10 ways. Here, since “10 + 5> 10”, the compiler apparatus 10 determines that the weakest way method is designated. That is, the programmer specifies to reduce the probability that reusable data (array c) is evicted from the cache memory.

  Next, in the cache control statement shown in FIG. 17, reusable data (array c) is stored in sector 1 of 1 way, and data other than reusable data (arrays a and b) is 9 ways. It is specified that the data is stored in the sector 0. Here, since the compiler apparatus 10 is “1 + 9 = 10”, it is determined that the local memory system is designated. That is, the programmer can completely prevent the reusable data (array c) from being unintentionally evicted from the cache memory due to a cache line conflict.

  Next, in the cache control statement shown in FIG. 18, in order to utilize the characteristics of the cache memory system with the sector function, the sector division ratio is designated for each loop, and the weakest way method and the local memory method are used together. Yes.

  That is, as shown in FIG. 18, in a certain loop, reusable data (array c) is stored in sector 1 of 1 way, and data other than reusable data (arrays a and b) is 9 A local way method for storing in sector 0 of the way is specified. As shown in FIG. 18, in another loop, the weakest way method for storing stream data (array d) in sector 1 of 5 ways is designated.

  Next, the cache control statement shown in FIG. 19 shows a modified example of the control area designation described above. That is, in the example shown in FIG. 19, “! Ocl loop sector_cache” is used instead of “! Ocl sector_cache_begin” and “! Ocl sector_cache_end” to indicate the sector division ratio and sector number for each loop. In general, the presence or absence of data reusability is often determined based on the DO control variable of the loop. That is, for the programmer, it is easier to specify a control area that focuses on the loop, so that it is easier to use. In this embodiment, it is possible to specify “! Ocl loop sector_cache”.

  When the local memory system is designated, it is not essential that the rotation speed of the innermost loop for designating the local memory system is statically known as shown in FIGS. For example, even if the rotational speed is a variable, if the programmer knows the maximum value that the variable can take, sector division by the local memory method is possible. For example, the grammar uses the PA (performance analyzer) tool for the actual execution module to obtain the maximum possible value of the variable.

  Here, the cache control statement shown in FIG. 20 is “6: 4” for the array c whose reusable array size is unknown, and a quasi-local memory to which the local memory method is applied as the sector division ratio. A method specification example is shown. However, in the quasi-local memory method, there is a possibility that the conflict of the cache line of sector 1 cannot be completely prevented with respect to the array c whose size is unknown. Further, in the quasi-local memory method, since there is a possibility that the number of ways in sector 1 is excessively increased with respect to the array c whose size is unknown, the number of ways for storing the remaining data is reduced, and the program is executed. In some cases, the performance is degraded.

  Therefore, when specifying the quasi-local memory system for a cache memory system with a sector function, for example, the programmer executes the execution module once, grasps the cache information with a PA (performance analyzer) tool, and then executes the cache control statement. Put in.

  Hereinafter, processing of the compiler apparatus 10 in the second embodiment when a source program in which a cache control statement is inserted is input will be described.

  The source analysis unit 31 in the second embodiment analyzes a cache control statement described in the input source program, and stores the analysis result as cache control statement data in the source analysis result storage unit 22 together with the intermediate language text described above. To do.

  For example, the source analysis unit 31 analyzes the cache control statement of the source program shown in FIG. 16 and, as shown in FIG. 21, “10” for “sector0_max”, “5” for “sector1_max”, “control start position” "10" is registered. FIG. 21 is a diagram for explaining the source analysis unit according to the second embodiment.

  Furthermore, as illustrated in FIG. 21, the source analysis unit 31 has one array in which the sector 0 is specified, and registers “c” in “sector0 [0]”. Further, as shown in FIG. 21, the source analysis unit 31 has two arrays in which sector 1 is designated, “a” in “sector1 [0]”, and “b” in “sector1 [1]”. Register. Furthermore, although not shown in FIG. 21, the source analysis unit 31 registers the analyzed value in the “control end position”.

  Then, the optimization unit 32 according to the second embodiment reads the cache control statement data and inserts a cache division instruction at the control start position. Specifically, a cache division instruction is inserted as shown in FIG. 13 described in the first embodiment.

  Specifically, the optimization unit 32 reads the cache control statement data, analyzes the data reusability, and determines whether or not the way duplication is allowed in the sector. Then, the optimization unit 32 determines the sector number of each memory access for all the memory access instructions (load, store, prefetch instructions) in the control area. However, the optimization unit 32 follows the sector designation when the sector designation has already been explicitly indicated in the cache control statement data.

  More specifically, the optimization unit 32 according to the second embodiment executes the sector determination process according to the procedure illustrated in FIG. FIG. 22 is a flowchart for explaining the sector determination process of the optimization unit according to the second embodiment.

  As illustrated in FIG. 22, the optimization unit 32 according to the second embodiment starts processing for each data (step S701), and determines whether “m + n” in the cache control statement is equal to or greater than the maximum number of ways of the system. (Step S702). Note that the optimization unit 32 obtains “m + n” by adding “sector0_max” and “sector1_max” illustrated in FIG. 21, for example.

  Here, when “m + n” is smaller than the maximum number of ways of the system (No at Step S702), the optimization unit 32 determines that no sector is designated (Step S703), and ends the process. That is, the optimizing unit 32 determines to execute the data storage process by the LRU method without dividing the sector.

  On the other hand, when “m + n” is equal to or greater than the maximum number of ways of the system (Yes at Step S702), the optimization unit 32 determines whether or not the data sector number is specified in the cache control statement data (Step S704). . That is, the optimization unit 32 determines whether there is an array in which a sector is specified in the data structure of the cache control statement.

  If the data sector number is specified (Yes at step S704), the optimization unit 32 sets a sector number for all memory accesses in the control area, and no sector number is specified in some data arrays. If there is something, it is set to sector 0 (step S705), and the process is terminated.

  On the other hand, when the sector number of the data is not specified (No in step S704), the optimization unit 32 determines whether or not all the stream data has no reusability as a result of the reusability determination by the subscript analysis for each memory access. (Step S706). Specifically, the optimization unit 32 analyzes the subscripts to determine whether or not all memory accesses in the loop are stream data that continuously accesses adjacent data depending on the DO control variable.

  Here, when all the stream data is not reusable (Yes in step S706), the optimization unit 32 determines that the data storage processing is to be executed by the LRU method without dividing the sector data, and performs the processing. finish.

  On the other hand, when all the data is not stream data having no reusability (No at Step S706), the optimization unit 32 determines whether “m + n” is larger than the maximum number of ways of the system (Step S707).

  Here, when “m + n” is the same value as the maximum number of ways of the system (No in step S707), the optimization unit 32 sets the reusable memory access as the sector number “1”, and sets the other as the sector number. “0” is designated (step S708), and the process is terminated. That is, the optimization unit 32 determines to divide the sector by the local memory method.

  On the other hand, when “m + n” is larger than the maximum number of ways of the system (Yes in step S707), the optimization unit 32 sets the memory access of the stream data without reusability as the sector number “1”, and sets the others as the sector number “ "0" is designated (step S709), and the process is terminated. That is, the optimization unit 32 determines to divide the sector by the weakest way method. The optimization unit 32 performs the determination as to whether or not the data array is reusable and whether or not the data array is stream data by the process described in the first embodiment.

  Thereby, the optimization unit 32 according to the second embodiment inserts the cache division instruction at the control start position, and stores the intermediate language text with the cache division instruction inserted in the optimization result storage unit 24. The file generation unit 33 generates an object file from the intermediate language text in which the cache division instruction is inserted, and outputs the object file to the information processing apparatus 40. As a result, the cache control statement is reflected in the execution module, and the information processing apparatus 40 executes cache control as intended by the programmer.

  As described above, according to the second embodiment, the optimization unit 32 uses the cache control statement to specify the sector division ratio from the source program in the cache control statement by the programmer when storing in the cache memory with the sector function. The presence / absence of reusability of the sequence data used in the loop is determined. Then, the optimization unit 32 determines the sector number based on whether the data array is reusable and the sector division ratio of the cache control statement, and adds the sector number to the sector division instruction and the memory access instruction. Insert statements into intermediate language text.

  Therefore, by using the compiler device 10 that can decode the cache control statement, the cache memory with the sector dividing function can be used effectively in accordance with the intention of the programmer, and the execution performance of the program can be improved. It becomes.

  In the second embodiment, the optimization unit 32 automatically determines the sector number by automatically determining whether the local memory method or the weakest way method from the sector division ratio specified in the cache control statement. It becomes possible to reduce the burden on the programmer.

  Of the processes described in the first and second embodiments described above, all or a part of the processes described as being automatically performed can be manually performed (for example, the hardware information is stored by the programmer. Manually). Alternatively, among the processes described in the present embodiment, all or a part of the processes described as being performed manually can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters (for example, the cache control statement shown in FIG. 15) shown in the above-mentioned document and drawings are not specifically described. Can be changed arbitrarily.

  Each component of each illustrated device is functionally conceptual and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. Further, all or any part of each processing function performed in each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware by wired logic.

  In the above embodiment, the case where various processes are realized by hardware logic has been described. However, the present invention is not limited to this, and a program prepared in advance may be executed by a computer. . Therefore, in the following, an example of a computer that executes a compiler program having the same function as the compiler apparatus 10 shown in the first embodiment will be described with reference to FIG. FIG. 23 is a diagram illustrating a computer that executes the compiler program according to the first embodiment.

  As shown in FIG. 23, a computer 100 as an information processing apparatus includes a keyboard 101, a display 102, a CPU 103, a ROM 104, an HDD 105, and a RAM 106. The keyboard 101, the display 102, the CPU 103, the ROM 104, the HDD 105, and the RAM 106 are connected by a bus 107 or the like. The computer 100 is connected to the information processing apparatus 40.

  The ROM 104 stores in advance a compiler program that exhibits the same function as the compiler apparatus 10 shown in the first embodiment, that is, a source analysis program 104a, an optimization program 104b, and a file generation program 104c as shown in FIG. It is remembered. Note that these programs 104a to 104c may be appropriately integrated or distributed in the same manner as each component of the compiler apparatus 10 shown in FIG.

Then, the CPU 103 reads these programs 104 a to 104 c from the ROM 104 and executes them. Thus, as shown in FIG. 23, the programs 104a to 104c
Functions as a source analysis process 103a, an optimization process 103b, and a file generation process 103c. The processes 103a to 103c correspond to the source analysis unit 31, the optimization unit 32, and the file generation unit 33 shown in FIG.

  Further, as shown in FIG. 23, the HDD 105 is provided with source program data 105a, source analysis data 105b, arche data 105c, and optimization result data 105d. Each of the program data 105a to 105d corresponds to the source program storage unit 21, the source analysis result storage unit 22, the arche data storage unit 23, and the optimization result storage unit 24 used in FIG. Then, the CPU 103 registers the source program data 106a with the source program data 105a, registers the source analysis data 106b with the source analysis data 105b, and registers the arche data 106c with the archi data 105c. Further, the CPU 103 registers the optimization result data 106d in the optimization result data 105d. Then, the CPU 103 reads the registered data, stores it in the RAM 106, and executes a compile process based on the source program data 106a, the source analysis data 106b, the arc data 106c, and the optimization result data 106d stored in the RAM 106.

  The above-described programs 104a to 104c are not necessarily stored in the ROM 104 from the beginning. For example, a flexible disk (FD), a CD-ROM, an MO disk, a DVD disk, and a magneto-optical disk inserted into the computer 100 are used. The computer 100 via a “portable physical medium” such as a disk or an IC card, or a “fixed physical medium” such as an HDD provided inside or outside the computer 100, and further via a public line, the Internet, a LAN, a WAN, etc. Each program may be stored in “another computer (or server)” connected to the computer, and the computer 100 may read and execute each program from these programs.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Supplementary Note 1) By analyzing a source program executed by an information processing apparatus equipped with a cache memory with a sector function, loop processing of a data set that is a set of data arrays processed in each loop of the source program Determine the presence or absence of reusability at the time of execution, and determine the sector division ratio in the cache memory and the data from the capacity required to store the data set for which the presence or absence of the reusability is stored and the capacity of the cache memory A decision procedure for determining a sector number for identifying a sector storing the set;
An insertion procedure for inserting an instruction control statement based on the sector division ratio and the sector number into the source program in the loop in which the sector division ratio and the sector number are determined by the determination procedure;
A file generation procedure for generating an object file from the source program in which the instruction control statement is inserted by the insertion procedure;
A compiler program characterized by causing a computer to execute.

(Supplementary Note 2) The determination procedure is required for storing a capacity required to store a data set of a data array determined to be reusable and a data set other than the data array determined to be reusable. The compiler program according to appendix 1, wherein the sector division ratio and the sector number are determined so that a sum of the capacities is equal to a capacity of the cache memory.

(Supplementary Note 3) When there is a data set that is determined as non-reusable stream data in a loop in which there is no reusable data array, the determination procedure is determined as non-reusable stream data. The sum of the capacity required to store the data set to be stored and the capacity required to store the data set other than the data array determined as the non-reusable stream data is larger than the capacity of the cache memory. The compiler program according to appendix 2, wherein the sector division ratio and the sector number are determined as described above.

(Supplementary Note 4) Accepting procedure for accepting a source program in which a sector division ratio when storing in a cache memory with a sector function is designated in a loop by the creator;
An extraction procedure for extracting array data used in a loop in which the sector division ratio is designated by the creator in the source program from the source program accepted by the acceptance procedure;
A determination procedure for determining a sector number when storing the array data in the cache memory based on the presence or absence of reusability of the array data extracted by the extraction procedure and the sector division ratio;
In the loop in which the sector number is determined by the determination procedure, an insertion procedure for inserting an instruction control statement based on the determined sector number and a sector division ratio designated by the creator into the source program;
A file generation procedure for generating an object file from the source program in which the instruction control statement is inserted by the insertion procedure;
A compiler program characterized by causing a computer to execute.

(Supplementary Note 5) In the determination procedure, the sector division ratio designated by the creator is divided within a range corresponding to the capacity of the cache memory, or from a range corresponding to the capacity of the cache memory. The compiler program according to appendix 4, wherein the sector number is determined after determining whether the sector is divided within a large range.

(Appendix 6) Loop processing of a data set that is a set of data arrays processed in each loop of the source program by analyzing a source program executed by an information processing apparatus equipped with a cache memory with a sector function Determine the presence or absence of reusability at the time of execution, and determine the sector division ratio in the cache memory and the data from the capacity required to store the data set for which the presence or absence of the reusability is stored and the capacity of the cache memory A determination unit for determining a sector number for identifying a sector storing the set;
An insertion unit for inserting an instruction control statement based on the sector division ratio and the sector number into the source program in a loop in which the sector division ratio and the sector number are determined by the determination unit;
A file generation unit that generates an object file from a source program in which the instruction control statement is inserted by the insertion unit;
A compiler apparatus comprising:

(Additional remark 7) The said determination part is required in order to store the capacity | capacitance required to store the data set of the data arrangement | sequence determined to have reusability, and data sets other than the data array determined to have the said reusability 7. The compiler apparatus according to appendix 6, wherein the sector division ratio and the sector number are determined so that a sum of the capacities is equal to a capacity of the cache memory.

(Supplementary Note 8) When there is a data set that is determined as non-reusable stream data in a loop in which there is no reusable data array, the determination unit determines that the data is not reusable stream data The sum of the capacity required to store the data set to be stored and the capacity required to store the data set other than the data array determined as the non-reusable stream data is larger than the capacity of the cache memory. The compiler apparatus according to appendix 7, wherein the sector division ratio and the sector number are determined as described above.

(Supplementary Note 9) A reception unit that receives a source program in which a sector division ratio specified in a loop by a creator is stored in a cache memory with a sector function;
An extraction unit that extracts array data used in a loop in which the sector division ratio is specified by the creator in the source program from the source program received by the reception unit;
A determination unit for determining a sector number when storing the sequence data in the cache memory based on the presence or absence of reusability of the sequence data extracted by the extraction unit and the sector division ratio;
In the loop in which the sector number is determined by the determination unit, an insertion unit that inserts an instruction control statement based on the determined sector number and a sector division ratio specified by the creator into the source program;
A file generation unit that generates an object file from a source program in which the instruction control statement is inserted by the insertion unit;
A compiler apparatus comprising:

(Additional remark 10) The said determination part is a sector division ratio designated by the said creator divided | segmented within the range corresponding to the capacity | capacitance of the said cache memory, or from the range corresponding to the capacity | capacitance of the said cache memory. The compiler apparatus according to appendix 9, wherein the sector number is determined after determining whether the sector is divided within a large range.

DESCRIPTION OF SYMBOLS 10 Compiler apparatus 11 Source program input part 12 Object file output part 13 Communication part 14 Input / output control I / F part 20 Storage part 21 Source program storage part 22 Source analysis result storage part 23 Arche data storage part 24 Optimization result storage part 30 Processing unit 31 Source analysis unit 32 Optimization unit 33 File generation unit 40 Information processing device

Claims (7)

By analyzing a source program executed by an information processing device equipped with a cache memory with a sector function, a data set, which is a set of data arrays processed in each loop of the source program, is reproduced at the time of loop processing execution. The presence / absence of usability is determined, and the sector division ratio in the cache memory and the data set are stored from the capacity required to store the data set for which the reusability is determined and the capacity of the cache memory. A determination procedure for determining a sector number for identifying a sector;
An insertion procedure for inserting an instruction control statement based on the sector division ratio and the sector number into the source program in the loop in which the sector division ratio and the sector number are determined by the determination procedure;
A file generation procedure for generating an object file from the source program in which the instruction control statement is inserted by the insertion procedure;
A compiler program characterized by causing a computer to execute.   The determination procedure is a sum of a capacity required to store a data set of a data array determined to be reusable and a capacity required to store a data set other than the data array determined to be reusable. 2. The compiler program according to claim 1, wherein the sector division ratio and the sector number are determined so as to be a capacity of the cache memory.   In the determination procedure, when there is a data set determined as non-reusable stream data in a loop where there is no reusable data array, the data set determined as non-reusable stream data The sum of the capacity required to store the data and the capacity required to store the data set other than the data array determined as the non-reusable stream data is larger than the capacity of the cache memory. The compiler program according to claim 2, wherein a division ratio and the sector number are determined. An acceptance procedure for accepting a source program in which a sector division ratio when storing in a cache memory with a sector function is specified in a loop by the creator;
An extraction procedure for extracting array data used in a loop in which the sector division ratio is designated by the creator in the source program from the source program accepted by the acceptance procedure;
A determination procedure for determining a sector number when storing the array data in the cache memory based on the presence or absence of reusability of the array data extracted by the extraction procedure and the sector division ratio;
In the loop in which the sector number is determined by the determination procedure, an insertion procedure for inserting an instruction control statement based on the determined sector number and a sector division ratio designated by the creator into the source program;
A file generation procedure for generating an object file from the source program in which the instruction control statement is inserted by the insertion procedure;
A compiler program characterized by causing a computer to execute.   In the determination procedure, the sector division ratio specified by the creator is divided within a range corresponding to the capacity of the cache memory, or within a range larger than the range corresponding to the capacity of the cache memory. The compiler program according to claim 4, wherein the sector number is determined after determining whether the data is divided. By analyzing a source program executed by an information processing device equipped with a cache memory with a sector function, a data set, which is a set of data arrays processed in each loop of the source program, is reproduced at the time of loop processing execution. The presence / absence of usability is determined, and the sector division ratio in the cache memory and the data set are stored from the capacity required to store the data set for which the reusability is determined and the capacity of the cache memory. A determination unit for determining a sector number for identifying the sector;
An insertion unit for inserting an instruction control statement based on the sector division ratio and the sector number into the source program in a loop in which the sector division ratio and the sector number are determined by the determination unit;
A file generation unit that generates an object file from a source program in which the instruction control statement is inserted by the insertion unit;
A compiler apparatus comprising: A receiving unit for receiving a source program in which a sector division ratio when storing in a cache memory with a sector function is designated in a loop by the creator;
An extraction unit that extracts array data used in a loop in which the sector division ratio is specified by the creator in the source program from the source program received by the reception unit;
A determination unit for determining a sector number when storing the sequence data in the cache memory based on the presence or absence of reusability of the sequence data extracted by the extraction unit and the sector division ratio;
In the loop in which the sector number is determined by the determination unit, an insertion unit that inserts an instruction control statement based on the determined sector number and a sector division ratio specified by the creator into the source program;
A file generation unit that generates an object file from a source program in which the instruction control statement is inserted by the insertion unit;
A compiler apparatus comprising:

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