JP2010244204A - Compiler program and compiler device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve execution performance of a program by effectively using a cache. <P>SOLUTION: A loop structure analysis part 31, an arrangement analysis part 32, and an access pattern analysis part 33 analyze context of each loop of a source program, arrangement data used in each loop, and an access pattern of the data. A dependency relation analysis part 34 analyzes dependency relation of the data processed in back-and-forth loops from the access pattern. A partial cache instruction part 35 performs determination such that a storage destination of the data processed in the preceding loop is allocated to one of a memory and the cache based on the dependency relation. An optimization part 36 generates a new source program wherein the preceding loop determined with the storage destination is replaced with a loop of cache use and a loop of a block store instruction. An object file generation part 37 generates an object file from the new source program. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a compiler program and a compiler apparatus.

  Traditionally, in business systems built between grid computing and companies, application programs generated by compilers from source programs are used for scientific computation and business by running on systems with various hardware configurations. Yes. Here, it is required to execute processing at high speed for an application program used for scientific computation or business.

  As a method for improving the processing speed, generally, a small-capacity cache capable of high-speed access is arranged between a CPU (Central Processing Unit) and a memory, and data stored in the cache is used. Has been done.

  However, in recent years, the data to be processed by the application program is increasing in the case of a large amount of data that does not fit in the cache size, for example, stream data for moving image distribution or the like. For this reason, even when data is stored on the cache, the probability of a cache hit when accessing the CPU is very low.

  Here, the cache status when the CPU repeatedly accesses the stream data in accordance with the program will be described with reference to FIG. FIG. 26 is a diagram for explaining the cache status when the stream data is repeatedly accessed.

  For example, the CPU sequentially reads stream data from the memory to a register according to a program, executes predetermined processing, stores the processed stream data in a cache, and then stores the data in the memory. In this case, as shown in FIG. 26A, the CPU stores the stream data 1 after processing in the cache and then stores it in the memory. Further, the CPU sequentially stores the stream data 2 to stream data n after processing. , Store in memory after overwriting the cache.

  However, when the CPU executes loading of stream data in the next process according to the program, the data stored in the cache is the last part of the previous process as shown in FIG. (Stream data n). Therefore, when the CPU first loads the stream data 1 in the next process, a cache miss occurs as shown in FIG.

  In this way, when the data size to be processed by the program, such as stream data, does not fit within the cache size, a cache hit cannot be expected when data is re-accessed, and the reusability of data using the cache is low. As a result, the execution performance of the program is degraded.

  For this reason, as one of solutions for improving the execution performance of the program, there is a method using a prefetch instruction (see, for example, Patent Documents 1 and 2). Specifically, the data used for processing is prefetched and a prefetch instruction is inserted into the source program, so that the data used for processing is stored in the cache in advance from the memory to reduce cache misses.

  However, in continuous data such as stream data, it is difficult to accurately retrieve data to be reused into a cache with a prefetch instruction. For this reason, as another method for improving the execution performance of the program, there is a method using a block store instruction.

  As shown in FIG. 27, the block store instruction reduces the transfer time by directly writing data (stream data 1, stream data 2,..., Stream data n) to the memory without saving in the cache. This is a method for improving the execution performance of a program. By using the block store instruction, the execution performance of the program can be improved without executing a complicated calculation such as inserting a prefetch instruction into the program. FIG. 27 is a diagram for explaining a block store instruction.

JP-A-10-283192 JP 2006-330813 A

  However, the above-described conventional technique has a problem that the execution performance of the program may be deteriorated because the cache cannot be used effectively. For example, when all store instructions for stream data are replaced with block store instructions by the above-described conventional technique, the CPU cannot use the cache at the time of executing the load instruction, and as a result, the load execution performance is improved. It drops significantly. In particular, when a program repeatedly executes update processing on stream data, the execution performance of the program is degraded if the cache cannot be utilized by using a block store instruction.

  In the above description, it has been described that there is a problem that the execution performance of the program may be deteriorated because the cache cannot be effectively used when the stream data is a processing target. However, if large-capacity continuous data that does not fit in the size of the cache is a processing target, there is a similar problem even if the conventional technique described above is used.

  Accordingly, the disclosed technique has been made to solve the above-described problems of the prior art, and a compiler program and a compiler apparatus that can improve the execution performance of a program by effectively using a cache. The purpose is to provide.

In order to solve the above-described problems and achieve the object, this program includes an access pattern analysis procedure for analyzing an access pattern to data of each loop in the source program,
From the access pattern analyzed by the access pattern analysis procedure, a dependency analysis procedure for analyzing a dependency relationship between data processed in the current loop and data processed in the next loop is analyzed by the dependency analysis procedure. Based on the dependency, a storage destination determination procedure for allocating a storage destination of data processed in the current loop to either a memory or a cache, and a storage destination is determined by the storage destination determination procedure A new source that generates a new source program from the source program by replacing the current loop with a first loop for storing processed data in the memory and a second loop for storing processed data in the cache Program generation procedure and the new source program And an object file generation step of generating object files from the new source program generated by the formation procedures, and the requirements that cause a computer to execute the.

  According to the disclosed program, it is possible to improve the execution performance of the program by effectively using the cache.

FIG. 1 is a diagram for explaining the concept of processing by the compiler apparatus in this embodiment. FIG. 2 is a block diagram showing the configuration of the compiler apparatus in this embodiment. FIG. 3 is a diagram for explaining the loop structure analysis unit. FIG. 4 is a diagram for explaining the loop data storage unit. FIG. 5 is a flowchart for explaining processing by the loop structure analysis unit. FIG. 6 is a diagram for explaining types of loops. FIG. 7 is a diagram for explaining the sequence analysis unit. FIG. 8 is a diagram for explaining the loop data storage unit and the sequence data storage unit after processing by the sequence analysis unit. FIG. 9 is a flowchart for explaining processing by the sequence analysis unit. FIG. 10 is a diagram for explaining the access pattern analysis unit. FIG. 11 is a diagram for explaining the array data storage unit after processing by the access pattern analysis unit. FIG. 12 is a flowchart for explaining processing by the access pattern analysis unit. FIG. 13 is a diagram for explaining the dependency analysis unit. FIG. 14 is a diagram for explaining the array data storage unit after processing by the dependency analysis unit. FIG. 15 is a flowchart for explaining the directionality determination processing by the dependency relationship analysis unit. FIG. 16 is a diagram for explaining the hardware information storage unit. FIG. 17 is a flowchart for explaining processing by the partial cache instruction unit. FIG. 18 is a diagram for explaining the outline of the loop deformation instruction for patterns 1 to 4. FIG. 19 is a diagram for explaining a loop deformation instruction of pattern 1. FIG. 20 is a diagram for explaining a loop deformation instruction for pattern 2. FIG. FIG. 21 is a diagram for explaining a loop deformation instruction of the pattern 3. FIG. 22 is a diagram for explaining a loop deformation instruction of the pattern 4. FIG. 23 is a flowchart for explaining processing of the compiler apparatus according to this embodiment. FIG. 24 is a flowchart for explaining a modification of the processing by the partial cache instruction unit. FIG. 25 is a diagram illustrating a computer that executes the compiler program of this embodiment. FIG. 26 is a diagram for explaining a cache state when the stream data is repeatedly accessed. FIG. 27 is a diagram for explaining a block store instruction.

  Exemplary embodiments of a compiler program and a compiler apparatus disclosed in the present application will be described below in detail with reference to the accompanying drawings. In the following, a compiler apparatus that executes a compiler program disclosed in the present application will be described as an embodiment.

  First, the concept of processing by the compiler apparatus in this embodiment will be described. FIG. 1 is a diagram for explaining the concept of processing by the compiler apparatus in this embodiment.

  The compiler apparatus according to the present embodiment can effectively use the cache when the “following loop” loads the data stored by the “previous loop” during the processing of the loop unit described in the source program. to decide. Then, the compiler apparatus according to the present embodiment, at the end of the process executed in the “previous loop”, is requested for data (data to be loaded) requested at the head of the process executed in the “later loop”. Transform the "previous loop" to access and store in the cache. When a source program that has been subjected to the “previous loop” transformation process is executed, the data loaded at the head of the process executed in the “subsequent loop” is a cache hit.

  For example, as shown in FIG. 1A, the compiler apparatus according to the present embodiment processes the stream data 1 processed at the head of the “following loop” at the end of the “previous loop”, and The “previous loop” is modified so that only stream data 1 is stored in the cache. Further, for example, as shown in FIG. 1A, the compiler apparatus according to the present embodiment directly stores the stream data 2 to n other than the stream data 1 processed in the “previous loop” in the memory. The “previous loop” is modified to use the block store instruction to perform. As a result, as shown in FIG. 1A, the stream data 1 loaded at the beginning of the processing in the “later loop” becomes a cache hit.

  The above-described processing will be described more specifically using a specific example of the source program shown in FIG. When the source program as shown in FIG. 1B is executed, the data of the array a, the array b, and the array c are initialized in the loop X, the data of the array a is determined in the loop Y, and the loop Z The data of the array a is referred to. Here, assuming that the data of the array a, the array b, and the array c is stream data that does not fit in the cache, when the cache is used by a normal store instruction, the data of the array a is “a (n−cache size)”. To a (n) ". However, in the next loop Z to be executed, since the array a is loaded from the beginning of the data, the cache data cannot be used. On the other hand, when the block store instruction is used, the data of the array a is not stored in the cache, so that the cache cannot be used effectively.

  Therefore, the compiler apparatus in the present embodiment analyzes the dependency of the data access pattern between the loops before and after in the source program. For example, in the loop Z of the source program shown in FIG. It is determined that the data of the processed array a is referred to. Then, the compiler apparatus according to the present embodiment determines to partially use the cache between the loop Y and the loop Z as shown in FIG. The compiler apparatus according to the present embodiment transforms the loop Y into two loops, that is, a loop in which a cache store instruction is written and a loop in which a block store instruction is written.

  The compiler apparatus according to the present embodiment generates an object file after optimizing the loop-modified source program. As a result, in the information processing apparatus that executes the object file output from the compiler apparatus according to the present embodiment, access to the stream data is made efficient by using the cache effectively although it is partial, and the program Execution performance can be improved.

  Next, the configuration of the compiler apparatus in this embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the compiler apparatus in this embodiment.

  As shown in FIG. 2, the compiler apparatus 10 according to the present embodiment includes a source program input unit 11, an object file output unit 12, a communication unit 13, an input / output control I / F unit 14, a storage unit 20, And a processing unit 30. Further, the compiler apparatus 10 in this embodiment is connected to the information processing apparatus 40 as shown in FIG.

  The information processing device 40 is a device such as a PC (Personal computer) that executes the object file output from the compiler device 10. In the present embodiment, the case where the compiler apparatus 10 and the information processing apparatus 40 are independent apparatuses will be described. However, the present embodiment is not limited to this, and the compiler apparatus 10 is included in the information processing apparatus 40. It may be a case where it is incorporated.

  The source program input unit 11 receives a source program created by a programmer, and the object file output unit 12 outputs the object file generated by the processing unit 30 to the information processing apparatus 40. The communication unit 13 receives hardware information described later from the information processing apparatus 40.

  The communication unit 13 receives hardware information described later from the information processing apparatus 40.

  The input / output control I / F unit 14 controls data transfer among the source program input unit 11, the object file output unit 12 and the communication unit 13, and the storage unit 20 and the processing unit 30.

  The storage unit 20 stores the source program received by the source program input unit 11 and various processing results by the processing unit 30 described later. Here, the storage unit 20 is particularly closely related to the present embodiment, and as shown in FIG. 2, a source program storage unit 21, a loop data storage unit 22, an array data storage unit 23, a hardware An information storage unit 24 and a new source program storage unit 25 are included.

  The source program storage unit 21 stores the source program received by the source program input unit 11. For example, the source program storage unit 21 stores a source program as shown in FIG.

  The loop data storage unit 22, the array data storage unit 23, the hardware information storage unit 24, and the new source program storage unit 25 will be described in detail when the processing unit 30 is described.

  The processing unit 30 executes various processes when the source program transferred from the input / output control I / F unit 14 is stored in the source program storage unit 21. Here, the processing unit 30 is particularly closely related to the present embodiment, and as shown in FIG. 2, a loop structure analysis unit 31, a sequence analysis unit 32, an access pattern analysis unit 33, and a dependency relationship analysis. Unit 34 and a partial cache instruction unit 35. Further, the processing unit 30 has an optimization unit 36 and an object file generation unit 37 as shown in FIG. 2 as being particularly closely related to the present embodiment. The loop structure analysis unit 31, the sequence analysis unit 32, the access pattern analysis unit 33, the dependency relationship analysis unit 34, and the partial cache instruction unit 35 are processing units that execute the analysis processing of the source program in a distributed manner.

  The loop structure analysis unit 31 analyzes the loop structure in the source program stored in the source program storage unit 21. Specifically, the loop structure analysis unit 31 extracts a DO loop, a FOR loop, and the like in the source program, and analyzes a rough flow of processing between the extracted loops. Here, when the extracted loop is a multiple loop, the loop structure analysis unit 31 performs a subsequent process on the innermost loop (the innermost loop) among the loops in which the operation of the data array is described. The loop that is the target of (the target loop). The processing in the case of multiple loops will be described in detail later.

  For example, the loop structure analysis unit 31 analyzes the source program shown in FIG. 1B, and “loop X (do j)”, “loop Y (do j)”, and “loop Z” that are the innermost loops. (Do j) "is extracted. Then, as shown in FIG. 3, the loop structure analysis unit 31 changes the source program shown in FIG. 1B from “loop X” to “loop Y”, from “loop Y” to “loop Z”. Analyze the loop structure as the process proceeds. FIG. 3 is a diagram for explaining the loop structure analysis unit.

  Then, the loop structure analysis unit 31 performs initial setting of loop data stored in the loop data storage unit 22 based on the analysis result. For example, as shown in FIG. 4, the loop structure analysis unit 31 initializes loop data of “loop X”, “loop Y”, and “loop Z”. FIG. 4 is a diagram for explaining the loop data storage unit.

  That is, as shown in FIG. 4, the loop structure analyzing unit 31 stores three pieces of loop data “loop name: X”, “loop name: Y”, and “loop name: Z” in the loop data storage unit 22. Initial setting. Here, items of “prev” and “next” indicating the flow of processing between loops are prepared as the analysis result of the loop structure analysis unit 31 in the loop data. By setting the items “prev” and “next”, each loop data stores information about the chain between loops.

  For example, “prev: NULL” is stored in the loop data of “loop name: X” because there is no loop executed before “loop X”. The loop data “loop name: X” stores “next: * Y” because the loop executed after “loop X” is “loop Y”.

  Further, “prev: * X” and “next: * Z” are stored in the loop data of “loop name: Y”, and “prev: * Y” and “prev: * Y” are stored in the loop data of “loop name: Z”. “Next: NULL” is stored.

  In the loop data, the data stored in the “array data” shown in FIG. 4 is determined by the processing described later, and therefore all of the data is “NULL” at the time of initial setting by the loop structure analysis unit 31.

  Here, a detailed processing procedure by the loop structure analysis unit 31 will be described with reference to FIGS. 5 and 6. FIG. 5 is a flowchart for explaining processing by the loop structure analysis unit, and FIG. 6 is a diagram for explaining types of loops.

  As shown in FIG. 5, when the source program is input (Yes at Step S101), the loop structure analyzing unit 31 reads the source program from the source program storage unit 21 and searches for an outer loop in the function (Step S102). ). That is, the loop structure analysis unit 31 searches the source program for a loop in the scope immediately below the function in the source program.

  Then, the loop structure analysis unit 31 analyzes whether or not the searched outer loop is a multiple loop (step S103). The loop structure analysis unit 31 processes the searched outer loops in the order of appearance in the source program.

  Here, when the searched outer loop is not a multiple loop (No at Step S103), the loop structure analysis unit 31 includes the searched loop (outer loop) in the target loop (Step S104), and creates loop data (Step S104). Step S107). Specifically, the loop structure analysis unit 31 creates loop data in which the loop name of the target loop is set.

  On the other hand, when the searched outer loop is a multiple loop (Yes at Step S103), the loop structure analysis unit 31 analyzes whether the multiple loop is a title loop (Step S105).

  Here, a title loop (a title loop) is a loop in which no processing is performed between the loops. For example, the outer loop “loop X” shown on the left side of FIG. 6A is a multiple loop including “loop Y” that executes “A = A + B”, but “loop X” and “loop Y” Since there is no processing executed between the two, it becomes a tight loop. On the other hand, the outer loop “loop X” shown on the right side of FIG. 6A is a multiple loop including “loop Y” for executing “A = A + B”, but “C = C + D” in “loop X”. Since this process is executed, the loop is not a title.

  Returning to FIG. 5, if the searched outer loop is a multiple loop, but is not a title loop (No in step S <b> 105), the loop structure analyzing unit 31 determines that the searched outer loop is not subject to subsequent processing. It is determined whether or not all the outer loops have been processed (step S108). For example, “loop X” shown on the right side of FIG. 6B is excluded.

  On the other hand, if the searched outer loop is a multiple loop and is a title loop (Yes in step S105), the loop structure analyzing unit 31 includes the innermost loop of the title loop in the target loop (step S106). Data creation is executed (step S107). Then, the loop structure analyzing unit 31 determines whether or not all the searched outer loops have been processed (step S108).

  For example, in the outer “loop X” shown on the left side of FIG. 6A, “loop Y” is the target loop. When the loop in the title loop is a sibling loop, there are a plurality of target loops. For example, as shown on the left side of FIG. 6B, “Loop A” and “Loop B” in the same hierarchy are sibling loops, and the loop structure analysis unit 31 performs “Loop A” and “Loop B”. Is the target loop. On the other hand, as shown on the right side of FIG. 6B, “Loop A” and “Loop B” that are not in the same hierarchy are not sibling loops, and the loop structure analysis unit 31 is inside “Loop B”. Let “Loop A” be the target loop.

  Returning to FIG. 5, when there is an unprocessed outer loop (No at Step S <b> 108), the loop structure analyzing unit 31 returns to Step S <b> 103 and executes processing for the next outer loop.

  On the other hand, when all the searched outer loops have been processed (Yes at Step S108), the loop structure analyzing unit 31 ends the processing. The loop structure analysis unit 31 sets the loop names of the loops before and after “prev” and “next” of the loop data in accordance with the order in which the loop names of the target loop are set.

  Returning to FIG. 2, the sequence analysis unit 32 reanalyzes the target loop set in the loop data as a result of the analysis by the loop structure analysis unit 31, and the sequence of data used in the target loop (hereinafter referred to as sequence and sequence). List).

  For example, the sequence analysis unit 32 analyzes the source program shown in FIG. 1B, and as shown in FIG. 7, the sequences used in “loop X” are “array a, array b, array c”. The three sequences are listed. Further, the sequence analysis unit 32 analyzes the source program shown in FIG. 1B, and as shown in FIG. 7, the sequences used in the “loop Y” are “array a, array b, array c”. The three sequences are listed. Further, the sequence analysis unit 32 analyzes the source program shown in FIG. 1B, and as shown in FIG. 7, the sequence used in “loop Z” is one sequence of “array a”. Are listed. FIG. 7 is a diagram for explaining the sequence analysis unit.

  Then, the sequence analysis unit 32 sets the analysis result as loop data in the loop data storage unit 22 and initializes the sequence data in the sequence data storage unit 23.

  For example, as illustrated in FIG. 8, the sequence analysis unit 32 displays “array [3] indicating that the number of sequences used for the item“ sequence data ”in the loop data“ loop name: loop X ”is three. ] ”. Similarly, as shown in FIG. 8, the sequence analysis unit 32 sets “array [3]” to the item “array data” in the loop data of “loop name: loop Y”, and “loop name: loop Z”. “Array [1]” is set in the item “array data” in the loop data of. FIG. 8 is a diagram for explaining the loop data storage unit and the array data storage unit after processing by the sequence analysis unit.

  Further, as shown in FIG. 8, the sequence analysis unit 32 is linked to the loop data of “loop name: X”, and an array whose “array name” is “a”, “b”, “c” ”. Initialize the data. Similarly, as shown in FIG. 8, the sequence analysis unit 32 is linked to the loop data “loop name: Y”, and the “array name” is composed of “a”, “b”, and “c”. Array data is initialized, and array data whose “array name” is “a” is linked to the loop data of “loop name: loop Z”.

  As shown in FIG. 8, the array data includes items including “initial value”, “final value”, and “increment value”. Since the items of “initial value”, “final value”, and “increment value” are set by processing of the access pattern analysis unit 33 described later, all of the items “NULL” are set when the array data is initially set by the sequence analysis unit 32. Is set.

  Here, a detailed processing procedure by the sequence analysis unit 32 will be described with reference to FIG. FIG. 9 is a flowchart for explaining processing by the sequence analysis unit.

  As illustrated in FIG. 9, when the target loop is extracted by the loop structure analysis unit 31 (Yes in step S201), the sequence analysis unit 32 starts the sequence data setting process from the sequence name described in the target loop. (Step S202). That is, the sequence analysis unit 32 starts the following process for each extracted target loop.

  Then, the array analysis unit 32 extracts a variable name used for the first dimension subscript of the array (step S203), and determines whether or not the extracted variable name variable is a control variable of the target loop. (Step S204). For example, in the source program shown in FIG. 1B, the sequence analysis unit 32 makes “variable name: j” appear as a control variable of “array a” in “loop X (do j)” that is the target loop. It is determined whether or not to do.

  Here, when the variable is not a control variable of the target loop (No at Step S204), the array analysis unit 32 deletes the target loop from the chain of loop data (Step S206).

  On the other hand, if the variable is a control variable of the target loop (Yes at Step S204), the array analysis unit 32 sets array data linked to the loop data (Step 205). For example, in the source program shown in FIG. 1B, the sequence analysis unit 32 sets “variable name: j” as a control variable of “array a to c” in “loop X (do j)” that is a target loop. Is determined to appear. As a result, the sequence analysis unit 32 initializes sequence data whose “sequence name” is “a”, “b”, “c” in a chain with the loop data of “loop name: loop X”. .

  After the processing of step S205 and step S206, the sequence analysis unit 32 determines whether all the target loops have been processed (step S207).

  If there is an unprocessed target loop (No at Step S207), the sequence analysis unit 32 returns to Step S202 and starts processing for the next target loop.

  On the other hand, the arrangement | sequence analysis part 32 complete | finishes a process, when all the object loops are processed (step S207 affirmation).

  Returning to FIG. 2, the access pattern analysis unit 33 analyzes the access pattern of data in the array of the target loop in which the array data is set. For example, the access pattern analysis unit 33 determines the access pattern of “array a” in “loop X (do j)” of the source program shown in FIG. 1B in which the array data of “array name: a” is set. To analyze.

  Then, as shown in FIG. 10, the access pattern analysis unit 33 is a pattern in which the control variable “j” of “array a” in “loop X” is incremented by 1 from “1” to “n”. And analyze. Similarly, the access pattern analysis unit 33 controls “array b, c” in “loop X”, “array a, b, c” in “loop Y”, and “array a” in “loop Z”. Each variable “j” is analyzed to be a pattern that changes from “1” to “n” by one increment. FIG. 10 is a diagram for explaining the access pattern analysis unit.

  Then, as shown in FIG. 11A, for example, the access pattern analysis unit 33 links the array data stored in the array data storage unit 23 with the loop data “loop name: loop X”. “Initial value: 1”, “End value: n”, and “Increment value: 1” are set. FIG. 11 is a diagram for explaining the array data storage unit after the processing by the access pattern analysis unit.

  In order to cope with the case where the regions are the same even if the array names are different, the access pattern analysis unit 33 stores an address conversion table in the array data storage unit 23 separately from the array data. The access pattern analysis unit 33 acquires an address on a memory for specifying an area by analyzing the source program. Thereby, the access pattern analysis unit 33, for example, as shown in FIG. 11B, the address of “array name: a” is “0xaaaaaaa” and the address of “array name: b” is “0xbbbbbbb”. And that the address of “array name: c” is “0xcccccccc”. Then, the access pattern analysis unit 33 stores the acquired address in the array data storage unit 23 as an address conversion table associated with the array name. When the address is not acquired, the access pattern analysis unit 33 stores “address: NULL” in the address conversion table in association with the array name.

  When there are a plurality of data access patterns for the same sequence in the target loop, the access pattern analysis unit 33 sets the sequence data having the same sequence name for each access pattern. For example, for a “sequence name: a” in a loop, a pattern in which the control variable is incremented by 1 from “1” to “n” and the control variable is decremented by 1 from “n” to “1”. , And a pattern in which the control variable is changed by incrementing from “2” to “n” by one. In this case, as shown in FIG. 11C, the access pattern analysis unit 33 uses “initial value: 1, final value: n, incremental value: 1”, “initial value: n” in “array name: a”. , Final value: 1, incremental value: −1 ”and“ initial value: 2, final value: n, incremental value: 1 ”are set.

  Here, a detailed processing procedure by the access pattern analysis unit 33 will be described with reference to FIG. FIG. 12 is a flowchart for explaining processing by the access pattern analysis unit.

  As shown in FIG. 12, when the sequence data is set by the sequence analysis unit 32 (Yes in step S301), the access pattern analysis unit 33 starts processing for each sequence data.

  First, the access pattern analysis unit 33 acquires an address from the array name, and constructs an address conversion table in the array data storage unit 23 (step S302).

  Then, the access pattern analysis unit 33 acquires the initial value, final value, and increment value of the control variable for each array, and updates the array data (step S303). If there are a plurality of data access patterns for the same array in the target loop, the access pattern analysis unit 33 sets and updates the array data having the same array name for each access pattern.

  After that, the access pattern analysis unit 33 determines whether or not all the sequence data set by the sequence analysis unit 32 has been updated (step S304).

  If there is unprocessed array data (No at Step S304), the access pattern analysis unit 33 returns to Step S302 and starts processing for the next array data.

  On the other hand, when all the array data has been updated (Yes at Step S304), the access pattern analysis unit 33 ends the process.

  Returning to FIG. 2, the dependency relationship analysis unit 34 analyzes the dependency relationship in the data of the array processed between the preceding and succeeding loops from the data access pattern in the sequence of the target loop analyzed by the access pattern analysis unit 33. For example, the access pattern analysis unit 33 analyzes the dependency relationship between the loops in the “array a” of the source program shown in FIG.

  That is, as shown in FIG. 13A, the dependency relationship analysis unit 34, between the loop X and the loop Y, the data of the “array a” processed in the order of 1 to n in the loop X, It is analyzed that the dependency is processed in the order of 1 to n in the loop Y. Further, as shown in FIG. 13A, the dependency relationship analysis unit 34 stores the data of the “array a” processed in the order of 1 to n in the loop Y between the loop Y and the loop Z. It is analyzed that the dependency is processed in the order of 1 to n in the loop Z. FIG. 13 is a diagram for explaining the dependency relationship analysis unit.

  Specifically, the dependency relationship analysis unit 34 refers to the loop data set in each of the preceding and following loops, the array data linked to the loop data, and the address conversion table, and the loops in the data of the same array Analyze the dependency between them.

  For example, as shown in FIG. 13B, the dependency relationship analysis unit 34 links the loop data “loop name: X” and “loop name: Y” with the loop data “loop name: X”. The array data of “array name: a” that is linked with the array data of “array name: a” and the loop data of “loop name: Y” and the address conversion table are read. Then, as shown in FIG. 13B, the dependency relationship analysis unit 34 refers to the address conversion table to determine sequence matching from the addresses, and then compares the sequence data.

  At this time, the dependency relationship analysis unit 34 refers to the increment value of each array data, determines that the access direction is “+”, and increments the loop X and the loop as shown in FIG. It is analyzed that the access direction of Y is a forward direction that matches. Then, as shown in FIG. 13B, the dependency relationship analysis unit 34 newly adds “next loop: forward direction” to the array data of “array a” linked to the loop data of “loop name: X”. Set.

  By the processing described with reference to FIG. 13B, the dependency relationship analysis unit 34 newly adds an item “next loop” to the array data of “array a” linked to the loop data of loops X, Y, and Z. Set. For example, as shown in FIG. 14, the dependency relationship analysis unit 34 sets “next loop: forward direction” to the array data of “array a” that is linked to the loop data of loop X, and is linked to the loop data of loop Y. “Next loop: forward direction” is set in the array data of “array a”. Further, as illustrated in FIG. 14, the dependency relationship analysis unit 34 sets “next loop: none” to the array data of “array a” linked to the loop data of the loop Z. FIG. 14 is a diagram for explaining the array data storage unit after the processing by the dependency analysis unit.

  In addition, when there are a plurality of sequence data for the same sequence because there are a plurality of access patterns, the dependency relationship analysis unit 34 searches for and compares the same access pattern, and forward or reverse Determine the directionality of the direction. As for the initial value, the closing price, and the increment value, even if they are variables, the sameness can be ensured in order to compare by the address of the variable.

  Here, the detailed procedure for determining the directionality by the dependency relationship analysis unit 34 will be described with reference to FIG. FIG. 15 is a flowchart for explaining the directionality determination processing by the dependency relationship analysis unit.

  As shown in FIG. 15, when the initial value, the final value, and the increment value are updated in all the array data by the access pattern analyzing unit 33 (Yes in step S401), the dependency relationship analyzing unit 34 The reverse value is initialized (step S402). At this time, the dependency analysis unit 34 extracts sequence data linked to loop data of a loop to be processed (hereinafter referred to as a self loop) from the sequence data storage unit 23, and then forwards and reverses the counter. The value of is initialized.

  Then, the dependency relationship analysis unit 34 determines whether or not there is the same sequence name in the sequence data linked to the next loop that is the loop next to the own loop (step S403).

  If the next loop has the same sequence name (Yes at step S403), the dependency analysis unit 34 determines whether or not the access direction of the sequence data having the same sequence name in the next loop is the forward direction ( Step S404). Note that the processing after step S404 is sequentially executed for each array data having the same array name.

  If the current direction is the forward direction (Yes at Step S404) and the initial value of the own loop and the initial value of the next loop are the same (Yes at Step S405), the dependency relationship analysis unit 34 increments the value of the forward direction counter ( Step S406).

  In the reverse direction (No at Step S404), if the initial value of the own loop and the initial value of the next loop are the same (Yes at Step S407), the dependency relationship analysis unit 34 increments the value of the reverse direction counter. (Step S408).

  Here, when “the forward direction (Yes at Step S404) and the initial value of the own loop and the initial value of the next loop are different (No at Step S405)”, the dependency relationship analysis unit 34 returns to Step S403 and proceeds to the next. It is determined whether there is unprocessed sequence data having the same sequence name in the loop.

  Also, the dependency relationship analysis unit 34 returns to step S403 and returns to the next step when “in the reverse direction (No at Step S404) and the initial value of the own loop and the initial value of the next loop are different (No at Step S407)”. It is determined whether there is unprocessed sequence data having the same sequence name in the loop.

  Also, the dependency relationship analysis unit 34 returns to step S403 even when the processing of step S406 is completed and when the processing of step S408 is completed, and the unprocessed sequence data of the same sequence name is stored in the next loop. It is determined whether or not there is.

  On the other hand, when there is no unprocessed array data with the same array name in the next loop (No in step S403), the dependency relationship analysis unit 34 determines whether or not both the forward and backward counter values are “0”. Determination is made (step S409).

  When both the forward and backward counter values are “0” (Yes at Step S409), the dependency analysis unit 34 updates the item of the next loop in the array data as “None” (Step S410), and performs processing. Exit.

  If one of the forward and backward counter values is not “0” (No in step S409), it is determined whether or not the forward counter value is greater than or equal to the backward value (step S409). S411).

  If the value of the forward counter is greater than or equal to the backward value (Yes at Step S411), the dependency relationship analysis unit 34 updates the item of the next loop in the array data as “Forward” (Step S412). ), The process is terminated.

  On the other hand, if the value of the forward counter is less than the value in the reverse direction (No in step S411), the dependency analysis unit 34 updates the item of the next loop in the array data as “reverse direction” (step S413). The process is terminated.

  Returning to FIG. 2, the hardware information storage unit 24 stores the hardware information of the information processing apparatus 40 received by the communication unit 13. Here, the hardware information is stored in the hardware information storage unit 24 by the communication unit 13 inquiring of the OS of the information processing apparatus 40 as an extension of the initialization process when the compiler apparatus 10 is activated.

  For example, as illustrated in FIG. 16, the hardware information storage unit 24 stores hardware information in which the capacity (cache size) of the cache installed in the information processing apparatus 40 is “cache”. FIG. 16 is a diagram for explaining the hardware information storage unit.

  Further, as shown in FIG. 16, the hardware information storage unit 24 indicates “possible” or “impossible” as information as to whether or not the CPU of the information processing apparatus 40 can execute backward hardware prefetch. Hardware information is stored. Note that backward hardware prefetching is a function that allows data access in the direction of subtracting addresses in hardware prefetching.

  Returning to FIG. 2, the partial cache instruction unit 35 determines, based on the dependency analysis result by the dependency analysis unit 34, to allocate the storage destination of the data processed in its own loop to either the memory or the cache. That is, the partial cache instruction unit 35 instructs the optimization unit 36 to be described later to transform the loop into an access pattern considering the cache size from the analysis result of the dependency relationship. Specifically, the partial cache instruction unit 35 determines a shape to be deformed based on the direction of the next loop, the cache size, and the presence / absence of the backward hardware prefetch function.

  Here, the partial cache instruction unit 35 will be described in detail with reference to FIGS. FIG. 17 is a flowchart for explaining the processing by the partial cache instruction unit, and FIG. 18 is a diagram for explaining the outline of the loop modification instructions for patterns 1 to 4. FIG. 19 is a diagram for explaining a loop deformation instruction for pattern 1, and FIG. 20 is a diagram for explaining a loop deformation instruction for pattern 2. FIG. 21 is a diagram for explaining a loop deformation instruction for pattern 3, and FIG. 22 is a diagram for explaining a loop deformation instruction for pattern 4.

  As shown in FIG. 17, when the dependency relationship (item: next loop) of the array data is updated (Yes at step S501), the partial cache instruction unit 35 determines that the next loop updated with the array data to be processed. It is determined whether or not the directionality is forward (step S502).

  If the direction of the next loop is the forward direction (Yes at Step S502), the partial cache instruction unit 35 refers to the hardware information and determines whether or not the information processing apparatus 40 can perform the backward hardware prefetch processing. Determination is made (step S503).

  If the backward hardware prefetch process is possible (Yes at Step S503), the partial cache instruction unit 35 instructs the optimization unit 36 to perform the loop deformation process for Pattern 1 (Step S504), and the process is terminated.

  If the backward hardware prefetch process is not possible (No at Step S503), the partial cache instruction unit 35 instructs the optimization unit 36 to perform the loop transformation process for Pattern 2 (Step S505), and ends the process.

  On the other hand, when the directionality of the next loop is the reverse direction (No in step S502), the partial cache instruction unit 35 refers to the hardware information and determines whether or not the information processing apparatus 40 can perform the reverse direction hardware prefetch process. Is determined (step S506).

  If the backward hardware prefetch process is possible (Yes at Step S506), the partial cache instruction unit 35 instructs the optimization unit 36 to perform the loop deformation process of Pattern 3 (Step S507), and ends the process.

  If the backward hardware prefetch process is not possible (No at Step S506), the partial cache instruction unit 35 instructs the optimization unit 36 to perform the loop deformation process of Pattern 4 (Step S508), and ends the process.

  The outline of the loop deformation instructions for patterns 1 to 4 will be described with reference to FIG. In FIG. 18, “A” is an initial value of the loop to be deformed, and “B” is a value obtained by adding a value corresponding to the cache size (cash) to the initial value of the loop to be deformed. In FIG. 18, “C” is a value obtained by subtracting a value corresponding to the cache size (cash) from the closing price of the loop to be deformed, and “D” is the closing price of the loop to be deformed. In FIG. 18, “new loop for executing cache use” created in the loop to be transformed is described as “another loop”.

  In the loop modification instruction of pattern 1 that is executed when the next loop is forward and backward hardware prefetch is possible, the creation position of another loop is set to “first” as shown in FIG. Specifically, in the loop modification instruction of pattern 1, the first half part corresponding to the cache size of the data processed in the modified loop is instructed to be processed by the cache use loop. In the loop deformation instruction of pattern 1, the initial value of another loop is “B”, the final value of another loop is “A”, and the reverse hardware prefetch function is provided. Becomes the “reverse direction”.

  A specific example of the loop deformation instruction for pattern 1 will be described with reference to FIG. When the input source program is described as shown on the left side of FIG. 19A, the directionality of the array a processed in the subsequent loop is the forward direction with respect to the previous loop. Here, when the data size of the array a does not fit in the cache size, as shown on the left side of FIG. 19B, the control variable of the data at the tail of the cache after the processing of the previous loop is “ej”. It is. That is, the data of the control variable “sj” processed at the head of the subsequent loop processing has fallen from the cache, and a cache miss occurs. Therefore, conventionally, a block store instruction is used as a cache unnecessary.

  Therefore, in the loop modification instruction of pattern 1, as shown on the right side of FIG. 19A, data corresponding to the cache size is used for cache at the head (first half part) of the previous loop, and one control variable is used. Create a new loop with subtraction (-1). Further, regarding the data in the latter half other than the former half corresponding to the cache size, the block store instruction is used in the previous loop.

  In addition, the partial cache instruction unit 35 instructs the block store loop to be executed before the new cache use loop.

  As a result, as shown on the right side of FIG. 19B, at the time of program execution, the data in the second half other than the first half corresponding to the cache size is first processed in the previous loop, and the cache is not used. Stored directly in memory. Then, the first half of the data corresponding to the cache size is processed and stored in the cache in a new reverse rotation loop. As a result, the initial value data processed by the previous loop is stored at the end of the cache, and a cache hit is reliably obtained in the subsequent loop. In addition, with respect to data not using the cache, the data can be loaded by directly accessing the memory, so that the processing speed is increased.

  Returning to FIG. 18, in the loop modification instruction for pattern 2 that is executed when the next loop is in the forward direction and the backward hardware prefetch is not possible, the creation position of another loop is “head” as in pattern 1. " That is, in the loop modification instruction of pattern 2, as in pattern 1, the first half corresponding to the cache size of the data processed in the loop to be modified is instructed to be processed by the cache use loop. In the loop modification instruction of pattern 2, the initial value of another loop is “A”, the final value of another loop is “B”, and there is no backward hardware prefetch function. Is the “forward direction”.

  A specific example of the pattern 2 loop deformation instruction will be described with reference to FIG. The source program shown on the left side of FIG. 20A is the same as the source program shown on the left side of FIG. Further, the left side of FIG. 20B shows that when the source program shown on the left side of FIG. 20A is executed, a cache miss occurs in a later loop when the cache is used. Since it is the same as the content demonstrated using the left side of 19 (B), description is abbreviate | omitted.

  Therefore, in the loop modification instruction of pattern 2 which is different from pattern 1 in that there is no backward hardware prefetch function, as shown on the right side of FIG. 20A, it corresponds to the cache size at the head (first half part) of the previous loop. A new loop is created that uses the data to be cached and increments the control variable by one. Further, regarding the data in the latter half other than the former half corresponding to the cache size, the block store instruction is used in the previous loop.

  Similarly to the pattern 1, the partial cache instruction unit 35 instructs the block store loop to be executed before the new cache use loop.

  As a result, as shown on the right side of FIG. 20B, at the time of program execution, the data in the second half other than the first half corresponding to the cache size is first processed in the previous loop, and the cache is not used. Stored directly in memory. Then, in the new forward rotation loop, the first half of the data corresponding to the cache size is processed and stored in the cache. As a result, even if the initial value data processed by the previous loop is first stored in the cache, it is prevented from falling out of the cache, and a cache hit is surely made in the subsequent loop. In addition, with respect to data not using the cache, the data can be loaded by directly accessing the memory, so that the processing speed is increased.

  Returning to FIG. 18, in the loop modification instruction of the pattern 3 executed when the next loop is in the reverse direction and the reverse direction hardware prefetch is possible, the creation position of another loop is “final”. Specifically, in the loop modification instruction of pattern 1, the second half part corresponding to the cache size of the data processed in the modified loop is instructed to be processed by the cache use loop. Also, in the loop deformation instruction of pattern 3, the initial value of another loop is “D”, the final value of another loop is “C”, and the reverse hardware prefetch function is provided. Becomes the “reverse direction”.

  A specific example of the pattern 3 loop deformation instruction will be described with reference to FIG. When the input source program is described as shown on the left side of FIG. 21A, the directionality of the array a processed in the rear loop is the reverse direction to that of the front loop. Here, when the data size of the array a does not fit in the cache size, as shown on the left side of FIG. 21B, the control variable of the data at the tail of the cache after the processing of the previous loop is “ej”. It is. That is, the data of the control variable “ej” processed at the beginning of the processing of the subsequent loop is a cache hit, but the data other than the latter half corresponding to the cache size of the data processed in the previous loop is cached. I can't expect a hit. Conventionally, a block store instruction is used as a cache unnecessary.

  Therefore, in the loop deformation instruction of pattern 3, as shown on the right side of FIG. 21A, the data corresponding to the cache size is used for the cache at the last (second half) of the previous loop, and one control variable is used. Create a new loop with subtraction (-1). In addition, regarding the data in the first half other than the second half corresponding to the cache size, the block store instruction is used in the previous loop.

  Similarly to the patterns 1 and 2, the partial cache instruction unit 35 instructs the block store loop to be executed before the new cache use loop.

  As a result, as shown on the right side of FIG. 21B, at the time of program execution, data in the first half other than the second half corresponding to the cache size is first processed in the previous loop, and the cache is not used. Stored directly in memory. Then, the second half of the data corresponding to the cache size is processed and stored in the cache in a new reverse rotation loop. As a result, the closing price data processed by the previous loop is stored at the end of the cache, and a cache hit is surely made in the subsequent loop. In addition, with respect to data not using the cache, the data can be loaded by directly accessing the memory, so that the processing speed is increased.

  Returning to FIG. 18, in the loop modification instruction for pattern 4 that is executed when the next loop is in the reverse direction and the reverse direction hardware prefetch is not possible, the creation position of another loop is “final” as in pattern 3. " That is, in the loop modification instruction for pattern 4, as in pattern 3, the latter half corresponding to the cache size of the data processed in the modified loop is instructed to be processed by the cache utilization loop. Also, in the loop deformation instruction of pattern 4, the initial value of another loop is “C”, the final value of another loop is “D”, and there is no backward hardware prefetch function. Is the “forward direction”.

  A specific example of the pattern 4 loop deformation instruction will be described with reference to FIG. Note that the source program shown on the left side of FIG. 22A is the same as the source program shown on the left side of FIG. Further, on the left side of FIG. 22B, as described on the left side of FIG. 21B, when the source program shown on the left side of FIG. This indicates that a cache hit cannot be expected for data other than the latter half corresponding to the cache size of the data processed in the previous loop.

  Therefore, in the loop modification instruction of pattern 4 which is different from pattern 3 in that there is no backward hardware prefetch function, as shown on the right side of FIG. 22A, it corresponds to the cache size at the last (second half) of the previous loop. A new loop is created that uses the data to be cached and increments the control variable by one. In addition, regarding the data in the first half other than the second half corresponding to the cache size, the block store instruction is used in the previous loop.

  Similarly to the patterns 1 to 3, the partial cache instruction unit 35 instructs the block store loop to be executed before the new cache use loop.

  As a result, as shown on the right side of FIG. 22B, at the time of program execution, data in the first half other than the second half corresponding to the cache size is first processed in the previous loop, and the cache is not used. Stored directly in memory. Then, in the new forward rotation loop, the latter half of the data corresponding to the cache size is processed and stored in the cache. As a result, even if the closing price data processed by the previous loop is first stored in the cache, it is prevented from falling out of the cache, and a cache hit is surely made in the subsequent loop. In addition, with respect to data not using the cache, the data can be loaded by directly accessing the memory, so that the processing speed is increased.

  Returning to FIG. 2, the optimization unit 36 generates a source program in which a new loop is inserted into the source program in accordance with the loop transformation instruction from the partial cache instruction unit 35. Then, the optimization unit 36 generates a new source program by executing a conventional optimization process such as software prefetch on the source program into which the new loop is inserted, and the generated new source program is converted into the new source program. Store in the storage unit 25.

  The object file generation unit 37 generates an object file from the new source program stored in the new source program storage unit 25, and outputs the generated object file to the object file output unit 12.

  Next, the flow of processing of the compiling device 10 in this embodiment will be described with reference to FIG. FIG. 23 is a flowchart for explaining the processing of the compiler apparatus according to this embodiment.

  As shown in FIG. 23, in the compiler apparatus 10 according to the present embodiment, when a source program is input from the source program input unit 11 (Yes in step S601), the loop structure analysis unit 31 extracts a target loop, and loop data Is set (step S602). The compiler apparatus 10 acquires hardware information from the information processing apparatus 40 when the own apparatus is activated.

  Then, the sequence analysis unit 32 analyzes the target loop and lists the sequence of data used in the target loop, thereby setting sequence data linked to the loop data (step S603).

  After that, the access pattern analysis unit 33 constructs an address conversion table and updates the initial value, final value, and increment value of the array data based on the set array data array name (step S604).

  Further, the dependency relationship analysis unit 34 refers to the set loop data, the sequence data linked to the loop data, and the address conversion table, and the dependency relationship of the sequence data having the same sequence name between the loops ( Next loop item) is updated (step S605).

  Then, the partial cache instruction unit 35 issues a loop modification instruction in accordance with the dependency of the array data, the cache size, and the backward hardware prefetch function (step S606).

  Thereafter, the optimization unit 36 inserts a new loop into the source program in accordance with the loop transformation instruction, performs optimization processing, and generates a new source program (step S607).

  Furthermore, the object file generation unit 37 generates an object file from the new source program (step S608), and ends the process.

  As described above, according to the present embodiment, the loop structure analysis unit 31, the sequence analysis unit 32, and the access pattern analysis unit 33 determine the context of each loop of the source program, the sequence and data used in each loop. The dependency analysis unit 34 analyzes the dependency between the data processed in the previous loop and the data processed in the next loop from the access pattern. Then, the partial cache instruction unit 35 determines to allocate the storage destination of the data processed in the previous loop to either the memory or the cache based on the dependency, and the optimization unit 36 determines the storage destination. A new source program is generated by replacing the previous loop with a loop using a cache and a loop of a block store instruction, and the object file generation unit 37 generates an object file from the new source program.

  Therefore, at the time of program execution, the data that should use the cache and the data that should be stored directly in the memory can be divided in the same loop, and the execution performance of the program is improved by using the cache effectively It becomes possible to do.

  In the present embodiment, the dependency relationship analysis unit 34 determines whether the order of data processed in the previous loop and the order in which processed data of the previous loop are processed in the next loop are forward as the dependency relationship. If the dependency relationship is forward, the partial cache instruction unit 35 determines that the first half portion corresponding to the cache capacity of the processed data of the previous loop is used as a cache, and the dependency relationship is In the reverse direction, the latter half of the processed data of the previous loop corresponding to the cache capacity is determined as cache usage.

  Therefore, when the program is executed, the data stored in the cache is surely a cache hit in the next loop, and the execution performance of the program can be further improved.

  Further, in this embodiment, the partial cache instruction unit 35 instructs the optimization unit 36 to insert a cache loop after the block store loop, so that the data stored in the cache is more reliable in the next loop. As a result, a cache hit occurs and the execution performance of the program can be further improved.

  In this embodiment, the partial cache instruction unit 35 instructs to reverse the data processing order in the cache use loop if the backward hardware prefetch process can be executed. If the backward hardware prefetch process cannot be executed, the partial cache instruction unit 35 instructs the data processing order in the cache use loop to be the same.

  Therefore, according to the function of the device that executes the program, it is possible to create a cache use loop in which the data stored in the cache reliably causes a cache hit in the next loop, and appropriately improve the execution performance of the program Is possible.

  In the above, when the loop transformation instruction sets the directionality of rotation in a new loop using cache according to the dependency relationship of array data, the cache size, and the backward hardware prefetch function. Explained. However, the present embodiment is not limited to this. For example, if it is desirable that the processing order be in the forward direction as in stream data such as moving images, the loop deformation instruction is executed based on different criteria. It may be the case. This will be described with reference to FIG. FIG. 24 is a flowchart for explaining a modification of the processing by the partial cache instruction unit.

  As shown in FIG. 24, the partial cache instruction unit 35 in the modification example needs to guarantee the sequential access pattern when the array data dependency is updated (Yes in step S701). It is determined whether or not (step S702).

  Here, when it is not necessary to guarantee the sequential access pattern (No at Step S702), the partial cache instruction unit 35 executes the processing after Step S502 described with reference to FIG. 17, and ends the processing.

  On the other hand, when it is necessary to guarantee the sequential access pattern (Yes in step S702), the partial cache instruction unit 35 sets the initial value, the end value, and the increment value of the cache use loop in the target loop to be subjected to the modification instruction. (Step S704). That is, the partial cache instruction unit 35 sets the initial value, the end value, and the increment value of the cache use loop so as to guarantee the sequential access pattern.

  Then, the partial cache instruction unit 35 corrects the loop index calculation (step S705), and excludes the rotation of the newly created cache use loop from the target loop (step S706).

  After that, the partial cache instruction unit 35 changes the store of the target loop that processes data other than the data processed in the cache use loop to a block store (step S707), and ends the process.

  As a result, even when it is necessary to guarantee the sequential access pattern in the stream data to be reused, it is possible to improve the program execution process by effectively using the cache.

  In addition, among the processes described in the present embodiment, all or a part of the processes described as being automatically performed can be manually performed (for example, a programmer manually inputs hardware information). Such). Alternatively, among the processes described in the present embodiment, all or a part of the processes described as being performed manually can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

  Each component of each illustrated device is functionally conceptual and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, the loop structure analysis unit 31, the sequence analysis unit 32, the access pattern analysis unit 33, and the dependency relationship analysis unit 34 may be integrated into a source program analysis unit. Further, all or any part of each processing function performed in each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware by wired logic.

  In the above embodiment, the case where various processes are realized by hardware logic has been described. However, the present invention is not limited to this, and a program prepared in advance may be executed by a computer. . In the following, an example of a computer that executes a compiler program having the same function as that of the compiler apparatus 10 shown in the above embodiment will be described with reference to FIG. FIG. 25 is a diagram illustrating a computer that executes the compiler program of this embodiment.

  As shown in FIG. 25, a computer 100 as an information processing apparatus includes a keyboard 101, a display 102, a CPU 103, a ROM 104, an HDD 105, and a RAM 106. The keyboard 101, the display 102, the CPU 103, the ROM 104, the HDD 105, and the RAM 106 are connected by a bus 107 or the like. The computer 100 is connected to the information processing apparatus 40.

  The ROM 104 stores in advance a compiler program that exhibits the same function as the compiler apparatus 10 shown in the above-described embodiment, that is, as shown in FIG. 25, a loop structure analysis program 104a and an array analysis program 104b. The ROM 104 stores in advance an access pattern analysis program 104c, a dependency relationship analysis program 104d, and a partial cache instruction program 104e. The ROM 104 stores an optimization program 104f and an object file generation program 104g in advance. Note that these programs 104a to 104g may be appropriately integrated or distributed in the same manner as each component of the compiler apparatus 10 shown in FIG.

  Then, the CPU 103 reads out these programs 104a to 104g from the ROM 104 and executes them. As a result, as shown in FIG. 25, the program 104a and the program 104b function as a loop structure analysis process 103a and a sequence analysis process 103b. The programs 104c to 104e function as an access pattern analysis process 103c, a dependency relationship analysis process 103d, and a partial cache instruction process 103e. In addition, the program 104f and the program 104g function as an optimization process 103f and an object file generation process 103g. Each of the processes 103a to 103g includes the loop structure analysis unit 31, the sequence analysis unit 32, the access pattern analysis unit 33, the dependency relationship analysis unit 34, the partial cache instruction unit 35, the optimization unit 36, the object shown in FIG. Each corresponds to the file generation unit 37.

  As shown in FIG. 25, the HDD 105 is provided with source program data 105a, loop data 105b, array data 105c, hardware information data 105d, and new source program data 105e. Each data 105a to 105e corresponds to the source program storage unit 21, the loop data storage unit 22, the array data storage unit 23, the hardware information storage unit 24, and the new source program storage unit 25 used in FIG. The CPU 103 registers the source program data 106a with the source program data 105a, registers the loop data 106b with the loop data 105b, and registers the array data 106c with the array data 105c. Further, the CPU 103 registers the hardware information data 106d with respect to the hardware information data 105d, and registers the new source program data 106e with respect to the new source program data 105e. Then, the CPU 103 reads out the registered data and stores it in the RAM 106, and compile processing based on the source program data 106a, loop data 106b, array data 106c, hardware information data 106d, and new source program data 106e stored in the RAM 106. Execute.

  The above-described programs 104a to 104g are not necessarily stored in the ROM 104 from the beginning. For example, a flexible disk (FD), a CD-ROM, an MO disk, a DVD disk, and a magneto-optical disk that are inserted into the computer 100. The computer 100 via a “portable physical medium” such as a disk or an IC card, or a “fixed physical medium” such as an HDD provided inside or outside the computer 100, and further via a public line, the Internet, a LAN, a WAN, etc. Each program may be stored in “another computer (or server)” connected to the computer, and the computer 100 may read and execute each program from these programs.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Supplementary Note 1) Access pattern analysis procedure for analyzing access pattern to data of each loop in source program;
From the access pattern analyzed by the access pattern analysis procedure, a dependency analysis procedure for analyzing a dependency relationship between data processed in the current loop and data processed in the next loop;
A storage location determination procedure for determining to allocate a storage location of data processed in the current loop to either a memory or a cache based on the dependency relationship analyzed by the dependency relationship analysis procedure;
By replacing the current loop whose storage location is determined by the storage location determination procedure with a first loop for storing processed data in the memory and a second loop for storing processed data in the cache, A new source program generation procedure for generating a new source program from the source program;
An object file generation procedure for generating an object file from the new source program generated by the new source program generation procedure;
A compiler program characterized by causing a computer to execute.

(Supplementary Note 2) In the dependency relationship analysis procedure, as the dependency relationship, the order of data processed in the current loop and the order in which processed data of the current loop are processed in the next loop are forward. Or reverse direction,
The storage location determination procedure determines that the first half portion corresponding to the cache capacity of the processed data of the current loop is stored in the cache when the dependency relationship analyzed by the dependency relationship analysis procedure is forward. When the dependency relationship analyzed by the dependency relationship analysis procedure is in the reverse direction, it is determined that the second half portion corresponding to the cache capacity of the processed data of the current loop is stored in the cache. The compiler program according to 1.

(Additional remark 3) The said storage location determination procedure directs the said new source program production | generation procedure so that the new source program which performs said 2nd loop after the said 1st loop may be produced | generated. The compiler program described in.

(Supplementary Note 4) Collecting hardware information of an information processing apparatus that executes the object file, and further executing a determination procedure for determining whether or not the information processing apparatus is capable of executing backward hardware prefetch processing on the computer Let
In the storage location determination procedure, when it is determined by the determination procedure that the information processing apparatus can execute backward hardware prefetch processing, the data processing order in the second loop is changed to the processing order in the current loop. When the information processing apparatus determines that the backward hardware prefetch process cannot be executed by the determination procedure, the data processing order in the second loop is changed. The compiler program according to appendix 3, wherein the new source program generation procedure is instructed to generate the new source program in the same processing order as in the current loop.

(Supplementary Note 5) An access pattern analysis unit that analyzes an access pattern to data of each loop in the source program;
From the access pattern analyzed by the access pattern analysis unit, a dependency analysis unit that analyzes a dependency relationship between data processed in the current loop and data processed in the next loop;
A storage location determination unit that determines to allocate a storage location of data processed in the current loop to either a memory or a cache based on the dependency relationship analyzed by the dependency relationship analysis unit;
A new source in which the current loop whose storage destination is determined by the storage destination determination unit is replaced with a first loop for storing processed data in the memory and a second loop for storing processed data in the cache A new source program generator for generating a program;
An object file generation unit that generates an object file from the new source program generated by the new source program generation unit;
A compiler apparatus comprising:

(Additional remark 6) The said dependence analysis part is a forward direction as said dependence, the order of the data processed in the said current loop, and the order in which the processed data of the said current loop are processed in the said next loop. Or reverse direction,
The storage destination determining unit determines to store, in the cache, the first half portion corresponding to the cache capacity of the processed data of the current loop when the dependency relationship analyzed by the dependency relationship analyzing unit is forward. When the dependency relationship analyzed by the dependency relationship analysis unit is in the reverse direction, it is determined that the second half portion corresponding to the cache capacity of the processed data of the current loop is stored in the cache. 5. The compiler apparatus according to 5.

(Supplementary note 7) The storage destination determination unit instructs the new source program generation unit to generate a new source program that executes the second loop after the first loop. The compiler apparatus described in 1.

(Additional remark 8) It further has the determination part which collects the hardware information of the information processing apparatus which performs the said object file, and determines whether the said information processing apparatus can perform reverse direction hardware prefetch processing,
When the information processing apparatus determines that the information processing apparatus can execute backward hardware prefetch processing by the determination unit, the storage destination determination unit changes the data processing order in the second loop to the processing order in the current loop. On the other hand, when generating the new source program and the determination unit determines that the information processing apparatus cannot execute backward hardware prefetch processing, the processing order of the data in the second loop is The compiler apparatus according to appendix 7, wherein the new source program generation unit is instructed to generate the new source program in the same processing order as in the current loop.

DESCRIPTION OF SYMBOLS 10 Compiler apparatus 11 Source program input part 12 Object file output part 13 Communication part 14 Input / output control I / F part 20 Storage part 21 Source program storage part 22 Loop data storage part 23 Array data storage part 24 Hardware information storage part 25 New Source program storage unit 30 Processing unit 31 Loop structure analysis unit 32 Sequence analysis unit 33 Access pattern analysis unit 34 Dependency analysis unit 35 Partial cache instruction unit 36 Optimization unit 37 Object file generation unit 40 Information processing device

Claims (5)

An access pattern analysis procedure for analyzing the access pattern to the data of each loop in the source program;
From the access pattern analyzed by the access pattern analysis procedure, a dependency analysis procedure for analyzing a dependency relationship between data processed in the current loop and data processed in the next loop;
A storage location determination procedure for determining to allocate a storage location of data processed in the current loop to either a memory or a cache based on the dependency relationship analyzed by the dependency relationship analysis procedure;
By replacing the current loop whose storage location is determined by the storage location determination procedure with a first loop for storing processed data in the memory and a second loop for storing processed data in the cache, A new source program generation procedure for generating a new source program from the source program;
An object file generation procedure for generating an object file from the new source program generated by the new source program generation procedure;
A compiler program characterized by causing a computer to execute. In the dependency relationship analyzing procedure, as the dependency relationship, the order of data processed in the current loop and the order in which processed data of the current loop are processed in the next loop are forward or backward. Analyzing whether there is
The storage location determination procedure determines that the first half portion corresponding to the cache capacity of the processed data of the current loop is stored in the cache when the dependency relationship analyzed by the dependency relationship analysis procedure is forward. When the dependency relationship analyzed by the dependency relationship analysis procedure is in the reverse direction, it is determined that the second half portion corresponding to the cache capacity of the processed data of the current loop is stored in the cache. Item 1. The compiler program according to item 1.   The said storage location determination procedure directs the said new source program production | generation procedure so that the new source program which performs said 2nd loop after the said 1st loop may be produced | generated. Compiler program. Collecting hardware information of the information processing apparatus that executes the object file, and causing the computer to further execute a determination procedure for determining whether or not the information processing apparatus is capable of executing backward hardware prefetch processing,
In the storage location determination procedure, when it is determined by the determination procedure that the information processing apparatus can execute backward hardware prefetch processing, the data processing order in the second loop is changed to the processing order in the current loop. On the other hand, the new source program is generated and when the information processing apparatus is determined not to be able to execute backward hardware prefetch processing by the determination procedure, the processing order of the data in the second loop is 4. The compiler program according to claim 3, wherein the new source program generation procedure is instructed to generate the new source program in the same processing order as in the current loop. An access pattern analysis unit for analyzing the access pattern to the data of each loop in the source program;
From the access pattern analyzed by the access pattern analysis unit, a dependency analysis unit that analyzes a dependency relationship between data processed in the current loop and data processed in the next loop;
A storage location determination unit that determines to allocate a storage location of data processed in the current loop to either a memory or a cache based on the dependency relationship analyzed by the dependency relationship analysis unit;
A new source in which the current loop whose storage destination is determined by the storage destination determination unit is replaced with a first loop for storing processed data in the memory and a second loop for storing processed data in the cache A new source program generator for generating a program;
An object file generation unit that generates an object file from the new source program generated by the new source program generation unit;
A compiler apparatus comprising:

Images