JP2010243525A - Liquid crystal display panel and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display panel and a method of manufacturing the same, securing moisture resistance of a top gate type TFT while using an insulating film much thinner than the conventional protective insulating film as an insulating film covering the surface of metal wiring, the surface of which is formed of Mo. <P>SOLUTION: In the liquid crystal display panel 1, the surface of a signal line 16 is formed of Mo, the surface of the signal line 16 is coated with an insulating film 19 having a thickness from 0.005 to 0.02 μm, and formed of silicon nitride, and further the surface of the insulating film 19 is coated with an interlayer resin film 20. A pixel electrode 21 and a drain electrode D of a TFT are electrically connected to each other through a contact hole 22, and a second opening 19a is formed simultaneously with cleaning in a cleaning process using a solution of hydrofluoric acid before the pixel electrode is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention provides a top gate type thin film transistor as a switching element, which has an insulating film extremely thinner than a conventional protective insulating film between a metal wiring such as a signal line whose surface is formed of molybdenum and an interlayer resin film. The present invention relates to a liquid crystal display panel having (TFT: Thin Film Transistor) and a manufacturing method thereof. Specifically, the present invention secures the moisture resistance of the top gate TFT while using an insulating film that is extremely thinner than the conventional protective insulating film as the insulating film covering the surface of the metal wiring formed with molybdenum. In addition, the present invention relates to a liquid crystal display panel that can suppress floating and peeling of an interlayer resin film and a method for manufacturing the same.

TFTs as switching elements for driving pixels of a liquid crystal display panel include those using amorphous silicon (hereinafter referred to as “a-Si”) as a semiconductor layer and polysilicon (hereinafter referred to as “p-Si”). The one used is known. TFT using p-Si
There are those manufactured at high temperatures and those manufactured at low temperatures.

A TFT using p-Si manufactured at a low temperature (hereinafter referred to as “LTPS-TFT”, see Patent Document 1 below) is made by excimer laser annealing (ELA) of a-Si formed on a transparent glass substrate. It is produced by polycrystallization by the method described above. This LTPS-TFT
Since it can be manufactured at a low temperature of 400 ° C. to 600 ° C., a driver circuit or the like for driving a liquid crystal can be simultaneously formed on a glass substrate. Moreover, since p-Si has a property of higher carrier mobility than a-Si, it is possible to reduce the size of the TFT, so that high response speed, high resolution, and high brightness can be achieved while narrowing the frame. The liquid crystal display panel can be manufactured.

In the liquid crystal display panel, TFTs using a-Si exclusively are adopted because of the ease of manufacturing of the semiconductor layer, etc., but liquid crystal projectors and in-vehicle head-up displays (HUD: Head)
Up display) and other small liquid crystal display panels have LTPS-TF for the reasons described above.
T is often adopted.

The LTPS-TFT is roughly classified into a top gate type and a bottom gate type because of its structure, and the self-alignment of the source / drain regions with respect to impurity implantation (channel doping) into the semiconductor layer is easy. For the reason, the top gate type is mainstream. Here, an example of a liquid crystal display panel using a conventional top gate type LTPS-TFT will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view of a display area for one sub-pixel of an array substrate of a liquid crystal display panel using the LTPS-TFT of the first conventional example.

The array substrate of the liquid crystal display panel 30 of the conventional example includes a transparent substrate 31, a light shielding film 32 for preventing the backlight and stray light from entering the LTPS-TFT, the light shielding film 32, and the transparent substrate 31.
A buffer insulating film 33 covering the exposed surface, an LTPS layer 34 formed on the surface of the buffer insulating film 33, a gate insulating film 35 covering the surfaces of the LTPS layer 34 and the buffer insulating film 33, A pair of gate electrodes G, a source electrode S, a drain electrode D, and a pixel electrode 36 formed on the surface of the gate insulating film 35 are provided.

The surfaces of the pair of gate electrodes G and the gate insulating film 35 are covered with an interlayer insulating film 37, and metal wirings such as signal lines 38 and routing wirings (not shown) are formed on the surface of the interlayer insulating film 37. These metal wirings are formed of an opaque metal such as aluminum (Al), aluminum alloy, molybdenum (Mo), for example. Then, the interlayer insulating film 37 and the gate insulating film 3
5 is provided with a first contact hole 39 exposing the source region of the LTPS layer 34, and a part of the signal line 38 is connected to the source region via the contact hole 39. The connection portion of the signal line 38 with the source region constitutes the source electrode S. Similarly, a second contact hole 40 that exposes the drain region of the LTPS layer 34 is formed in the interlayer insulating film 37 and the gate insulating film 35, and is formed to be an isolated pattern at the same time using the same material as the signal line 38. The metal wiring thus formed is connected to the drain region through the second contact hole 40. The connection portion of the metal wiring with the drain region constitutes the drain electrode D.

Further, the exposed surfaces of the signal line 38, the source electrode S, the drain electrode D, and the interlayer insulating film 37 are further covered with a passivation film 41. This passivation film 41 is composed of
It is provided to protect the metal wiring formed on the surface of the interlayer insulating film 37 and to guarantee the moisture resistance of the channel region of the LTPS-TFT. As the material, for example, silicon nitride, silicon oxide, or the like is employed, but silicon nitride is particularly often used from the viewpoint of ensuring moisture resistance and the ease of etching. Note that the channel region in this specification refers to LTPS-TFT, a-S.
Both i-TFTs indicate regions where current flows between the source and drain regions of the semiconductor layer.

The surface of the passivation film 41 is further covered with an interlayer resin film 42. The interlayer resin film 42 planarizes the substrate surface before the pixel electrode 36 is formed, and the signal line 38 and the pixel electrode 36.
For example, a photosensitive resin such as acrylic or siloxane. The pixel electrode 36 is formed on the surface of the interlayer resin film 42 with a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrode 36 is formed on the passivation film 41 and the interlayer resin film 42. It is electrically connected to the drain electrode D through the three contact holes 43. Reference numeral 44 indicates a storage capacitor line formed in the same layer as the gate electrode G.

In the conventional liquid crystal display panel 30, specifically, the buffer insulating film 33 has a thickness of about 0.3 to 0.5 μm, and the gate insulating film 35 has a thickness of about 0.03 to 0. .15μ
m, the thickness of the interlayer insulating film 37 is about 0.6 to 0.7 μm, the thickness of the passivation film 41 is about 0.2 to 0.4 μm, and the thickness of the interlayer resin film 42 is about 1.0 to 3.mu.m. It is about 0 μm.

JP 2007-156442 A

In the liquid crystal display panel 30 employing the top gate type TFT as described above, the LTPS layer 34 is covered with a gate insulating film 35 and an interlayer insulating film 37, and the gate insulating film 35 and the interlayer insulating film 37 are passivated. The film 41 is formed of the same silicon nitride or the like. For this reason, the inventors have found that in the liquid crystal display panel 30 employing the above-described top gate type TFT, sufficient moisture resistance of the channel region of the TFT can be ensured even if the passivation film 41 is omitted. I found it. If the passivation film 41 can be omitted, it is possible to simplify the film formation structure formed on the substrate and reduce the manufacturing cost, and the metal wiring formed on the surface of the interlayer insulating film 37 is formed by the interlayer resin film 42. Since it is covered, the metal wiring can be sufficiently protected.

However, according to the detailed examination results by the inventors, especially when the metal wiring having the surface made of Mo is adopted, if the passivation film 41 is omitted, the space between the Mo and the interlayer resin film 42 made of a photosensitive resin or the like is omitted. It has been found that the adhesiveness of the metal is weak, and floating and peeling are likely to occur near the interface between the metal wiring and the interlayer resin film. Such a problem also occurs in a liquid crystal display panel that employs, for example, a top gate type a-Si-TFT as a switching element.

The present invention has been made in view of the above-described problems, and its purpose is that the surface is M.
While using an insulating film that is extremely thinner than the conventional protective insulating film as the insulating film covering the surface of the metal wiring such as signal lines made of o, the moisture resistance of the top gate type TFT is ensured, and the interlayer resin film An object of the present invention is to provide a liquid crystal display panel and a method for manufacturing the same that can suppress the lifting and peeling of the liquid crystal.

In order to achieve the above object, a liquid crystal display panel of the present invention has a pair of transparent substrates that sandwich a liquid crystal layer, a semiconductor layer formed on one surface side of the pair of transparent substrates, and the semiconductor A first insulating film covering a surface of the layer; a gate electrode formed at a position corresponding to the semiconductor layer on the first insulating film; and a surface of the gate electrode and the exposed first insulating film. A drain electrode and a source electrode electrically connected to the semiconductor layer through a second insulating film covering the surface, a metal wiring formed in the second insulating film, and a contact hole formed in the second insulating film A third insulating film that forms the surface of the second insulating film that is exposed, the metal wiring, the drain electrode, the source electrode, an interlayer resin film formed on the surface of the third insulating film, and the interlayer Transparent formed on the surface of the resin film A liquid crystal display panel having a conductive electrode, wherein the metal wire surface is a Mo, and said third insulating film is not less than 0.005μm thickness, 0.
It consists of silicon nitride of 02 micrometers or less.

According to the liquid crystal display panel of the present invention, the thickness of the third insulating film, which is conventionally about 0.3 μm, is extremely thin, 0.005 μm or more and 0.02 μm or less. The time required for the film can be greatly reduced. The TFT originally expected for the third insulating film
The effect of ensuring moisture resistance with respect to the channel region can be ensured by the first insulating film and the second insulating film disposed in the upper layer of the semiconductor layer. Therefore, even if the third insulating film is a thin film having a thickness of 0.02 μm or less, there is no particular problem with respect to moisture resistance. And in the liquid crystal display panel of this invention, Mo of the surface of metal wiring is coat | covered with the 3rd insulating film which consists of silicon nitride with comparatively favorable adhesiveness with an interlayer resin film. Thereby, since the adhesiveness between the interlayer resin films is maintained by the silicon nitride film formed on the surface of Mo, the occurrence of the floating or peeling of the interlayer resin films is greatly suppressed. If the thickness of the third insulating film is less than 0.005 μm, it becomes difficult to suppress poor adhesion of the third insulating film, and if it exceeds 0.02 μm, the time required for film formation and contact holes are formed. Therefore, the time required for the etching becomes long, and the above effect is difficult to obtain.

In the liquid crystal display panel of the present invention, the semiconductor layer is preferably made of low-temperature polysilicon.

A TFT made of low-temperature polysilicon can be manufactured at a low temperature of 400 ° C. to 600 ° C., so that a driver circuit for driving a liquid crystal can be simultaneously formed on a glass substrate, and p-Si is a- Because it has the property of high carrier mobility compared to Si,
The TFT can be reduced in size. Therefore, according to the liquid crystal display panel of the present invention, a liquid crystal display panel with high response speed, high resolution, and high brightness can be produced while narrowing the frame, and an optimal liquid crystal display panel for a liquid crystal projector, an in-vehicle HUD, or the like can be obtained. Obtainable.

In the liquid crystal display panel of the present invention, the transparent conductive electrode is a pixel electrode, and the pixel electrode is electrically connected to the drain electrode through a contact hole formed in the interlayer resin film and the third insulating film. Are preferably connected.

With such a configuration, in addition to the above-described effect of the liquid crystal display panel of the present invention, the third insulating film that has been separately formed for the purpose of forming a contact hole for electrically connecting the pixel electrode and the drain electrode is conventionally used. An effect is obtained that the opening portion forming step, that is, the photolithography step, the etching step, and the resist stripping step can be omitted and the opening can be manufactured at low cost. That is, after forming an interlayer resin film having an opening on the surface of the third insulating film through exposure and development with an alkaline solution, cleaning with a hydrofluoric acid solution before forming a pixel electrode on the surface of the interlayer resin film is performed. By doing so, the opening portion can be formed by etching away the portion of the third insulating film exposed from the opening portion, using the interlayer resin film as a mask, and the manufacturing cost can be reduced. At this time, since the third insulating film is extremely thin, the time required for performing the necessary and sufficient etching can be shortened, so that the third insulating film can be manufactured in a short time.

Furthermore, in order to achieve the above object, a method for producing a liquid crystal display panel of the present invention is a method for producing a liquid crystal display panel in which a liquid crystal layer is sandwiched between a pair of transparent substrates,
On one liquid crystal layer side of the transparent substrate, a semiconductor layer for a thin film transistor, a first insulating film covering the surface of the semiconductor layer, and a position corresponding to the semiconductor layer on the first insulating film are formed. A gate electrode; a second insulating film covering the surface of the gate electrode and the surface of the first insulating film; a metal wiring formed on the surface of the second insulating film and made of Mo; and the second insulating film. Preparing a substrate having a drain electrode and a source electrode electrically connected to the semiconductor layer via contact holes formed in the film;
The metal wiring, the drain electrode, the source electrode, and the exposed surface of the second insulating film,
Coating with a third insulating film having a thickness of 0.005 μm or more and 0.02 μm or less,
Covering the surface of the third insulating film with an interlayer resin film having a first opening that partially exposes the third insulating film at a corresponding position of the drain electrode;
By performing hydrofluoric acid cleaning on the substrate obtained in the step, the surface of the interlayer resin film is cleaned, and at the same time, the interlayer resin film having the first opening is exposed from the first opening as a mask. Etching a portion of the third insulating film to form a second opening in the third insulating film, and exposing the drain electrode from the first and second openings;
A pixel electrode made of a transparent conductive material is formed on the surface of the interlayer resin film, and the first electrode
Electrically connecting the pixel electrode and the drain electrode through the opening and the second opening;
It is characterized by including.

According to the method for producing a liquid crystal display panel of the present invention, the liquid crystal display panel of the present invention having the above-described effects can be produced in a short time.

FIG. 1A is a schematic plan view showing a schematic configuration of the liquid crystal display panel according to the present embodiment without a color filter substrate, and FIG. 1B is a schematic cross-sectional view taken along line IB-IB in FIG. 1A. It is principal part sectional drawing for 1 sub pixel in a display area. FIG. 3 is a cross-sectional view sequentially showing manufacturing steps of the array substrate shown in FIG. 2. FIG. 4 is a cross-sectional view sequentially showing the manufacturing process of the array substrate subsequent to FIG. 3. FIG. 5 is a cross-sectional view sequentially showing the manufacturing process of the array substrate subsequent to FIG. 4. It is a schematic sectional drawing of the display area for 1 sub pixel of the array substrate of the liquid crystal display panel using the conventional LTPS-TFT.

Hereinafter, embodiments of the present invention will be described with reference to the embodiments and drawings.
A case of a vertical electric field type liquid crystal display panel using TPS-TFT will be described as an example. In addition,
The embodiments shown below are not intended to limit the invention to those described herein. The present invention provides a liquid crystal using a single top gate type LTPS-TFT, a single top gate type or a dual top gate type a-Si-TFT, unless departing from the technical idea shown in the claims. The present invention can also be applied to a display panel. In each drawing used for the description in this specification, each layer and each member are displayed in different scales so that each layer and each member can be recognized on the drawing. However, it is not necessarily displayed in proportion to the actual dimensions.

The liquid crystal display panel 1 of this embodiment is a TN mode transmissive liquid crystal display panel using dual top gate LTPS-TFTs, and the configuration of the main part will be described with reference to FIG.
1A is a schematic plan view showing a schematic configuration of the liquid crystal display panel according to the present embodiment without a color filter substrate, and FIG. 1B is a schematic cross-sectional view taken along line IB-IB in FIG. 1A.

In the liquid crystal display panel 1 of this embodiment, the liquid crystal layer LC is sandwiched between the array substrate AR and the color filter substrate CF. The array substrate AR includes a first transparent substrate 2 as shown in FIG. 1A.
On the surface of the first transparent substrate 2 in FIG. 1A, a display region 3 in which pixel electrodes, TFTs and the like are formed, a peripheral region 4 in which a lead-out wiring is formed around the display region 3 A circuit formation region 5 in which peripheral circuits are formed at the left and right end portions and an external circuit mounting terminal region 6 at the lower end portion of the first transparent substrate 2 are formed.

The display area 3 includes a plurality of scanning lines and signal lines that are arranged in a matrix and divide the display area 3 into sub-pixels, and dual switching elements arranged near the intersections of the scanning lines and the signal lines. A top gate type LTPS-TFT, pixel electrodes electrically connected to the TFT, and the like are stacked. Although these laminated structures will be described later, in FIG. 1B, these are schematically shown as first structures 7. In the peripheral region 4, lead wirings (not shown) for connecting scanning lines and signal lines to an IC driver circuit or the like formed in the circuit formation region 5 are formed.

On the other hand, as shown in FIG. 1B, the color filter substrate CF has a color filter layer and a light shielding member such as a black matrix on the second transparent substrate 8 made of a transparent material such as glass. The color filter layer is provided with a colored layer corresponding to each sub-pixel, and is disposed so as to face the pixel electrode of the array substrate AR. The light shielding member is at least the array substrate A.
The TFTs are arranged at positions corresponding to the R TFTs, scanning lines, and signal lines. The second transparent substrate 8 further includes a counter electrode (common electrode) made of a transparent conductive material such as ITO or IZO.
It is arranged so as to face the display area 3 of R. Although a specific configuration of these color filter layers and the like is omitted, in FIG. 1B, these are schematically shown as second structures 9.

The array substrate AR and the color filter substrate CF are bonded to each other with a sealing material 10 made of, for example, a thermosetting resin such as an epoxy resin or a photocurable resin, and a liquid crystal is supplied between the substrates from a liquid crystal injection port (not shown). Is injected to obtain the liquid crystal display panel 1 of the embodiment.

Here, the configuration of the main part of the array substrate AR will be described with reference to FIG. FIG. 2 is a cross-sectional view of the main part of one sub pixel in the display area 3 (see FIG. 1A) of the array substrate AR. Display area 3
In FIG. 2, a light shielding film 11 made of Mo patterned on the surface of the first transparent substrate 2 is formed so as to shield light directly below all LTPS-TFTs. The surface of the first transparent substrate 2 is covered with a buffer insulating film 12. Note that the configuration of the light shielding film 11 is the same as that of a known one, and a detailed description thereof will be omitted. Further, on the surface of the buffer insulating film 12, for example, an Lch constituting an Nch-TFT for each subpixel.
A semiconductor layer 13 made of TPS is formed, and the surfaces of the semiconductor layer 13 and the exposed buffer insulating film 12 are covered with a gate insulating film (corresponding to the first insulating film of the present invention) 14.

A pair of gate electrodes G of a dual gate LTPS-TFT is formed on the surface of the gate insulating film 14. In the gate electrode G, a part of the scanning line (not shown) is formed in the semiconductor layer 13.
For example, a single layer made of Mo, a MoW alloy, or a laminated structure made of Mo / Al / Mo is formed. The exposed surfaces of the pair of gate electrodes G and the gate insulating film 14 are covered with an interlayer insulating film (corresponding to the second insulating film of the present invention) 15.

On the surface of the interlayer insulating film 15, metal wirings such as signal lines 16 and routing wirings (not shown) are formed. Like the scanning lines, they are made of a single layer made of Mo, MoW alloy, or made of Mo / Al / Mo. It is a laminated structure. The interlayer insulating film 15 and the gate insulating film 14 are provided with a semiconductor layer 13.
A first contact hole 17 is provided to expose the source region composed of the N + region. A part of the signal line 16 is extended and connected to the source region via the first contact hole 17, and this connection portion constitutes the source electrode S.

The interlayer insulating film 15 and the gate insulating film 14 are provided with a second contact hole 18 that exposes the drain region of the semiconductor layer 13. A metal wiring that is simultaneously and in an isolated pattern with the same material as the signal line 16 is connected to the drain region via the second contact hole 18, and this connection portion constitutes the drain electrode D. In this example, the signal line 16, the source electrode S, and the drain electrode D are formed of the same material at the same time.
Whether the same material is used or whether it is formed simultaneously is a design matter that can be appropriately changed by those skilled in the art, and does not necessarily need to be formed simultaneously using the same material.

The surfaces of the signal line 16, the source electrode S, the drain electrode D, and the interlayer insulating film 15 are further provided with an insulating film (
(Corresponding to the third insulating film of the present invention) 19. The insulating film 19 is made of silicon nitride and is a very thin film having a thickness of 0.005 μm or more and 0.02 μm or less. Furthermore, the insulating film 1
9 is covered with an interlayer resin film 20 made of a photosensitive resin or the like. The pixel electrode 21 is formed on the surface of the interlayer resin film 20, and a part of the pixel electrode 21 is electrically connected to the drain electrode D through the third contact hole 22 formed in the interlayer resin film 20 and the insulating film 19. Yes.

An auxiliary capacitance line 23 is formed on the gate insulating film 14 formed on the surface of the drain electrode D, and an auxiliary capacitance is formed between the auxiliary capacitance line 23 and the drain electrode D. The auxiliary capacitance line 23 has a single layer made of Mo, MoW alloy, or a laminated structure made of Mo / Al / Mo, like the gate electrode G and the scanning line (not shown) formed on the surface of the gate insulating film 14. The gate electrode G and the like are simultaneously formed in the same process.

Next, a method for manufacturing the liquid crystal display panel 1 according to the present embodiment will be described with reference to FIGS. First, a thin film made of Mo or Mo alloy having a film thickness of about 0.05 to 0.2 μm is formed on the entire surface of the first transparent substrate 2 by sputtering, and the light-shielding film 11 is formed on all LTPS-TFTs in the display region 3. The light shielding film 1 is formed by dry etching so as to be disposed immediately below.
1 is formed by patterning (FIG. 3A). This dry etching is preferably reactive ion etching (R) using sulfur fluoride (SF ₆ ) and oxygen (O ₂ ) as etching gases.
IE: Reactive Ion Etching is used.

Next, the exposed surfaces of the light-shielding film 11 and the first transparent substrate 2 are formed on the surface of the silicon nitride by a plasma chemical vapor deposition (CVD) method.
It is covered with a 3-0.5 μm buffer insulating film 12 (FIG. 3B). The buffer insulating film 12
May be a single film of silicon oxide or a laminated film made of silicon oxide and silicon nitride, but since the insulating film 19 according to the present invention uses silicon nitride in particular, an example using silicon nitride alone is also shown here. . The same applies to the gate insulating film 14 and the interlayer insulating film 15.

Next, an a-Si layer serving as a p-Si starting material is formed on the entire surface of the substrate obtained in the above step by plasma CVD, and is polycrystallized by excimer laser annealing (ELA). A semiconductor thin film 13a is formed (FIG. 3C). Next, the semiconductor thin film 1
The semiconductor layer 13 is formed by patterning 3a by photolithography (FIG. 3D).
).

Next, in order to control the threshold value of the Nch-TFT to a desired value, boron (B) is ion-doped on the surface of the semiconductor layer 13 with a low acceleration and a low dose by using an ion doping apparatus. The dose amount of B is appropriately adjusted according to a desired control threshold value. Next, Nch-TF
The portion other than the N + region of T is covered with photoresists 24a and 24b, and phosphorus (P) is ion-doped on the substrate surface with low acceleration and high dose by using an ion doping apparatus.
As a result, a source region and a drain region made of an N + region are formed in the semiconductor layer 13 (FIG. 3E). The photoresists 24a and 24b are stripped and removed after ion doping. Next, a gate insulating film 14 made of silicon nitride and having a thickness of about 0.03 to 0.15 μm is formed by plasma CVD so as to cover the entire surface of the substrate (FIG. 3F).

Next, on the entire surface of the substrate obtained by the above process, a single layer made of Mo, MoW alloy, or Mo
A metal thin film 25 having a laminated structure of / Al / Mo was formed by sputtering (FIG. 4A).
Then, the scanning line (not shown), the gate electrode G, and the auxiliary capacitance line 23 are patterned by photolithography (FIG. 4B). Next, P is formed on the surface of the substrate obtained in the above process.
Is ion-doped with high acceleration and low dose. As a result, the gate electrode G is used as a mask on the semiconductor layer 13, and the LDD (Li
ghtly Doped Drain) region is formed (FIG. 4C).

Next, a film thickness of about 0.6-0.
A 7 μm interlayer insulating film 15 is formed by plasma CVD, and further heat treatment is performed to electrically activate B and P, which are impurities doped in the semiconductor layer 13 (FIG. 4D). Next, the first contact hole 17 and the second contact hole 18 that expose the source region and the drain region of the semiconductor layer 13 are formed in the interlayer insulating film 15 by dry etching (FIG. 4E). As this dry etching, for example, SF ₆ / C
RIE using HF ₃ (or C ₂ HF _5, which is a CHF-based higher gas) or SF ₆ / C ₄ F ₈ + H ₂ , ICP (Inductive Coupled Plasma) -RIE, or the like is used. The first
The contact hole 17 and the second contact hole 18 are formed by buffered hydrofluoric acid (BH
It is also possible to carry out by wet etching using F).

Next, a metal thin film made of Mo / Al / Mo is formed on the substrate surface by sputtering,
This is patterned by photolithography, and simultaneously with the metal wiring such as the signal line 16 and the routing wiring, the source electrode S and the second contact electrically connected to the source region of the semiconductor layer 13 through the first contact hole 17. A drain electrode D electrically connected to the drain region of the semiconductor layer 13 through the hole 18 is formed (FIG. 5A).

Next, an insulating film 19 made of silicon nitride that covers the exposed surface of the interlayer insulating film 15 together with the metal wiring, source electrode S, and drain electrode formed on the surface of the interlayer insulating film 15 is formed by plasma CVD. (FIG. 5B). In this embodiment, since the thickness of the passivation film, which has been conventionally about 0.3 μm, is extremely thin as 0.02 μm or less, the time required for forming the insulating film 19 can be greatly shortened. Further, conventionally, after the insulating film 19 is formed, a contact hole for connecting the pixel electrode and the drain electrode D is formed at a position corresponding to the drain electrode D and the pixel electrode 21 (a position indicated by reference numeral A). The opening part which makes a part is formed (refer FIG. 5C). However, in this embodiment, since the insulating film 19 is thin, the opening is formed at the same time in a cleaning step (FIG. 5D) using a hydrofluoric acid solution before pixel electrode formation shown in FIG. 5E. ing. Thereby, an effect is obtained that the step of forming an opening in the insulating film 19, that is, the photolithography step, the etching step, and the resist stripping step can be omitted and it can be manufactured at low cost.

Next, an opening (a position indicated by a symbol A) corresponding to the drain electrode D and the pixel electrode 21
(Corresponding to the first opening of the present invention) Interlayer resin film 20 having a film thickness of about 1.0 to 3.0 μm having 20a
(FIG. 5C). The opening 20a partially exposes the surface of the insulating film 19, and after a photosensitive resin such as acryl or siloxane is applied to the surface of the insulating film 19, the formation region of the opening 20a is masked. By being exposed and developed, the interlayer resin film 20 and the interlayer resin film 20 are formed integrally.

Next, as a treatment before forming the pixel electrode 21 on the surface of the interlayer resin film 20, cleaning with a hydrofluoric acid solution is performed. At the same time, using the interlayer resin film 20 as a mask, the opening 20a
The portion of the insulating film 19 exposed from the etching is removed by etching to form an opening (corresponding to the second opening of the present invention) 19a. Thereby, the third contact hole 22 for connection between the pixel electrode 21 and the drain electrode D of the semiconductor layer 13 is completed (FIG. 5D).

Then, the pixel electrode 21 made of a transparent conductive material such as ITO or IZO is formed on the interlayer resin film 2.
It is formed on the surface of 0 by sputtering and etching. Thereby, the pixel electrode 21 is electrically connected to the drain electrode D of the semiconductor layer 13 through the third contact hole 22, and the array substrate AR of the liquid crystal display panel according to the present invention is completed (FIG. 5E).

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel 2 ... 1st transparent substrate 3 ... Display area 4 ... Peripheral area 5 ... Circuit formation area 6 ... External circuit mounting terminal area 7 ... 1st structure 8 ... 2nd transparent substrate 9 ... 2nd structure DESCRIPTION OF SYMBOLS 10 ... Sealing material 11 ... Light shielding film 12 ... Buffer insulating film 13 ... Semiconductor layer 13a ...
Semiconductor thin film 14 ... Gate insulating film 15 ... Interlayer insulating film 16 ... Signal line 17 ... First contact hole 18 ... Second contact hole 19 ... Insulating film 19a ... Second opening 20 ...
Interlayer resin film 20a ... first opening 21 ... pixel electrode 22 ... third contact hole 23
... Auxiliary capacitance lines 24a, 24b ... Photoresist AR ... Array substrate CF ... Color filter substrate LC ... Liquid crystal layer

Claims (4)

Having a pair of transparent substrates holding the liquid crystal layer,
A semiconductor layer formed on one surface side of the pair of transparent substrates;
A first insulating film covering the surface of the semiconductor layer;
A gate electrode formed at a position corresponding to the semiconductor layer on the first insulating film;
A second insulating film covering the surface of the gate electrode and the exposed surface of the first insulating film;
A drain electrode and a source electrode electrically connected to the semiconductor layer through a metal wiring formed in the second insulating film and a contact hole formed in the second insulating film;
A third insulating film forming a surface of the metal wiring, drain electrode, source electrode and the exposed second insulating film;
An interlayer resin film formed on the surface of the third insulating film;
A transparent conductive electrode formed on the surface of the interlayer resin film;
A liquid crystal display panel comprising:
The metal wiring has a surface made of Mo, and
The third insulating film is made of silicon nitride having a thickness of 0.005 μm or more and 0.02 μm or less,
A liquid crystal display panel characterized by that. The liquid crystal display panel according to claim 1, wherein the semiconductor layer is made of low-temperature polysilicon. The transparent conductive electrode is a pixel electrode;
The liquid crystal display panel according to claim 1, wherein the pixel electrode is electrically connected to the drain electrode through a contact hole formed in the interlayer resin film and the third insulating film. A method of manufacturing a liquid crystal display panel in which a liquid crystal layer is sandwiched between a pair of transparent substrates,
On one liquid crystal layer side of the transparent substrate, a semiconductor layer for a thin film transistor, a first insulating film covering the surface of the semiconductor layer, and a position corresponding to the semiconductor layer on the first insulating film are formed. A gate electrode; a second insulating film covering the surface of the gate electrode and the surface of the first insulating film; a metal wiring formed on the surface of the second insulating film and made of Mo; and the second insulating film. Preparing a substrate having a drain electrode and a source electrode electrically connected to the semiconductor layer via contact holes formed in the film;
The metal wiring, the drain electrode, the source electrode, and the exposed surface of the second insulating film,
Coating with a third insulating film having a thickness of 0.005 μm or more and 0.02 μm or less,
Covering the surface of the third insulating film with an interlayer resin film having a first opening that partially exposes the third insulating film at a corresponding position of the drain electrode;
By performing hydrofluoric acid cleaning on the substrate obtained in the step, the surface of the interlayer resin film is cleaned, and at the same time, the interlayer resin film having the first opening is exposed from the first opening as a mask. Etching a portion of the third insulating film to form a second opening in the third insulating film, and exposing the drain electrode from the first and second openings;
A pixel electrode made of a transparent conductive material is formed on the surface of the interlayer resin film, and the first electrode
Electrically connecting the pixel electrode and the drain electrode through the opening and the second opening;
A method for producing a liquid crystal display panel, comprising:

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