JP2010239166A - Pin type light receiving element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pin-type light receiving element having a low dark current owing to the reduction of a leak current and having a high speed response and high light receiving sensitivity owing to the reduction of an element capacity. <P>SOLUTION: There are laminated in succession on a semiconductor substrate 20 composed of InP etc. an n-type semiconductor layer 30 composed of Si doped GaInAs, an i-type semiconductor layer 31 composed of undoped GaInAs, and a p-type semiconductor layer 32 composed of Zn doped GaInAs with surroundings of the i-type semiconductor layer 31 and the p-type semiconductor layer 32 formed into mesa forms. The surrounding of the mesa has a passivation semiconductor layer 40. Furthermore, the thickness h2 of a light receiving region at a messa central part of the p-type semiconductor layer 32 is made thinner than the thickness h1 of its surrounding. In a pin-type light receiving element having such a structure depletion layer capacity is reduced while keeping a low dark current characteristic to largely improve a responce speed. Furthermore, light absorption at the p-type semiconductor layer 32 is reduced and high receiving sensitivity is also largely improved. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pin type semiconductor light receiving element used in an optical information transmission system.

  The pin type light receiving element is used as a light receiving device for optical fiber communication. In particular, as a light receiving device used in an optoelectronic integrated circuit, a pin type light receiving element having a mesa structure is formed. An optoelectronic integrated circuit is a device in which an optical device and an electronic circuit are formed on the same substrate in order to realize an optical function and high performance and low cost optical device corresponding to high speed and large capacity of a communication system. . A pin-type light receiving element having a mesa structure is superior to a planar structure widely used in the field of optical communication at present in terms of easy integration and easy insulation between elements. Further, since the mesa pin light receiving element is formed by epitaxial growth with high uniformity of doping in the pin structure, it is easy to increase the diameter of the wafer, and cost reduction can be expected. Further, the mesa type has a feature that the element capacity is small and high-speed response is possible because unnecessary portions that do not contribute to the operation are removed.

  In the mesa-type pin light receiving element, the pn junction region of the mesa portion and the surface of the semiconductor layer are exposed, so that the dark current based on the surface leakage current is larger than in other light receiving elements. In order to reduce this dark current, a structure is employed in which the side surface of the mesa portion is covered with an insulator protective film or an InP passivation semiconductor film. In particular, in the method using the InP passivation structure, dark current can be significantly reduced. For example, as the prior art, it is described in detail in the documents “Electronic Information Communication Society General Conference Proceedings of 1996, Electronics 1, SC-2-3, pp. 435-436, 1996”, “JP 09-213988”, and the like. Yes.

  FIG. 11 shows an element structure of a mesa-type pin light receiving element having a conventional InP passivation structure. On the InP semiconductor substrate 20, an n-type semiconductor layer 30 / i-type semiconductor layer 31 / p-type semiconductor layer 32 are sequentially stacked. The i-type semiconductor layer 31 and the p-type semiconductor layer 32 are made of the same first semiconductor material. Here, for example, GaInAs is used as the first semiconductor material. The surface of the light-receiving layer for optical signal light formed in a mesa shape is covered with a non-doped InP material having a band gap energy larger than that of the first semiconductor material. As a result, the mesa surfaces of the i-type semiconductor layer 31 and the p-type semiconductor layer 32 formed in a mesa shape are good semiconductor heterojunctions with a so-called wide band gap semiconductor layer. The interface state density of the semiconductor heterojunction made of a semiconductor-semiconductor having different band gap energies is very low compared to the interface state density of the semiconductor-insulator protective film, so that the leakage current based on the interface state can be reduced. Therefore, the dark current can be remarkably reduced.

  In addition, according to the document “1996 Electronic Information Communication Society General Conference Proceedings Electronics 1, SC-2-3, pp. 435-436, 1996), the response speed of the mesa-type pin light-receiving element having the InP passivation structure is An element having a light receiving diameter of 100 μmφ has a high response speed of around 2 GHz even when driven at a relatively low voltage of −1 V or less.

JP 09-213988

“The 1996 IEICE General Conference Proceedings Electronics 1, SC-2-3, pp. 435-436, 1996)

  However, in recent optical communication systems, demands for large capacity and high speed are increasing rapidly, and it is necessary to further increase the operation speed and response speed of semiconductor optical devices. The mesa-type pin light-receiving element structure having the InP passivation structure shown in FIG. 11 is difficult to use for a light-receiving device for high-speed optical communication of about 40 GHz, which will be the mainstay of next-generation optical transmission. The response speed of the mesa-type pin light receiving element having the InP passivation structure is limited mainly by the CR time constant determined by the product CR of the element resistance R and the element capacitance C. In particular, in the conventional structure shown in FIG. 11, zinc (Zn), which is a p-type impurity, diffuses from the p-type semiconductor layer into the i-type semiconductor layer, and the depletion layer capacitance increases. There is a problem that it is difficult.

  Further, in order to increase the response speed of the mesa-type pin light-receiving element, it is necessary to reduce the mesa diameter of the mesa-type light-receiving element as a means for reducing the element capacity of the element. Since the light receiving diameter is also reduced, there is a problem that the light receiving sensitivity is also reduced.

  As a result of repeating trial and error and making a large number of pin-type light receiving elements as prototypes, the inventors of the present application, as a means for reducing the element capacity of the pin-type light receiving element and improving the light receiving sensitivity, in addition to reducing the mesa diameter. The present inventors have found a method for reducing the thickness of the p-type semiconductor layer. However, it has been found that by reducing the thickness of the p-type semiconductor layer, the dark current of the device gradually increases and the device characteristics deteriorate.

  Therefore, the present invention achieves an improvement in response speed and an improvement in light receiving sensitivity by reducing the element capacitance of the element without increasing the dark current of the mesa-type pin light receiving element, and monolithically with other electronic devices. An object of the present invention is to provide a light receiving element for an optical transmission system that can be easily integrated.

  In order to achieve the above object, a pin type light receiving element according to claim 1 of the present invention includes: (a) a semiconductor substrate; and (b) an impurity of a first conductivity type formed on the semiconductor substrate. A first semiconductor layer configured by doping; and (c) a second semiconductor layer formed on the first semiconductor layer and configured without intentionally doping impurities into the first semiconductor material; (D) a third semiconductor layer formed on the second semiconductor layer and configured by doping the first semiconductor material with an impurity of a second conductivity type different from the first conductivity type; The second semiconductor layer and the third semiconductor layer form one mesa portion, the thickness of the second semiconductor layer is uniform in the mesa portion, and the third semiconductor layer is around the mesa portion. (E) the first to third half portions are formed to be thicker than the thickness at the center of the mesa portion. A second semiconductor material formed so as to cover the body layer and having a band gap energy larger than that of the first semiconductor material, the fourth semiconductor layer configured without intentionally doping impurities. It is a feature.

  In such a pin-type light receiving element, in the vicinity of the mesa, impurities are intentionally added to the second semiconductor material having a larger band gap energy than the first semiconductor materials constituting the second and third semiconductor layers. A fourth semiconductor layer configured without doping is formed to cover the first to third semiconductor layers. Therefore, in such a structure, a structure similar to the conventional mesa type InP passivation structure is realized, and the interface of the pn junction region between the first semiconductor layer and the third semiconductor layer is the interface state. It is a good heterojunction with a so-called wide band gap semiconductor layer having a low density. As a result, the interface state density along the wall surfaces of the second and third semiconductor layers is similar to that of the conventional mesa pin light-receiving element having the InP passivation structure in which the third semiconductor layer is formed with a uniform thickness. Based on this, the leakage current flowing on the mesa surface can be remarkably reduced. Further, the leakage current flowing on the mesa surface is related to the thickness of the third semiconductor layer in the vicinity of the mesa area, and only the thickness of the third semiconductor layer in the vicinity of the mesa area is set to a predetermined thickness or more. This leakage current can be sufficiently reduced.

  Furthermore, since the pin type light receiving element according to the present invention has a structure in which the third semiconductor layer at the center of the mesa portion is thin, light absorption in the third semiconductor layer with respect to incident signal light is reduced. The light receiving sensitivity is improved by increasing the amount of signal reaching the second semiconductor layer where photocarriers are generated.

  Further, in the pin type light receiving element according to the present invention, the third semiconductor layer in the center of the mesa portion has a thin thickness, so that impurities from the third semiconductor layer into the second semiconductor layer during the manufacturing process can be obtained. Diffusion can be suppressed, and the element capacitance of the element can be reduced.

  The response speed of the mesa-type pin light-receiving element is limited by the CR time constant determined by the element resistance and the element capacitance, and thus does not reach the operating speed limit of the element determined by the travel time of electrons and holes. Therefore, in the pin type light receiving element of the present invention, it is possible to expand the response speed to a high frequency band of about 40 GHz.

  The pin type light receiving element according to claim 2 is characterized in that, in the pin type light receiving element according to claim 1, the first semiconductor material is GaInAs and the second semiconductor material is InP.

  The pin type light receiving element according to claim 3 is the pin type light receiving element according to claim 1, further comprising an insulator layer formed so as to cover the semiconductor substrate and the first to fourth semiconductor layers. And

  The pin type light receiving device according to claim 4 is the pin type light receiving device according to any one of claims 1 to 3, wherein the first conductivity type is n-type and the second conductivity type is p-type. It is characterized by.

  The pin type light receiving element according to claim 5 is the pin type light receiving element according to any one of claims 1 to 4, wherein the third semiconductor layer is formed on the third semiconductor layer in a region where the thickness is small. And a first electrode layer formed in ohmic contact with the first electrode layer. Thereby, since the area | region where the thickness of a 3rd semiconductor layer is thin can be formed to a mesa peripheral part area | region, it becomes possible to enlarge a light-receiving area. For this reason, it is relatively easy to increase the light receiving sensitivity, and when the signal light is received through the optical fiber, the alignment between the optical fiber and the mesa pin-PD can be facilitated.

  The pin type light receiving element according to claim 6 is the pin type light receiving element according to any one of claims 1 to 4, wherein the third semiconductor layer is formed on the third semiconductor layer in a region where the third semiconductor layer is thick. And a first electrode layer formed in ohmic contact with the first electrode layer. This is because the distance between the first electrode layer and the pn junction region between the first semiconductor layer and the second semiconductor layer is increased by forming the electrode in the peripheral portion where the third semiconductor layer is thick. Therefore, the dark current can be further reduced. Further, by increasing the thickness of the third semiconductor layer under the first electrode layer, the element capacity can be further reduced. The element characteristics can be remarkably improved based on the reduction of the element capacitance and the suppression of dark current.

  The pin type light receiving device according to claim 7 is the pin type light receiving device according to any one of claims 1 to 6, wherein the thickness h1 around the mesa portion of the third semiconductor layer is 0.2 μm ≦ It is in the range of h1 ≦ 0.5 μm.

  This is because if the thickness h1 around the mesa portion of the third semiconductor layer is 0.2 μm or more, the leakage current that flows on the mesa surface along the wall surface of the second and third semiconductor layers based on the interface state density It has been clarified by experiments that can be sufficiently suppressed. Conversely, as the thickness h1 around the mesa portion of the third semiconductor layer increases, the element capacitance also increases. For this reason, an increase in element capacitance can be suppressed by setting the thickness h1 around the mesa portion of the third semiconductor layer to 0.5 μm or less.

  The pin type light receiving device according to claim 8 is the pin type light receiving device according to any one of claims 1 to 7, wherein the thickness h2 of the center of the mesa portion of the third semiconductor layer is 0.02 μm <. It is characterized by being in the range of h2 ≦ 0.25 μm.

  This is because the light receiving sensitivity can be improved and the device capacitance can be reduced by making the thickness h2 of the third semiconductor layer in the center of the mesa portion thinner than 0.25 μm, but the device resistance is increased at the same time. Therefore, holes generated in the second semiconductor layer travel through the third semiconductor layer and travel time for reaching the first electrode layer becomes longer, causing a decrease in sensitivity and a deterioration in frequency characteristics. It becomes. By setting the layer thickness h2 of the third semiconductor layer at the center of the mesa portion to 0.02 μm or more, it is possible to suppress an increase in element resistance, a decrease in sensitivity, and a deterioration in frequency characteristics.

  As described above in detail, in the pin type light receiving element of the present invention, in the third semiconductor layer of the first mesa portion, by reducing only the thickness of the light receiving region at the center of the mesa, the element capacitance is reduced. Reduced. Therefore, since the CR time constant that limits the response speed of the light receiving element can be reduced, high-speed response characteristics can be obtained. Further, the light absorption of the signal light in the third semiconductor layer is reduced and the amount of light reaching the second semiconductor layer is increased, so that the light receiving sensitivity is also improved.

  Further, by maintaining the thickness of the third semiconductor layer around the mesa portion in a thick state, each of the i-type semiconductor layer and the p-type semiconductor layer is similar to the conventional pin-type light receiving element including the InP passivation semiconductor layer. Leakage current flowing along the wall can be reduced

  Therefore, in the pin type light receiving element of the present invention, it is possible to provide an effect that the element characteristics are improved based on the reduction of the element capacity and the improvement of the light receiving sensitivity while suppressing the dark current.

  Next, in the manufacturing method of the pin type light receiving element of the present invention, a thick first semiconductor material is formed in the mesa peripheral region of the third semiconductor layer processed into the mesa type, and the mesa type center that is the light receiving region is formed. A structure in which the third semiconductor layer is thin only in the region is easily realized with good reproducibility. Further, a fourth semiconductor layer, which is a wide band gap semiconductor layer, is formed around the second and third semiconductor layers that are both formed of the first semiconductor material. Therefore, the crystallinity of the fourth semiconductor layer is maintained relatively well, and the arrangement of the pn junction region is determined based only on the process of forming the first to third semiconductor layers. Therefore, the effect that the pn junction region is completely covered by the fourth semiconductor layer can be provided.

It is sectional drawing which shows the structure of the pin type light receiving element which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the pin type light receiving element which concerns on the 2nd Embodiment of this invention. FIG. 3 is a cross-sectional view sequentially showing manufacturing steps of the pin type light receiving element of FIG. 1. FIG. 4 is a cross-sectional view sequentially illustrating manufacturing steps subsequent to FIG. 3 in the pin type light receiving element of FIG. 1. 3 is a graph showing experimental results on the relationship between the thickness of a p-type semiconductor layer and the element capacitance of the element in the pin-type light-receiving element of FIG. 1 and the pin-type light-receiving element of FIG. 2. 3 is a graph showing experimental results on the relationship between the thickness of a p-type semiconductor layer and the light-receiving sensitivity of the element in the pin-type light-receiving element of FIG. 1 and the pin-type light-receiving element of FIG. 3 is a graph showing bias voltage-dark current characteristics in the pin type light receiving element of FIG. 2. 3 is a graph showing experimental results on the relationship between the thickness of a p-type semiconductor layer and the dark current of the element in the pin-type light-receiving element of FIG. 1 and the pin-type light-receiving element of FIG. 2. It is a graph which shows the experimental result about the relationship between the thickness of the p-type semiconductor layer, the element capacity of an element, and the light receiving sensitivity in the pin type light receiving element provided with the conventional InP passivation semiconductor layer. It is a graph which shows the experimental result about the relationship between the thickness of the p-type semiconductor layer in the pin type light receiving element provided with the conventional InP passivation semiconductor layer, and the dark current of an element. It is sectional drawing which shows the structure of the pin-type light receiving element provided with the conventional InP passivation semiconductor layer.

  Hereinafter, configurations and functions of various embodiments according to the present invention will be described with reference to FIGS. 1 to 4. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratios in the drawings do not necessarily match those described.

(First embodiment)
As shown in FIG. 1, pin-PD 1 as a pin-type light receiving element, n-type semiconductor layer 30, i-type semiconductor layer 31, and p-type semiconductor layer 32 as first to third semiconductor layers are formed on a semiconductor substrate 20. It is configured by sequentially stacking. The i-type semiconductor layer 31 and the p-type semiconductor layer 32 are each formed in a mesa shape, and integrally form a truncated cone-shaped first mesa portion. The p-type semiconductor layer 32 whose periphery forms the first mesa portion is thick only at the mesa periphery, and the light receiving region at the center of the mesa is formed thin to a predetermined thickness. In addition, the periphery of the n-type semiconductor layer 30 constitutes a second mesa portion having a truncated cone shape formed in a mesa shape. The second mesa portion is independent from the periphery of the n-type semiconductor layer 30 outside the bonding surface with the i-type semiconductor layer 31 below the bottom surface of the first mesa portion, without being continuous with the first mesa portion. It is composed.

  On the top surface of the second mesa portion, an n-type electrode layer 60 having a predetermined pattern is formed as a second electrode layer in ohmic contact with the n-type semiconductor layer 30. A p-type electrode layer 61 having a predetermined pattern as the first electrode layer is in ohmic contact with the p-type semiconductor layer 32 on the top surface of the thin p-type semiconductor layer 32 at the center of the first mesa portion. Is formed. The p-type semiconductor layer 32, i-type is formed on the top surface and the side wall including the thick and thin portions of the p-type semiconductor layer of the first mesa portion and on the top surface of the second mesa portion. A passivation semiconductor layer 40 is formed as a fourth semiconductor layer around the semiconductor layer 31 and the n-type semiconductor layer 30.

  Further, a first passivation insulator layer 80 is formed as an insulator layer covering the surface of the semiconductor substrate 20, the sidewall of the n-type semiconductor layer 30, and the surface of the passivation semiconductor layer 40. However, the first passivation insulator layer 80 has openings on the surfaces of the n-type electrode layer 60 and the p-type electrode layer 61, respectively.

The semiconductor substrate 20 is made of semi-insulating InP having a diameter of 3 inches and a thickness of 600 μm doped with Fe at a concentration of about 0.7 to 0.8 wt · ppm. The n-type semiconductor layer 30 is made of n-type GaInAs doped with Si as a first conductivity type impurity at a concentration of about 4 × 10 ¹⁸ cm ⁻³ and has a layer thickness of about 500 nm. In addition, as a material constituting the n-type semiconductor layer 30, a material that lattice matches with an InP substrate such as InP or GaInAsP may be used. The i-type semiconductor layer 31 is made of high-resistance i-type GaInAs that is not intentionally doped with impurities by using GaInAs as the first semiconductor material, and has a layer thickness of about 2.5 μm. However, in general, the i-type semiconductor layer 31 is composed of n ⁻ -type GaInAs having substantially the first conductivity type due to impurities contained at a relatively low concentration. The p-type semiconductor layer 32 uses p-type semiconductor doped with Zn as a second conductivity type impurity different from the first conductivity type at a concentration of about 1 × 10 ¹⁹ cm ⁻³ by using GaInAs as the first semiconductor material. The mesa portion peripheral region has a layer thickness h1 of about 300 nm, and the mesa central region, which is a light receiving region, has a layer thickness h2 of about 50 nm. In particular, the layer thickness h1 of the p-type semiconductor layer is desirably 200 nm or more in order to sufficiently suppress dark current. Conversely, as the thickness h1 of the p-type semiconductor layer increases, the device capacity also increases. Therefore, in order to suppress the increase in device capacity, it is desirable that the thickness be 500 nm or less. On the other hand, by reducing the thickness h2 of the p-type semiconductor layer, it is possible to improve the light receiving sensitivity and reduce the element capacitance, but at the same time, the element resistance increases. Therefore, the travel time for holes generated in the i-type semiconductor layer 31 to travel through the p-type semiconductor layer 32 and reach the p-type electrode layer 61 becomes longer, causing a decrease in sensitivity and a deterioration in frequency characteristics. Therefore, the layer thickness h2 of the p-type semiconductor layer is desirably 20 nm to 250 nm.

  In addition, the passivation semiconductor layer 40 is composed of high-resistance, i-type InP that is not intentionally doped with impurities by using InP as the second semiconductor material having a larger band gap energy than the first semiconductor material. Although the layer thickness is about 10 to 500 nm, it is desirable that the thickness be 300 nm or more so as to completely cover the mesa surface. The n-type electrode layer 60 is made of AuGe / Ni, and has thicknesses of about 100 nm and about 30 nm, respectively, for the AuGe region and the Ni region. The p-type electrode layer 61 is made of Ti / Pt / Au, and has thicknesses of about 20 nm, about 40 nm, and about 100 nm as thicknesses of the Ti region, the Pt region, and the Au region, respectively. The first passivation insulator layer 80 is made of SiN and has a layer thickness of about 100 to 200 nm.

  Here, the i-type semiconductor layer 31 and the p-type semiconductor layer 32 are both composed of GaInAs having a band gap energy of about 0.75 eV as the first semiconductor material, but have different conductivity types. The passivation semiconductor layer 40 is an InP having a band gap energy of about 1.35 eV as a second semiconductor material having a larger band gap energy than the first semiconductor material constituting the i-type semiconductor layer 31 and the p-type semiconductor layer 32. It has a high resistance.

Subsequently, a manufacturing process of the pin-PD 1 according to the first embodiment will be described. First, as shown in FIG. 3A, an n-type semiconductor layer 30 and an i-type semiconductor layer are formed on the surface of a semiconductor substrate 20 based on a normal metal organic vapor phase epitaxy (MOVPE) method. 31 and a p-type semiconductor layer 32 are sequentially stacked. Triethyl gallium (TEG) and tri-methyl indium (TMI) were used as Group III materials, and arsine (AsH ₃ ; Arsine) and phosphine (PH ₃ ; Phosphine) were used as Group V materials. . As a dopant impurity material, silane (Si ₂ H ₆ ) can be used for an n-type semiconductor, and diethylzinc (DEZ; Di-ethyl Zinc) can be used for a p-type semiconductor. A desired thickness, mixed crystal composition, and carrier concentration are realized by supplying the above gas at a predetermined flow rate as appropriate. The growth temperature of the n-type semiconductor layer 30 to the p-type semiconductor layer 32 may be set as appropriate, but it is preferably 600 ° C. to 700 ° C. for any layer in consideration of crystallinity.

Subsequently, as shown in FIG. 3B, a first mask having a circular pattern is formed on the first mesa portion forming region of the p-type semiconductor layer 32 based on a normal photolithography technique. Next, based on a normal wet etching method, the peripheral region of the p-type semiconductor layer 32 and the peripheral region of the i-type semiconductor layer 31 exposed from the first mask are formed into the i-type semiconductor layer 31 and the n-type semiconductor layer 30. It is removed with a phosphoric acid (H ₃ PO ₄ ) -based etching solution until the interface is exposed. For this reason, the p-type semiconductor layer 32 and the i-type semiconductor layer 31 are sequentially processed into a mesa shape, thereby forming a first mesa portion.

Subsequently, as shown in FIG. 3C, a concentric second mask is formed on the top surface of the mesa portion based on a normal photolithography technique. Next, based on a normal wet etching method, the p-type semiconductor layer 32 is removed from the mesa central region of the p-type semiconductor layer 32 exposed from the second mask with a phosphoric acid (H ₃ PO ₄ ) -based etching solution. Etching is performed leaving a predetermined thickness. Therefore, a concave shape 50 is formed by thinly etching only the p-type semiconductor layer 32 in the signal light receiving region at the center of the mesa while maintaining the original thick film at the mesa periphery of the p-type semiconductor layer 32. .

  Subsequently, as shown in FIG. 3D, the passivation is performed on each surface of the p-type semiconductor layer 32 and the i-type semiconductor layer 31, that is, at least around the first mesa portion, based on a normal MOVPE method. The semiconductor layer 40 is formed.

  Here, since the p-type semiconductor layer 32 and the i-type semiconductor layer 31 of the first mesa portion are composed of the same semiconductor material, GaInAs, the p-type semiconductor layer is formed when the passivation semiconductor layer 40 is formed. The treatment to be performed so as not to evaporate the elements from the constituent materials of the 32 and i-type semiconductor layers 31 is easy. That is, in order to prevent GaInAs from evaporating, the partial pressure of As in the reaction gas may be controlled. Therefore, the epitaxial growth of the passivation semiconductor layer 40 is good and easy around the p-type semiconductor layer 32 and the i-type semiconductor layer 31.

  If the p-type semiconductor layer 32 and the i-type semiconductor layer 31 of the first mesa portion are composed of different semiconductor materials, for example, if there are a plurality of semiconductor materials such as GaInAs and InP, The procedure to prevent the elements from evaporating is complicated. That is, in order to prevent the evaporation of GaInAs and InP, it is necessary to balance and control the partial pressure of As and the partial pressure of P in the reaction gas. Therefore, it is difficult to achieve good epitaxial growth of the passivation semiconductor layer 40 around the p-type semiconductor layer 32 and the i-type semiconductor layer 31. Therefore, the p-type semiconductor layer 32 and the i-type semiconductor layer 31 are made of the same semiconductor material. It is desirable to configure.

  Subsequently, the crystal interface between the n-type semiconductor layer 30, the i-type semiconductor layer 31, the p-type semiconductor layer 32, and the passivation semiconductor layer 40 formed on the surface of these layers is adjusted, and the interface state of the regrowth interface is adjusted. In order to further reduce, heat treatment is performed at a temperature of 550 to 700 ° C. for 90 minutes to 120 minutes. Thus, Zn is diffused and doped as an impurity of the second conductivity type from the p-type semiconductor layer 32 into each interface region of the passivation semiconductor layer 40 and the i-type semiconductor layer 31 bonded to the p-type semiconductor layer 32. Therefore, an impurity diffusion region is formed in each interface region of the passivation semiconductor layer 40 and the i-type semiconductor layer 31 bonded to the p-type semiconductor layer 32. Thus, in the vicinity of the heterojunction region between the passivation semiconductor layer 40 and the p-type semiconductor layer 32, the interface of the pn junction region between the n-type semiconductor layer 30 and the p-type semiconductor layer 32 is within the passivation semiconductor layer 40. Homozygous. Therefore, the leakage current that flows along the wall surfaces of the i-type semiconductor layer 31 and the p-type semiconductor layer 32 can be further reduced. The second conductivity type impurity diffused from the p-type semiconductor layer 32 to the passivation semiconductor layer 40 and the i-type semiconductor layer 31 is not necessarily limited to Zn. For example, Be, Mn, Cd Any element that exhibits the second conductivity type may be used, but an element that easily diffuses is preferable.

  Thereafter, as shown in FIG. 4A, a third mask having a predetermined pattern is formed on the surface of the passivation semiconductor layer 40, and the inner region of the passivation semiconductor layer 40 exposed from the third mask is formed with hydrochloric acid (HCl). ) Remove with an etching solution. As a result, a predetermined region of the p-type semiconductor layer 32 is exposed as a p-type electrode layer formation region. At the same time, a predetermined region of the n-type semiconductor layer 30 is exposed as an n-type electrode layer forming region. At this time, the second mesa portion formation region around the first mesa portion is also removed by the passivation semiconductor layer 40 formed on the n-type semiconductor layer 30, and the n-type semiconductor layer 30 is exposed.

Subsequently, as shown in FIG. 4B, a fourth mask having a circular pattern is formed on the second mesa portion formation region of the n-type semiconductor layer 30 based on a normal photolithography technique. Then, based on a normal wet etching method, the peripheral region of the n-type semiconductor layer 30 exposed from the fourth mask is removed with a phosphoric acid (H ₃ PO ₄ ) -based etching solution. As a result, the n-type semiconductor layer 30 is sequentially processed into a mesa shape to form a second mesa portion. In this step, element separation between an electronic element manufactured on the same substrate (not shown) and a mesa-type pin light receiving element is performed.

  After that, based on a normal wet etching method, the periphery of the n-type semiconductor layer 30, the i-type semiconductor layer 31, the p-type semiconductor layer 32, and the passivation semiconductor layer 40 is hydrochloric acid-based (HCl) -based or hydrofluoric acid (HF). Immerse in any cleaning solution in the system. As a result, the exposed surfaces of the n-type semiconductor layer 30, i-type semiconductor layer 31, p-type semiconductor layer 32, and passivation semiconductor layer 40 are cleaned by removing oxide films and various impurities.

  As a cleaning liquid for performing such surface treatment, the n-type semiconductor layer 30, the i-type semiconductor layer 31, the p-type semiconductor layer 32, and the semiconductor material constituting the passivation semiconductor layer 40 are hardly etched, It is desirable to react at a very low etching rate, and to react only with oxide films, various impurities, etc. existing on the surface of these semiconductor materials.

  Thereafter, as shown in FIG. 4C, the semiconductor substrate 20, the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type are formed on the basis of an ordinary plasma chemical vapor deposition (CVD) method. A first passivation insulator layer 80 is formed on each exposed surface of the semiconductor layer 32 and the passivation semiconductor layer 40.

  Further, a fifth mask having a predetermined pattern is formed on the surface of the first passivation insulator layer 80 based on a normal photolithography technique, and the first passivation insulator layer 80 exposed from the fifth mask is formed. Remove the inner region of. Thereby, the surfaces of the n-type semiconductor layer 30 and the p-type semiconductor layer 32 on which the n-type electrode layer 60 and the p-type electrode layer 61 are formed are exposed as various wiring layer formation regions, respectively.

  Next, a method for forming the n-type electrode layer 60 and the p-type electrode layer 61 in predetermined regions of the n-type semiconductor layer 30 and the p-type semiconductor layer 32 exposed in the above process will be described. A normal negative resist is applied, a sixth mask having a predetermined pattern is formed on the surface of the negative resist based on a normal photolithography technique, and a predetermined p-type semiconductor layer 32 exposed from the sixth mask is formed. A p-type electrode layer 61 is formed in the region based on a normal vacuum deposition method. Thereafter, the metal deposited in a region other than the region where the p-type electrode layer 61 is formed is simultaneously removed when the resist is removed using a normal lift-off method to form a p-type electrode pattern. Similarly, a normal negative resist is applied, a seventh mask having a predetermined pattern is formed on the surface of the negative resist based on a normal photolithography technique, and the n-type semiconductor layer exposed from the seventh mask is formed. The n-type electrode layer 60 is formed in the predetermined region where the n-type semiconductor layer 30 is exposed in the predetermined region 30 based on a normal vacuum deposition method. At this time, the metal deposited in the region other than the region where the n-type electrode layer 60 is formed is simultaneously removed when the resist is removed using a normal lift-off method to form an n-type pattern electrode, and FIG. The pin type light receiving element shown in FIG.

  In such a manufacturing process, the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 32 that are both composed of the first semiconductor material GaInAs are larger than the first semiconductor material. A passivation semiconductor layer 40 made of InP, which is a second semiconductor material having band gap energy, is formed. Thus, the passivation semiconductor layer 40 is formed as a wide band gap semiconductor layer on the surfaces of the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 32 made of the same semiconductor material.

  As a result, the second semiconductor material constituting the passivation semiconductor layer 40 maintains constant lattice matching with respect to the first semiconductor material constituting the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 32. Therefore, it is formed with relatively good crystallinity. Further, since the arrangement of the pn junction region between the n-type semiconductor layer 30 and the p-type semiconductor layer 32 does not depend on the process of forming the passivation semiconductor layer 40, the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 30. It is determined based only on the process of forming the type semiconductor layer 32. Therefore, the pn junction region can be completely covered with the passivation semiconductor layer 40.

  Next, the operation of pin-PD1 will be described. In this pin-PD1, since the thickness h2 of the light receiving region in the central portion of the mesa is reduced in the p-type semiconductor layer 32 of the first mesa portion, the i-type is changed from the p-type semiconductor layer 32 of the first mesa portion. Since the diffusion of zinc (Zn) impurities into the semiconductor layer 31 is suppressed, the depletion layer capacitance is reduced. Therefore, the CR time constant of the element is reduced and the response speed can be improved. Furthermore, in the p-type semiconductor layer 32 of the first mesa portion, the light absorption in the p-type semiconductor layer 32 with respect to the incident signal light is reduced by reducing the thickness h2 of the light receiving region in the central portion of the mesa, and the i-type semiconductor. Since the amount of signal light to the layer 31 increases, the generation of photocarriers in the i-type semiconductor layer 31 increases. As a result, the light receiving sensitivity of the mesa pin light receiving element is further improved.

  In addition, since the p-type semiconductor layer 32 at the center of the first mesa can be formed as a concave light receiving region, it can be formed up to the peripheral region of the first mesa portion, so that the light receiving area can be increased. Therefore, it is relatively easy to increase the light receiving sensitivity, and when the signal light is received through the optical fiber, the alignment between the optical fiber and the mesa pin-PD can be facilitated.

  On the other hand, as a second semiconductor material having a larger band gap energy than GaInAs, which is the first semiconductor material constituting the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 32, impurities are intentionally added to InP. A passivation semiconductor layer 40 that is not doped is formed around the n-type semiconductor layer 30, the i-type semiconductor layer 31, and the p-type semiconductor layer 32. As a result, the interface of the pn junction region between the n-type semiconductor layer 30 and the p-type semiconductor layer 32 becomes a heterojunction with respect to the good passivation semiconductor layer 40 with few interface states. Therefore, the leakage current flowing along the wall surfaces of the i-type semiconductor layer 31 and the p-type semiconductor layer 32 can be reduced.

  In particular, in the p-type semiconductor layer 32 in the first mesa portion, only the thickness h2 of the light receiving region in the mesa central portion is reduced, and the thickness h1 of the p-type semiconductor layer 32 in the mesa peripheral portion region is maintained at a predetermined thickness. While kept thick. Therefore, from the interface of the pn junction region between the n-type semiconductor layer 30 and the p-type semiconductor layer 32, the leakage current flowing along the respective wall surfaces of the i-type semiconductor layer 31 and the p-type semiconductor layer 32 can be sufficiently reduced. Since the distance to the top surface around the first mesa portion of the p-type semiconductor layer 32 can be made sufficiently large, device characteristics can be improved based on suppression of dark current.

(Second Embodiment)
Next, a second embodiment of the pin type light receiving element according to the present invention will be described. As shown in FIG. 2, pin-PD2 as a pin-type light receiving element is configured in substantially the same manner as pin-PD1 of the first embodiment. However, the light-receiving region in the central portion of the mesa that has been thinned by etching into the concave shape of the p-type semiconductor layer 32 in the first mesa portion has a smaller diameter than the pin-PD1 of the first embodiment, and the p-type electrode. It is formed inside the layer 61.

  The p-type electrode layer 61 of this predetermined pattern is in ohmic contact with the p-type semiconductor layer 32 on the top surface of the thick p-type semiconductor layer 32 around the first mesa portion as the second electrode layer. Is formed.

  Next, the manufacturing process of pin-PD2 is demonstrated. This pin-PD2 is manufactured in substantially the same manner as the pin-PD1 of the first embodiment. However, in the pin-PD1, in the step of etching only the mesa central region of the p-type semiconductor layer 32 on the top of the first mesa portion, the pin-PD1 is formed on the top surface of the first mesa portion as shown in FIG. The concentric second mask thus formed has a relatively large concentric pattern. As a result, in the subsequent etching process, the p-type semiconductor layer 32 is thinly etched to the vicinity of the periphery of the mesa portion, and a relatively large concentric concave shape 50 is formed. On the other hand, in pin-PD2, the concentric second mask formed on the top surface of the first mesa portion is the mesa center region of the p-type semiconductor layer 32 exposed from the second mask. A concave shape formed in the etching step has a small diameter pattern. Accordingly, in the subsequent p-type electrode layer forming step, the p-type electrode layer 61 of the p-type semiconductor layer 32 is only formed in a region maintaining the thick film around the mesa remaining without being etched. Can be secured.

  Next, the operation of pin-PD2 will be described. This pin-PD2 acts in substantially the same manner as the pin-PD1 of the first embodiment. However, the pn junction region between the p-type electrode layer 61 and the n-type semiconductor layer 30 and the p-type semiconductor layer 32 is formed by forming an electrode in the peripheral portion where the thickness of the p-type semiconductor layer of the first mesa portion is thick. Therefore, the dark current can be further reduced as compared with the pin-PD1 of the first embodiment. Furthermore, by increasing the thickness of the p-type semiconductor layer under the p-type electrode layer, the device capacity can be further reduced. The element characteristics can be remarkably improved based on the reduction of the element capacitance and the suppression of the dark current.

  Embodiments according to the present invention will be described below with reference to FIGS. First, in order to investigate the relationship between the structure and element characteristics of a mesa-type pin light-receiving element, the present inventors investigated the thickness of the p-type semiconductor layer of the mesa-type pin light-receiving element, the element capacity of the pin light-receiving element, the light-receiving sensitivity, An experimental study was conducted on the relationship between dark current. The results will be described below.

  In the conventional pin-type light receiving element shown in FIG. 11, the signal light is greatly absorbed by the p-type semiconductor layer. Therefore, the signal light in the p-type semiconductor layer is reduced by reducing the thickness of the p-type semiconductor layer. The light receiving sensitivity is improved by increasing the amount of light that reaches the i-type semiconductor layer where photocarriers mainly composed of electrons and holes are mainly generated. Therefore, in order to improve the light receiving sensitivity of the pin type light receiving element, a large number of pin type light receiving elements having different thicknesses of the p type semiconductor layer were manufactured, and the element characteristics were evaluated.

  FIG. 9 shows an experimental result on the relationship between the light receiving sensitivity and the thickness of the p-type semiconductor layer in the pin-type light receiving element using GaInAs as the first semiconductor material. In addition, FIG. 9 also shows the relationship of the element capacitance to the thickness of the p-type semiconductor layer. Here, in FIG. 9, the horizontal axis indicates the thickness of the p-type semiconductor layer, and the vertical axis indicates the light receiving sensitivity and capacitance value of the element. The light receiving sensitivity of the pin light receiving element is indicated by a round black dot, and the element capacitance is indicated by a square black dot. FIG. 10 shows the experimental results regarding the relationship between the dark current and the thickness of the p-type semiconductor layer. The light receiving diameter of the pin type light receiving element at this time is 100 μm, and the measurement condition is that the applied voltage at the time of measuring the element capacitance is −3 V, the applied voltage at the time of dark current measurement is −5 V, and the element is placed in a dark place. The values obtained were plotted. In FIG. 10, similarly, the horizontal axis indicates the thickness of the p-type semiconductor layer, and the vertical axis indicates the dark current value.

  As shown in FIG. 9, it can be seen that the light receiving sensitivity is improved by reducing the thickness of the p-type semiconductor layer in the mesa region. Furthermore, it was found that the element capacity of the element, which was a problem of the conventional pin type light receiving element shown in FIG. By reducing the thickness of the p-type -GaInAs layer from the conventional 250 nm to 50 nm, the element capacitance of the element could be reduced to about 2/3. This is presumably because the diffusion of zinc (Zn), which is an impurity doped in the p-type semiconductor layer, into the i-type semiconductor layer is suppressed by reducing the thickness of the p-type semiconductor layer.

  As described above, by reducing the thickness of the p-type semiconductor layer in the mesa region, it is possible to improve the light-receiving sensitivity of the pin-type light-receiving element and improve the element characteristics based on the reduction of the element capacitance. In order to reduce the element capacity and improve the light receiving sensitivity of this element, it is only necessary to reduce the thickness of the window region at the center of the mesa for receiving signal light in the mesa pin light receiving element.

  Next, the relationship between the thickness of the p-type semiconductor layer and the dark current was investigated. As shown in FIG. 10, when the thickness of the p-type semiconductor layer in the mesa region is uniformly reduced, the dark current of the element gradually increases.

  However, in the pin-type light receiving elements of the first and second embodiments according to the present invention, an increase in current is suppressed by maintaining the thickness of the p-type semiconductor layer around the mesa portion at a predetermined thickness or more. In addition, it has been found that the device characteristics can be improved based on the reduction of the device capacity and the improvement of the light receiving sensitivity by reducing the thickness of the p-type semiconductor layer.

  The pin-type light receiving element of the first and second embodiments in which the thickness h1 of the p-type semiconductor layer around the first mesa portion is increased and the thickness h2 of the p-type semiconductor layer in the center of the mesa portion is decreased. On the other hand, in order to similarly examine the relationship between the structure and the element characteristics of the pin light receiving element, the thickness of the p type semiconductor layer of the pin light receiving element of the first embodiment and the second embodiment and the element of the pin light receiving element. An experimental study was conducted on the relationship between capacitance, light receiving sensitivity, and dark current. The results will be described below.

  In the pin type light receiving element formed in a concave shape by reducing the thickness of the p type semiconductor layer in the light receiving region formed in the central part of the first mesa substantially the same as described in the first and second embodiments above. FIG. 5 shows the result of measuring the element capacitance value when the thickness h2 of the p-type semiconductor layer at the center of the first mesa is changed. The measured light receiving diameter of each pin type light receiving element is 50 μm. The measurement was performed by applying a bias voltage of −3 V to the element. In FIG. 5, the horizontal axis indicates the thickness h2 of the p-type semiconductor layer at the center of the mesa, and the vertical axis indicates the capacitance value of the element. Also, the experimental result of the pin type light receiving element of the first embodiment is indicated by a round black point, and the experimental result of the pin type light receiving element of the second embodiment is indicated by a round white point.

  As shown in FIG. 5, in both the pin type light receiving elements of the first embodiment and the second embodiment, by reducing the thickness h2 of the p type semiconductor layer at the center of the first mesa, The element capacity is reduced. The typical value of the element capacitance of a conventional pin type light receiving element with an InP passivation semiconductor layer having a uniform thickness of 250 nm and a thick film structure of the p-type semiconductor layer of the conventional first mesa portion is 0.47 pF. is there. Therefore, for example, the element capacity of the pin-type light receiving element of the first embodiment in which the thickness h2 of the p-type semiconductor layer at the center of the first mesa is 50 nm is the pin-type light receiving with the conventional InP passivation semiconductor layer. It is reduced to about 87% of the element. In particular, in the pin type light receiving element of the second embodiment, the element capacitance is further reduced by about 2% compared to the pin type light receiving element of the first embodiment.

  From the above experimental results, in both the pin-type light-receiving elements of the first embodiment and the second embodiment, the element capacitance of the element is reduced by reducing the thickness h2 of the p-type semiconductor layer at the center of the first mesa. It can be seen that is reduced.

  Similarly, FIG. 6 shows the result of measurement of the relationship between the light receiving sensitivity and the thickness h2 of the p-type semiconductor layer at the center of the first mesa using the pin light receiving element described in the above embodiment. In FIG. 6, the horizontal axis indicates the thickness h2 of the p-type semiconductor layer in the center of the mesa, and the vertical axis indicates the light receiving sensitivity value of the pin-type light receiving element. Also, the experimental result of the pin type light receiving element of the first embodiment is indicated by a round black point, and the experimental result of the pin type light receiving element of the second embodiment is indicated by a round white point.

  As shown in FIG. 6, the thickness h2 of the p-type semiconductor layer at the center of the first mesa is reduced in almost the same manner in both of the pin-type light receiving elements of the first and second embodiments. As a result, the light receiving sensitivity of the pin type light receiving element is greatly improved. In particular, it can be seen that a large light receiving sensitivity can be obtained by setting the thickness h2 of the p-type semiconductor layer in the center of the mesa to about 125 nm or less.

  Next, only the thickness of the p-type semiconductor layer in the light-receiving region at the center of the first mesa is compared with the mesa-type pin light-receiving element substantially the same as described in the first and second embodiments. The thickness of the p-type semiconductor layer in the peripheral region of the mesa portion is reduced, and the thickness of the p-type semiconductor layer in the conventional mesa portion is uniform so that the thickness of the p-type semiconductor layer in the conventional mesa portion is uniform. An experiment was conducted to confirm that the dark current was suppressed in the same manner as the pin type light receiving element including the semiconductor layer. Here, as two types of contrasting pin type light receiving elements, only the thickness of the p type semiconductor layer in the light receiving region formed in the central portion of the first mesa is substantially the same as the description in the second embodiment up to h2 = 90 nm. A thin pin-type light receiving element formed in a concave shape and a different one from the description of the first embodiment only in that the thickness of the p-type semiconductor layer of the first mesa portion is uniform were each prototyped.

  FIG. 7 shows the result of measuring each current-voltage characteristic after installing these two types of pin type light receiving elements in a dark place. In FIG. 7, the voltage value of the bias voltage is set on the horizontal axis, and the current value of the dark current is set on the vertical axis. Further, only the thickness of the p-type semiconductor layer in the light-receiving region formed in the center of the first mesa is thinned, and the characteristic curve of the pin-type light-receiving element formed in a concave shape is shown by a solid line, and the thickness of the conventional p-type semiconductor layer is A characteristic curve of the uniform and thick pin type light receiving element is indicated by a dotted line.

  As shown in FIG. 7, the thickness of the p-type semiconductor layer in the light receiving region formed at the center of the first mesa is reduced, and the peripheral region of the mesa is left as a thick film. Low dark current characteristics similar to those of the pin-type light-receiving element having a uniform InP passivation semiconductor layer with a uniform thickness of the p-type semiconductor layer in the mesa portion are obtained. Here, the current-voltage characteristic of the pin type light receiving element of the second embodiment is shown, but the same low dark current characteristic is also obtained for the pin type light receiving element of the first embodiment.

  Therefore, in the pin type light receiving element of the first embodiment and the second embodiment of the present application, the pin including the InP passivation semiconductor layer in which the thickness of the p type semiconductor layer of the conventional mesa portion is uniform and is thick. As with the type light receiving element, it can be seen that the generation of dark current is suppressed based on the formation of the passivation semiconductor layer.

  Similar to FIGS. 5 and 6, FIG. 8 shows the result of measurement of the relationship between the dark current and the thickness h <b> 2 of the p-type semiconductor layer at the center of the first mesa using the pin light-receiving element described in the above embodiment. Show. The measurement was performed by applying a bias voltage of −5 V to the element. In FIG. 8, the horizontal axis represents the thickness h2 of the p-type semiconductor layer in the center of the mesa, and the vertical axis represents the dark current value of the pin-type light receiving element. Also, the experimental result of the pin type light receiving element of the first embodiment is indicated by a round black point, and the experimental result of the pin type light receiving element of the second embodiment is indicated by a round white point.

  As shown in FIG. 8, in the pin type light receiving element of the second embodiment, in addition to the reduction of dark current based on the formation of the passivation semiconductor layer similar to the pin type light receiving element of the first embodiment, the mesa portion It can be seen that the dark current is further reduced by forming the electrode in the peripheral portion where the p-type semiconductor layer is thick.

  DESCRIPTION OF SYMBOLS 1, 2 ... Pin type light receiving element, 20 ... Semiconductor substrate, 30 ... 1st semiconductor layer, 31 ... 2nd semiconductor layer, 32 ... 3rd semiconductor layer, 40 ... 4th semiconductor layer, 60 ... 1st Electrode layer, 61... Second electrode layer, 80... First passivation insulator layer, h1... Thickness of third semiconductor layer in mesa peripheral portion, h2... Thickness of third semiconductor layer in mesa central portion

Claims (8)

A semiconductor substrate;
A first semiconductor layer formed on the semiconductor substrate and doped with an impurity of the first conductivity type;
A second semiconductor layer formed on the first semiconductor layer and configured without intentionally doping impurities in the first semiconductor material;
A third semiconductor layer formed on the second semiconductor layer, wherein the first semiconductor material is doped with an impurity of a second conductivity type different from the first conductivity type; The second semiconductor layer and the third semiconductor layer form one mesa portion, the thickness of the second semiconductor layer is uniform in the mesa portion, and the third semiconductor layer is the mesa portion. The thickness around the part is formed thicker than the thickness at the center of the mesa part,
A fourth semiconductor material formed so as to cover the first to third semiconductor layers and having a larger band gap energy than the first semiconductor material is formed without intentionally doping impurities. A pin type light receiving element comprising: a semiconductor layer.   2. The pin type light receiving element according to claim 1, wherein the first semiconductor material is GaInAs and the second semiconductor material is InP. 3.   3. The pin type light receiving element according to claim 1, further comprising an insulator layer formed to cover the semiconductor substrate and the first to fourth semiconductor layers.   4. The pin type light receiving element according to claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type. 5.   The first electrode layer formed in ohmic contact with the third semiconductor layer in a region where the thickness of the third semiconductor layer is thin. The pin type light receiving element as described in one.   5. The device according to claim 1, further comprising: a first electrode layer formed in ohmic contact with the third semiconductor layer in a region where the third semiconductor layer is thick. The pin type light receiving element as described in one.   7. The pin according to claim 1, wherein in the third semiconductor layer, a thickness h1 around the mesa portion is in a range of 0.2 μm ≦ h1 ≦ 0.5 μm. Type light receiving element.   8. The pin according to claim 1, wherein in the third semiconductor layer, the thickness h <b> 2 at the center of the mesa portion is in a range of 0.02 μm <h <b> 2 ≦ 0.25 μm. Type light receiving element.

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