JP2010232215A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem: it is difficult to establish compatibility between the high reliability of an n-type MIS transistor and the high performance of a p-type MIS transistor when a sidewall width is the same in the n-type MIS transistor and the p-type MIS transistor. <P>SOLUTION: A semiconductor device includes the n-type MIS transistor and the p-type MIS transistor. The n-type MIS transistor includes a first gate insulating film 13a and a first gate insulating electrode 14a which are sequentially formed on a first active region 10a in the semiconductor substrate 10, and a first side wall 16a formed on the side surface of the first gate electrode 14a. The p-type MIS transistor includes a second gate insulating film 13b and a second gate electrode 14b which are sequentially formed on a second active region 10b in the semiconductor substrate 10, and a second side wall 16b formed on the side surface of the second gate electrode 14b. The second side wall 16b has a side wall width smaller than that of the first side wall 16a. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a sidewall on a side surface of a gate electrode and a manufacturing method thereof.

  Along with the high integration and high speed of semiconductor integrated devices, miniaturization of MISFET (hereinafter referred to as “MIS transistor”) has been promoted, and in particular, the gate length has been remarkably miniaturized in recent years.

  On the other hand, in such a semiconductor device, a sidewall made of an insulating film is generally provided on the side surface of the gate electrode for the purpose of suppressing deterioration of the transistor due to hot carriers. By forming an extension region extending from the drain region in the region immediately below the sidewall, the electric field concentration in this region is alleviated and the occurrence of hot carry is suppressed. A semiconductor device having a conventional CMIS (Content Management Interoperability Services) structure will be described below.

  5A and 5B are a plan view and a cross-sectional view showing a conventional semiconductor device. In FIG. 5A, “nMIS” shown on the upper side indicates an n-type MIS formation region where an n-type MIS transistor is formed, and “pMIS” shown on the lower side indicates that a p-type MIS transistor is formed. A p-type MIS formation region is shown. 5B is a cross-sectional view taken along the line AA in FIG. 5A, and the right side of FIG. 5B is a cross-sectional view taken along the line BB in FIG. 5A. In FIG. 5A, the metal silicide film 109a formed on the gate electrode 104a is omitted without illustration, and the metal silicide film 109b formed on the gate electrode 104b is not shown. Omitted. In FIG. 5B, the contact plugs 111a and 111b illustrated in FIG. 5A are not shown.

  The semiconductor device includes an n-type MIS transistor provided in the first active region 100a and a p-type MIS transistor provided in the second active region 100b. An element isolation region 101 in which an insulating film is embedded is formed so as to partition the first active region 100a in which the 102a is formed and the second active region 100b in which the n-type well region 102b is formed. ing.

  The n-type MIS transistor includes a gate insulating film 103a and a gate electrode 104a formed on the first active region 100a, a sidewall 106a formed on the side surface of the gate electrode 104a, and a side in the first active region 100a. An n-type extension region 105a formed in a region immediately below the wall 106a, an n-type source / drain region 108a formed in a region below the sidewall 106a in the first active region 100a, a gate electrode 104a, and an n-type A metal silicide film 109a formed on the source / drain region 108a and a contact plug 111a provided to connect to the metal silicide film 109a on the n-type source / drain region 108a are provided.

  On the other hand, the p-type MIS transistor includes a gate insulating film 103b and a gate electrode 104b formed on the second active region 100b, a sidewall 106b formed on the side surface of the gate electrode 104b, and a second active region 100b. A p-type extension region 105b formed in a region immediately below the sidewall 106b, a p-type source / drain region 108b formed in a region below the sidewall 106b in the second active region 100b, a gate electrode 104b, A metal silicide film 109b formed on the p-type source / drain region 108b and a contact plug 111b provided to connect to the metal silicide film 109b on the p-type source / drain region 108b are provided.

In the semiconductor device having such a structure, low-concentration extension regions 105a and 105b extending from the high-concentration source / drain regions 108a and 108b are provided in regions immediately below the sidewalls 106a and 106b, respectively. Therefore, the hot carrier effect can be suppressed.
JP 2008-205385 A

  However, in the conventional semiconductor device, when the side wall widths of the n-type MIS transistor and the p-type MIS transistor are reduced with the miniaturization of the gate length, the following problems have become apparent.

  In the conventional semiconductor device, since the sidewall of the n-type MIS transistor and the sidewall of the p-type MIS transistor are formed in the same process, they are formed with the same sidewall width. When the sidewall width is small, the driving power of the p-type MIS transistor increases, but there is a problem that the substrate current, which is one of the indexes indicating the amount of hot carriers generated in the n-type MIS transistor, increases. On the other hand, when the sidewall width is large, the substrate current in the n-type MIS transistor is reduced, but there is a problem in that the driving power of the p-type MIS transistor is reduced.

  In view of the above, an object of the present invention is to provide a semiconductor device capable of achieving both high reliability of an n-type MIS transistor and high performance of a p-type MIS transistor, and a method for manufacturing the same.

  In order to achieve the above object, the present inventors have studied the dependency of the substrate width on the sidewall width and the dependency of the transistor driving force on the sidewall width, and as a result, have obtained the following findings. Regarding the dependence of the substrate current on the sidewall width, the substrate current in the n-type MIS transistor increases as the sidewall width decreases, whereas the substrate current in the p-type MIS transistor does not increase and depends on the sidewall width. It was found that the substrate current value was two to three orders of magnitude lower than that of the n-type MIS transistor. Regarding the sidewall width dependency on the driving power of the transistor, the driving power in the p-type MIS transistor increases as the side wall width decreases, whereas the driving power in the n-type MIS transistor does not increase. It was found that there was no wall width dependency.

  From the above, by reducing the side wall width in the p-type MIS transistor compared to the side wall width in the n-type MIS transistor, high reliability is achieved by reducing the substrate current in the n-type MIS transistor, and in the p-type MIS transistor. High performance can be achieved at the same time by increasing the driving force.

  Specifically, the semiconductor device according to the present invention includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate insulating film formed on a first active region in a semiconductor substrate, a first gate electrode formed on the first gate insulating film, and a first gate electrode. And a first sidewall formed on the side surface. The p-type MIS transistor includes a second gate insulating film formed on the second active region in the semiconductor substrate, a second gate electrode formed on the second gate insulating film, and a second gate electrode. And a second sidewall formed on the side surface. The second sidewall has a smaller sidewall width than the first sidewall.

  With the above configuration, since the substrate current in the n-type MIS transistor can be reduced, the hot carrier resistance in the n-type transistor can be improved, and thus the reliability of the n-type MIS transistor can be improved. In addition, since the driving force of the p-type MIS transistor can be increased, the performance of the p-type MIS transistor can be improved.

  In this specification, the “side wall width” is the maximum width of the distance from the side surface of the gate electrode to the surface of the side wall.

  In the semiconductor device according to the present invention, the n-type extension region formed in the region below the side of the first gate electrode in the first active region and the lower side outside the first sidewall in the first active region. An n-type source / drain region formed in the region, a p-type extension region formed in a region below the second gate electrode in the second active region, and a second sidewall in the second active region It is preferable to further include a p-type source / drain region formed in a region below the outer side of the.

  With the above structure, electric field concentration in the region immediately below the sidewall can be reduced, so that generation of hot carriers in the semiconductor device can be further suppressed.

  The semiconductor device according to the present invention preferably further includes a p-type SiGe layer embedded in a recess portion provided above the p-type source / drain region in the second active region.

  With the above configuration, compressive stress can be applied in the gate length direction in the channel region of the p-type MIS transistor, so that distortion occurs in the channel region of the p-type MIS transistor. Thereby, the driving power of the p-type MIS transistor can be further improved.

  In a preferred embodiment described later, the n-type MIS transistor is a drive transistor in an SRAM (Static Random Access Memory) memory cell, and the p-type MIS transistor is a load transistor in an SRAM memory cell.

  The method for manufacturing a semiconductor device according to the present invention includes an n-type MIS transistor having a first gate electrode on a first gate insulating film and a p-type MIS transistor having a second gate electrode on a second gate insulating film. A method for manufacturing a semiconductor device comprising: Specifically, a step (a) of forming a first active region and a second active region surrounded by an element isolation region on a semiconductor substrate, a first gate insulating film and a first active region on the first active region A step (b) of forming a first gate electrode and forming a second gate insulating film and a second gate electrode on the second active region; and a first gate electrode on the side surface of the first gate electrode. Forming a sidewall and forming a second sidewall having the same sidewall width as the first sidewall on the side surface of the second gate electrode; and after the step (c), A step (d) in which the sidewall width of the second sidewall is made smaller than the sidewall width of the first sidewall by etching the second sidewall.

  In the above manufacturing method, the hot carrier resistance of the n-type MIS transistor can be improved, and the driving force of the p-type MIS transistor can be increased. Therefore, a semiconductor device including an n-type MIS transistor with high reliability and a p-type MIS transistor with excellent performance can be manufactured.

  In the method for manufacturing a semiconductor device according to the present invention, after the step (b) and before the step (c), an n-type extension region is formed in a region laterally below the first gate electrode in the first active region. On the other hand, it is preferable to include a step (e) of forming a p-type extension region in a region below the second gate electrode in the second active region, and after the step (d), the first active region is provided. An n-type source / drain region is formed in a region below the first sidewall in the active region, while a p-type source / drain region is formed in a region below the second sidewall in the second active region. It is preferable to further include a step (f) of forming.

  In the above manufacturing method, electric field concentration in the region directly under the sidewall can be relaxed, so that a semiconductor device in which the generation of hot carriers is further suppressed can be manufactured.

  In some cases, after the step (f), a metal silicide film is formed on the p-type source / drain region and a contact plug connected to the metal silicide film is formed. In this case, since the side wall width in the p-type MIS transistor is smaller than the side wall width in the n-type MIS transistor, even if the contact plug is formed so as to be shifted toward the second gate electrode, the contact plug is formed in the p-type extension. It can suppress forming in direct contact with a part of region. Therefore, an increase in source contact resistance and an increase in leakage current can be suppressed.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, the second sidewall in the p-type MIS transistor has a smaller sidewall width than the first sidewall in the n-type MIS transistor. The carrier resistance can be improved and the driving force of the p-type MIS transistor can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. Moreover, below, the same code | symbol may be attached | subjected to the same member and the description may be abbreviate | omitted.

<< First Embodiment >>
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. FIGS. 1A to 1F are cross-sectional views showing a method of manufacturing a semiconductor device according to this embodiment in the order of steps, and are main-portion cross-sectional views in the gate length direction. In the figure, “nMIS” shown on the left side indicates an n-type MIS formation region where an n-type MIS transistor is formed, and “pMIS” shown on the right side indicates a p-type MIS formation where a p-type MIS transistor is formed. Indicates the area.

  First, as shown in FIG. 1A, an element isolation in which an insulating film is embedded in a trench on a semiconductor substrate 10 made of, for example, p-type silicon by, for example, an embedded element isolation (Shallow Trench Isolation: STI) method. The region 11 is selectively formed. As a result, the first active region 10 a made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the n-type MIS formation region, and the p-type MIS formation region is surrounded by the element isolation region 11. A second active region 10b made of the semiconductor substrate 10 is formed (step (a)). Thereafter, a p-type impurity such as B (boron), for example, is implanted into the n-type MIS formation region in the semiconductor substrate 10 by lithography and ion implantation, while, for example, P ( An n-type impurity such as phosphorus is implanted. Thereafter, heat treatment is performed on the semiconductor substrate 10. As a result, the p-type well region 12 a is formed in the n-type MIS formation region in the semiconductor substrate 10, while the n-type well region 12 b is formed in the p-type MIS formation region in the semiconductor substrate 10.

  Thereafter, a gate insulating film forming film (a film serving as a gate insulating film) and a silicon film made of a polysilicon film are sequentially formed on the semiconductor substrate 10, and then P (phosphorus) or As While an n-type impurity such as (arsenic) is ion-implanted, a p-type impurity such as B (boron) is ion-implanted into the silicon film in the p-type MIS formation region. Thereafter, a resist (not shown) having a gate pattern shape is formed on the silicon film by photolithography, and then the silicon film and the gate insulating film formation film are patterned by dry etching using the resist as a mask. Thus, the first gate insulating film 13a and the first gate electrode 14a made of n-type silicon are sequentially formed on the first active region 10a in the n-type MIS formation region, and the second in the p-type MIS formation region. A second gate insulating film 13b and a second gate electrode 14b made of p-type silicon are sequentially formed on the active region 10b (step (b)). Then, the resist is removed.

Thereafter, a resist (not shown) that opens the n-type MIS formation region and covers the p-type MIS formation region is formed on the semiconductor substrate 10, and the first gate is formed in the first active region 10 a of the n-type MIS formation region. For example, an n-type impurity such as As (arsenic) is implanted using the electrode 14a as a mask. Thus, an n-type extension region 15a having a relatively shallow junction depth is formed in a self-aligned manner in a region below the first gate electrode 14a in the first active region 10a (step (e)). Further, using the first gate electrode 14a as a mask, for example, B (boron), In (indium), or p-type impurities such as B and I are implanted. As a result, a p-type pocket region (not shown) is formed in a self-aligned manner below the n-type extension region 15a in the first active region 10a. Thereafter, the resist is removed. On the other hand, a resist (not shown) that covers the n-type MIS formation region and opens the p-type MIS formation region is formed on the semiconductor substrate 10, and a second gate is formed in the second active region 10b of the p-type MIS formation region. A p-type impurity such as B or BF ₂ is implanted using the electrode 14b as a mask. Thus, a p-type extension region 15b having a relatively shallow junction depth is formed in a self-aligned manner in a region below the second gate electrode 14b in the second active region 10b (step (e)). Further, an n-type impurity such as P or As is implanted using the second gate electrode 14b as a mask. As a result, an n-type pocket region (not shown) is formed in a self-aligned manner below the p-type extension region 15b in the second active region 10b. Thereafter, the resist is removed. Here, after forming offset spacers on the side surfaces of the first gate electrode 14a and the second gate electrode 14b, ion implantation for forming extension regions and pocket regions may be performed.

  Next, as shown in FIG. 1B, a silicon oxide film having a thickness of, for example, 10 nm and a silicon oxide film are formed on the entire surface of the semiconductor substrate 10 by, eg, CVD (Chemical Vapor Deposition). An insulating film 16 made of a silicon nitride film having a thickness of 30 nm is formed.

  Next, as shown in FIG. 1C, anisotropic etching is performed on the insulating film 16. Thus, the first sidewall 16a is formed on the side surface of the first gate electrode 14a, and the second sidewall 16b is formed on the side surface of the second gate electrode 14b. At this time, the sidewall width d1 of the first sidewall 16a is formed with the same width (d1 = d2) as the sidewall width d2 of the second sidewall 16b, for example, 40 nm (step (c)).

  Next, as shown in FIG. 1D, a resist 17 is formed on the semiconductor substrate 10 so as to open the p-type MIS formation region and cover the n-type MIS formation region, and then further to the second sidewall 16b. Anisotropic etching is performed. Thereby, the sidewall width d2 of the second sidewall 16b is made narrower than the sidewall width d1 of the first sidewall 16a (step (d)). For example, the sidewall width d1 of the first sidewall 16a is 40 nm, whereas the sidewall width d2 of the second sidewall 16b is 36 nm. Thereafter, the resist 17 is removed.

Next, as shown in FIG. 1E, a resist (not shown) that opens the n-type MIS formation region and covers the p-type MIS formation region is formed on the semiconductor substrate 10. An n-type impurity such as As or As and P is implanted into one active region 10a using the first gate electrode 14a and the first sidewall 16a as a mask. Thereafter, the resist is removed. Thereafter, a resist (not shown) that covers the n-type MIS formation region and opens the p-type MIS formation region is formed on the semiconductor substrate 10, and the second gate is formed in the second active region 10b of the p-type MIS formation region. A p-type impurity such as B or B and BF ₂ is implanted using the electrode 14b and the second sidewall 16b as a mask. Thereafter, after removing the resist, the semiconductor substrate 10 is subjected to heat treatment. As a result, the n-type source / drain having a junction depth deeper than the junction depth of the n-type extension region 15a in a region outside the first sidewall 16a in the first active region 10a of the n-type MIS formation region. While the region 18a is formed in a self-aligned manner, a junction deeper than the junction depth of the p-type extension region 15b is formed in a region outside the second sidewall 16b in the second active region 10b of the p-type MIS formation region. A p-type source / drain region 18b having a depth is formed in a self-aligned manner (step (f)).

  Next, as shown in FIG. 1F, the upper portions of the first gate electrode 14a and the n-type source / drain region 18a are silicided to form a metal silicide film 19a, and the second gate electrodes 14b and p Each upper part of the type source / drain region 18b is silicided to form a metal silicide film 19b. Thereafter, after forming an interlayer insulating film 20 on the semiconductor substrate 10, a contact plug 21a that penetrates the interlayer insulating film 20 and reaches the metal silicide film 19a on the n-type source / drain region 18a is formed, and the interlayer insulating film A contact plug 21b that penetrates 20 and reaches the metal silicide film 19b on the p-type source / drain region 18b is formed. Thereafter, metal wiring (not shown) connected to the contact plugs 21 a and 21 b is formed on the interlayer insulating film 20.

  As described above, the semiconductor device according to the present embodiment, that is, the n-type MIS transistor having the first sidewall 16a formed with the sidewall width d1 on the side surface of the first gate electrode 14a, and the second A p-type MIS transistor having a second sidewall 16b formed with a sidewall width d2 smaller than the sidewall width d1 of the first sidewall 16a on the side surface of the gate electrode 14b is manufactured. can do.

  Hereinafter, the structure of the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 2 is a plan view showing the semiconductor device according to the present embodiment. In FIG. 2, the metal silicide film 19a formed on the first gate electrode 14a is omitted without being shown, and the metal silicide film 19b formed on the second gate electrode 14b is illustrated. It is omitted without being shown. In FIG. 2, “nMIS” shown on the upper side indicates an n-type MIS formation region where an n-type MIS transistor is formed, and “pMIS” shown on the lower side indicates a p-type where a p-type MIS transistor is formed. A MIS formation region is shown. Further, the left side of FIG. 1 (f) is a cross-sectional view taken along the line AA in FIG. 2, and the right side of FIG. 1 (f) is a cross-sectional view taken along the line BB in FIG.

  As shown in FIG. 1F, in the upper part of the semiconductor substrate 10, an element isolation region in which an insulating film is embedded in a trench so as to partition the first active region 10a and the second active region 10b. 11 is formed. The semiconductor device includes an n-type MIS transistor provided in the first active region 10a and a p-type MIS transistor provided in the second active region 10b.

  Here, as shown in FIG. 1F, the n-type MIS transistor is formed on the first gate insulating film 13a formed on the first active region 10a and on the first gate insulating film 13a. The first gate electrode 14a, the first sidewall 16a formed on the side surface of the first gate electrode 14a with the sidewall width d1, and the side of the first gate electrode 14a in the first active region 10a The n-type extension region 15a formed in the lower region and the outer region of the first active region 10a on the outer side of the first sidewall 16a and having a deeper junction depth than the n-type extension region 15a. n-type source / drain region 18a, metal silicide film 19a formed on n-type source / drain region 18a and first gate electrode 14a, and first gate electrode 1 An interlayer insulating film 20 formed on a, on the n-type source drain region 18a, and a contact plug 21a provided through the interlayer insulating film 20 to be connected to the metal silicide film 19a.

  On the other hand, as shown in FIG. 1F, the p-type MIS transistor is formed on the second gate insulating film 13b and the second gate insulating film 13b formed on the second active region 10b. A second gate electrode 14b; a second sidewall 16b formed on the side surface of the second gate electrode 14b with a sidewall width d2 smaller than the sidewall width d1 of the first sidewall 16a; The p-type extension region 15b formed in the region below the second gate electrode 14b in the active region 10b and the region outside the second sidewall 16b in the second active region 10b. The p-type source / drain region 18b having a junction depth deeper than that of the p-type extension region 15b, the p-type source / drain region 18b, and the second gate electrode 14b. The metal silicide film 19b formed on the second gate electrode 14b, the interlayer insulating film 20 formed on the second gate electrode 14b, and the p-type source / drain region 18b are connected to the metal silicide film 19b through the interlayer insulating film 20 The contact plug 21b is provided.

  Here, the structural features of the semiconductor device according to the present embodiment are the following points.

  As shown in FIG. 2, the sidewall width d2 of the second sidewall 16b formed on the side surface of the second gate electrode 14b of the p-type MIS transistor is equal to that of the first gate electrode 14a of the n-type MIS transistor. It is smaller than the sidewall width d1 of the first sidewall 16a formed on the side surface. According to this configuration, in the n-type MIS transistor, the substrate current can be reduced, so that the hot carrier resistance can be improved. In addition, in the p-type MIS transistor, the driving force can be improved. Therefore, in this embodiment, a semiconductor device including an n-type MIS transistor excellent in reliability and a high-performance p-type MIS transistor can be provided.

<< Second Embodiment >>
A semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing the semiconductor device according to the present embodiment. In the figure, “nMIS” shown on the left side indicates an n-type MIS formation region where an n-type MIS transistor is formed, and “pMIS” shown on the right side indicates a p-type MIS formation where a p-type MIS transistor is formed. Indicates the area.

  Hereinafter, the semiconductor device according to the present embodiment will be described with a focus on differences from the semiconductor device according to the first embodiment described above, and common points will be omitted as appropriate.

  Here, the structural differences between the first embodiment and the second embodiment described above are as follows.

  In the first embodiment described above, as shown in FIG. 1F, the p-type MIS transistor formed in the p-type MIS formation region is formed on the outer side of the second sidewall 16b in the second active region 10b. Only the p-type source / drain region 18b is provided in the lower region. On the other hand, in the present embodiment, as shown in FIG. 3, the p-type MIS transistor formed in the p-type MIS formation region is formed in a region below the second sidewall 16 b in the second active region 10 b. A p-type source / drain region 18b and a p-type SiGe layer 22 are provided. That is, the feature of the present embodiment is that the region of the second active region 10b that is located outside the second sidewall 16b is provided above the p-type source / drain region 18b and the p-type source / drain region 18b. The p-type SiGe layer 22 is embedded in the part. The n-type MIS transistor has the same structure as that of the first embodiment, and the p-type MIS transistor is the same as that of the first embodiment except that the p-type SiGe layer 22 is formed. It has a structure. The p-type SiGe layer 22 functions as a part of the source / drain region of the p-type MIS transistor.

  As described above, according to the semiconductor device according to the present embodiment, the side of the second sidewall 16b formed on the side surface of the second gate electrode 14b of the p-type MIS transistor, as in the first embodiment. The wall width d2 is smaller than the sidewall width d1 of the first sidewall 16a formed on the side surface of the first gate electrode 14a of the n-type MIS transistor. According to this configuration, it is possible to provide a semiconductor device capable of improving the hot carrier resistance of the n-type MIS transistor and improving the driving force of the p-type MIS transistor.

  Further, the region outside the second sidewall 16b in the second active region 10b is a p-type SiGe buried in a recess portion provided above the p-type source / drain region 18b and the p-type source / drain region 18b. Therefore, it is possible to generate a strain by applying a compressive stress in the gate length direction (the direction indicated by the solid arrow in FIG. 3) in the channel region of the p-type MIS transistor. Therefore, the distance x2 between the pair of second sidewalls 16b of the p-type MIS transistor can be made shorter than the distance x1 between the pair of first sidewalls 16a of the n-type MIS transistor. Thereby, the driving force of the p-type MIS transistor can be further improved.

  Although a detailed description of the method for manufacturing the semiconductor device according to the present embodiment has been omitted, the method for manufacturing the semiconductor device according to the first embodiment described above is performed after the step of FIG. A step of forming a recess portion by etching the upper portion of the p-type source / drain region 18b and selectively forming the p-type SiGe layer 22 in the recess portion may be added.

<< Third Embodiment >>
In the third embodiment of the present invention, a case where an SRAM memory cell is configured using the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 4A is a plan view showing the layout of the SRAM memory cell, and FIG. 4B is a cross-sectional view showing a case where the contact plug is not displaced at the CC position in FIG. 4A. FIG. 4C is a cross-sectional view showing a case where the contact plug is misaligned at the CC position in FIG. 4A.

  As shown in FIG. 4A, the SRAM memory cell includes load transistors LT1 and LT2, drive transistors DT1 and DT2, and access transistors TF1 and TF2. The load transistors LT1 and LT2 are formed in the p-type MIS transistor formation region, that is, are p-type MIS transistors. Drive transistors DT1, DT2 and access transistors TF1, TF2 are formed in the n-type MIS transistor formation region, that is, are n-type MIS transistors.

  The configuration of the load transistor LT2 will be described with reference to FIG.

  The load transistor LT2 has a configuration similar to that of the p-type MIS transistor (see FIG. 1F) in the first embodiment described above. That is, the n-type well region 12b formed in the semiconductor substrate 10, the second active region 10b made of the semiconductor substrate 10 surrounded by the element isolation region 11, and the second active region 10b formed on the second active region 10b. Gate insulating film 13b, a second gate electrode 14b2 formed on the second gate insulating film 13b, a second sidewall 16b formed on the side surface of the second gate electrode 14b2, and a second The p-type extension region 15b formed in the region below the second gate electrode 14b2 in the active region 10b and the region outside the second sidewall 16b in the second active region 10b. A p-type source / drain region 18b, a metal silicide film 19b formed on the p-type source / drain region 18b and the second gate electrode 14b2, and Contact plug 21b and shared contact plug provided so as to penetrate through interlayer insulating film 20 formed on gate electrode 14b2 and to connect to metal silicide film 19b through interlayer insulating film 20 on p-type source / drain region 18b. 21bS. The shared contact plug 21bS is commonly connected to one side (drain region) of the p-type source / drain region 18b and the second gate electrode 14b1 of the load transistor LT1 extending on the element isolation region 11. Further, the other (source region) side of the p-type source / drain region 18b is a source region common to adjacent load transistors, and is connected to an upper layer wiring (not shown) via a contact plug 21b. .

  In the SRAM memory cell according to the present embodiment, for example, a load transistor LT2 which is a p-type MIS transistor and a drive transistor DT2 which is an n-type MIS transistor have the same configuration as that shown in FIG. The dual gate structure has a long width. The sidewall width d2 of the second sidewall 16b formed on the side surface of the second gate electrode 14b2 of the load transistor LT2 is the first width formed on the side surface of the first gate electrode 14a of the drive transistor DT2. The first sidewall 16a is formed smaller than the sidewall width d1. On the other hand, in the conventional SRAM memory cell, the side wall width of the load transistor is the same as the side wall width d1 of the drive transistor. Therefore, in the configuration of the present embodiment, the distance from the end of the contact plug 21b to the end of the second sidewall 16b on the source side of the load transistor LT2 (“L” shown in FIG. 4B) is the conventional configuration. Compared to the difference, the difference of the sidewall width (d1-d2) is larger. Thus, in the configuration of the present embodiment, the metal silicide film 19b is formed wider on the second gate electrode 14b2 side by the difference in the sidewall width on the other side (source region) side of the p-type source / drain region 18b. Can do.

  As a result, in the SRAM memory cell according to the present embodiment, as shown in FIG. 4C, even when the contact plug 21b is shifted to the second gate electrode 14b2 side, the contact plug is in contact with only the metal silicide film 19b. 21b can be formed. On the other hand, in the conventional configuration, the side wall width of the load transistor is the same as the side wall width d1 of the drive transistor. Therefore, when the contact plug 21b is shifted to the second gate electrode 14b2 side, the contact plug 21b is loaded. It is formed by removing a part of the sidewall of the transistor. Therefore, in the conventional configuration, the contact plug 21b is formed in direct contact with a part of the p-type extension region 15b, and the driving capability of the load transistor is deteriorated due to an increase in source contact resistance or an increase in leakage current. was there. On the other hand, according to the configuration of the present embodiment, there is a very low possibility that the contact plug 21b is formed in direct contact with a part of the p-type extension region 15b, so that an increase in source contact resistance or an increase in leakage current can be suppressed. it can.

  In the present embodiment, the load transistor of the SRAM memory cell is used as the transistor having a reduced sidewall width, but the present invention is not limited to this. For example, among all the transistors constituting the semiconductor integrated circuit, the sidewall width of all the p-type MIS transistors may be smaller than the sidewall width of the n-type MIS transistor, or all the p-type MIS transistors Of these, only the side wall width of a specific p-type MIS transistor, for example, a load transistor of an SRAM memory cell, may be reduced.

  Further, although the configuration has been described in which the sidewall width of the p-type MIS transistor is smaller than the sidewall width of the n-type MIS transistor, the present invention is not limited to this. For example, when the sidewall widths of the n-type MIS transistor and the p-type MIS transistor constituting the peripheral circuit unit are both set to the width d1, the sidewall widths of the n-type MIS transistor and the p-type MIS transistor constituting the SRAM memory cell are In any case, the width d2 may be smaller than the width d1.

  The present invention is useful for a semiconductor device that improves the hot carrier resistance of an n-type MIS transistor and the driving force of a p-type MIS transistor, and a method for manufacturing the same.

(A)-(f) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in order of a process, and is principal part sectional drawing in a gate length direction. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. (A) is a top view which shows the layout of the SRAM memory cell in the 3rd Embodiment of this invention, (b) shows the case where the position shift of the contact plug has not arisen in CC location of (a). It is sectional drawing, (c) is sectional drawing which shows the case where the position shift of the contact plug has arisen in CC location of (a). (A) And (b) is the top view and sectional drawing which show the conventional semiconductor device, respectively.

10 Semiconductor substrate
10a First active region
10b Second active region
11 Device isolation region
12a p-type well region
12b n-type well region
13a First gate insulating film
13b Second gate insulating film
14a First gate electrode
14b Second gate electrode
15a n-type extension region
15b p-type extension region
16 Insulating film
16a first sidewall
16b second sidewall
17 resist
18a n-type source / drain region
18b p-type source / drain region
19a Metal silicide film
19b Metal silicide film
20 Interlayer insulation film
21a Contact plug
21b Contact plug
21bS shared contact plug
22 p-type SiGe layer
LT1 Load transistor DT2 Drive transistor LT2 Load transistor

Claims (6)

A semiconductor device comprising an n-type MIS transistor and a p-type MIS transistor,
The n-type MIS transistor is
A first gate insulating film formed on the first active region in the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first sidewall formed on a side surface of the first gate electrode,
The p-type MIS transistor is
A second gate insulating film formed on a second active region in the semiconductor substrate;
A second gate electrode formed on the second gate insulating film;
A second sidewall formed on a side surface of the second gate electrode,
The semiconductor device according to claim 1, wherein the second sidewall has a smaller sidewall width than the first sidewall. The semiconductor device according to claim 1,
An n-type extension region formed in a region laterally below the first gate electrode in the first active region;
An n-type source / drain region formed in a region outside the first sidewall in the first active region;
A p-type extension region formed in a region laterally below the second gate electrode in the second active region;
And a p-type source / drain region formed in a region outside the second sidewall in the second active region. The semiconductor device according to claim 1 or 2,
A semiconductor device, further comprising a p-type SiGe layer embedded in a recess portion provided above the p-type source / drain region in the second active region. The semiconductor device according to any one of claims 1 to 3,
The n-type MIS transistor is a drive transistor in an SRAM memory cell,
The p-type MIS transistor is a load transistor in the SRAM memory cell. A method of manufacturing a semiconductor device comprising an n-type MIS transistor having a first gate electrode on a first gate insulating film and a p-type MIS transistor having a second gate electrode on a second gate insulating film. There,
Forming a first active region and a second active region surrounded by an element isolation region in a semiconductor substrate (a);
The first gate insulating film and the first gate electrode are formed on the first active region, and the second gate insulating film and the second gate electrode are formed on the second active region. Step (b) to perform,
A first sidewall is formed on the side surface of the first gate electrode, and a second sidewall having the same sidewall width as the first sidewall is formed on the side surface of the second gate electrode. Step (c) to perform,
After the step (c), the second sidewall is etched to reduce the sidewall width of the second sidewall compared to the sidewall width of the first sidewall (d). A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 5,
After the step (b) and before the step (c), an n-type extension region is formed in a region below the first gate electrode in the first active region, while the second type A step (e) of forming a p-type extension region in a region under the side of the second gate electrode in the active region;
After the step (d), an n-type source / drain region is formed in a region outside the first sidewall in the first active region, while the second side in the second active region is formed. A method of manufacturing a semiconductor device, further comprising a step (f) of forming a p-type source / drain region in a region below the wall.

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