JP2010231645A - Arithmetic processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve processing speed when arithmetic processing is implemented by hardware. <P>SOLUTION: An arithmetic processing unit includes a first circuit that executes arithmetic processing corresponding to a predetermined operation expression using at least any one of a plurality of arithmetic circuits, a memory, a first data storage part that stores first data including information about an arithmetic circuit to be used, a second data storage part that stores second data including an address showing an area in the memory in which operation data to be used in the arithmetic operation is stored, a sequencer that reads the first data stored in the first data storage part and outputs it to the first circuit, and a scheduler that reads the second data stored in the second data storage part and reads the operation data from the memory according to the read second data to output it to the first circuit. Each of the arithmetic circuits includes a computing unit that executes a calculation corresponding to a predetermined operator on input data and outputs an operation result to the other arithmetic circuits, and selectors for selecting data to be used as input data and outputting it to the computing unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present technology relates to a technology in the field of performing numerical arithmetic processing using a dynamic reconfiguration arithmetic circuit.

  For example, high-level languages such as Fortran are used for advanced scientific calculations. A high-level language such as Fortran is originally a language intended for software processing, but speeds up processing by replacing part of the processing with programmable hardware such as FPGA (Field Programmable Gate Array). Is planned.

  For example, in order to realize the processing for three arithmetic expressions (1) x = a ÷ b−c, (2) x = (a + b) × c, and (3) x = a−b + c by hardware, Circuits as shown in FIGS. 18A to 18C need to be mounted on the FPGA. 18A is a circuit corresponding to the arithmetic expression (1), FIG. 18B is a circuit corresponding to the arithmetic expression (2), and FIG. 18C corresponds to the arithmetic expression (3). Each circuit is shown. That is, a circuit corresponding to the arithmetic expression must be mounted for each arithmetic expression. In a high-level language such as Fortran, the arithmetic expression may be complicated, and the circuit scale increases as the calculation becomes complicated. On the other hand, hardware resources such as FPGA are limited, and when the circuit scale becomes large, circuits corresponding to all arithmetic expressions cannot be mounted on the FPGA.

As a countermeasure to such a problem related to resource limitation, a technique is known in which a calculation formula is subdivided and processing is performed using a circuit that can repeatedly use four arithmetic units as shown in FIG. In FIG. 19, four arithmetic units, an adder, a subtracter, a multiplier, and a divider, are provided so that data (IN1 and IN2 in FIG. 19) read from the memory is input to each arithmetic unit. It has become. Then, the selector selects a calculation result to be written in the memory from the calculation results from the respective arithmetic units based on the external signal (OP in FIG. 19). For example, the arithmetic expression (1) is divided into two steps of (1-1) x ₁ = a ÷ b and (1-2) x = x ₁ -c. Writes the calculation result from the divider among the calculation results output from each calculator, and writes the calculation result from the subtractor to the memory in the second stage of processing.

JP-A-11-203145 JP 2007-172569 A Japanese Patent No. 2879070

  However, the conventional technique has a problem that the processing speed cannot be improved because reading from the memory and writing to the memory occur each time.

  Accordingly, an object of the present technology is to provide a technology for improving the processing speed when the arithmetic processing by software is realized by hardware.

  The arithmetic processing apparatus includes a plurality of arithmetic circuits, a dynamic reconfiguration arithmetic circuit that performs arithmetic processing corresponding to a predetermined arithmetic expression using at least one of the arithmetic circuits, and stores arithmetic data A sequence data storage unit that stores, for each predetermined arithmetic expression, sequence data including information relating to an arithmetic circuit to be used in the arithmetic processing corresponding to the predetermined arithmetic expression, and an arithmetic process corresponding to the predetermined arithmetic expression The schedule data storage unit that stores the calculation data to be used and stores the schedule data including the address indicating the area in the memory, and when the calculation start instruction is received, the sequence data is read from the sequence data storage unit If a sequencer that outputs to a static reconfiguration arithmetic circuit and an operation start instruction are accepted, the schedule data storage unit Read the schedule data, and a scheduler for outputting read the operation data from the memory to the dynamically reconfigurable processor circuit in accordance with the schedule data. Each of the plurality of arithmetic circuits described above performs a calculation corresponding to a predetermined operator on the input data, outputs an operation result data to another arithmetic circuit, and an operation from the scheduler. A selector that selects data to be used as input data based on sequence data from the data and operation result data from another arithmetic circuit and outputs the selected data to the arithmetic unit.

  In the case where arithmetic processing by software is realized by hardware, the processing speed can be improved.

It is a system outline figure concerning this embodiment. It is a block diagram of the calculating part in the system which concerns on this Embodiment. It is a block diagram of the calculation macro in a calculating part. It is a figure which shows an example of the schedule data stored in a schedule table. It is a figure for demonstrating schedule data. It is a figure which shows an example of the sequence data stored in a sequence table. It is a figure for demonstrating sequence data. It is a figure for demonstrating sequence data. It is a figure which shows an example of sequence data. It is a figure which shows the flow of data in the case of performing the process of arithmetic expression a / bc. It is a figure which shows an example of sequence data. It is a figure which shows the flow of data in the case of performing the process of arithmetic expression (a + b) * c. It is a figure which shows an example of sequence data. It is a figure which shows the flow of data in the case of performing the process of arithmetic expression ab + c. It is a figure which shows the processing flow of the system which concerns on this Embodiment. It is a figure which shows the processing flow of the system which concerns on this Embodiment. It is a figure which shows the processing flow of the system which concerns on this Embodiment. It is a figure for demonstrating a prior art. It is a figure for demonstrating a prior art.

  A system overview according to an embodiment of the present technology is shown in FIG. For example, in a network 1 such as an in-house LAN (Local Area Network) or the Internet, a user terminal (user terminals A and B in FIG. 1) and an arithmetic processing device 3 that performs main processing in the present embodiment are provided. It is connected. Note that the number of user terminals is not limited to two.

  The arithmetic processing unit 3 includes a memory 31 for storing arithmetic data or arithmetic results to be used for arithmetic processing, a schedule table 32 for storing schedule data to be described later, and a sequence table 33 for storing sequence data to be described later. A memory controller 34 that accesses the memory 31 in accordance with an instruction from the scheduler 35, a scheduler 35 that reads schedule data from the schedule table 32, and performs processing such as calculation data reading and calculation result writing according to the schedule data The sequence data is read out from the sequence table 33 and output to the calculation unit 37. The calculation process is performed based on the data from the scheduler 35 and the sequencer 36, and the calculation result is output to the scheduler 35. And a part 37. Note that the arithmetic unit 37 is configured by programmable hardware such as an FPGA.

  A specific configuration of the calculation unit 37 will be described with reference to FIGS. 2 and 3. FIG. 2 is a configuration diagram of the calculation unit 37. As shown in FIG. 2, the arithmetic unit 37 includes a plurality of arithmetic macros (in FIG. 2, arithmetic macro A, arithmetic macro B, arithmetic macro C, arithmetic macro D,...). Calculation data from the scheduler 35 is input to each calculation macro. Further, the calculation result data of the calculation macro is output to another calculation macro. For example, the operation macro A (addition macro) includes operation data from the scheduler 35 and operation result data from other operation macros (operation macro B, operation macro C, operation macro D,... In FIG. 2). Are input, and the operation macro A (addition macro) outputs the operation result data to other operation macros (operation macro B, operation macro C, operation macro D,...). Further, a final calculation result (that is, a calculation result of a predetermined calculation formula) is output to the scheduler 35.

  FIG. 3 shows a configuration diagram of the operation macro. FIG. 3 shows a configuration diagram of the addition macro. The addition macro includes selectors 3701A to 3704A, flip-flop circuits (hereinafter referred to as FFs) 3705A and 3706A, and an adder 3710. The sequence data from the sequencer 36 is input to each of the selectors 3701A to 3704A. The selector outputs data specified by the sequence data among the input data. 3 represents sequence data from the sequencer 36.

  In FIG. 3, the calculation data from the scheduler 35 is input to the selectors 3701A and 3702A. In FIG. 3, the number of inputs from the scheduler 35 is four, but the number of inputs is not limited to this. Then, the selector 3701A outputs the data designated by the sequence data among the operation data from the scheduler 35 to the selector 3703A via the FF 3705A. Similarly, the selector 3702A outputs the data designated by the sequence data among the calculation data from the scheduler 35 to the selector 3704A via the FF 3706A.

  On the other hand, the selector 3703A receives the operation data from the FF 3705A and the operation result data from another operation macro. In FIG. 3, the number of inputs from other arithmetic macros is three, but the number of inputs is not limited to this. Then, selector 3703A outputs the data specified by the sequence data among the operation data from FF 3705A and the operation result data from another operation macro to adder 3710. Similarly, calculation data from the FF 3706A and calculation result data from other calculation macros are input to the selector 3704A. In FIG. 3, the number of inputs from other arithmetic macros is three, but the number of inputs is not limited to this. Then, selector 3704A outputs the data designated by the sequence data, out of the operation data from FF 3706A and the operation result data from another operation macro, to adder 3710.

  Adder 3710 performs addition processing using the data from selector 3703A and the data from selector 3704A, and outputs the operation result data to another operation macro.

  Although the addition macro has been described above as an example, the basic configuration is the same for the subtraction macro, multiplication macro, and division macro. However, in the case of a subtraction macro, a multiplication macro, and a division macro, instead of the adder 3710, a subtracter 3720 that performs subtraction processing, a multiplier 3730 that performs multiplication processing, and a divider 3740 that performs division processing, respectively. Have.

  FIG. 4 shows an example of schedule data stored in the schedule table 32. In the example of FIG. 4, the schedule data includes a command type (CMD), a buffer number (BUF No), a head address (AS1), a last address (AE1), and a first interval (ARPT1) of continuous areas. And the second interval (ARPT2) of the continuous area, the number of continuous additions of ARPT1 (NRPT1), the number of continuous additions of ARPT2 (NRPT2), and the number of words (NCW) of the continuous area. Here, the continuous area refers to an area to be read or written.

  In the command type (CMD), for example, a value (hexadecimal number in FIG. 4) representing data read or data write is set. For example, if the upper 4 bits are “0000”, it indicates data read, and if the upper 4 bits are “0001”, it indicates data write. In the example of FIG. 4, the first to third lines are schedule data related to data read, and the fourth line is schedule data related to data write. In addition, the head address (AS1) is set with the head address of the continuous area (the head continuous area when there are a plurality of continuous areas). In the final address (AE1), an address indicating the end of the continuous area (or the leading continuous area when there are a plurality of continuous areas) is set. For example, as shown in FIG. 5, when there are continuous areas 501 to 506, the start address (AS1) is set with the start address of the continuous area 501 and the final address (AE1) indicates the end of the continuous area 501. An address is set. The first interval (ARPT1) is set with an interval from one continuous area to the next continuous area (interval between head addresses). In the example of FIG. 5, the interval between the continuous region 501 and the continuous region 502, the interval between the continuous region 502 and the continuous region 503, the interval between the continuous region 504 and the continuous region 505, and the interval between the continuous region 505 and the continuous region 506 are All have the same interval, and this interval is set as the first interval (ARPT1). The second interval (ARPT2) is an interval from one continuous region to the next continuous region, and is different from the first interval (ARPT1). In the example of FIG. 5, the interval between the continuous region 503 and the continuous region 504 is set as the second interval (ARPT2). When accessing a continuous area (the continuous areas 501 to 503 in FIG. 5) arranged at the first interval (ARPT1), the first interval (ARPT1) is added to the current address and the next continuous. The area is accessed, and the number of additions is set to the number of continuous additions (NRPT1) of ARPT1. Similarly, when the next continuous area is accessed by adding the second interval (ARPT2) to the current address, the number of additions is set as the number of consecutive additions of ARPT2 (NRPT2). Further, the size of the continuous area is set as the number of words (NCW) in the continuous area. For example, in the case of a data write command, the write destination area is specified by the head address (AS1) and the number of words in the continuous area (NCW).

  FIG. 6 shows an example of sequence data stored in the sequence table 33. 6 shows an example of sequence data for causing the arithmetic unit 37 having one addition macro, one subtraction macro, one multiplication macro, and one division macro to execute processing of a predetermined arithmetic expression as shown in FIG. Indicates. In the example of FIG. 6, the sequence table 33 includes the number of the arithmetic expression ((1) No), the type of the arithmetic expression ((2) type), and a selection signal ((3) Select for the selector in the addition macro. For ADD), a selection signal for the selector in the subtraction macro ((4) Select For SUB), a selection signal for the selector in the multiplication macro ((5) Select For MULT), and a selection signal for the selector in the division macro ( (6) Select For DIV), delay value for input port ((7) CALCIN_DLAY), skip interval during loop ((8) SKIP_INTERVAL), and data indicating whether or not to skip for the first time ((9) SKIP_WORK ) And The delay (7) for the input port includes a delay (7a) for the input port a, a delay (7b) for the input port b, a delay (7c) for the input port c, and a delay (7d) for the input port d. And are included.

  The selection signal (3) for the selector in the addition macro includes a selection signal (3a) for the selector 3701A, a selection signal (3b) for the selector 3702A, a selection signal (3c) for the selector 3703A, and a selection for the selector 3704A. Signal (3d). The selection signal (4) for the selector in the subtraction macro includes a selection signal (4a) for the selector 3701B, a selection signal (4b) for the selector 3702B, a selection signal (4c) for the selector 3703B, and a selection for the selector 3704B. Signal (4d). Further, the selection signal (5) for the selector in the multiplication macro includes a selection signal (5a) for the selector 3701C, a selection signal (5b) for the selector 3702C, a selection signal (5c) for the selector 3703C, and a selection for the selector 3704C. Signal (5d). The selection signal (6) for the selector in the division macro includes a selection signal (6a) for the selector 3701D, a selection signal (6b) for the selector 3702D, a selection signal (6c) for the selector 3703D, and a selection for the selector 3704D. Signal (6d).

  In the present embodiment, for example, as shown in FIG. 8, when “0” is set in the selection signal s for a certain selector, the selector converts the data input from the input port a to the output data. Output as x. When the selection signal is “1”, the selector outputs data input from the input port b as output data x. Further, when the selection signal is “2”, the selector outputs data input from the input port c as output data x. When the selection signal is “3”, the selector outputs data input from the input port d as output data x.

  For example, the operation of the arithmetic unit 37 when executing the processing of arithmetic expression a ÷ bc will be described with reference to FIGS. FIG. 9 shows sequence data for executing the processing of arithmetic expression a ÷ bc. FIG. 10 shows the flow of data in the arithmetic unit 37 when the processing of the arithmetic expression a ÷ bc is executed with the sequence data as shown in FIG. In FIG. 10, input ports a, b, and c indicate inputs from the scheduler 35.

  For example, in FIG. 9, “0” is set to the selection signal (6a) for the selector 3701D in the division macro, and “1” is set to the selection signal (6b) for the selector 3702D. Therefore, as shown in FIG. 10, the selector 3701D selects the data (referred to as data a) input from the input port a according to the selection signal (6a), and outputs it to the selector 3703D via the FF 3705D. The selector 3702D selects data (referred to as data b) input from the input port b in accordance with the selection signal (6b), and outputs the data to the selector 3704D via the FF 3706D.

  In FIG. 9, “3” is set to the selection signal (6c) for the selector 3703D, and “3” is also set to the selection signal (6d) for the selector 3704D. Therefore, as shown in FIG. 10, the selector 3703D selects the data a from the FF 3705D according to the selection signal (6c) and outputs it to the divider 3740. Further, the selector 3704D selects the data b from the FF 3706D according to the selection signal (6d) and outputs it to the divider 3740. Then, the divider 3740 calculates a ÷ b using the data a from the selector 3703D and the data b from the selector 3704D.

  On the other hand, in FIG. 9, “2” is set in the selection signal (4b) for the selector 3702B in the subtraction macro. Accordingly, the selector 3702B selects the data (referred to as data c) input from the input port c according to the selection signal (4b), and outputs it to the selector 3704B via the FF 3706B. In FIG. 9, since “10” is set in delay (7c) for the input port c, the selector 3702B outputs the output after delaying by this value.

  In FIG. 9, “2” is set to the selection signal (4c) for the selector 3703B in the subtraction macro, and “3” is set to the selection signal (4d) for the selector 3704B. Accordingly, the selector 3703B selects the data from the divider 3740 (that is, the result of a ÷ b, referred to as data d) according to the selection signal (4c), and outputs it to the subtractor 3720. Further, the selector 3704B selects the data c from the FF 3706B according to the selection signal (4d) and outputs it to the subtractor 3720. Then, the subtracter 3720 calculates dc using the data d from the selector 3703B and the data c from the selector 3704B. Then, the calculation result of dc (= a ÷ bc) is output from the subtracter 3720 to the scheduler 35.

  Next, as another example, the operation of the calculation unit 37 when executing the processing of the calculation formula (a + b) × c will be described with reference to FIGS. 11 and 12. FIG. 11 shows sequence data for executing the processing of the arithmetic expression (a + b) × c. FIG. 12 shows the flow of data in the arithmetic unit 37 when the processing of the arithmetic expression (a + b) × c is executed with the sequence data as shown in FIG. In FIG. 12, input ports a, b, and c indicate inputs from the scheduler 35.

  For example, in FIG. 11, “0” is set to the selection signal (3a) for the selector 3701A in the addition macro, and “1” is set to the selection signal (3b) for the selector 3702A. Therefore, as shown in FIG. 12, the selector 3701A selects the data (referred to as data a) input from the input port a according to the selection signal (3a), and outputs it to the selector 3703A via the FF 3705A. The selector 3702A selects data (referred to as data b) input from the input port b according to the selection signal (3b), and outputs the data to the selector 3704A via the FF 3706A.

  In FIG. 11, “3” is set to the selection signal (3c) for the selector 3703A, and “3” is also set to the selection signal (3d) for the selector 3704A. Accordingly, as shown in FIG. 12, the selector 3703A selects the data a from the FF 3705A according to the selection signal (3c), and outputs it to the adder 3710. Further, the selector 3704A selects the data b from the FF 3706A according to the selection signal (3d) and outputs it to the adder 3710. Adder 3710 calculates a + b using data a from selector 3703A and data b from selector 3704A.

  On the other hand, in FIG. 11, “2” is set in the selection signal (5b) for the selector 3702C in the multiplication macro. Accordingly, the selector 3702C selects the data (referred to as data c) input from the input port c according to the selection signal (5b), and outputs it to the selector 3704C via the FF 3706C. In FIG. 11, since “5” is set in delay (7c) for the input port c, the selector 3702C delays this value before outputting.

  In FIG. 11, “0” is set to the selection signal (5c) for the selector 3703C in the multiplication macro, and “3” is set to the selection signal (5d) for the selector 3704C. Therefore, the selector 3703C selects the data from the adder 3710 (that is, the result of a + b, referred to as data e) in accordance with the selection signal (5c), and outputs it to the multiplier 3730. The selector 3704C selects the data c from the FF 3706C according to the selection signal (5d), and outputs it to the multiplier 3730. Multiplier 3730 calculates e × c using data e from selector 3703C and data c from selector 3704C. Then, a calculation result of e × c (= (a + b) × c) is output from the multiplier 3730 to the scheduler 35.

  As another example, the operation of the calculation unit 37 when executing the processing of the calculation expression a−b + c will be described with reference to FIGS. 13 and 14. FIG. 13 shows sequence data for executing the processing of the arithmetic expression a−b + c. FIG. 14 shows the flow of data in the arithmetic unit 37 when the processing of the arithmetic expression a−b + c is executed with the sequence data as shown in FIG. In FIG. 14, input ports a, b, and c indicate inputs from the scheduler 35.

  For example, in FIG. 13, “0” is set to the selection signal (4a) for the selector 3701B in the subtraction macro, and “1” is set to the selection signal (4b) for the selector 3702B. Therefore, as shown in FIG. 14, the selector 3701B selects the data (referred to as data a) input from the input port a according to the selection signal (4a), and outputs it to the selector 3703B via the FF 3705B. The selector 3702B selects data (referred to as data b) input from the input port b according to the selection signal (4b), and outputs the data to the selector 3704B via the FF 3706B.

  In FIG. 13, “3” is set to the selection signal (4c) for the selector 3703B, and “3” is also set to the selection signal (4d) for the selector 3704D. Therefore, as shown in FIG. 14, the selector 3703B selects the data a from the FF 3705B according to the selection signal (4c) and outputs it to the subtractor 3720. The selector 3704B selects the data b from the FF 3706B according to the selection signal (4d), and outputs it to the subtractor 3720. Then, the subtractor 3720 calculates a−b by using the data a from the selector 3703B and the data b from the selector 3704B.

  On the other hand, in FIG. 13, “2” is set in the selection signal (3b) for the selector 3702A in the addition macro. Accordingly, the selector 3702A selects the data (referred to as data c) input from the input port c according to the selection signal (3b), and outputs it to the selector 3704A via the FF 3706A. In FIG. 13, since “5” is set in delay (7c) for the input port c, the selector 3702A delays this value before outputting.

  In FIG. 13, “0” is set to the selection signal (3c) for the selector 3703A in the addition macro, and “3” is set to the selection signal (3d) for the selector 3704A. Accordingly, the selector 3703A selects the data from the subtractor 3720 (that is, the result of ab, referred to as data f) according to the selection signal (3c), and outputs it to the adder 3710. The selector 3704A selects the data c from the FF 3706A according to the selection signal (3d), and outputs the data c to the adder 3710. Adder 3710 then calculates f + c using data f from selector 3703A and data c from selector 3704A. Then, the calculation result of f + c (= a−b + c) is output from the adder 3710 to the scheduler 35.

  The schedule data and sequence data described above may be created from a program or may be created manually.

  Next, processing of the system shown in FIG. 1 will be described with reference to FIGS. Here, it is assumed that schedule data and sequence data created in advance are stored in the user terminal. First, the user sets necessary data in the arithmetic processing unit 3 as a stage before starting the processing. Specifically, the user accesses the arithmetic processing device 3 by operating the user terminal. And a user operates a user terminal and transmits the arithmetic data used for a process to the arithmetic processing apparatus 3. FIG. The arithmetic processing device 3 receives the arithmetic data from the user terminal and stores it in the memory 31 (FIG. 15: step (S1)). Further, the user operates the user terminal to transmit schedule data to the arithmetic processing device 3. The arithmetic processing unit 3 receives the schedule data from the user terminal and stores it in the schedule table 32 (step (S2)). In addition, the user operates the user terminal to transmit the sequence data to the arithmetic processing device 3. The arithmetic processing unit 3 receives the sequence data from the user terminal and stores it in the sequence table 33 (step (S3)). This completes the previous process.

  Then, the user operates the user terminal to transmit a calculation start instruction to the calculation processing device 3 (FIG. 16: Step (S4)). The arithmetic processing device 3 receives a calculation start instruction from the user terminal and outputs the calculation start instruction to the scheduler 35 and the sequencer 36.

  When the scheduler 35 receives the calculation start instruction, the scheduler 35 reads the schedule data from the schedule table 32 (FIG. 17: Step (S5)). For example, in the schedule data shown in FIG. 4, the first to third lines are data read and the fourth line is data write, and the schedule data as shown in FIG. If it is, the schedule data for 4 records is read out. When the sequencer 36 receives the calculation start instruction, the sequencer 36 reads sequence data for one record from the sequence table 33 (step (S6)).

  Then, the scheduler 35 reads calculation data from the memory 31 via the memory controller 34 in accordance with the read schedule data (step (S7)), and outputs the read calculation data to the calculation unit 37 (step (S8)). Specifically, the scheduler 35 reads out the calculation data according to the schedule data regarding the data read. For example, when schedule data for three records related to data read is read, the calculation data is read for each record according to the setting of the record, and is calculated via the input port a, b, or c. Is output to the unit 37.

  The sequencer 36 outputs the read sequence data for one record to the calculation unit 37 (step (S9)).

  And the calculating part 37 performs a calculation process according to the input calculation data and sequence data (step (S10)). That is, according to each selection signal included in the sequence data, each selector in the calculation macro in the calculation unit 37 performs the operation as described above, thereby executing a calculation process corresponding to a predetermined calculation expression.

  Then, when the arithmetic processing based on the sequence data is completed, the arithmetic unit 37 outputs arithmetic expression result data as a final arithmetic result to the scheduler 35 (step (S11)). The scheduler 35 receives arithmetic expression result data from the arithmetic unit 37. Then, the scheduler 35 writes arithmetic expression result data to the memory 31 via the memory controller 34 in accordance with the schedule data (step (S12)). Specifically, according to the schedule data related to data / write read in step (S5), the calculation result data is stored in the area specified by the start address (AS1) of the schedule data and the number of words in the continuous area (NCW). Write. Then, the scheduler 35, the sequencer 36, and the calculation unit 37 repeat the processing from step (S7) to step (S12) according to the schedule data and the sequence data. Note that (8) SKIP_INTERVAL and (9) SKIP_WORK in the sequence data can be appropriately set to skip the processing at predetermined intervals.

  Then, after all the arithmetic processing is completed, the user operates the user terminal, acquires the processing result from the memory 31 of the arithmetic processing device 3, and displays it on the display device or the like (step (S13)). In addition, you may make it display the data in the middle of a process on the display apparatus of a user terminal.

  By carrying out the processing as described above, it is possible to set calculation data readout and calculation circuit reconfiguration to schedule data and sequence data, respectively, so that the degree of freedom is increased and rational calculation processing is realized. be able to. For example, when the processing is skipped at predetermined intervals in the loop processing, it can be realized by appropriately setting the sequence data.

  Although one embodiment of the present technology has been described above, the present invention is not limited to this. For example, the configuration of the schedule data shown in FIG. 4 and the sequence data shown in FIG. 6 is an example, and other configurations can be used as long as the operation data can be read and the operation circuit can be reconfigured as described above. It is also possible to adopt.

  The present embodiment can be summarized as follows.

  The arithmetic processing apparatus includes a plurality of arithmetic circuits, a dynamic reconfiguration arithmetic circuit that performs arithmetic processing corresponding to a predetermined arithmetic expression using at least one of the arithmetic circuits, and stores arithmetic data A sequence data storage unit that stores, for each predetermined arithmetic expression, sequence data including information relating to an arithmetic circuit to be used in the arithmetic processing corresponding to the predetermined arithmetic expression, and an arithmetic process corresponding to the predetermined arithmetic expression The schedule data storage unit that stores the calculation data to be used and stores the schedule data including the address indicating the area in the memory, and when the calculation start instruction is received, the sequence data is read from the sequence data storage unit If a sequencer that outputs to a static reconfiguration arithmetic circuit and an operation start instruction are accepted, the schedule data storage unit Read the schedule data, and a scheduler for outputting read the operation data from the memory to the dynamically reconfigurable processor circuit in accordance with the schedule data. Each of the plurality of arithmetic circuits described above performs a calculation corresponding to a predetermined operator on the input data, outputs an operation result data to another arithmetic circuit, and an operation from the scheduler. A selector that selects data to be used as input data based on sequence data from the data and operation result data from another arithmetic circuit and outputs the selected data to the arithmetic unit.

  According to this configuration, since the arithmetic unit in the arithmetic circuit outputs the arithmetic result to another arithmetic circuit, the number of accesses to the memory is reduced, and the processing speed can be improved. Further, since the dynamic reconfiguration arithmetic circuit is used, the hardware resource limitation is not a problem.

  In addition, the dynamic reconfiguration arithmetic circuit described above selects the arithmetic expression result data corresponding to the result of the arithmetic processing corresponding to the predetermined arithmetic expression from the operation result data based on the sequence data, and outputs it to the scheduler You may make it have.

  Furthermore, the schedule data described above may include an address indicating an area in the memory where the arithmetic expression result data is stored. Then, the scheduler described above may write the arithmetic expression result data from the dynamic reconfiguration arithmetic circuit in the memory according to the schedule data.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1)
A dynamic reconfiguration arithmetic circuit that has a plurality of arithmetic circuits and performs arithmetic processing corresponding to a predetermined arithmetic expression using at least one of the plurality of arithmetic circuits;
A memory for storing calculation data;
A sequence data storage unit that stores, for each of the predetermined arithmetic expressions, sequence data including information on the arithmetic circuit to be used in the arithmetic processing corresponding to the predetermined arithmetic expression;
A schedule data storage unit for storing schedule data including an address indicating an area in the memory, which stores the calculation data to be used in the calculation process corresponding to the predetermined calculation formula;
When receiving a calculation start instruction, a sequencer that reads the sequence data from the sequence data storage unit and outputs the sequence data to the dynamic reconfiguration arithmetic circuit;
When the calculation start instruction is accepted, the scheduler reads the schedule data from the schedule data storage unit, reads the calculation data from the memory according to the schedule data, and outputs the calculation data to the dynamic reconfiguration calculation circuit;
Have
Each of the plurality of arithmetic circuits is
An arithmetic unit that performs a calculation corresponding to a predetermined operator on the input data and outputs the operation result data to another arithmetic circuit;
A selector that selects data to be used as the input data based on the sequence data from among the calculation data from the scheduler and calculation result data from the other calculation circuit, and outputs to the calculator
An arithmetic processing unit having

(Appendix 2)
The dynamic reconfiguration arithmetic circuit is:
The arithmetic processing apparatus according to claim 1, further comprising a circuit that selects arithmetic expression result data corresponding to a result of arithmetic processing corresponding to the predetermined arithmetic expression from the arithmetic result data based on the sequence data, and outputs the selected arithmetic expression result data to the scheduler.

(Appendix 3)
The schedule data includes an address indicating an area in the memory that is a storage destination of the arithmetic expression result data,
The arithmetic processing device according to claim 2, wherein the scheduler writes the arithmetic expression result data from the dynamic reconfiguration arithmetic circuit in the memory according to the schedule data.

DESCRIPTION OF SYMBOLS 1 Network 3 Arithmetic processor 31 Memory 32 Schedule table 33 Sequence table 34 Memory controller 35 Scheduler 36 Sequencer 37 Operation part

Claims (3)

A dynamic reconfiguration arithmetic circuit that has a plurality of arithmetic circuits and performs arithmetic processing corresponding to a predetermined arithmetic expression using at least one of the plurality of arithmetic circuits;
A memory for storing calculation data;
A sequence data storage unit that stores, for each of the predetermined arithmetic expressions, sequence data including information on the arithmetic circuit to be used in the arithmetic processing corresponding to the predetermined arithmetic expression;
A schedule data storage unit for storing schedule data including an address indicating an area in the memory, which stores the calculation data to be used in the calculation process corresponding to the predetermined calculation formula;
When receiving a calculation start instruction, a sequencer that reads the sequence data from the sequence data storage unit and outputs the sequence data to the dynamic reconfiguration arithmetic circuit;
When the calculation start instruction is accepted, the scheduler reads the schedule data from the schedule data storage unit, reads the calculation data from the memory according to the schedule data, and outputs the calculation data to the dynamic reconfiguration calculation circuit;
Have
Each of the plurality of arithmetic circuits is
An arithmetic unit that performs a calculation corresponding to a predetermined operator on the input data and outputs the operation result data to another arithmetic circuit;
A selector that selects data to be used as the input data based on the sequence data from among the calculation data from the scheduler and calculation result data from the other calculation circuit, and outputs to the calculator
An arithmetic processing unit having The dynamic reconfiguration arithmetic circuit is:
The arithmetic processing device according to claim 1, further comprising: a circuit that selects arithmetic expression result data corresponding to a result of arithmetic processing corresponding to the predetermined arithmetic expression from the arithmetic result data based on the sequence data, and outputs the selected arithmetic expression result data to the scheduler. . The schedule data includes an address indicating an area in the memory that is a storage destination of the arithmetic expression result data,
The arithmetic processing apparatus according to claim 2, wherein the scheduler writes the arithmetic expression result data from the dynamic reconfiguration arithmetic circuit in the memory according to the schedule data.

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