JP2010231542A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute an instruction in which the timing conditions of transmission of the data of a semiconductor element is changed, and read by a branch instruction, under predetermined timing conditions. <P>SOLUTION: Instruction data (100) of a branch instruction are read, and instruction data (011) passing through a critical path are read, and one of two clock signals clk1 is masked for preparing the passage of the instruction data (011) through the critical path, and even when the decrease of the frequency of the clock signal clk to be input to the semiconductor element of the critical path is started (T9), the masking of the clock signal clk1 is stopped (T10) in the case of reading and executing the instruction data according to the instruction data (100) of a branch instruction. Thus, the instruction read according to the branch instruction is executed under predetermined timing conditions. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a data transmission method of the semiconductor integrated circuit device, and in particular, includes a first semiconductor integrated circuit unit and a second semiconductor integrated circuit unit, and sequentially reads a plurality of instruction data. , A semiconductor integrated circuit device for transmitting each of a plurality of read command data to the first semiconductor integrated circuit unit or the second semiconductor integrated circuit unit determined according to each command data, and a data transmission method for the semiconductor integrated circuit device It is about.

  2. Description of the Related Art Conventionally, some semiconductor integrated circuit devices include a clock generation circuit, a central processing unit (hereinafter referred to as a CPU), a memory controller, a memory, and a regulator.

  The memory of such a semiconductor integrated circuit device stores a plurality of different instruction data for identifying instructions for instructing execution of processing. The CPU includes a plurality of semiconductor integrated circuit units each including a plurality of semiconductor elements, and controls the memory controller to transmit the instruction data read from the memory to the semiconductor integrated circuit unit determined according to the instruction data. Thus, an instruction identified by the instruction data is executed.

  Such a semiconductor integrated circuit device incorporates a computer system in one integrated circuit and is optimized for controlling electronic devices. Compared to general-purpose microprocessors used in personal computers, this is a type of microprocessor that emphasizes self-sufficiency and low cost.

  By the way, each of the plurality of semiconductor integrated circuit units included in the central processing unit has each semiconductor in a predetermined timing condition (for example, input timing of a clock signal input at a predetermined period) that affects the timing of data transmission. Data can be transmitted between elements in a predetermined time. However, there are some cases where data transmission between the semiconductor elements is not completed unless the time is longer than the predetermined time under such a predetermined timing condition. Such a route through which data of the semiconductor integrated circuit portion is transmitted is called a critical path.

  Here, when the CPU tries to transmit the instruction data read from the memory to the critical path under the predetermined timing condition, the following occurs. That is, as described above, in the critical path, data is not transmitted between the semiconductor elements unless the time is longer than the predetermined time. Therefore, even if a certain semiconductor element transmits data to the next semiconductor element that must transmit data under the above timing condition, the data is transmitted from the certain semiconductor element by the timing at which the next semiconductor element transmits data. The data may not be in time.

  Therefore, in view of such a fact, conventionally, as a change in the timing condition only when instruction data is transmitted on a critical path, for example, a technique for increasing the input interval of a clock signal has been proposed (for example, see Patent Document 1). ).

  By the way, there are the following techniques for increasing the input interval of the clock signal.

  In other words, in the case of a portable computer, if the battery is used without knowing that the battery is exhausted, the computer may suddenly go down. In order to prevent the system from going down by suppressing the battery exhaustion after the battery is exhausted to some extent, a technology to reduce the frequency of the clock that operates the computer has been proposed. (For example, refer to Patent Document 2). However, since the measure for lowering the clock frequency is not taken until the battery is depleted to some extent, it is insufficient from the viewpoint of extending the life of the battery.

  Therefore, conventionally, not only the most recently executed instruction data but also a plurality of consecutively executed instruction data are read in advance from a memory in which instruction data for identifying an instruction executed by the CPU is stored. When the data is an idle instruction that can put the CPU in an idle state, a technique for sending a frequency change command to the clock generator to reduce the clock frequency to a predetermined low frequency has been proposed. (For example, refer to Patent Document 3).

JP 2009-48264 A JP-A-3-269711 JP-A-6-332562

  By the way, in addition to the idle instruction, the instruction includes an interrupt instruction, that is, a branch instruction that determines whether a certain condition is satisfied and determines an instruction to be executed next according to the determination result. The instructions read continuously may be a branch instruction, an idle instruction, or an idle instruction.

  However, in this case, when the instruction read according to the determination result by the branch instruction is executed, the idle instruction is continuously read as described above, and the clock frequency is lowered. Accordingly, the read instruction is executed at a reduced clock frequency, and the operation performance becomes slow.

  The present invention has been made in view of the above-described facts, and is a semiconductor in which a timing condition for data transmission of a semiconductor element is changed and an instruction read by a branch instruction can be executed under a predetermined timing condition. An object of the present invention is to provide an integrated circuit device and a data transmission method for a semiconductor integrated circuit device.

  In order to achieve the above object, a semiconductor integrated circuit device according to a first aspect of the present invention comprises storage means for storing a plurality of different instruction data for identifying instructions instructing execution of processing, and a plurality of semiconductor elements, A first semiconductor integrated circuit unit capable of transmitting data between the semiconductor elements in a first time under a predetermined timing condition that affects the timing of data transmission; and a plurality of semiconductor elements. And a second semiconductor integrated circuit unit that does not finish transmitting data between the semiconductor elements unless the second time is longer than the first time. Next, an instruction for sequentially reading a plurality of instruction data including the instruction data of the instruction to be executed is given, and each of the plurality of instruction data read in order according to the instruction is input to each instruction data. Control means to be transmitted to the first semiconductor integrated circuit portion or the second semiconductor integrated circuit portion determined in accordance with the data, and the read instruction is given by the control means, and the plurality of instruction data according to the instruction Are sequentially read out from the storage means and input to the control means, and a reference signal serving as a reference for data transmission timing is generated in each semiconductor element at the first time interval. The second semiconductor integrated circuit unit completes the transmission of the data within a predetermined time determined according to the input interval of the reference signal while the generation means for inputting to the element and the predetermined instruction signal are continuously input. A change means for changing the timing condition for the second semiconductor integrated circuit portion, and the plurality of instruction data output by the read input means are sequentially input, When the input command data is the first command data that is predetermined to be transmitted to the second semiconductor integrated circuit unit, the control means causes the second semiconductor integrated circuit unit to When the first instruction data starts to be transmitted, the instruction means for continuously inputting the instruction signal to the changing means and the second instruction data for identifying the instruction to be executed next are read out from the storage means. Is determined in advance, the plurality of instruction data output by the read input means are sequentially input, and the input instruction data is the third instruction data. And the instruction means inputs the instruction signal to the changing means, the second command data read from the storage means is transferred to the first semiconductor collection by the control means. Stop means for stopping the input of the instruction signal by the instruction means and returning the changed timing condition to the predetermined timing condition when transmitted to the product circuit section.

  A semiconductor integrated circuit device according to a second aspect of the present invention is the semiconductor integrated circuit device according to the first aspect, wherein the second instruction data is stored in the branch instruction only when a predetermined execution condition is satisfied. A conditional branch instruction to be read next from the storage means is included; and the third instruction data includes fourth instruction data for identifying the conditional branch instruction; It is determined whether or not the execution condition is satisfied in response to the input of the fourth instruction data, and when it is determined that the execution condition is not satisfied, the interruption by the stop unit is invalidated. It is characterized by controlling to.

  According to a third aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first or second aspect, wherein the changing means increases the input interval of the reference signal as the change of the timing condition. At least one of the changing process and the second changing process for increasing the voltage applied to each semiconductor element is performed.

  According to a fourth aspect of the present invention, there is provided a data transmission method for a semiconductor integrated circuit device according to the first aspect, wherein the control means includes the third command data, the first command data, and the second command data. An instruction for sequentially reading instruction data is given, and the reading input means reads out the third instruction data, the first instruction data, and the second instruction data from the storage means in order according to the instruction. When the control means, the instruction means, and the stop means are input, the instruction means inputs the instruction signal to the change means in response to the input of the first command data; and the change means However, while the instruction signal continues to be input, the second semiconductor integrated circuit unit finishes the transmission of the data within a predetermined time determined according to the input interval of the reference signal. A step of changing the timing condition for the semiconductor integrated circuit unit; and the control means ignores the first instruction data input next to the third instruction data, and outputs the second instruction data. The step of transmitting to the first semiconductor integrated circuit section; and the stopping means when the second command data is transmitted to the first semiconductor integrated circuit section by the control means. Stopping the input of the instruction signal and returning the changed timing condition to the predetermined timing condition.

  A fifth aspect of the present invention is the data transmission method of the semiconductor integrated circuit device according to the first aspect, wherein the control means includes the first command data, the third command data, and the second command data. An instruction to sequentially read out the instruction data is given, and the reading input means reads out the first instruction data, the third instruction data, and the second instruction data from the storage means in order according to the instruction. When the control means, the instruction means, and the stop means are input, the control means transmits the first command data to the second semiconductor integrated circuit unit, and the instruction means includes the The step of inputting the instruction signal to the changing means in response to the input of the first command data, and the changing means is determined according to the input interval of the reference signal while the instruction signal is continuously input. Changing the timing condition for the second semiconductor integrated circuit unit so that the second semiconductor integrated circuit unit finishes transmission of the data within a predetermined time; and the control means includes the first The command data is transmitted to the second semiconductor integrated circuit unit, and then the second command data input by the read input unit is transmitted to the first semiconductor integrated circuit unit; When the second command data is transmitted to the first semiconductor integrated circuit unit by the control unit, the input of the instruction signal by the instruction unit is stopped and the changed timing condition is determined in advance. Returning to the set timing condition.

  A sixth aspect of the present invention is the data transmission method of the semiconductor integrated circuit device according to the second aspect, wherein the control means gives an instruction to sequentially read the fourth instruction data and the first instruction data. At the same time, the read input means reads the fourth command data and the first command data from the storage means in order according to the instruction, and inputs them to the control means, the instruction means, and the stop means. The instruction means inputs the instruction signal to the change means in response to the input of the first command data; and the change means inputs the reference signal while the instruction signal is continuously input. The timing condition for the second semiconductor integrated circuit unit is changed so that the second semiconductor integrated circuit unit completes the transmission of the data within a predetermined time determined according to the interval. And the control means determines whether or not the predetermined execution condition is satisfied according to the input of the fourth instruction data, and determines that the execution condition is not satisfied And the step of controlling the interruption by the stopping means to be invalid and transmitting the first command data to the second semiconductor integrated circuit unit.

  A data transmission method for a semiconductor integrated circuit device according to a seventh aspect of the present invention is the data transmission method according to any one of the fourth to sixth aspects, wherein the changing means is configured to change the reference signal as the change of the timing condition. At least one of a first changing process for increasing the input interval and a second changing process for increasing the voltage applied to each semiconductor element.

  According to the present invention, when the branch instruction data is read and the timing condition is changed, when the instruction data corresponding to the branch instruction data is transmitted to the semiconductor integrated circuit unit, the changed timing condition is set in advance. Since the timing is returned to the predetermined timing condition, there is an effect that the instruction read according to the branch instruction can be executed under the predetermined timing condition.

It is a block diagram which shows the microcontroller 100 of a prior art. It is a figure which shows the read data example 200 at the time of the instruction fetch of a prior art. It is a figure which shows the example instruction opcode 300 of a prior art. It is a conceptual diagram of a critical path. It is a circuit diagram of the command prefetch circuit 120 of a prior art. It is a circuit diagram of the clock mask circuit 130 of a prior art. It is a time chart of a prior art. It is a time chart through a critical path. It is another time chart of a prior art. FIG. 2 is a circuit diagram of an instruction prefetch circuit 120 in the first embodiment of the present invention. It is a time chart of the critical path instruction after the branch instruction in 1st Embodiment of this invention. It is a time chart of the branch instruction after the critical path instruction in the first embodiment of the present invention. It is a block diagram of the microcontroller 100 in 2nd Embodiment of this invention. It is a circuit diagram of the instruction prefetch circuit 120 in the 2nd Embodiment of this invention. It is a time chart of the critical path instruction after the branch instruction in the second embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  Since the following first embodiment and second embodiment of the present invention are based on the contents of Patent Document 1 of the above prior art, this technique will be described in detail below.

(Construction of conventional technology)
FIG. 1 is a block diagram showing a conventional microcontroller 100.

  The microcontroller 100 includes a clock generation circuit 102 (generation means), a master 104 (control means), a slave 106 (read input means), a memory 108 (storage means), and a regulator 110.

  The clock generation circuit 102 includes a clock mask circuit 130 (processing mode changing means). Based on a clock clk0 signal supplied from the outside of the microcontroller 100, the clock signals clk and clk1 are supplied to the inside of the microcontroller 100. It has a function to supply to each block. The clock signals clk and clk1 are signals serving as a reference for data transmission timing to synchronize processing between each circuit in the computer or between each element of each circuit. The clock clk, The speed of the clk1 signal (including other clock signals) is called a clock frequency (an operating frequency, also simply called a clock).

  Further, the clock mask circuit 130 will be described in detail with reference to FIG.

  Further, the master 104 is constituted by a CPU, for example, and has a function of performing processing according to a predetermined program (stored in the memory 108 or the like). That is, the master 104 includes a plurality of semiconductor elements, and a plurality of semiconductor integrated circuits that transmit data between the respective semiconductor elements under a predetermined timing condition (clock signal input timing) that affects the data transmission timing. A circuit part is provided. The master 104 may be anything that outputs a command (instruction) for data processing.

  Further, the slave 106 includes, for example, an instruction prefetch circuit 120 as a memory controller, and has a function of receiving an access signal from the master 104 and returning a response. The slave 106 may be a system controller, and may employ a system such as DMA (Direct Memory Access). The instruction prefetch circuit 120 will be described in detail with reference to FIG.

  The memory 108 is a device that stores data (command data), a program, and the like.

  Further, the regulator 110 has a function of supplying a power supply voltage Vdd0 supplied from the outside of the microcontroller 100 to each circuit block (clock generation circuit 102, master 104, slave 106, and memory 108) inside the microcontroller 100. In addition, the regulator (Regulator) 110 means an adjustment device, and is called a power supply stabilization device or a transformer device in a computer system. Specifically, the present invention is a voltage rectifying element that uses a three-terminal regulator, has three terminals of input, ground, and output, and outputs an input DC power supply by making it a smooth constant current.

  More specifically, the clock generation circuit 102 is connected to the master 104, the slave 106, the memory 108, and the regulator 110, and the clock clk signal output from the clock generation circuit 102 is the master 104, the slave 106, and the memory 108. , And to the regulator 110. The regulator 110 is connected to the clock generation circuit 102, the master 104, the slave 106, and the memory 108. The power supply voltage Vdd output from the regulator 110 is the clock generation circuit 102, the master 104, the slave 106, and the memory. 108.

  The microcontroller 100 operates according to a predetermined sequence. The sequence is sequence control (Sequential Control), and is control in which each step of control is sequentially advanced according to a predetermined order or procedure, and is used for each step at that time. Terminology will be explained in advance.

(Instruction fetch, op_fetch signal, and ready signal)
The master 104 performs instruction fetch (takes out an instruction opcode (instruction data) processed by the processor from the memory and transfers it to a register) in order to execute a program to be executed. In addition, the master 104 outputs an op_fetch signal indicating that instruction fetch is being executed to the slave 106. Then, an instruction issued by the master 104 and a ready signal indicating that the next instruction can be executed are received. Specifically, this instruction fetch access reads (reads) a program stored in the memory 108 via the slave 106.

(Read access)
Since the instruction fetch is executed from the master 104, the slave 106 performs read access (access for reading desired data) to the memory.

(Read data rdata1)
The memory 108 outputs read data rdata1 that is data stored at an address corresponding to read access from the slave 106 to the slave 106.

(Read data rdata2)
When the read data rdata1 is input from the memory 108, the slave 106 inputs the read data rdata2 to the master 104.

(Clock clk1 signal)
The clock clk1 signal is a clock (clock signal) that is supplied from the clock mask circuit 130 and operates the instruction prefetch circuit 120.

(Cri_flag signal)
The cri_flag signal (instruction signal) is output from the instruction prefetch circuit 120 to the clock mask circuit 130, and the clock frequency is slowed by masking the clock signal clk0 at a predetermined interval (one clock signal for two clock signals). The instruction to output the clock signal clk is a signal.

(Instruction execution)
The master 104 executes a program based on the read data rdata2 received from the memory 108 via the slave 106. Specifically, an instruction code (see FIG. 2) is provided in the read data rdata2 received on the basis of the instruction fetch, op_fetch signal, and ready signal transmitted from the master 104 to the slave 106 so that the master 104 can determine the instruction to be executed. Instruction opcode) is stored. Then, the instruction code stored in the read data rdata2 is transmitted to the semiconductor integrated circuit unit determined according to the instruction code, and a predetermined program is executed.

  The read data at the time of instruction fetch stores data such as an instruction opcode as shown in FIG. The instruction opcode is a code in which an instruction to be executed by the master 104 is stored in the 8th to 10th bits of the read data rdata1 (refer to the instruction opcode example 300 in FIG. 3). ).

  For example, the instruction code load instruction is the instruction opcode “000”, and the instruction code store instruction is the instruction opcode “001”, indicating the relationship between the instruction code and the instruction opcode. Note that each value of the instruction opcode is located at the 10th to 8th bits in the read data rdata1 from the left.

  As shown in FIG. 2, the other bits of the read data rdata1 store a source address and a destination address used when the master 104 executes an instruction. That is, the 0th to 3rd bits indicate a source address Rs (which is an authority address and is an address to which data used for processing is referred) and is represented as rdata1 [3: 0]. The fourth to seventh bits indicate the destination address Rd (the destination address, which is the address where the processing result is stored), and is represented as rdata1 [7: 4]. Further, as described above, the 8th to 10th bits indicate Opcode (instruction opcode), which is represented as rdata1 [10: 8]. The 11th to 31st bits indicate other codes etc, which are represented as rdata1 [31:11]. As described above, the read data rdata1 example 300 at the time of instruction fetch is shown by a 32-bit bus configuration represented by codes of “0” and “1”.

  The master 104 executes the program according to the read data rdata2 received by the instruction fetch. At that time, depending on the type of instruction, there is an instruction passing through the critical path 420.

  The critical path 420 is a path (path) that takes the most time for signal propagation as described above, and is a path that regulates the operation of the circuit. Note that which semiconductor integrated circuit unit is the critical path 420 among the plurality of semiconductor integrated circuit units is specified in advance by simulation using a computer or the like. Any means that can identify the critical path 420 may be used.

  Accordingly, signal propagation in the critical path 420 includes gate delay and wiring delay.

  The gate delay is a delay generated when a signal passes through a gate such as an AND circuit. Furthermore, the wiring delay is literally a delay in the timing at which a signal is transmitted to the wiring. As a result of the progress in miniaturization and the increase in transistor performance to the limit, there is a delay in signal transmission that occurs between the transistors on the connection wiring. Therefore, the performance of the entire microcontroller 100 has been hindered.

  FIG. 4 shows a conceptual diagram of the critical path 420.

  The flip-flop circuit 402, the flip-flop circuit 404, and the flip-flop circuit 406 operate at the rising edge of the clock clk signal generated by the clock generation circuit 102.

  The flip-flop circuit 402 is connected to the flip-flop circuit 404 via four stages of buffers 410 412 414 416.

  Therefore, the signal I input to the flip-flop circuit 402 is input to the flip-flop circuit 404 via the four stages of buffers 410, 412, 414, and 416, and the signal VII is output.

  Further, the flip-flop circuit 406 and the flip-flop circuit 402 are connected via a one-stage buffer 418.

  Specifically, the signal II output from the flip-flop circuit 402 is input to the buffer 410 and outputs the signal III. Further, the buffer 412 to which the signal III is input outputs the signal IV. Further, the buffer 414 to which the signal IV is input outputs the signal V. The buffer 416 to which the signal V is input outputs the signal VI, and the flip-flop circuit 404 to which the signal VI is input outputs the signal VII.

  Note that the clock clk signal is input to the flip-flop circuit 402, the flip-flop circuit 404, and the flip-flop circuit 406 and used as a synchronization signal. The power supply voltage Vdd is supplied to each circuit (the flip-flop circuit 402, the flip-flop circuit 404, the flip-flop circuit 406, and the buffers 410, 412, 414, 416, and 418).

  Here, it is assumed that the critical path 420 of this circuit is a path from the flip-flop circuit 402 to the flip-flop circuit 404.

  All these cells (the flip-flop circuit 402, the flip-flop circuit 404, the flip-flop circuit 406, and the cells of the buffers 410, 412, 414, 416, and 418) operate with the power supply voltage Vdd. Note that a cell is a minimum unit representing a function of a semiconductor when designing a semiconductor integrated circuit.

  FIG. 5 shows a circuit diagram of the instruction prefetch circuit 120.

  The instruction prefetch circuit 120 receives the op_fetch signal, the ready signal, the clock clk1 signal supplied from the clock mask circuit 130, and the read data rdata1 from the memory 108, and outputs a cri_flag signal.

  The flip-flop circuit 512 and the flip-flop circuit 514 of the instruction prefetch circuit 120 operate at the rising edge of the clock clk1 signal.

  The output terminal of the AND circuit 520 is connected to the input of the AND circuit 522.

  An output signal of the AND circuit 520 to which the op_fetch signal and the ready signal are input is transmitted to the AND circuit 522.

  Read data rdata1 [10] (10th bit) from the outside of the instruction prefetch circuit 120 is connected to the input of the AND circuit 522 via the inverter 530. Read data rdata1 [9] (9th bit) and read data rdata1 [8] (8th bit) are connected to the input of the AND circuit 522 from the outside of the instruction prefetch circuit 120. Further, the output terminal of the AND circuit 522 is connected to the input of the selector circuit 540 and the input of the inverter 534.

  The AND circuit 522 receives a signal obtained by inverting the 10th bit of the read data rdata1 by the inverter 530, a 9th bit signal of the read data rdata1, and an 8th bit signal of the read data rdata1.

  The output signal of the AND circuit 522 is transmitted as a select signal of the selector circuit 540 (a control signal for selecting and controlling the output signal of the selector circuit 540) and an input signal of the inverter 534.

  The AND circuit 522 outputs a signal when the value of the read data rdata1 to the AND circuit 522 is a multiplication instruction (“011” in FIG. 2) of an instruction fetch data passing through the critical path 420 (premise) conditions).

  The selector circuit 540 is connected to the output of the AND circuit 522, 1'b1 ("1" of 1-bit binary (binary number)), and the output terminal of the AND circuit 524. Further, the output terminal of the selector circuit 540 is connected to the input terminal of the flip-flop circuit 512, and the selector circuit 542 and the AND circuit 524 are connected to the output terminal of the flip-flop circuit 512.

  The output signal of the selector circuit 540 is input to the flip-flop circuit 512. Therefore, when the select signal input to the selector circuit 540 is “H”, the output signal of the selector circuit 540 is “H” (1′b1). When the select signal input to the selector circuit 540 is “L”, the output signal of the selector circuit 540 is the output signal of the AND circuit 524.

  Note that the output signal of the flip-flop circuit 512 is output from the instruction prefetch circuit 120 as a cri_flag signal, and is also transmitted as an input signal of the AND circuit 524 and a select signal of the selector circuit 542.

  The selector circuit 542 is connected to terminals of the output of the flip-flop circuit 512, the output of the counter circuit 560, and the output of the flip-flop circuit 514. The output terminal of the inverter 534 is connected to the input terminal of the flip-flop circuit 514 via the asynchronous reset terminal (negative reset terminal) rn, and the output terminal of the selector circuit 542 is also connected to the input terminal of the flip-flop circuit 514. ing. Further, the output terminal of the flip-flop circuit 514 is connected to the input of the selector circuit 542, the input of the counter circuit 560, and the input terminal of the comparison circuit 550. In the comparison circuit 550, the output of the flip-flop circuit 514 and ‘d100 (“ 100 ”in decimal digits) are input. The output terminal of the comparison circuit 550 is connected to the other input terminal of the AND circuit 524 via the inverter 532.

  The output signal of the selector circuit 542 is input to the flip-flop circuit 514. Therefore, when the select signal input to the selector circuit 542 is “H”, the output signal of the selector circuit 542 becomes the value of the output signal + 1 of the flip-flop circuit 514 by the counter circuit 560. When the select signal input to the selector circuit 542 is “L”, the output signal of the selector circuit 542 is the output signal of the flip-flop circuit 514.

  Then, the flip-flop circuit 514 receives an asynchronous reset signal (a negative reset signal indicating an inverted reset) via the inverter 534 and the negative reset terminal rn, holds “0” when “L”, and performs a reset. . Further, the comparison circuit 550 compares the output signal of the flip-flop circuit 514 with a fixed decimal number “100” and sets the output signal “H” when the value of the flip-flop circuit 514 reaches 100, otherwise In this case, the output is “L”. Specifically, when the value of the flip-flop circuit 514 becomes 100 and becomes the output signal “H”, the value of the flip-flop circuit 514 is reset, and when the output signal is “L”, the value of the flip-flop circuit 514 is Continue counting by +1.

  The clock clk1 signal is input to the flip-flop circuit 512 and the flip-flop circuit 514 so as to operate in synchronization with each other.

  Further, the asynchronous reset signal is first reset asynchronously with a trigger of the AND circuit 522 rising.

  The reason why the inverter 530 and the AND circuit 523 are provided is that the multiplication instruction data passing through the critical path 420 is “011”. Accordingly, when it is not a multiplication instruction when passing through the critical path 420, for example, in the case of the AND instruction “101”, there is no inverter 530 at the place where the read data rdata1 [10] is input, and the read data rdata1 [9] is input. An inverter 530 is installed at the input location. As described above, in the critical path 420, the delay of elements, wiring, etc. is large only after a certain place is known based on conditions such as what instruction takes time and how often it is involved. Therefore, a multiplication instruction as in the present invention may not be a precondition.

  FIG. 6 shows a circuit diagram of the clock mask circuit 130.

  The selector circuit 630 is connected with an output terminal from the instruction prefetch circuit 120 (cri_flag signal), a fixed value “0”, and an output terminal of the inverter 620 as a controller signal. The output terminal of the selector circuit 630 is connected to the input terminal of the flip-flop circuit 610. Further, in the flip-flop circuit 610, the output terminal of the flip-flop circuit 610 is connected to the input of the inverter 620 and the input terminal of the OR circuit 640. The clock clk0 signal terminal is connected to the input terminal of the flip-flop circuit 610 and the input terminal of the OR circuit 640 from the outside of the microcontroller 100.

  The clock mask circuit 130 receives a clock clk0 signal supplied from the outside of the microcontroller 100 and a cri_flag signal that is an output signal from the instruction prefetch circuit 120. The clock mask circuit 130 outputs a clock clk1 signal for operating the instruction prefetch circuit 120. Further, the clock mask circuit 130 outputs a clock clk signal for operating the master 104, the slave 106, the memory 108, and the regulator 110.

  The input signal cri_flag signal is transmitted as a select signal of the selector circuit 630.

  In the selector circuit 630, when the select signal (cri_flag signal) is “0”, the output of the selector circuit 630 is fixed at “0”. When the select signal (cri_flag signal) is “1”, the output signal of the selector circuit 630 selects the output signal of the inverter 620.

  The output signal of the flip-flop circuit 610 is transmitted to the selector circuit 630 via the inverter 620. Further, the output signal of the flip-flop circuit 610 is input as an input signal of the OR circuit 640. The flip-flop circuit 610 holds the initial value “0” because the clock clk0 signal is input from outside the microcontroller 100.

  The clock clk0 signal is input to the other input of the OR circuit 640, and the output signal is output from the clock mask circuit 130 as the clock clk signal. The other output signal clock clk1 signal is the same as the clock clk0 signal (clock clk1 signal = clock clk0 signal).

(Operation of conventional technology)
Next, the operation of the prior art will be described below.

  First, with reference to FIG. 7, an operation in the case where reading of branch instruction data is not instructed will be described.

  At time T1, instruction fetch from the master 104 to the address 0x0000_0000 (Hexadecimal) is executed. At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T2, a read access from the slave 106 to the memory 108 occurs.

  At time T3, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is the critical path multiplication instruction “011”.

  At time T4, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the AND circuit 522, the selector circuit 540, and the ready signal of the instruction prefetch circuit 120 become “H” (trigger).

  At time T5, the output signal of the AND circuit 522 of the instruction prefetch circuit 120 becomes “L”, and the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “H”, so that the cri_flag signal also becomes “H”, and the flip-flop circuit 514 Starts counting up from zero. Specifically, at time T4, the “H” signal of the AND circuit 522 is triggered to start counting. Further, the master 104 outputs an instruction fetch for the next address 0x0000_0004 (Hexadecimal).

  At time T6, when the cri_flag signal becomes “H” at time T5, the flip-flop circuit 610 of the clock mask circuit 130 also becomes “H”, and one cycle (= clock clk1 signal) follows the rising edge of the clock clk0 signal (= clock clk1 signal). (Period) masks one by one. The period of the clock clk1 signal (clock clk0 signal), which is the normal clock frequency, is delayed and changed to the clock clk signal that has been reduced to half the normal clock frequency so as not to cause a malfunction even if it passes through the critical path. The

  At time T7, the flip-flop circuit 514 of the instruction prefetch circuit 120 becomes' d100 (decimal number 100), and the input signal of the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes "L".

  At time T8, since the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “L”, the cri_flag signal also becomes “L”, and the clock clk signal changed to half the normal clock frequency becomes the normal clock frequency. Work back.

  Next, referring to FIG. 8, a time chart 800 through the critical path 420 is shown.

  A time chart 800 is a time chart of the circuit of FIG.

  (Proceeding 1-1) At time T1, the signal I of the flip-flop circuit 402 changes to “1” by the rise of the clock clk signal.

  (Progress 1-2) At time T2, the signal I is held in the flip-flop circuit 402 at the rising edge of the clock clk signal.

  (Progress 1-3) At time T3, the signal II changes to “1”.

  (Progress 1-4) At time T4, the signal III changes to “1”.

  (Progress 1-5) At time T5, the signal IV changes to “1”.

  (Progress 1-6) At time T6, the signal V changes to “1”.

  (Progress 1-7) At time T7, the signal VI changes to “1”.

  (Progress 1-8) When the signal VI changes to “1” at time T8, since there is no rising edge of the clock clk signal, there is no next rising edge of the clock clk signal held by the flip-flop circuit 402.

  (Progress 1-9) At time T9, since the input data is held at the rising edge of the clock clk signal, the flip-flop circuit 404 holds the signal VI.

  (Progress 1-10) Since the signal VII is output as “1” at time T10, the signal propagation time from the flip-flop circuit 402 to the flip-flop circuit 404 is 1 which is a predetermined cycle of the clock frequency of the clock clk signal. Within a cycle (1 cycle).

  As described above, in the conventional technique, the frequency of the clock frequency can be reduced only when passing through the critical path 420 by prefetching the instruction passing through the critical path 420.

Next, referring to FIG. 9, the operation when the reading of the branch instruction data is instructed in the above-described prior art will be described.
Here, as described above, the branch instruction is an interrupt instruction, that is, an instruction whose content is to read the next instruction to be executed next from the memory. Accordingly, when an instruction fetch is executed from the normal master, the address is incremented. However, when control is transferred to an address away from a series of instructions by a branch instruction, the instruction address is not simply incremented. As an example, in the instruction fetch of ARM926, when fetching an instruction, the instruction fetch address is +4 such as 0x0000_0014 (Hexadecimal) after 0x0000_0010 (Hexadecimal), but 0xD000_0000 (after 0x0000_0010 (Hexadecimal) for a branch instruction Control is transferred to a distant address, not just an increment, as in (Hexadecimal).
At time T1, instruction fetch from the master 104 to the address 0x0000_0010 (Hexadecimal) is executed. At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T2, a read access from the slave 106 to the memory 108 occurs.

  At time T3, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is a branch instruction “100”.

At time T4, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the ready signal becomes “H”.
At time T5, the master 104 outputs an instruction fetch for the next address 0x0000_0014 (Hexadecimal). At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T6, read access from the slave 106 to the memory 108 occurs.

  At time T7, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is the critical path multiplication instruction “011”.

  At time T8, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the AND circuit 522, the selector circuit 540, and the ready signal of the instruction prefetch circuit 120 become “H” (trigger).

  At time T9, the output signal of the AND circuit 522 of the instruction prefetch circuit 120 becomes “L”, and the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “H”, so that the cri_flag signal also becomes “H”, and the flip-flop circuit 514 Starts counting up from zero. Specifically, at time T8, the “H” signal of the AND circuit 522 becomes a trigger pulse and starts counting. Further, the master 104 outputs an instruction fetch for the next address 0xD000_0000 (Hexadecimal). This address is an address branched by the branch instruction received by the master 104 at time T1. By executing the branch instruction, the master 104 does not execute the instruction 0x0000_0014 (Hexadecimal) that is the instruction next to the branch instruction. This instruction 0x0000_0014 (Hexadecimal) is executed by fetching the instruction again when returning from the branch instruction.

  At time T10, when the cri_flag signal becomes “H” at time T9, the flip-flop circuit 610 of the clock mask circuit 130 also becomes “H”, and one cycle (= clock clk1 signal) follows the rising edge of the clock clk0 signal (= clock clk1 signal). (Period) masks one by one. The period of the clock clk1 signal (clock clk0 signal), which is the normal clock frequency, is delayed and changed to the clock clk signal that has been reduced to half the normal clock frequency so as not to cause a malfunction even if it passes through the critical path. The

  Even at the time T11, even if the clock frequency is slowed down, the multiplication instruction with a critical path is not executed by the branch instruction, so that only the clock frequency slows down as a whole LSI. Therefore, there is a problem that the performance of the entire LSI is degraded.

  At time T13, the branch instruction for the address 0x0000_0010 (Hexadecimal) is completed, and the master 104 outputs an instruction fetch for the next address 0x0000_0014 (Hexadecimal). At the same time, the ready signal changes from “H” to “L”.

  At time T14, a read access from the slave 106 to the memory 108 occurs.

  At time T15, the flip-flop circuit 514 of the instruction prefetch circuit 120 becomes' d100 (decimal number 100), and the output of the input signal selector 540 of the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes "L". At the same time, read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is the critical path multiplication instruction “011”.

  At time T16, since the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “L”, the cri_flag signal also becomes “L”, and the clock clk signal changed to half the normal clock frequency becomes the normal clock frequency. Work back. Further, read data rdata2 is output from the slave 106 to the master 104. At the same time, the AND circuit 522, the selector circuit 540, and the ready signal of the instruction prefetch circuit 120 become “H” (trigger).

At time T17, the output signal of the AND circuit 522 of the instruction prefetch circuit 120 becomes “L” and the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “H”, so that the cri_flag signal also becomes “H”, and the flip-flop circuit 514 Starts counting up from zero. Specifically, at time T16, the “H” signal of the AND circuit 522 becomes a trigger pulse and starts counting.
Thus, during the period from time T9 to time T16 when the branch instruction is executed, the clock frequency is slowed down, and the performance of the entire LSI is degraded.

(First embodiment)
Next, a first embodiment of the present invention will be described.

(Configuration of the first embodiment)
FIG. 10 shows a circuit diagram of the instruction prefetch circuit 120 in the first embodiment. The same components as those in the above-described prior art instruction prefetch circuit 120 are designated by the same reference numerals, and the description thereof is omitted.

  The instruction prefetch circuit 120 in the first embodiment is provided with an instruction prefetch addition circuit 121 surrounded by a dotted line in FIG. 10 in addition to the circuit of the prior art instruction prefetch circuit 120 described above.

  The flip-flop circuit 730 of the instruction prefetch addition circuit 121 in the first embodiment operates at the rising edge of the clock clk1 signal.

  In the AND circuit 700, an output signal of the AND circuit 520, a 10th bit signal of the read data rdata1 from the outside, a signal obtained by inverting the 9th bit of the read data rdata1 from the outside by the inverter circuit 711, and a read data rdata1 from the outside A signal obtained by inverting the eighth bit of the inverter circuit 710 is input. Therefore, the AND circuit 700 outputs a signal (H) when the branch instruction data “100” exists in the read data rdata1.

  The output signal terminal of the AND circuit 700 is connected to the OR circuit 740, and the output signal terminal of the inverter circuit 712 is connected to the other input terminal of the OR circuit 740.

  The inverter circuit 712 receives a signal that becomes “H” when the output signal of the flip-flop circuit 730 is zero.

  The output signal of the OR circuit 740 is connected to the select signal of the selector circuit 720. The selector circuit 720 is connected to an output signal of the flip-flop circuit 730 and a signal obtained by adding +1 to the output signal.

  In the selector circuit 721, each of the output of the selector circuit 720, a signal that becomes “H” when the output signal of the flip-flop circuit 730 is 5, and 3′b000 (3-bit binary (binary) “000”) terminals Is connected. The select signal of the selector circuit 721 is a signal that becomes “H” when the output signal of the flip-flop circuit 730 is “5”.

  Further, the output terminal of the selector circuit 721 is connected to the input terminal of the flip-flop circuit 730. Therefore, when the select signal input to the selector circuit 721 is “H”, the output signal of the selector circuit 721 is 3′b000. When the select signal input to the selector circuit 721 is “L”, the output signal of the selector circuit 721 is the output signal of the selector circuit 720. That is, when the select signal input to the selector circuit 721 is “L” and the select signal input to the selector circuit 720 is “H”, the output signal of the selector circuit 721 is a signal obtained by adding 1 to the output of the flip-flop 730. When the select signal input to the selector circuit 721 is “L” and the select signal input to the selector circuit 720 is “L”, the output signal of the flip-flop 730 is output as the output signal of the selector circuit 721. Note that the initial value of the flip-flop 730 is “0”.

  A signal that becomes “H” when the output signal of the flip-flop circuit 730 is 5 is input to the inverter circuit 713 and connected to the AND circuit 701. The AND circuit 701 replaces the AND circuit 524 of the conventional instruction prefetch circuit, but the AND circuit 701 has the same configuration as the AND circuit 524 except that the output signal of the inverter circuit 713 is input to the input. .

(Operation of the first embodiment)
Next, the operation of the first embodiment will be described. FIG. 11 shows a time chart of the critical path instruction after the branch instruction in the first embodiment of the present invention.

In the first embodiment of the present invention, it is assumed that a critical path is passed during a multiplication instruction (precondition). Further, it is assumed that the master 104 executes the branch instruction after 5 cycles after receiving the read data rdata2 (branch instruction).
At time T1, instruction fetch from the master 104 to the address 0x0000_0010 (Hexadecimal) is executed. At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. As described above, since the instruction fetch is executed by the master 104, the ready signal simultaneously changes from “H” to “L” in order to follow this instruction by the slave 106.

  At time T2, a read access from the slave 106 to the memory 108 occurs.

  At time T3, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. It is assumed that the instruction data at this time is branch instruction data “100”.

At time T4, the slave 106 outputs read data rdata2 to the master 104 and the instruction prefetch circuit 120. Thus, since the slave 106 has executed the instruction fetch by the master 104, the ready signal is set to “H” in order to enable the next instruction fetch. As described above, since the 10th to 8th bits of the read data rdata2 are 1, 0 and 0 of the branch instruction data, the 1st and 9th bits of the 10th bit are inverted by the inverter 711, and 8th The bit 0 is inverted by the inverter 710 and input to the AND circuit 700 of the instruction prefetch circuit 120, and the output signal of the AND circuit 700 also becomes “H”.
At time T5, the master 104 outputs an instruction fetch for the next address 0x0000_0014 (Hexadecimal). At this time, the signal op_fetch signal indicating the instruction fetch remains “H”. As described above, the ready signal is changed from “H” to “L”.

  At this time, since the signal of the flip-flop circuit 730 is 0 and not 5, the L signal is input to the selector 721 as the select signal. Further, the signal added by +1 circuit is input to the 1 (H) side of the selector circuit 720. Then, as described above, when the output signal of the AND circuit 700 becomes “H”, the select signal of the selector circuit 720 becomes “H” via the OR circuit 740, and the +1 signal becomes the selector circuit 720, the selector The signal is input to the flip-flop circuit 730 via the circuit 721, and the flip-flop circuit 730 starts counting up from the initial value “0”.

  At time T6, read access from the slave 106 to the memory 108 occurs. Note that the signal op_fetch signal indicating the instruction fetch remains “H”.

  At time T7, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. It is assumed that the instruction at this time is critical path multiplication instruction data “011”.

  At time T8, the slave 106 outputs the read data rdata2 (the 10th to 8th bits are 0, 1, 1) to the master 104 and the instruction prefetch circuit 120, and the ready signal is “ It is changed from “L” to “H”.

  The 10th bit (0) of the read data rdata2 is inverted by the inverter 530, and the 9th bit (1) and the 8th bit (1) are respectively input to the AND circuit 522 of the instruction prefetch circuit 120, and as described above Since the signal op_fetch signal indicating instruction fetch remains “H” and the ready signal is also “H”, the output signal of the AND circuit 522 becomes “H” (trigger). As a result, the output signal (H) is input from the select circuit 540 to the flip-flop circuit 512 of the instruction prefetch circuit 120.

  Thus, since the output signal (H) is input from the select circuit 540 to the flip-flop circuit 512 of the instruction prefetch circuit 120, the output signal of the flip-flop circuit 512 becomes “H”. Therefore, the cri_flag signal becomes “H” immediately after time T9, and the flip-flop circuit 514 starts counting up from zero.

  By the way, as described above, the output of the flip-flop circuit 730 that starts counting up from 0 at time T4 every time the clock signal clk1 is input becomes “5” at time T9. The signal (H) is output from the circuit that outputs H), the select signal of the selector circuit 721 becomes “H”, 0 (3′b000) is output from the select circuit 721, and the flip-flop 730 stops counting, The output of the inverter circuit 713 is “L”. When the output of the inverter circuit 713 becomes “L”, the output of the AND circuit 701 also becomes “L”, and the output of the selector circuit 540 also becomes “L”. At the same time, the input signal of the flip-flop circuit 512 becomes “L”.

  On the other hand, the master 104 outputs an instruction fetch for the next address 0xD000_0000 (Hexadecimal) according to the branch instruction data. This address is an address branched by the branch instruction of the instruction fetch address issued by the master 104 at time T1. Since the master 104 executes the branch instruction, it does not execute the instruction 0x0000_0014 (Hexadecimal) that is the instruction next to the branch instruction.

  As described above, since the cri_flag signal becomes “H” at time T9, the flip-flop circuit 610 of the clock mask circuit 130 also becomes “H”, and one cycle follows the rising of the clock clk0 signal (= clock clk1 signal). As described above, since the input signal to the flip-flop circuit 512 is “L” immediately after time T9, the cri_flag signal is also “L” immediately after time T10. Since the select signal to the selector circuit 721 becomes “H” immediately after time T9, 0 is output from the select circuit 721 and the output of the flip-flop circuit 730 is “0”.

  At time T11, the multiplication instruction is not executed due to the execution of the branch instruction (does not pass through the critical path), so there is no need to reduce the clock frequency. In this regard, first, immediately after time T8, the output of the AND circuit 522 becomes H, and immediately after time T9, the cri_flag signal becomes H, but the output of the flip-flop 730 becomes 5, and when it is 5, the signal (H) is output. A signal (H) is output from the circuit, inverted by the inverter 713, input to the AND circuit 701, the output of the AND circuit 701 becomes L, input to the flip-flop circuit 512, and the cri_flag signal of the flip-flop circuit 512 is also “L”. ", The flip-flop 610 is stopped, and the clock frequency is restored.

  On the other hand, read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1.

At time T <b> 12, the read data rdata <b> 2 is output from the slave 106 to the master 104. At the same time, the ready signal becomes “H”. Thereafter, the clock frequency is not changed by the critical path, and the instruction (instruction code 000 (load)) designated and read at time T9 is executed under normal conditions.
FIG. 12 shows a time chart of the branch instruction after the critical path instruction in the first embodiment of the present invention.

  At time T1, instruction fetch from the master 104 to the address 0x0000_0010 (Hexadecimal) is executed. At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T2, a read access from the slave 106 to the memory 108 occurs.

  At time T3, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is assumed to be a critical path multiplication instruction “011”.

  At time T4, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the AND circuit 522, the selector circuit 540, and the ready signal of the instruction prefetch circuit 120 become “H” (trigger).

  At time T5, the output signal of the AND circuit 522 of the instruction prefetch circuit 120 becomes “L”, and the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “H”, so that the cri_flag signal also becomes “H”, and the flip-flop circuit 514 Starts counting up from zero. Specifically, at time T4, the “H” signal of the AND circuit 522 is triggered to start counting. Further, the master 104 outputs an instruction fetch for the next address 0x0000_0014 (Hexadecimal). At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T6, when the cri_flag signal becomes “H” at time T5, the flip-flop circuit 610 of the clock mask circuit 130 also becomes “H”, and one cycle (= clock clk1 signal) follows the rising edge of the clock clk0 signal (= clock clk1 signal). (Period) masks one by one. The period of the clock clk1 signal (clock clk0 signal), which is the normal clock frequency, is delayed and changed to the clock clk signal that has been reduced to half the normal clock frequency so as not to cause a malfunction even if it passes through the critical path. The Also, read access from the slave 106 to the memory 108 occurs.

  At time T7, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. It is assumed that the instruction at this time is a branch instruction “100”. At the same time, the flip-flop circuit 610 of the clock mask circuit 130 becomes “L”, and the clk signal is masked one cycle (period) at the rising edge of the clock clk0 signal (= clock clk1 signal).

At time T8, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the ready signal becomes “H”. Further, the AND circuit 700 of the instruction prefetch circuit 120 is also set to “H”.
At time T9, the master 104 outputs an instruction fetch for the next address 0x0000_0018 (Hexadecimal). At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”. Further, the flip-flop circuit 730 has an initial value “0” because the select signal of the selector circuit 720 is “H” and the select signal of the selector circuit 721 is “L” when the AND circuit 700 becomes “H”. Start counting up.

  At time T10, read access from the slave 106 to the memory 108 occurs.

  At time T11, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is assumed to be a load instruction “000”.

  At time T <b> 12, the read data rdata <b> 2 is output from the slave 106 to the master 104. At the same time, the ready signal becomes “H”.

At time T13, the master 104 outputs an instruction fetch for the next address 0xD000_0004 (Hexadecimal). This address is at time T5
This is the address branched by the branch instruction of the instruction fetch address issued by the master 104. By executing the branch instruction, the master 104 does not execute the instruction 0x0000_0018 (Hexadecimal) that is the instruction next to the branch instruction.

  At time T14, since the output of the flip-flop circuit 730 becomes “5”, the select signal of the selector circuit 721 becomes “H” and the output of the inverter circuit 713 becomes “L”. When the output of the inverter circuit 713 becomes “L”, the output of the AND circuit 701 also becomes “L”, and the output of the selector circuit 540 also becomes “L”. At the same time, the input signal of the flip-flop circuit 512 becomes “L”.

  At time T15, since the input signal of the flip-flop circuit 512 is “L” at time T14, the cri_flag signal is also “L”. At time T14, since the select signal of the selector circuit 721 becomes “H”, the output of the flip-flop circuit 730 becomes “0”.

At time T16, since the master 104 executes the branch instruction, the multiplication instruction with the critical path is not executed. Therefore, since it is not necessary to slow down the clock frequency, the count-up of the flip-flop circuit 514 is stopped and the clock frequency is restored. Thereafter, normal operation is performed without changing the clock frequency by the critical path.
As described above, according to the first embodiment of the present invention, even when there are branch instructions before and after the critical path instruction, when executing the branch instruction, the instruction is executed with the clock frequency restored. Therefore, during the period in which the branch instruction is executed, the operation is performed at a normal clock frequency, and the performance of the entire LSI can be prevented from being deteriorated. As a result, the master processing time can be reduced and the performance of the entire LSI can be improved.

(Second Embodiment)
(Configuration of Second Embodiment)
FIG. 13 shows a configuration diagram according to the second embodiment of the present invention. The same components as those in the above-described prior art microcontroller 100 are designated by the same reference numerals and their description is omitted.

The microcontroller 100 outputs the address 150 (addr) from the master 104 and inputs it to the slave 106.
FIG. 14 is a circuit diagram of the instruction prefetch circuit 120 according to the second embodiment of the present invention. The same reference numerals are given to the same components as those in the configuration diagram showing the circuit of the instruction prefetch circuit 120 in the first embodiment in FIG.

  The instruction prefetch circuit 120 is further provided with an instruction prefetch addition circuit 122 surrounded by a dotted line in FIG. 14 to the instruction prefetch circuit 120 in the first embodiment of FIG.

  The flip-flop circuit 800 of the instruction prefetch addition circuit 122 in the second embodiment operates at the rising edge of the clock clk1 signal.

  The flip-flop circuit 800 is connected to an output terminal for an address addr from the outside.

  The address addr from the outside and a signal obtained by adding +4 to the output signal of the flip-flop 800 are connected to the comparison circuit 810. The comparison circuit 810 outputs “H” when the address addr from the outside is the same value as the output signal of the flip-flop 800 or a signal obtained by adding +4 to the output signal of the flip-flop 800, and outputs “L” when the value is other than that. "Is output.

  The output signal terminal of the comparison circuit 810 is connected to the OR circuit 820, and the output signal terminal of the inverter circuit 713 is connected to the other input of the OR circuit 820.

  An output signal terminal of the OR circuit 820 is connected to the AND circuit 830. The connection of the AND circuit 830 is different from the AND circuit 701 of the circuit of the instruction prefetch circuit 120 in the first embodiment of FIG. 10 of the present invention only in the one connection, but other than that, the connection of the AND circuit 830 of FIG. The configuration is the same as that of the AND circuit 701 of the instruction prefetch circuit 120 in the first embodiment.

(Operation of Second Embodiment)
The operation of the second embodiment of the present invention will be described below. FIG. 15 shows a time chart of a critical path instruction after a branch instruction in the second embodiment of the present invention.

  FIG. 13 shows a time chart of a critical path instruction after a branch instruction in the second embodiment of the present invention. This branch instruction is a conditional branch instruction, and is a case where the condition of the conditional branch instruction is not satisfied in the time chart of FIG. Here, the conditional branch instruction is an instruction that branches (reads the next instruction data) only when a certain condition is satisfied, and does not branch when a certain condition is not satisfied.

In the second embodiment of the present invention, it is assumed that a critical path is taken during a multiplication instruction (precondition). Further, it is assumed that the master 104 executes the branch instruction after 5 cycles after receiving the read data rdata2 (branch instruction).
At time T1, instruction fetch from the master 104 to the address 0x0000_0010 (Hexadecimal) is executed. At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”.

  At time T2, a read access from the slave 106 to the memory 108 occurs. At the same time, the flip-flop 800 holds the value 0x0000_0010 of the address addr. The output of the comparison circuit 810 is “H” because the address addr and the output signal value of the flip-flop 800 are the same.

  At time T3, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is a branch instruction “100”. However, this branch instruction is a conditional branch instruction.

At time T4, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the ready signal becomes “H”. Further, the AND circuit 700 of the instruction prefetch circuit 120 is also set to “H”.
At time T5, the master 104 outputs an instruction fetch for the next address 0x0000_0014 (Hexadecimal). At this time, the signal op_fetch signal indicating the instruction fetch becomes “H”. At the same time, the ready signal changes from “H” to “L”. Further, the flip-flop circuit 730 has an initial value “0” because the select signal of the selector circuit 720 is “H” and the select signal of the selector circuit 721 is “L” when the AND circuit 700 becomes “H”. Start counting up. At this time, the output of the comparison circuit 810 becomes “H” because the value added to the address addr and the output signal of the flip-flop 800 is +4.

  At time T6, read access from the slave 106 to the memory 108 occurs. At the same time, the flip-flop 800 holds the value 0x0000_0014 of the address addr. The output of the comparison circuit 810 is “H” because the address addr and the output signal value of the flip-flop 800 are the same.

  At time T7, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. The instruction at this time is the critical path multiplication instruction “011”.

  At time T8, the read data rdata2 is output from the slave 106 to the master 104. At the same time, the AND circuit 522, the selector circuit 540, and the ready signal of the instruction prefetch circuit 120 become “H” (trigger).

  At time T9, the output signal of the AND circuit 522 of the instruction prefetch circuit 120 becomes “L”, and the flip-flop circuit 512 of the instruction prefetch circuit 120 becomes “H”, so that the cri_flag signal also becomes “H”, and the flip-flop circuit 514 Starts counting up from zero. Specifically, at time T8, the “H” signal of the AND circuit 522 becomes a trigger pulse and starts counting. Since the output of the flip-flop circuit 730 is “5”, the select signal of the selector circuit 721 is “H”, and the output of the inverter circuit 713 is “L”. Although the output of the inverter circuit 713 is “L”, the output of the comparison circuit 810 is “H”, so the output of the OR circuit 820 is also “H”, the output of the AND circuit 701, the output of the selector circuit 540, and The input signal of the flip-flop circuit 512 remains “H”. Here, the master 104 outputs an instruction fetch for the next address 0x0000_0018 (Hexadecimal). This address is an address that is branched by the branch instruction of the instruction fetch address issued by the master 104 at time T1. In this case, since the condition of the conditional branch instruction is not satisfied, the incremented address 0x0000_0018 (Hexadecimal) Issue.

  At time T10, when the cri_flag signal becomes “H” at time T9, the flip-flop circuit 610 of the clock mask circuit 130 also becomes “H”, and one cycle (= clock clk1 signal) follows the rising edge of the clock clk0 signal (= clock clk1 signal). (Period) masks one by one. Further, since the select signal of the selector circuit 721 becomes “H” at time T9, the output of the flip-flop circuit 730 becomes “0”.

  At time T11, the read data rdata1 is output from the memory 108, and the slave 106 receives the read data rdata1. Thereafter, while the multiplication instruction is being executed, the clock frequency is changed to operate.

  As described above, according to the second embodiment of the present invention, in addition to the effect of the first embodiment of the present invention, even when not branching by a conditional branch instruction, the operation is performed at the optimum clock frequency. It is possible to prevent the performance of the entire LSI from being degraded. As a result, the master processing time can be reduced and the performance of the entire LSI can be improved.

(Modification of the first embodiment and the second embodiment)
In the first embodiment and the second embodiment described above, the process of increasing the input interval of the clock signal (first change process) is executed as the change of the timing condition. It is not limited to this. That is, as shown in Patent Document 1 described above, if the voltage applied to each semiconductor element in the critical path is increased, the data transmission speed of each semiconductor element is increased. Therefore, the input interval of the clock signal is increased. Even if it is not, data transmission can be completed within one cycle by increasing the data transmission speed of each semiconductor element. Therefore, instead of the first change process, a process for increasing the voltage applied to each semiconductor element in the critical path (second change process) may be performed.

  In the second change process, since the voltage is increased, the power consumption is increased accordingly. On the other hand, since the input interval of the clock signal is lengthened in the first change processing, the processing performance is lowered accordingly. Therefore, in order to suppress the increase in power consumption to some extent and to suppress the degradation in processing performance to some extent, the first change processing in which the input interval of the clock signal is made shorter than in the above example and the application to each semiconductor element in the critical path from the above example. The second change process in which the increase in voltage to be reduced is reduced may be performed simultaneously.

100 Microcontroller 120 Instruction prefetch circuit 130 Clock mask circuit (changing means)
420 critical path 420 critical path (second semiconductor integrated circuit section)

Claims (7)

Storage means for storing a plurality of different instruction data for identifying instructions instructing execution of processing;
A first semiconductor integrated circuit section including a plurality of semiconductor elements and capable of transmitting data between the semiconductor elements in a first time under a predetermined timing condition that affects a data transmission timing; and a plurality of semiconductors A second semiconductor integrated circuit unit that includes an element, and that transmits data between the semiconductor elements only in a second time longer than the first time under the predetermined timing condition, An instruction for sequentially reading a plurality of instruction data including an instruction to be executed and instruction data of an instruction scheduled to be executed next to the instruction is given, and each of the plurality of instruction data read in accordance with the instruction is input, Control means for transmitting to the first semiconductor integrated circuit unit or the second semiconductor integrated circuit unit determined according to the command data;
The reading instruction is given by the control means, and in response to the instruction, the plurality of instruction data are sequentially read out from the storage means and input to the control means;
Generating means for generating a reference signal serving as a reference for data transmission timing to each semiconductor element at the first time interval and inputting the reference signal to each semiconductor element;
While the predetermined instruction signal is continuously input, the second semiconductor integrated circuit is configured so that the second semiconductor integrated circuit unit finishes the data transmission within a predetermined time determined according to the input interval of the reference signal. Changing means for changing the timing condition for the circuit unit;
The plurality of command data output by the read input means are sequentially input, and a first command that is predetermined to be transmitted to the second semiconductor integrated circuit unit. In the case of data, the instruction means continues to input the instruction signal to the changing means from the time when the first instruction data starts to be transmitted to the second semiconductor integrated circuit unit by the control means;
Third instruction data for identifying a branch instruction whose content is to read the second instruction data for identifying the next instruction to be executed next from the storage means is predetermined and output by the read input means. When the plurality of instruction data are sequentially input, and the input instruction data is the third instruction data, and the instruction unit inputs the instruction signal to the change unit, read from the storage unit When the second command data is transmitted to the first semiconductor integrated circuit unit by the control means, the input of the instruction signal by the instruction means is stopped and the changed timing condition is set in advance. Stop means for returning to a defined timing condition;
A semiconductor integrated circuit device. The branch instruction includes a conditional branch instruction that instructs to read the second instruction data from the storage means only when a predetermined execution condition is satisfied,
The third instruction data includes fourth instruction data for identifying the conditional branch instruction;
The control means determines whether or not the execution condition is satisfied in response to the input of the fourth command data, and when determining that the execution condition is not satisfied, the control means by the stop means The semiconductor integrated circuit device according to claim 1, wherein the interruption is controlled to be invalid.   The change means performs at least one of a first change process for increasing the input interval of the reference signal and a second change process for increasing the voltage applied to each semiconductor element as the change of the timing condition. The semiconductor integrated circuit device according to claim 1 or 2. A data transmission method for a semiconductor integrated circuit device according to claim 1,
The control means gives an instruction to read the third instruction data, the first instruction data, and the second instruction data in order, and the read input means responds to the instruction with the third instruction data. When reading data, the first instruction data, and the second instruction data from the storage means in order and inputting them to the control means, the instruction means, and the stop means,
The instruction means inputs the instruction signal to the changing means in response to the input of the first instruction data;
While the instruction signal continues to be input, the changing means ends the transmission of the data within a predetermined time determined according to the input interval of the reference signal. Changing the timing condition for the semiconductor integrated circuit portion of 2;
The control means ignoring the first command data input next to the third command data and transmitting the second command data to the first semiconductor integrated circuit unit;
When the second instruction data is transmitted to the first semiconductor integrated circuit unit by the control means, the stop means stops the input of the instruction signal by the instruction means and the changed timing condition Returning to the predetermined timing condition;
A data transmission method for a semiconductor integrated circuit device comprising: A data transmission method for a semiconductor integrated circuit device according to claim 1,
The control means gives an instruction to read out the first instruction data, the third instruction data, and the second instruction data in order, and the read input means responds to the instruction with the first instruction data. When reading data, the third instruction data, and the second instruction data from the storage means in order, and inputting them to the control means, the instruction means, and the stop means,
The control means transmitting the first command data to the second semiconductor integrated circuit unit;
The instruction means inputs the instruction signal to the changing means in response to the input of the first instruction data;
While the instruction signal continues to be input, the changing means ends the transmission of the data within a predetermined time determined according to the input interval of the reference signal. Changing the timing condition for the semiconductor integrated circuit portion of 2;
The control unit transmits the first command data to the second semiconductor integrated circuit unit, and then transmits the second command data input by the read input unit to the first semiconductor integrated circuit unit. And steps to
When the second instruction data is transmitted to the first semiconductor integrated circuit unit by the control means, the stop means stops the input of the instruction signal by the instruction means and the changed timing condition Returning to the predetermined timing condition;
A data transmission method for a semiconductor integrated circuit device comprising: A data transmission method for a semiconductor integrated circuit device according to claim 2,
The control means gives an instruction to sequentially read the fourth instruction data and the first instruction data, and the read input means responds to the instruction with the fourth instruction data and the first instruction data. Are sequentially read from the storage means and input to the control means, the instruction means, and the stop means,
The instruction means inputs the instruction signal to the changing means in response to the input of the first instruction data;
While the instruction signal continues to be input, the changing means ends the transmission of the data within a predetermined time determined according to the input interval of the reference signal. Changing the timing condition for the semiconductor integrated circuit portion of 2;
When the control means determines whether or not the predetermined execution condition is satisfied in response to the input of the fourth command data, and determines that the execution condition is not satisfied, the stop means And the step of transmitting the first command data to the second semiconductor integrated circuit unit, and controlling so that the interruption by
A data transmission method for a semiconductor integrated circuit device comprising:   The change means performs at least one of a first change process for increasing the input interval of the reference signal and a second change process for increasing the voltage applied to each semiconductor element as the change of the timing condition. A data transmission method for a semiconductor integrated circuit device according to any one of claims 4 to 6.

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