JP2004334641A - Information processor, storage medium, and processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the malfunction of a circuit in an information processor for performing a compile processing for generating an object code to be executed by a processor by minimizing the change rate of a current consumed in the processor to suppress the drop of power supply voltage. <P>SOLUTION: This information processor which gives the object code generated by performing the compile processing to the processor comprises a trace means for executing a command trace processing for determining the change rate of the number of commands to be simultaneously executed in an initial object code determined from a source code, and a means for executing, when the change rate determined by the trace means is a predetermined value or more, the replacement of each command of the initial project code or the addition of a dummy command to the initial object code so as to minimize the change rate, thereby generating an optimum object code. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an information processing apparatus, a recording medium, and a processor, and more particularly, to an information processing apparatus that performs a compiling process for generating an object code to be given to a processor, a recording medium that records a program that causes the information processing device to execute a compiling process, and The present invention relates to a processor that performs an operation according to an object code generated by a compile process of an information processing device.
[0002]
[Prior art]
The power of the semiconductor integrated circuit is supplied from a power supply unit through a power supply line of a substrate or a semiconductor package. However, since the propagation characteristics of the power supply line of the substrate or the semiconductor package have an inductance component, if the current consumption changes suddenly in the semiconductor integrated circuit, the power supply voltage drops and the operation speed of the circuit decreases, and the circuit malfunctions. May cause
[0003]
Therefore, Japanese Patent Application Laid-Open No. 63-5551 proposes that a power supply voltage drop is suppressed by additionally connecting a capacitance element (capacitor) in a semiconductor integrated circuit.
[0004]
FIG. 12A shows a configuration in which a capacitive element C1 is additionally connected to an internal circuit of a semiconductor integrated circuit (LSI) disclosed in Japanese Patent Application Laid-Open No. 63-5551. Here, the inductances L1 and L2 represent the inductance included in the power supply line of the substrate of the LSI or the semiconductor package. N1 and N2 indicate power supply lines of the LSI internal circuit.
[0005]
Japanese Patent Application Laid-Open No. 2000-207209 discloses an information processing apparatus that performs a compiling process for generating an object code for causing a processor having a plurality of arithmetic units (ALUs) to execute a plurality of instructions at the same time.
[0006]
FIG. 13 is a diagram for explaining a compiling process performed by a conventional information processing apparatus disclosed in Japanese Patent Application Laid-Open No. 2000-207209.
[0007]
In the information processing apparatus 10 shown in FIG. 13, a procedure 11 for performing normal compile processing and scheduling on the source code 2 is executed. Based on the result of the compilation, it is determined whether or not to perform scheduling giving priority to power saving.
[0008]
In the case of performing scheduling with priority on power saving, a procedure 12 for exchanging commands is performed so that a non-operation command (NOP) for instructing not to perform an operation is consecutive in the compilation result.
[0009]
When the procedure 12 is completed, the first NOP in the consecutive NOPs is converted into a SUSPEND command (a command instructing to suspend the operation), and the last NOP is converted into a RESUME command (a command instructing to resume the operation). Step 13 is performed. When the procedure 13 ends, the information processing device 10 outputs the object code 3 at that time.
[0010]
In the compiling process performed by the information processing apparatus 10 in FIG. 13, in the program (object code) to be executed by the arithmetic unit, the start and end of the continuous portion of the non-executable command (NOP) are converted into the power save commands (SUSPEND, RESUME). Converting. This command conversion has an effect of suppressing a rapid current change.
[0011]
[Patent Document 1]
JP-A-63-5551
[0012]
[Patent Document 2]
JP 2000-207209 A
[0013]
[Problems to be solved by the invention]
However, even when the technology disclosed in Japanese Patent Application Laid-Open No. 63-5551 is applied, malfunction may occur if the current rapidly changes in a semiconductor integrated circuit (LSI).
[0014]
For example, in the case of the semiconductor integrated circuit (LSI) in FIG. 12A, it is assumed that the power supply voltage V = 1.2 V, the inductance L1 = L2 = 0.1 nH, and the capacitor capacitance C1 = 10 nF. FIG. 12B shows a case where a sudden change occurs in the current I1 flowing through the LSI internal circuit, and FIG. 12C shows a voltage change on the power supply line N1 side obtained by simulation.
[0015]
As shown in FIGS. 12B and 12C, a voltage drop of 0.25 V or more with respect to the power supply voltage of 1.2 V has been confirmed by simulation. This voltage drop is expected to delay the circuit delay by about 25%, which causes a malfunction.
[0016]
On the other hand, also in the conventional example of FIG. 13, the current consumed by issuing the power save command is sufficiently smaller than the current consumed by the normal command. In the command (RESUME) for restarting the operation, only the clock operates, so that, for example, current consumption required for data operation of the arithmetic unit does not occur. Since the data operation is complicated in a complicated processor, the power consumption at the time of executing the RESUME is estimated to be about １ ／ of the normal operation.
[0017]
For example, consider a case in which a VLIW (very_long_instruction_word) type processor capable of simultaneously executing four instructions in the conventional example of FIG. 13 is realized with the same circuit constants as the conventional example of FIG.
[0018]
FIG. 14 is a diagram for explaining the operation of the information processing apparatus 10 in FIG. FIG. 14A shows an example of a compilation result by the information processing apparatus 10, FIG. 14B shows a current change occurring in the VLIW processor when the compilation result is executed, and FIG. The obtained voltage change on the power supply line N1 side of the VLIW type processor is shown.
[0019]
As shown in FIG. 14, when a simulation is performed in which all four instructions are NOP and the transition to the normal instruction is performed simultaneously for four instructions after issuing the RESUME command. A voltage drop occurs. As a result, the circuit speed is reduced by about 20%, and there is a possibility that the circuit malfunctions.
[0020]
The present invention has been made in view of the above points, and in an information processing apparatus that performs a compiling process for generating an object code to be executed by a processor, a power supply by reducing a rate of change in current consumed by the processor. It is an object to suppress a voltage drop and prevent a malfunction of a circuit.
[0021]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an information processing apparatus according to the present invention is an information processing apparatus that provides an object code generated by performing a compile process to a processor, the number of instructions to be simultaneously executed in an initial object code obtained from a source code. A tracing means for performing an instruction tracing process for obtaining a change rate, and when the change rate obtained by the tracing means is a predetermined value or more, each instruction of the initial object code is replaced so as to reduce the change rate. In this case, there is provided an instruction replacing means for generating an optimal object code.
[0022]
In order to solve the above-mentioned problem, an information processing apparatus according to the present invention is an information processing apparatus that provides an object code generated by performing a compile process to a processor, the number of instructions to be simultaneously executed in an initial object code obtained from a source code. A tracing means for performing an instruction tracing process for obtaining a change rate; and when the change rate obtained by the tracing means is a predetermined value or more, a dummy instruction is added to the initial object code so as to reduce the change rate. And an instruction adding unit for generating an optimal object code.
[0023]
Further, in order to solve the above-mentioned problem, the recording medium of the present invention provides an information processing apparatus for generating an optimal object code from an initial object code obtained by a compiling process, the number of instructions to be simultaneously executed in the initial object code. A tracing means for performing an instruction tracing process for obtaining a change rate, wherein when the change rate obtained by the tracing means is equal to or more than a predetermined value, each instruction of the initial object code is replaced so as to reduce the change rate; Means for generating optimal object code by adding dummy instructions to object code
It is characterized by recording a program for functioning as.
[0024]
Further, in order to solve the above problem, a processor of the present invention is a processor that performs various operations according to an object code generated by a compile process of an information processing device, and includes an instruction decoder unit that decodes an object code, It is characterized by comprising a plurality of arithmetic circuits for performing various operations based on the result of decoding by the instruction decoder unit, and a dummy circuit for executing only a dummy instruction based on the result of decoding by the instruction decoder unit.
[0025]
According to the information processing apparatus of the present invention, it is possible to reduce the rate of change in the current consumed by the processor when performing the compile process of generating the object code by converting the source code of the program to be executed by the processor. Therefore, power supply voltage drop in the processor can be suppressed, and power supply noise can be suppressed. Further, malfunction of the processor can be prevented, and the processing speed of the processor can be increased.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0027]
FIG. 1 is a diagram for explaining a compiling process performed by the information processing apparatus of the present invention.
[0028]
In the information processing apparatus 20 shown in FIG. 1, in step 21, a conventional compiling process is performed on the source code 2 to convert the source code 2 into an object code that can be understood by the processor. Furthermore, in order to speed up the processing or reduce the power, in step 21, a processing (scheduling) of changing the order of the instructions is performed. The code generated by this procedure 21 is called the initial object code 4.
[0029]
Next, in step 23, the information processing apparatus 20 performs an instruction tracing process for obtaining a change rate of the number of instructions to be executed simultaneously in the initial object code 4.
[0030]
When the instruction tracing process in step 23 is completed, in step 24, the information processing apparatus 20 determines whether or not the rate of change in the number of concurrently executed instructions obtained in the instruction tracing process is equal to or less than a predetermined allowable value.
[0031]
If the determination result of step 24 is YES, the information processing device 20 outputs the object code at that time as the optimal object code 3.
[0032]
If the decision result in the step 24 is NO, in a step 22, the information processing apparatus 20 replaces the instruction of the initial object code 4 or adds a dummy instruction to the initial object code 4.
[0033]
In the information processing apparatus according to the present invention, when generating the object code to be executed by the processor, the instruction tracing process for determining the change rate of the number of concurrently executed instructions is performed. If the rate of change is equal to or greater than a predetermined allowable value, instructions are replaced or replaced with dummy instructions that are not necessary for the original operation so that the rate of change is reduced.
[0034]
Alternatively, instead of tracing the number of concurrently executed instructions, the current consumed in each clock cycle is predicted using a value correlated with the current consumption defined for each instruction, and the rate of change is equal to or greater than a predetermined value. If so, the instructions are replaced or replaced with dummy instructions that are not necessary for the original operation so that the rate of change is reduced.
[0035]
According to the information processing apparatus of FIG. 1, the rate of change of the current consumed by the processor can be reduced, the power supply voltage drop can be suppressed, and malfunction can be prevented.
[0036]
FIG. 2 shows a configuration of a system for operating a VLIW processor by applying the information processing apparatus according to the first embodiment of the present invention.
[0037]
The compile processing information processing apparatus 20 in FIG. 2 performs compile processing on the source code 2 and outputs the optimal object code 3. The VLIW type processor 30 includes an instruction cache unit 31, an instruction fetch unit 32, an instruction decoder unit 33, a data cache 34, a register file 35, and four operation units 36 (# 1 to # 4). .
[0038]
In the system shown in FIG. 2, the information processing device 20, the main memory 40, and the processor 30 are connected to each other by a bus 38.
[0039]
First, the information processing apparatus 20 of this embodiment inputs a source code describing how the processor 30 operates. The information processing device 20 outputs the optimal object code 3 generated by performing the processing shown in FIG. This object code 3 is stored in the main memory 40.
[0040]
The object code in the main memory 40 is transferred to the instruction cache 31 in the processor 30 at the timing of execution by the processor 30, and further transferred to the instruction decoder 33 through the instruction fetch unit 32.
[0041]
The data transfer process between the main memory 40 and the data cache 34, the data transfer process between the data cache 34 and the register file 35, or the value of the register file 35 is calculated based on the decoding result of the instruction decoder unit 33. Processing such as writing to the file 35 is performed.
[0042]
FIG. 3 is a diagram for explaining the operation of the information processing apparatus of this embodiment. FIG. 3A shows the result of the instruction tracing process performed in step 23, and FIG. 3B shows the result of the instruction replacement process performed in step 22.
[0043]
For example, as shown in FIG. 3A, it is assumed that the initial object code is in the order of executing the valid instructions (INST **) at the same time after the non-executable instructions (NOP) are consecutive for all four instructions.
[0044]
The number of simultaneous instructions is traced for the initial object code. For example, a function in which 1 is assigned to one valid instruction is prepared. The output value of this function is called the number of concurrently executed instructions.
[0045]
In the example of FIG. 3A, the number of simultaneous execution effective instructions is 0 since CYCLE0 to CYCLE4 are all NOPs, and the number of simultaneous execution effective instructions is 0 since all four instructions are CYCLE5 to CYCLE6. 4.
[0046]
From this trace result, the rate of change from CYCLE4 to CYCLE5 is calculated as 4. Here, it is assumed that the allowable maximum value of the rate of change in the number of simultaneously-executable instructions calculated from the power consumption of the processor, the inductance and capacitance of the power supply, and the noise resistance of the circuit is 1.
[0047]
In this case, the change rate 4 from CYCLE4 to CYCLE5 exceeds the allowable maximum value 1. Therefore, the determination result of the procedure 24 in FIG. 1 is NO, and the procedure 22 for performing the instruction replacement processing is executed.
[0048]
In this instruction replacement process, the order of valid instructions is changed so that the rate of change in the initial object code is equal to or less than the allowable maximum value. For example, as shown in FIG. 3B, the instructions of # 1 to # 3 are executed in order of preceding execution by 1CYCLE. When this code is used to calculate the rate of change in the number of simultaneously-executable instructions, it can be seen that the rate of change is at most 1 and therefore less than the allowable maximum value. Therefore, the information processing apparatus 20 of this embodiment outputs the code of FIG.
[0049]
FIG. 4 is a diagram for explaining the operation of the information processing apparatus according to the first embodiment of the present invention.
[0050]
FIG. 4A shows an example of an optimal object code (compilation result) generated by the information processing apparatus 20, and FIG. 4B shows a current change occurring in the VLIW processor 30 when the compilation result is executed. FIG. 4C shows a voltage change of the VLIW processor 30 obtained by simulation.
[0051]
When the optimum object code of FIG. 4A is executed by the VLIW processor 30, the amount of current consumed gradually increases from CYCLE2 and reaches the maximum value at CYCLE5 as shown in FIG. 4B. The amount of current change at this time is smaller than in the case of the conventional example in FIG. 14, and the voltage drop due to this is suppressed to 0.1 V or less (FIG. 4C). The deterioration of the circuit speed due to this voltage drop is 10% or less, and the circuit malfunction can be suppressed.
[0052]
Next, FIG. 5 is a diagram for explaining the operation of the information processing apparatus according to the second embodiment of the present invention. FIG. 5A shows the result of the instruction trace processing performed in step 23, and FIG. 5B shows the result of the processing performed in step 22.
[0053]
The embodiment of FIG. 5 performs a dummy instruction addition process of adding a dummy instruction (DUMMY) unnecessary for the original operation to the location of the NOP instead of the valid instruction replacement process performed in the embodiment of FIG. It is characterized by the following.
[0054]
In the dummy instruction, the current consumption in the processor is set to the same level as that of the valid instruction. For example, an instruction to write data in a register that is always rewritten by the next CYCLE is a dummy instruction. When calculating the number of simultaneous execution effective instructions, 1 is assigned to this dummy instruction in the same manner as the effective instruction.
[0055]
As shown in FIG. 5B, by adding a dummy instruction, the rate of change in the number of simultaneously executable instructions can be suppressed to a value equal to or less than the maximum allowable value. Thereby, the same effect as the current consumption and the voltage drop shown in FIG. 4 can be obtained. In this embodiment, there is no need to change the order of valid instructions, so that it is not necessary to pay attention to the context of valid instructions using the same register, and the effect can be easily obtained.
[0056]
FIG. 6 shows an information processing apparatus according to the third embodiment of the present invention. FIG. 7 is a diagram for explaining the operation of the information processing apparatus in FIG.
[0057]
While the information processing apparatus 20 of FIG. 1 performs an instruction trace process for obtaining the rate of change in the number of concurrently executed instructions, the information processing apparatus 20A of the present embodiment, as shown in FIG. It is characterized in that a current consumption tracing process using a numerical value (equivalent current consumption value) depending on the consumption is performed.
[0058]
In the information processing apparatus 20A of FIG. 6, the initial object code 4 is generated by the procedure 21 for performing the normal compiling process and scheduling on the source code 2. In the initial object code 4, a procedure 23A of performing a total equivalent current consumption tracing process for obtaining a change rate of a total sum of equivalent current consumption values of instructions executed simultaneously is executed.
[0059]
When the current consumption tracing process is completed, a procedure 24A for determining whether or not the change rate of the total equivalent current consumption is equal to or less than the allowable maximum value is executed.
[0060]
If the determination result of this step 24A is YES, the information processing device 20A outputs the object code at that time as the optimal object code 3.
[0061]
When the determination result of the procedure 24A is NO, the information processing device 20A executes a procedure 22 of replacing the instruction of the initial object code 4 or adding a dummy instruction to the initial object code 4.
[0062]
In the information processing apparatus 20A of FIG. 6, for example, each instruction is classified into the following three types. (A) Data transfer processing between the main memory 40 and the data cache 34 (INSTA **), (b) Data transfer processing between the data cache 34 and the register file 35 (INSTB **), (c) Value of the register file 35 Is calculated and written into the register file 35 (INSTC **). Here, “**” corresponds to the number (# 1 to # 4) of each computing unit 36.
[0063]
In the embodiment of FIG. 6, an equivalent current consumption value correlated with the current consumed by the processor 30 when executing each instruction is assigned to each instruction. For example, 0.5 is assigned to INSTA **, 1.0 is assigned to INSTB **, and 1.5 is assigned to INSTC **. The sum total of the equivalent current consumption values of the instructions executed simultaneously in each CYCLE is called the total equivalent current consumption.
[0064]
When the total equivalent current consumption is obtained in the initial object code shown in FIG. 7A and the rate of change of the total equivalent current consumption between CYCLEs is obtained, the maximum value is 4.
[0065]
Here, it is assumed that the allowable maximum value of the change rate of the total equivalent current consumption calculated from the power consumption of the processor 30, the inductance and capacitance of the power supply, and the noise resistance of the circuit is 1.
[0066]
In the initial object code of FIG. 7A, the rate of change 4 from CYCLE4 to CYCLE5 exceeds the allowable maximum value 1.
[0067]
In this case, in the information processing apparatus 20A of FIG. 6, a procedure 22 for replacing an instruction or adding a dummy instruction to the initial object code is executed. In the procedure 22 of this embodiment, the order of valid instructions is changed so that the rate of change is equal to or less than the maximum allowable value.
[0068]
As a result, in the optimal object code shown in FIG. 7B, the instructions of # 1 to # 3 are executed in order of being executed by 1CYCLE. When the rate of change of the total equivalent current consumption is calculated with this optimum object code, it is 1 at the maximum, and it can be seen that the rate is equal to or less than the allowable maximum value.
[0069]
The information processing device 30 of this embodiment outputs the optimal object code of FIG. 7B to the main memory 40 of the processor 30. When the optimum object code is executed by the VLIW processor 30, the effect as shown in the embodiment of FIG. 4 is exhibited, and the malfunction of the circuit can be suppressed.
[0070]
FIG. 8 is a diagram for explaining the operation of the information processing apparatus according to the fourth embodiment of the present invention.
[0071]
In the embodiment of FIG. 8, a dummy instruction (DUMMY) unnecessary for the original operation is added to the location of the NOP instead of performing the valid instruction replacement processing in the embodiment of FIG. In the dummy instruction, the current consumption in the processor is set to the same level as that of the valid instruction. For example, an instruction to write data in a register that is always rewritten by the next CYCLE is a dummy instruction.
[0072]
When calculating the change rate of the total equivalent current consumption, the dummy instruction assigns a value correlated to the current consumed when executing the dummy instruction. In the example of FIG. 8, as in the embodiment of FIG. 7, the equivalent current consumption value of each valid instruction is 0.5 for INSTA **, 1.0 for INSTB **, and 1.0 for INSTC **. Assigns 1.5 respectively.
[0073]
In the embodiment of FIG. 8, the change rate of the total equivalent current consumption can be suppressed to the maximum allowable value or less by adding a dummy instruction to which 1.0 is assigned as the equivalent current consumption. Thus, the same effects as the current consumption and the voltage drop shown in the embodiment of FIG. 4 can be obtained.
[0074]
In the embodiment of FIG. 8, there is no need to change the order of the valid instructions, so that there is no need to pay attention to the context of valid instructions using the same register, and the effect can be easily obtained.
[0075]
Further, in the embodiment of FIG. 8, since the evaluation is made based on the total equivalent current consumption instead of the number of simultaneously-executable instructions, the present invention can be applied to a processor in which the number of instructions is always 1 (a processor not a VLIW type). .
[0076]
FIG. 9 shows an information processing apparatus according to the fifth embodiment of the present invention and a processor capable of simultaneously issuing four instructions. FIG. 10 shows an example of a power consumption dummy circuit provided in the processor of FIG.
[0077]
The processor 30 according to the embodiment of FIG. 9 includes a circuit that realizes execution of a dummy instruction used in the optimal object code generated by the information processing apparatus according to the second or fourth embodiment described above. It is characterized in that it is provided separately from the processor 30.
[0078]
As illustrated in FIG. 9, the processor 30 includes a power consumption dummy circuit 37 that executes only a dummy instruction based on a result of decoding by the instruction decoder unit 33. The power consumption dummy circuit 37 is, for example, a circuit in which an AND circuit 71 and a plurality of inverter circuits 72 are connected as shown in FIG.
[0079]
In the above-described optimal object code of the second or fourth embodiment, the current consumption is substantially the same as that of the valid instruction and the same processing is performed as in the case where the dummy instruction is not added, by using the originally required circuit. You need to find such an instruction.
[0080]
However, according to the processor 30 of this embodiment, since the processor 30 is provided with the dummy circuit 37 for executing only the dummy instruction in advance, the dummy instruction can be added without depending on other instructions. Processing can be accelerated.
[0081]
Next, FIG. 11 shows an example of a multiprocessor to which the information processing apparatus according to one embodiment of the present invention is applied.
[0082]
In the above embodiments, the VLIW type processor is described as an example. However, the present invention can be similarly applied to a multiprocessor chip in which a plurality of processors are mounted on one chip as shown in FIG.
[0083]
The multiprocessor chip 100 of FIG. 11 includes an internal main processor 30-1, an internal subprocessor 30-2, and the like. Each processor 30-1, 30-2, etc. is a VLIW type processor. In this case, each of the VLIW-type instructions (# 1 to # 4) included in the optimal object code generated by the information processing apparatus of the present embodiment is replaced with an instruction given to each processor.
[0084]
(Supplementary Note 1) An information processing apparatus that provides an object code generated by performing a compile process to a processor, and a trace unit that performs an instruction trace process for determining a change rate of the number of instructions to be executed simultaneously in an initial object code obtained from a source code. And when the rate of change obtained by the tracing means is equal to or greater than a predetermined value, by replacing each instruction of the initial object code so as to reduce the rate of change, an instruction replacing means for generating an optimal object code. An information processing apparatus comprising:
[0085]
(Supplementary Note 2) An information processing apparatus that provides an object code generated by performing a compile process to a processor, and a tracing unit that performs an instruction tracing process for determining a change rate of the number of instructions to be executed simultaneously in the initial object code obtained from the source code An instruction adding means for generating an optimum object code by adding a dummy instruction to the initial object code so as to reduce the change rate when the change rate obtained by the tracing means is equal to or more than a predetermined value; An information processing apparatus comprising:
[0086]
(Supplementary Note 3) In place of the instruction tracing process, the tracing unit may input an equivalent current consumption value correlated with a current value consumed by the processor for each execution instruction, and execute the simultaneous execution in the initial object code. 3. The information processing apparatus according to claim 1, wherein a current consumption tracing process for obtaining a change rate of a total sum of equivalent current consumption values of the instructions is performed.
[0087]
(Supplementary Note 4) A tracing means for performing an instruction tracing process for obtaining a change rate of the number of instructions to be simultaneously executed in the initial object code to generate an optimal object code from the initial object code obtained by the compiling process; When the change rate obtained by the tracing means is a predetermined value or more, by replacing each instruction of the initial object code or adding a dummy instruction to the initial object code so as to reduce the change rate, A recording medium on which a program for functioning as a means for generating an optimal object code is recorded.
[0088]
(Supplementary Note 5) A processor that performs various operations in accordance with an object code generated by a compiling process of the information processing device, and includes an instruction decoder unit that decodes the object code, and various instructions based on a decoding result obtained by the instruction decoder unit. A processor comprising: a plurality of operation circuits for performing an operation; and a dummy circuit for executing only a dummy instruction based on a result of decoding by the instruction decoder unit.
[0089]
(Supplementary Note 6) An information processing method for providing an object code generated by performing a compile process to a processor, and a trace procedure for performing an instruction trace process for determining a change rate of the number of instructions to be simultaneously executed in an initial object code obtained from a source code When the change rate obtained by the tracing procedure is equal to or more than a predetermined value, replacing each instruction of the initial object code or adding a dummy instruction to the initial object code so as to reduce the change rate. And generating an optimal object code.
[0090]
(Supplementary Note 7) In the tracing procedure, instead of the instruction tracing process, an equivalent current consumption value correlated with a current value consumed by the processor is input for each execution instruction, and the simultaneous execution in the initial object code is performed. 7. The information processing method according to claim 6, wherein a current consumption tracing process for obtaining a change rate of a total sum of equivalent current consumption values of the instructions is performed.
[0091]
(Supplementary Note 8) A tracing means for performing an instruction tracing process for obtaining a change rate of the number of instructions to be executed simultaneously in the initial object code in order to generate an optimal object code from the initial object code obtained by the compiling process; When the change rate obtained by the tracing means is a predetermined value or more, by replacing each instruction of the initial object code or adding a dummy instruction to the initial object code so as to reduce the change rate, A program for functioning as a means for generating optimal object code.
[0092]
(Supplementary Note 9) In place of the instruction tracing processing, the tracing unit may input an equivalent current consumption value correlated with a current value consumed by the processor for each execution instruction, and execute the simultaneous execution in the initial object code. The recording medium according to claim 4, wherein a current consumption tracing process for obtaining a change rate of a total sum of equivalent current consumption values of the instructions is performed.
[0093]
(Supplementary Note 10) In place of the instruction tracing process, the tracing unit may input an equivalent current consumption value correlated with a current value consumed by the processor for each execution instruction, and execute the simultaneous execution in the initial object code. The program according to claim 8, wherein a current consumption tracing process for obtaining a change rate of a total sum of equivalent current consumption values of the instructions is performed.
[0094]
【The invention's effect】
As described above, according to the information processing apparatus of the present invention, the rate of change in the current consumed by the processor when performing the compile process of generating the object code by converting the source code of the program to be executed by the processor is described. Can be smaller. Therefore, power supply voltage drop in the processor can be suppressed, and power supply noise can be suppressed. Further, malfunction of the processor can be prevented, and the processing speed of the processor can be increased.
[0095]
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a compiling process performed by an information processing apparatus according to the present invention.
FIG. 2 is a block diagram illustrating an information processing apparatus according to a first embodiment of the present invention and a processor capable of simultaneously issuing four instructions.
FIG. 3 is a diagram for explaining the operation of the information processing apparatus according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining the operation of the information processing apparatus according to the first embodiment of the present invention.
FIG. 5 is a diagram for explaining the operation of the information processing apparatus according to the second embodiment of the present invention.
FIG. 6 is a block diagram illustrating an information processing apparatus according to a third embodiment of the present invention.
FIG. 7 is a diagram for explaining the operation of the information processing apparatus according to the third embodiment of the present invention.
FIG. 8 is a diagram for explaining the operation of the information processing apparatus according to the fourth embodiment of the present invention.
FIG. 9 is a block diagram illustrating an information processing apparatus according to a fifth embodiment of the present invention and a processor capable of simultaneously issuing four instructions.
FIG. 10 is a block diagram illustrating an example of a power consumption dummy circuit provided in the processor of FIG. 9;
FIG. 11 is a block diagram illustrating an example of a multiprocessor to which the information processing device according to an embodiment of the present invention is applied.
FIG. 12 is a diagram for explaining a power supply voltage drop of a conventional semiconductor integrated circuit when a current changes rapidly.
FIG. 13 is a diagram illustrating a compiling process performed by a conventional information processing apparatus.
FIG. 14 is a diagram for explaining the operation of the information processing apparatus in FIG. 13;
[Explanation of symbols]
2 Source code
3 Optimum object code
4 Initial object code
20 Information processing device
30 processor
31 Instruction Cache Unit
32 Instruction fetch unit
33 Instruction Decoder
34 Data Cache Unit
35 Register file
36 arithmetic unit
37 Power consumption dummy circuit
38 bus
40 main memory
30-1 Internal Main Processor
30-2 Internal Sub Processor
100 multiprocessor

Claims (5)

An information processing device for providing an object code generated by performing a compiling process to a processor,
Tracing means for performing an instruction tracing process for calculating a change rate of the number of instructions to be executed simultaneously in the initial object code obtained from the source code;
When the change rate obtained by the tracing means is equal to or more than a predetermined value, by replacing each instruction of the initial object code so as to reduce the change rate, an instruction replacing means for generating an optimal object code is provided. An information processing apparatus comprising: An information processing device for providing an object code generated by performing a compiling process to a processor,
Tracing means for performing an instruction tracing process for calculating a change rate of the number of instructions to be executed simultaneously in the initial object code obtained from the source code;
An instruction adding means for generating an optimal object code by adding a dummy instruction to the initial object code so as to reduce the change rate when the change rate obtained by the tracing means is a predetermined value or more; An information processing apparatus comprising: The tracing means inputs, in place of the instruction tracing processing, an equivalent current consumption value correlated with a current value consumed by the processor for each execution instruction, and an equivalent current of each instruction simultaneously executed in the initial object code. 3. The information processing apparatus according to claim 1, wherein a current consumption tracing process for determining a rate of change of a sum of consumption values is performed. An information processing device for generating an optimal object code from the initial object code obtained by the compiling process,
Tracing means for performing an instruction tracing process for determining a rate of change in the number of instructions executed simultaneously in the initial object code
When the change rate obtained by the tracing means is a predetermined value or more, by replacing each instruction of the initial object code so as to reduce the change rate, or by adding a dummy instruction to the initial object code, A recording medium on which a program for functioning as a means for generating an optimal object code is recorded. A processor that performs various operations according to an object code generated by a compile process of the information processing device,
An instruction decoder unit for decoding an object code;
A plurality of operation circuits that perform various operations based on the result of decoding by the instruction decoder unit;
A dummy circuit for executing only a dummy instruction based on a result of decoding by the instruction decoder unit.

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