JP2010231476A - Clock skew automatic adjustment circuit and method for adjusting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein high-accuracy clock skew adjustment cannot be performed in a conventional clock skew adjustment circuit. <P>SOLUTION: This clock skew automatic adjustment circuit includes: a clock driver 101 adjusting drive capability of a clock; a measurement circuit 102 measuring a time required from a signal change start of the clock to a signal change end; and a control circuit 103 generating a control signal based on a measurement time and a preset reference time, and outputting it to the clock driver. By such a circuit configuration, the high-accuracy clock skew adjustment can be performed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock skew automatic adjustment circuit and an adjustment method thereof.

  As a clock skew adjustment method for suppressing a design delay difference (skew) caused by a waveform inclination of the clock, there is a method of replacing a used clock driver (for example, a buffer) with a clock driver having a different drive capability (drive capability). In this adjustment method, a new clock driver is selected based on the wiring resistance and capacitance components around the clock driver. However, in this adjustment method, it is necessary to extract the wiring resistance and the capacitance component again after replacing the clock driver. Then, it is necessary to finely adjust the drive capability again based on the extracted wiring resistance and capacitance component. Therefore, the conventional technique has a problem that the design period increases. Further, in the prior art, when the drive capability of the clock driver fluctuates due to manufacturing variations of semiconductor integrated circuits, the drive capability cannot be automatically adjusted.

  Solutions to such problems are introduced in Patent Documents 1 to 3. Patent Document 1 proposes a semiconductor device that gives a delay to an AC signal using a delay element selected based on a comparison result with required specifications. Thereby, this semiconductor device can perform automatic adjustment of AC timing after the assembly process and the mounting process.

  However, the circuit disclosed in Patent Document 1 focuses only on the delay of input / output signals of a delay element used for skew adjustment. That is, the delay time due to the slope of the signal waveform is not considered. Therefore, there is a possibility that the circuit disclosed in Patent Document 1 cannot perform clock skew adjustment with high accuracy.

  Further, Patent Document 2 proposes a video signal processing device that increases the degree of freedom of power control. Here, the driving force determination unit 10a shown in Patent Document 2 (FIG. 1 in Patent Document 2) is based on the clock input to the AD converter 6 (FIG. 1 in Patent Document 2), and the GCA circuit 5 (in Patent Document 2). The slope of the output waveform in FIG. 1) is detected. The driving force determination unit 10a determines whether the output driving current is excessive or insufficient based on the detection result, and adjusts the bias current supplied to the GCA circuit 5.

  However, as shown in FIG. 5, the circuit shown in Patent Document 2 has a high possibility of measuring a minute potential difference, such as the difference Dab between the points A and B, for example. Therefore, when the output waveform of the GCA circuit 5 slightly fluctuates due to some factor, there is a possibility that highly accurate measurement cannot be performed.

  In addition, Patent Document 3 proposes a skew adjustment circuit that minimizes the influence of setting errors that occur during skew adjustment on the test results of semiconductor devices.

JP 2007-78400 A JP 2008-109266 A JP 2001-183419 A

  As described above, the conventional clock skew adjustment circuit has a problem in that it cannot perform highly accurate clock skew adjustment.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a clock skew automatic adjustment circuit and a method for adjusting the clock skew that can perform clock skew adjustment with high accuracy.

  The clock skew automatic adjustment circuit according to the present invention requires a clock driver (for example, the clock driver 101 in the first embodiment of the present invention) that adjusts the drive capability of the clock and the signal change start to signal end of the clock. A control signal is generated based on a measurement circuit that measures time (for example, the measurement circuit 102 in Embodiment 1 of the present invention), the measurement time, and a preset reference time, and is output to the clock driver. A control circuit (for example, the control circuit 103 according to the first embodiment of the present invention).

  Further, the adjustment method of the clock skew automatic adjustment circuit according to the present invention measures the time required from the start of the signal change of the clock to the end of the signal change, and based on the measurement time and a preset reference time, A control signal for adjusting the drive capability is output, and the drive capability of the clock is adjusted.

  According to the present invention, it is possible to provide a clock skew automatic adjustment circuit capable of highly accurate clock skew adjustment and an adjustment method thereof.

1 is a block diagram showing a configuration of a clock skew automatic adjustment circuit according to a first embodiment of the present invention; It is a figure which shows the structure of the clock skew automatic adjustment circuit concerning Embodiment 2 of this invention. It is a figure which shows the adjustment method of the clock skew automatic adjustment circuit concerning Embodiment 2 of this invention. It is a figure which shows the adjustment method of the clock skew automatic adjustment circuit concerning Embodiment 2 of this invention. 4 is a timing chart of the output waveform and clock of the GCA circuit of Patent Document 2.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.

Embodiment 1
Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 shows an automatic clock skew adjustment circuit 200 according to the first embodiment of the present invention. Here, the clock skew automatic adjustment circuit 200 is characterized by automatically adjusting the clock skew as a clock distribution circuit provided in the semiconductor integrated circuit. The circuit shown in FIG. 1 includes a clock skew automatic adjustment circuit 200, a PLL (Phase Locked Loop) 100, flip-flops (hereinafter simply referred to as FF) 114, 115, and 116, and hardware modules (hereinafter simply referred to as HM). 117). In the example of the circuit illustrated in FIG. 1, the FFs 114, 115, 116, and HM 117 are merely illustrated as examples of circuits that supply a clock.

  First, the circuit configuration of the clock skew automatic adjustment circuit 200 will be described. The clock skew automatic adjustment circuit 200 includes a clock driver 101, a measurement circuit 102, and a control circuit 103.

  The output terminal of the PLL 100 is connected to one input terminal of the clock driver 101. The output terminal of the clock driver 101 is connected to the respective clock input terminals of the FFs 114, 115, and 116, the clock input terminal of the HM 117, and one input terminal of the measurement circuit 102. A reset signal is supplied to the other input terminal of the measurement circuit 102. The output terminal of the measurement circuit 102 is connected to the input terminal of the control circuit 103. The output terminal of the control circuit 103 is connected to the other input terminal of the clock driver 101.

  Next, the operation of the clock skew automatic adjustment circuit 200 will be described. The PLL 100 supplies a clock to the clock driver 101. The clock driver 101 gives a predetermined drive capability to the input clock (input clock) and outputs it. A signal (output clock) output from the clock driver 101 is input to each clock input terminal of the FFs 114, 115, and 116, a clock input terminal of the HM 117, and one input terminal of the measurement circuit 102. A reset signal is supplied to the other input terminal of the measurement circuit 102. A signal output from the measurement circuit 102 is input to the input terminal of the control circuit 103. A signal output from the control circuit 103 is input to the other input terminal of the clock driver 101.

  In FIG. 1, the measurement circuit 102 has a function of measuring a delay time due to the slope of the output waveform of the clock driver 101. Here, the delay time due to the slope of the output waveform indicates the time required for signal change of the output clock (time required from the start of signal change to the end of signal change). The control circuit 103 compares the measured delay time (measurement time) due to the slope of the output waveform of the clock driver 101 with a reference delay time (reference time) set in advance based on design specifications and the like. Note that this reference delay time can be changed as needed.

  This comparison result indicates the excess or deficiency of the drive capability currently set by the clock driver 101. The control circuit 103 generates a control signal based on the comparison result and outputs it to the clock driver 101. The clock driver 101 adjusts the drive capability based on this control signal. That is, the clock driver 101 adjusts the drive capability so that the delay time due to the slope of the signal waveform of the output clock approaches the reference time. With such a circuit configuration, the clock skew automatic adjustment circuit 200 can automatically adjust the clock drive capability. Further, since the clock skew automatic adjustment circuit 200 automatically adjusts the time required for the signal change of the output clock, the clock skew adjustment can be performed with high accuracy.

Embodiment 2
Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 2 shows an automatic clock skew adjustment circuit 200 according to the second embodiment of the present invention.

  First, the circuit configuration of the clock skew automatic adjustment circuit 200 will be described. The clock skew automatic adjustment circuit 200 includes a clock driver 101, a measurement circuit 102, and a control circuit 103. The clock driver 101 also has N (N is a natural number) buffers that output a predetermined drive capability given to the input clock, and N switches (for example, transfer gates) corresponding to the buffers. In the second embodiment of the present invention, a case where three buffers 111, 112, 113 and three switches 108, 109, 110 are provided will be described as an example. The control circuit 103 includes a comparison circuit 104, a switch switching control circuit 105, and a drive capability storage circuit 106.

  The output terminal of the PLL 100 is connected to one terminal of the switch 108 provided in the clock driver 101, one terminal of the switch 109, and one terminal of the switch 110. The other terminal of the switch 108 is connected to the input terminal of the buffer 111. The other terminal of the switch 109 is connected to the input terminal of the buffer 112. The other terminal of the switch 110 is connected to the input terminal of the buffer 113. The output terminal of the buffer 111, the output terminal of the buffer 112, and the output terminal of the buffer 113 are each connected to a common node 107. Further, the node 107 is connected to the clock input terminals of the FFs 114, 115, and 116, the clock input terminal of the HM 117, and one input terminal of the measurement circuit 102 via one output terminal of the clock driver 101. . A reset signal is supplied to the other input terminal of the measurement circuit 102.

  The output terminal of the measurement circuit 102 is connected to one input terminal of the comparison circuit 104. A reference signal set in advance based on design specifications or the like is supplied to the other input terminal of the comparison circuit 104. The output terminal of the comparison circuit 104 is connected to one input terminal of the switch switching control circuit 105. The other output terminal of the clock driver 101 is connected to one input terminal of the drive capability memory circuit 106. An enable signal is supplied to the other input terminal of the drive capability memory circuit 106.

  The output terminal of the drive capability memory circuit 106 is connected to the other input terminal of the switch switching control circuit 105. Each output terminal of the switch switching control circuit 105 is connected to a control terminal of the switch 108, a control terminal of the switch 109, and a control terminal of the switch 110.

  Next, the operation of the clock skew automatic adjustment circuit 200 will be described. The PLL 100 supplies a signal (input clock) to the input terminal of the buffer 111 via the switch 108. The PLL 100 supplies a signal to the input terminal of the buffer 112 via the switch 109. The PLL 100 supplies a signal to the input terminal of the buffer 113 via the switch 110. The buffer 111, the buffer 112, and the buffer 113 supply a signal to the common node 107. A signal (output clock) supplied to the node 107 is connected to one of the clock input terminals of the FFs 114, 115, 116, the clock input terminal of the HM 117, and the measurement circuit 102 via one output terminal of the clock driver 101. Is input to one of the input terminals. A reset signal is supplied to the other input terminal of the measurement circuit 102.

  A signal output from the measurement circuit 102 is input to one input terminal of the comparison circuit 104. A reference signal set in advance based on design specifications or the like is supplied to the other input terminal of the comparison circuit 104. The signal output from the comparison circuit 104 is input to one input terminal of the switch switching control circuit 105. A signal output from the other output terminal of the clock driver 101 is input to one input terminal of the drive capability memory circuit 106. An enable signal is supplied to the other input terminal of the drive capability memory circuit 106.

  In FIG. 2, the measurement circuit 102 has a function of measuring a delay time due to the slope of the output waveform of the clock driver 101. Here, the delay time due to the slope of the output waveform indicates the time required for the signal change of the output clock (time required from the start of the signal change of the output waveform to the end of the signal change). Note that the measurement circuit 102 has a function of a counter that counts the time required for signal change of the output clock.

  First, the measurement circuit 102 resets the count number with a reset signal (initializes a delay time due to the slope of the signal waveform). Then, the measurement circuit 102 measures the delay time due to the slope of the output waveform of the clock driver 101. That is, the measurement circuit 102 measures the time required for signal change (for example, rise) of the output clock. Note that the signal change start time and signal change end time of the output clock are determined based on the voltage level of the output clock, respectively. That is, for example, the measurement circuit 102 sets the time when the voltage level of the output clock reaches 10% as the signal change start time. Similarly, the measurement circuit 102 sets the time when the voltage level of the output clock reaches 90% as the signal change end time. The voltage level that determines the signal change start time and signal change end time of the output clock can be changed as appropriate based on design specifications and the like.

  The measurement circuit 102 starts counting when the signal change of the output clock starts. Then, the measurement circuit 102 ends the counting when the signal change of the output clock ends. In the second embodiment of the present invention, as an example, the measurement circuit 102 will be described as performing the following operation. In the measurement circuit 102, when the signal change of the output clock starts (for example, the voltage level of the output clock reaches 10%), the control signal A rises. When the signal change of the output clock is completed (for example, when the voltage level of the output clock reaches 90%), the control signal B rises. When the control signal A rises, the counter control signal is turned on. Further, the counter control signal is turned off by the rise of the control signal B. While the counter control signal is on, counting by the counter is executed.

  The comparison circuit 104 compares the delay time (count number) due to the slope of the output waveform of the clock driver 101 output from the measurement circuit 102 with a reference delay time (count number) set in advance based on design specifications and the like. To do. Note that this reference delay time can be changed as needed. Then, the comparison circuit 104 outputs the difference in delay time as a comparison result. This comparison result indicates the excess or deficiency of the drive capability currently set by the clock driver 101.

  On the other hand, the buffers 111, 112, and 113 provided in the clock driver 101 each have a function of giving a predetermined drive capability to the input clock and outputting it. Here, the drive capability of the output clock can be adjusted by switching on and off the switches 108, 109, and 110 connected in series to each buffer.

  The drive capability storage circuit 106 stores information on the drive capability adjusted by the clock driver 101. Here, the drive capability storage circuit 106 may store, for example, the on / off status of the switches 108, 109, and 110 as drive capability information. Note that the drive capability storage circuit 106 includes, for example, an FF that holds the current drive capability state of the clock driver 101. Then, the drive capability storage circuit 106 outputs information on the drive capability currently set to the switch switching control circuit 105 based on the enable signal.

  The switch switching control circuit 105 outputs a control signal based on the comparison result (delay time difference) of the comparison circuit 104 and the currently set drive capability information. The switches 108, 109, and 110 control on / off switching based on this control signal. That is, the clock driver 101 adjusts the drive capability so that the delay time due to the slope of the signal waveform of the output clock approaches the reference delay time. With such a circuit configuration, the clock skew automatic adjustment circuit 200 can automatically adjust the drive capability of the clock driver 101. Further, since the clock skew automatic adjustment circuit 200 automatically adjusts the time required for the signal change of the output clock, the clock skew adjustment can be performed with high accuracy.

  Next, a skew adjustment method of the clock skew automatic adjustment circuit 200 according to the second embodiment of the present invention will be described with reference to FIGS.

  First, the output waveform (output clock) of the clock driver 101 is input to the measurement circuit 102. The measurement circuit 102 measures the time required for signal change (for example, rise) of the output clock. 3 and 4, in the measurement circuit 102, the control signal A rises when the voltage level of the output clock reaches 10%. Further, when the voltage level of the output clock reaches 90%, the control signal B rises. When the control signal A rises, the counter control signal is turned on. Further, the counter control signal is turned off by the rise of the control signal B. While the counter control signal is on, counting is performed by a counter provided in the measurement circuit 102.

  In the example of FIG. 3, the time required for the signal change of the output clock (delay time due to the slope of the output waveform of the clock driver 101) has a count number of “10”. On the other hand, the reference delay time set in advance according to the design specification or the like has a count number of “8”. The comparison circuit 104 compares the time required for the signal change of the output clock with the reference delay time. Then, the comparison circuit 104 outputs the difference in delay time as a comparison result. This comparison result indicates the excess or deficiency of the drive capability currently set by the clock driver 101. In this example, the comparison circuit 104 outputs “2” which is the difference in the number of counts as a comparison result.

  On the other hand, the drive capability storage circuit 106 stores information on the drive capability adjusted in the clock driver 101. The switch switching control circuit 105 outputs a control signal based on the count difference “2” and the drive capability information. That is, the clock driver 101 adjusts the drive capability so that the delay time due to the slope of the signal waveform of the output clock approaches the reference delay time. In this example, the clock driver 101 adjusts the drive capability so that the delay time of the count difference “2” is set to “0”. Specifically, for example, the clock driver 101 turns on the switches 108 and 109 to increase the drive capability.

  In the example of FIG. 4, the time required for the signal change of the output clock (delay time due to the slope of the output waveform of the clock driver 101) has a count number of “7”. On the other hand, the reference delay time set in advance according to the design specification or the like has a count number of “8”. At this time, the comparison circuit 104 outputs “−1”, which is the difference in the number of counts, as a comparison result.

  The switch switching control circuit 105 outputs a control signal based on the count difference “−1” and the drive capability information. That is, the clock driver 101 adjusts the drive capability so that the delay time due to the slope of the signal waveform of the output clock approaches the reference delay time. In this example, the clock driver 101 adjusts the drive capability so that the delay time of the count difference “−1” is set to “0”. Specifically, for example, the clock driver 101 turns off the switch 108 in order to reduce the drive capability.

  As described above, the clock skew automatic adjustment circuit 200 according to the embodiment described above is based on the delay time difference between the delay time due to the slope of the output waveform of the clock driver 101 and the preset reference delay time. It is possible to automatically adjust the drive capacity. Further, since the clock skew automatic adjustment circuit 200 automatically adjusts the time required for the signal change of the output clock, the clock skew adjustment can be performed with high accuracy. In addition, with such a circuit configuration, a design period (a period during which wiring resistance or capacitance is extracted or a period during which the drive capability of the clock driver is adjusted) can be significantly shortened.

  Further, the clock skew automatic adjustment circuit 200 can automatically adjust the clock drive capability even when the wiring resistance or capacitance component of the peripheral circuit varies due to manufacturing variations of the semiconductor integrated circuit. That is, the clock skew automatic adjustment circuit 200 can readjust the clock skew that has fluctuated due to manufacturing variations or the like. This is the same even when a resistance component such as a buffer constituting the clock driver 101 or a load capacitance fluctuates.

  Further, the clock skew automatic adjustment circuit 200 can suppress the drive capability of the output clock within a range that satisfies the required clock skew. Thereby, the power consumption of the semiconductor integrated circuit can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, although the clock skew automatic adjustment circuit illustrated in FIGS. 1 and 2 has been described as an example in which the output clock from the clock driver 101 is directly input to the measurement circuit 102, the present invention is not limited thereto. For example, the circuit configuration can be appropriately changed to a circuit configuration including a delay circuit (for example, a frequency divider circuit) that varies (for example, increases) the delay time due to the slope of the output waveform of the clock driver 101 at a constant rate. Thereby, the measurement circuit 102 can easily measure the delay time. Furthermore, the measurement circuit 102 can measure the delay time with higher accuracy because the accuracy of the count number by the counter is improved. In this case, the reference delay time needs to be adjusted at the same rate.

  In the embodiment of the present invention, the case where the delay time required for the rising of the clock is adjusted has been described as an example. However, the present invention is not limited to this. The circuit configuration in the case of adjusting the delay time required for the falling of the clock can be changed as appropriate.

100 PLL
DESCRIPTION OF SYMBOLS 101 Clock driver 102 Measuring circuit 103 Control circuit 104 Comparison circuit 105 Switch switching control circuit 106 Drive capability memory circuit 107 Node 108 Switch 109 Switch 110 Switch 111 Buffer 112 Buffer 113 Buffer 114 FF
115 FF
116 FF
117 HM
200 Clock skew automatic adjustment circuit

Claims (8)

A clock driver that adjusts the drive capability of the clock;
A measurement circuit for measuring the time required from the start of signal change to the end of signal change of the clock;
A clock skew automatic adjustment circuit comprising: a control circuit that generates a control signal based on the measurement time and a preset reference time and outputs the control signal to the clock driver. The measuring circuit is
The clock skew automatic adjustment circuit according to claim 1, further comprising a counter that counts a time required from a signal change start to a signal change end of the clock. The signal change start and signal change end of the clock are:
3. The clock skew automatic adjustment circuit according to claim 1, wherein each of the clock skew automatic adjustment circuits is determined based on a voltage level of the clock. The clock driver is
Multiple buffers connected in parallel;
A switch connected in series for each of the buffers,
4. The clock skew automatic adjustment circuit according to claim 1, wherein on / off switching of the switch is controlled based on the control signal. 5.   5. The clock skew automatic adjustment circuit according to claim 1, further comprising a frequency dividing circuit that adjusts a time required from a signal change start to a signal change end of the clock. 6. The control circuit includes:
A comparison circuit that compares the measurement time with the reference time and outputs a comparison result;
6. A clock skew automatic adjustment circuit according to claim 1, further comprising: a drive capability storage circuit that stores information of drive capability adjusted by the clock driver.   The clock skew automatic adjustment circuit according to claim 6, wherein the drive capability information is determined based on an on / off state of the switch. Measure the time required from the start of signal change to the end of signal change,
Output a control signal for adjusting the drive capability of the clock based on the measurement time and a preset reference time,
A method for adjusting the clock skew automatic adjustment circuit that adjusts the drive capability of the clock.

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