JP2010226649A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can be surely operated even when a power supply voltage is low. <P>SOLUTION: The invention relates to a semiconductor integrated circuit including: NMOS switches 5, 6 for performing ON/OFF control, in accordance with control signals SEL1, SEL2, on signals inputted to input terminals 1, 2; and an operational amplifier 8 for amplifying the signals on which ON/OFF control has been performed by the NMOS switches 5, 6. The integrated circuit includes a level shifter 31 for boosting the control signals SEL1, SEL2 to a voltage higher than a power supply voltage of the operational amplifier 8. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit used as a mixer circuit, a selector circuit, a volume circuit, or the like.

  FIG. 3 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit used as a mixer circuit or a selector circuit. In this figure, reference numeral 1 denotes an input terminal to which an input signal IN1 is applied, and is connected to the drain of an NMOS transistor (switch means) 5 via a resistor 3. A control signal SEL 1 is applied to the gate of the NMOS transistor, and the source is connected to the inverting input terminal of the operational amplifier (amplifying means) 8. Similarly, reference numeral 2 denotes an input terminal to which the input signal IN2 is applied, and is connected to the drain of the NMOS transistor (switch means) 6 through the resistor 4. A control signal SEL 2 is applied to the gate of the NMOS transistor, and the source is connected to the inverting input terminal of the operational amplifier 8. A voltage half of the power supply voltage VDD is applied to the non-inverting input terminal of the operational amplifier 8, a resistor 7 is connected between the inverting input terminal and the output terminal, and a signal obtained at the output terminal is output from the output terminal 9. Is done.

  When a circuit having such a configuration is used as a mixer circuit, an H level (power supply voltage VDD) signal is applied to the gates of the NMOS transistors 5 and 6 as the control signals SEL1 and SEL2. As a result, the NMOS transistors 5 and 6 are turned on, and a signal obtained by adding the input signals IN1 and IN2 is output from the output terminal 9.

  When used as a selector circuit, one of the control signals SEL1 and SEL2 is set to H level and the other is set to L level (ground level). For example, when the control signal SEL1 is set to H level and SEL2 is set to L level, the input signal IN1 is amplified and output from the output terminal 9. Conversely, when the control signal SEL2 is set to H level and SEL1 is set to L level, the input signal IN2 is amplified and output from the output terminal 9.

  FIG. 4 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit used as a volume circuit. In this figure, reference numeral 11 denotes an input terminal to which an input signal IN is applied, and is connected to one end of a resistor 12. The resistors 12 to 16 are series-connected resistors, the connection point of the resistors 12 and 13 is connected to the drain of the NMOS transistor 21, the connection point of the resistors 13 and 14 is connected to the drain of the NMOS transistor 22, and the resistors 14, The connection point of 15 is connected to the drain of the NMOS transistor 23, the connection point of the resistors 15 and 16 is connected to the drain of the NMOS transistor 24, and the other end of the resistor 16 is connected to the output terminal of the operational amplifier 25. Further, control signals VL4 to VL1 are applied to the gates of the NMOS transistors 21 to 24, respectively, and the respective sources are connected to the inverting input terminal of the operational amplifier 25. A voltage that is ½ of the power supply voltage VDD is applied to the non-inverting input terminal of the operational amplifier 25, and a signal obtained at the output terminal is output from the output terminal 26.

  In such a configuration, when an H level signal is added only to the control signal VL1, the input signal IN is amplified with an amplification factor determined by the combined resistance value of the resistors 12 to 15 and the resistance value of the resistor 16, and is output from the output terminal 26. Is done. In this case, the output signal is minimized. When an H level signal is added only to the control signal VL2, the input signal IN is amplified with an amplification factor determined by the combined resistance value of the resistors 12 to 14 and the combined resistance value of the resistors 15 and 16, and is output from the output terminal 26. The In this case, the level of the output signal becomes larger than that of the control signal VL1 alone. Similarly, when an H level signal is sequentially added only to the control signals VL3 and VL4, the signal at the output terminal 26 is sequentially increased. That is, the circuit of FIG. 4 operates as a volume.

Japanese Patent Application Laid-Open No. 07-221642

  By the way, in the above-described semiconductor integrated circuit, the voltage VDD / 2 is applied to the non-inverting input terminals of the operational amplifiers 8 and 25, and as a result, the operational amplifiers to which the sources of the NMOS transistors 5, 6, 21 to 24 are connected. Since the voltages at the inverting input terminals (virtual grounding points) of 8 and 25 are as high as VDD / 2, the threshold Vth of the NMOS transistors 5, 6, 21 to 24 is high due to the substrate effect. For this reason, when the power supply voltage is lowered, the NMOS transistors 5, 6, 21 to 24 cannot be turned on first, which causes a problem of a bottleneck in low voltage operation.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit that can be reliably operated even when a power supply voltage is low.

  In order to solve the above-described problems, the present invention provides switch means for controlling on / off of a signal input to an input terminal according to a control signal, and amplification means for amplifying a signal on / off controlled by the switch means. And a level shifter for boosting the control signal to a voltage higher than the power supply voltage of the amplifying means.

  In the semiconductor integrated circuit according to the present invention, the switch means is an NMOS switch, a gate electrode of the NMOS switch is connected to the level shifter, and a drain electrode of the NMOS switch is connected to the input terminal via a resistor. A source electrode of the NMOS switch is connected to a virtual ground point of the amplification means.

  According to the present invention, in the above semiconductor integrated circuit, the plurality of input terminals, the plurality of switch means for controlling on / off of signals input to the input terminals, and the outputs of the switch means are added and amplified. And amplifying means that operate as a mixer or a selector.

  Further, the present invention provides the semiconductor integrated circuit described above, wherein one input terminal, a series connection circuit of a plurality of resistors connected to the input terminal, and the plurality of resistors are switched to the input terminal of the amplification means. A plurality of switch means to be connected, and operate as a volume.

  According to the present invention, since the level shifter for boosting the control signal to a voltage higher than the power supply voltage of the amplification means is provided, there is an effect that the operation can be reliably performed even when the power supply voltage is low.

1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention. It is a circuit diagram which shows the structure of the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the conventional semiconductor integrated circuit used as a mixer circuit or a selector circuit. It is a circuit diagram which shows the structure of the conventional semiconductor integrated circuit used as a volume circuit.

Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention, and this circuit is used as a mixer circuit or a selector circuit. In this circuit, parts having the same configurations as those in the circuit shown in FIG.

  The circuit shown in this figure is different from the circuit shown in FIG. 3 in that the control signals SEL 1 and SEL 2 are not directly applied to the gates of the NMOS transistors 5 and 6 but are added via the level shifter 31. That is, in the figure, the booster circuit 32 is a circuit that boosts the power supply voltage VDD to a higher voltage VRR, and the boosted voltage VRR is applied to the level shifter 31. The level shifter 31 boosts the voltage to VRR and outputs it to the NMOS transistors 5 and 6 when the control signals SEL1 and SEL2 are at the H level (voltage VDD).

  With such a configuration, the NMOS transistors 5 and 6 can be reliably turned on even when the power supply voltage VDD is low.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention, and this circuit is used as a volume circuit. In this circuit, parts having the same configurations as those in the circuit shown in FIG.
The circuit shown in this figure is different from the circuit shown in FIG. 4 in that the control signals VL1 to VL4 are not directly applied to the gates of the NMOS transistors 21 to 24 but via the level shifter 33. That is, in the figure, the booster circuit 34 is a circuit that boosts the power supply voltage VDD to a higher voltage VRR, and the boosted voltage VRR is applied to the level shifter 33. When the control signals VL1 to VL4 are at the H level (voltage VDD), the level shifter 33 boosts the voltage to VRR and outputs it to the NMOS transistors 21 to 24.

  With such a configuration, the NMOS transistors 21 to 24 can be reliably turned on even when the power supply voltage VDD is low. Further, according to the above embodiment, since the bias level is lower than VDD / 2, the influence of the substrate effect is reduced. If the on-resistance is designed to be the same as the conventional one, the size of the NMOS switch is reduced. can do.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

3, 4, 12 to 16, resistors 5, 6, 21 to 24, NMOS transistors, 8, 25, operational amplifiers 31, 33, level shifters, 32, 34, booster circuits.

Claims (4)

In a semiconductor integrated circuit comprising switch means for on / off control of a signal input to an input terminal according to a control signal, and amplification means for amplifying a signal on / off controlled by the switch means,
A semiconductor integrated circuit comprising a level shifter for boosting the control signal to a voltage higher than a power supply voltage of the amplification means.   The switch means is an NMOS switch, the gate electrode of the NMOS switch is connected to the level shifter, the drain electrode of the NMOS switch is connected to the input terminal via a resistor, and the source electrode of the NMOS switch is the amplification means The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to a virtual ground point.   A plurality of the input terminals, a plurality of switch means for controlling on / off of signals input to the input terminals, and the amplifying means for adding and amplifying the outputs of the switch means. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit operates.   One input terminal, a series connection circuit of a plurality of resistors connected to the input terminal, and a plurality of the switch means for switching the plurality of resistors and connecting to the input terminal of the amplification means, The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit operates as.

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